Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This program is free software; you can redistribute it and/or | |
3 | * modify it under the terms of the GNU General Public License | |
4 | * as published by the Free Software Foundation; either version 2 | |
5 | * of the License, or (at your option) any later version. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | * | |
12 | * You should have received a copy of the GNU General Public License | |
13 | * along with this program; if not, write to the Free Software | |
14 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
15 | * | |
16 | * Copyright (C) 2000, 2001 Kanoj Sarcar | |
17 | * Copyright (C) 2000, 2001 Ralf Baechle | |
18 | * Copyright (C) 2000, 2001 Silicon Graphics, Inc. | |
19 | * Copyright (C) 2000, 2001, 2003 Broadcom Corporation | |
20 | */ | |
21 | #include <linux/cache.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/interrupt.h> | |
631330f5 | 25 | #include <linux/smp.h> |
1da177e4 LT |
26 | #include <linux/spinlock.h> |
27 | #include <linux/threads.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/time.h> | |
30 | #include <linux/timex.h> | |
31 | #include <linux/sched.h> | |
32 | #include <linux/cpumask.h> | |
1e35aaba | 33 | #include <linux/cpu.h> |
4e950f6f | 34 | #include <linux/err.h> |
8f99a162 | 35 | #include <linux/ftrace.h> |
fbde2d7d QY |
36 | #include <linux/irqdomain.h> |
37 | #include <linux/of.h> | |
38 | #include <linux/of_irq.h> | |
1da177e4 | 39 | |
60063497 | 40 | #include <linux/atomic.h> |
1da177e4 LT |
41 | #include <asm/cpu.h> |
42 | #include <asm/processor.h> | |
bdc92d74 | 43 | #include <asm/idle.h> |
39b8d525 | 44 | #include <asm/r4k-timer.h> |
fbde2d7d | 45 | #include <asm/mips-cpc.h> |
1da177e4 | 46 | #include <asm/mmu_context.h> |
7bcf7717 | 47 | #include <asm/time.h> |
b81947c6 | 48 | #include <asm/setup.h> |
e060f6ed | 49 | #include <asm/maar.h> |
1da177e4 | 50 | |
cafb45b2 | 51 | cpumask_t cpu_callin_map; /* Bitmask of started secondaries */ |
2dc2ae34 | 52 | |
1da177e4 | 53 | int __cpu_number_map[NR_CPUS]; /* Map physical to logical */ |
2dc2ae34 DD |
54 | EXPORT_SYMBOL(__cpu_number_map); |
55 | ||
1da177e4 | 56 | int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */ |
2dc2ae34 | 57 | EXPORT_SYMBOL(__cpu_logical_map); |
1da177e4 | 58 | |
0ab7aefc RB |
59 | /* Number of TCs (or siblings in Intel speak) per CPU core */ |
60 | int smp_num_siblings = 1; | |
61 | EXPORT_SYMBOL(smp_num_siblings); | |
62 | ||
63 | /* representing the TCs (or siblings in Intel speak) of each logical CPU */ | |
64 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; | |
65 | EXPORT_SYMBOL(cpu_sibling_map); | |
66 | ||
bda4584c HC |
67 | /* representing the core map of multi-core chips of each logical CPU */ |
68 | cpumask_t cpu_core_map[NR_CPUS] __read_mostly; | |
69 | EXPORT_SYMBOL(cpu_core_map); | |
70 | ||
cccf34e9 MC |
71 | /* |
72 | * A logcal cpu mask containing only one VPE per core to | |
73 | * reduce the number of IPIs on large MT systems. | |
74 | */ | |
75 | cpumask_t cpu_foreign_map __read_mostly; | |
76 | EXPORT_SYMBOL(cpu_foreign_map); | |
77 | ||
0ab7aefc RB |
78 | /* representing cpus for which sibling maps can be computed */ |
79 | static cpumask_t cpu_sibling_setup_map; | |
80 | ||
bda4584c HC |
81 | /* representing cpus for which core maps can be computed */ |
82 | static cpumask_t cpu_core_setup_map; | |
83 | ||
76306f42 PB |
84 | cpumask_t cpu_coherent_mask; |
85 | ||
fbde2d7d QY |
86 | #ifdef CONFIG_GENERIC_IRQ_IPI |
87 | static struct irq_desc *call_desc; | |
88 | static struct irq_desc *sched_desc; | |
89 | #endif | |
90 | ||
0ab7aefc RB |
91 | static inline void set_cpu_sibling_map(int cpu) |
92 | { | |
93 | int i; | |
94 | ||
8dd92891 | 95 | cpumask_set_cpu(cpu, &cpu_sibling_setup_map); |
0ab7aefc RB |
96 | |
97 | if (smp_num_siblings > 1) { | |
8dd92891 | 98 | for_each_cpu(i, &cpu_sibling_setup_map) { |
bda4584c HC |
99 | if (cpu_data[cpu].package == cpu_data[i].package && |
100 | cpu_data[cpu].core == cpu_data[i].core) { | |
8dd92891 RR |
101 | cpumask_set_cpu(i, &cpu_sibling_map[cpu]); |
102 | cpumask_set_cpu(cpu, &cpu_sibling_map[i]); | |
0ab7aefc RB |
103 | } |
104 | } | |
105 | } else | |
8dd92891 | 106 | cpumask_set_cpu(cpu, &cpu_sibling_map[cpu]); |
0ab7aefc RB |
107 | } |
108 | ||
bda4584c HC |
109 | static inline void set_cpu_core_map(int cpu) |
110 | { | |
111 | int i; | |
112 | ||
8dd92891 | 113 | cpumask_set_cpu(cpu, &cpu_core_setup_map); |
bda4584c | 114 | |
8dd92891 | 115 | for_each_cpu(i, &cpu_core_setup_map) { |
bda4584c | 116 | if (cpu_data[cpu].package == cpu_data[i].package) { |
8dd92891 RR |
117 | cpumask_set_cpu(i, &cpu_core_map[cpu]); |
118 | cpumask_set_cpu(cpu, &cpu_core_map[i]); | |
bda4584c HC |
119 | } |
120 | } | |
121 | } | |
122 | ||
cccf34e9 MC |
123 | /* |
124 | * Calculate a new cpu_foreign_map mask whenever a | |
125 | * new cpu appears or disappears. | |
126 | */ | |
127 | static inline void calculate_cpu_foreign_map(void) | |
128 | { | |
129 | int i, k, core_present; | |
130 | cpumask_t temp_foreign_map; | |
131 | ||
132 | /* Re-calculate the mask */ | |
d825c06b | 133 | cpumask_clear(&temp_foreign_map); |
cccf34e9 MC |
134 | for_each_online_cpu(i) { |
135 | core_present = 0; | |
136 | for_each_cpu(k, &temp_foreign_map) | |
137 | if (cpu_data[i].package == cpu_data[k].package && | |
138 | cpu_data[i].core == cpu_data[k].core) | |
139 | core_present = 1; | |
140 | if (!core_present) | |
141 | cpumask_set_cpu(i, &temp_foreign_map); | |
142 | } | |
143 | ||
144 | cpumask_copy(&cpu_foreign_map, &temp_foreign_map); | |
145 | } | |
146 | ||
87353d8a | 147 | struct plat_smp_ops *mp_ops; |
82d45de6 | 148 | EXPORT_SYMBOL(mp_ops); |
87353d8a | 149 | |
078a55fc | 150 | void register_smp_ops(struct plat_smp_ops *ops) |
87353d8a | 151 | { |
83738e30 TS |
152 | if (mp_ops) |
153 | printk(KERN_WARNING "Overriding previously set SMP ops\n"); | |
87353d8a RB |
154 | |
155 | mp_ops = ops; | |
156 | } | |
157 | ||
fbde2d7d QY |
158 | #ifdef CONFIG_GENERIC_IRQ_IPI |
159 | void mips_smp_send_ipi_single(int cpu, unsigned int action) | |
160 | { | |
161 | mips_smp_send_ipi_mask(cpumask_of(cpu), action); | |
162 | } | |
163 | ||
164 | void mips_smp_send_ipi_mask(const struct cpumask *mask, unsigned int action) | |
165 | { | |
166 | unsigned long flags; | |
167 | unsigned int core; | |
168 | int cpu; | |
169 | ||
170 | local_irq_save(flags); | |
171 | ||
172 | switch (action) { | |
173 | case SMP_CALL_FUNCTION: | |
174 | __ipi_send_mask(call_desc, mask); | |
175 | break; | |
176 | ||
177 | case SMP_RESCHEDULE_YOURSELF: | |
178 | __ipi_send_mask(sched_desc, mask); | |
179 | break; | |
180 | ||
181 | default: | |
182 | BUG(); | |
183 | } | |
184 | ||
185 | if (mips_cpc_present()) { | |
186 | for_each_cpu(cpu, mask) { | |
187 | core = cpu_data[cpu].core; | |
188 | ||
189 | if (core == current_cpu_data.core) | |
190 | continue; | |
191 | ||
192 | while (!cpumask_test_cpu(cpu, &cpu_coherent_mask)) { | |
193 | mips_cpc_lock_other(core); | |
194 | write_cpc_co_cmd(CPC_Cx_CMD_PWRUP); | |
195 | mips_cpc_unlock_other(); | |
196 | } | |
197 | } | |
198 | } | |
199 | ||
200 | local_irq_restore(flags); | |
201 | } | |
202 | ||
203 | ||
204 | static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) | |
205 | { | |
206 | scheduler_ipi(); | |
207 | ||
208 | return IRQ_HANDLED; | |
209 | } | |
210 | ||
211 | static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) | |
212 | { | |
213 | generic_smp_call_function_interrupt(); | |
214 | ||
215 | return IRQ_HANDLED; | |
216 | } | |
217 | ||
218 | static struct irqaction irq_resched = { | |
219 | .handler = ipi_resched_interrupt, | |
220 | .flags = IRQF_PERCPU, | |
221 | .name = "IPI resched" | |
222 | }; | |
223 | ||
224 | static struct irqaction irq_call = { | |
225 | .handler = ipi_call_interrupt, | |
226 | .flags = IRQF_PERCPU, | |
227 | .name = "IPI call" | |
228 | }; | |
229 | ||
230 | static __init void smp_ipi_init_one(unsigned int virq, | |
231 | struct irqaction *action) | |
232 | { | |
233 | int ret; | |
234 | ||
235 | irq_set_handler(virq, handle_percpu_irq); | |
236 | ret = setup_irq(virq, action); | |
237 | BUG_ON(ret); | |
238 | } | |
239 | ||
240 | static int __init mips_smp_ipi_init(void) | |
241 | { | |
242 | unsigned int call_virq, sched_virq; | |
243 | struct irq_domain *ipidomain; | |
244 | struct device_node *node; | |
245 | ||
246 | node = of_irq_find_parent(of_root); | |
247 | ipidomain = irq_find_matching_host(node, DOMAIN_BUS_IPI); | |
248 | ||
249 | /* | |
250 | * Some platforms have half DT setup. So if we found irq node but | |
251 | * didn't find an ipidomain, try to search for one that is not in the | |
252 | * DT. | |
253 | */ | |
254 | if (node && !ipidomain) | |
255 | ipidomain = irq_find_matching_host(NULL, DOMAIN_BUS_IPI); | |
256 | ||
578bffc8 PB |
257 | /* |
258 | * There are systems which only use IPI domains some of the time, | |
259 | * depending upon configuration we don't know until runtime. An | |
260 | * example is Malta where we may compile in support for GIC & the | |
261 | * MT ASE, but run on a system which has multiple VPEs in a single | |
262 | * core and doesn't include a GIC. Until all IPI implementations | |
263 | * have been converted to use IPI domains the best we can do here | |
264 | * is to return & hope some other code sets up the IPIs. | |
265 | */ | |
266 | if (!ipidomain) | |
267 | return 0; | |
fbde2d7d QY |
268 | |
269 | call_virq = irq_reserve_ipi(ipidomain, cpu_possible_mask); | |
270 | BUG_ON(!call_virq); | |
271 | ||
272 | sched_virq = irq_reserve_ipi(ipidomain, cpu_possible_mask); | |
273 | BUG_ON(!sched_virq); | |
274 | ||
275 | if (irq_domain_is_ipi_per_cpu(ipidomain)) { | |
276 | int cpu; | |
277 | ||
278 | for_each_cpu(cpu, cpu_possible_mask) { | |
279 | smp_ipi_init_one(call_virq + cpu, &irq_call); | |
280 | smp_ipi_init_one(sched_virq + cpu, &irq_resched); | |
281 | } | |
282 | } else { | |
283 | smp_ipi_init_one(call_virq, &irq_call); | |
284 | smp_ipi_init_one(sched_virq, &irq_resched); | |
285 | } | |
286 | ||
287 | call_desc = irq_to_desc(call_virq); | |
288 | sched_desc = irq_to_desc(sched_virq); | |
289 | ||
290 | return 0; | |
291 | } | |
292 | early_initcall(mips_smp_ipi_init); | |
293 | #endif | |
294 | ||
1da177e4 LT |
295 | /* |
296 | * First C code run on the secondary CPUs after being started up by | |
297 | * the master. | |
298 | */ | |
078a55fc | 299 | asmlinkage void start_secondary(void) |
1da177e4 | 300 | { |
5bfb5d69 | 301 | unsigned int cpu; |
1da177e4 LT |
302 | |
303 | cpu_probe(); | |
6650df3c | 304 | per_cpu_trap_init(false); |
7bcf7717 | 305 | mips_clockevent_init(); |
87353d8a | 306 | mp_ops->init_secondary(); |
c7754e75 | 307 | cpu_report(); |
e060f6ed | 308 | maar_init(); |
1da177e4 LT |
309 | |
310 | /* | |
311 | * XXX parity protection should be folded in here when it's converted | |
312 | * to an option instead of something based on .cputype | |
313 | */ | |
314 | ||
315 | calibrate_delay(); | |
5bfb5d69 NP |
316 | preempt_disable(); |
317 | cpu = smp_processor_id(); | |
1da177e4 LT |
318 | cpu_data[cpu].udelay_val = loops_per_jiffy; |
319 | ||
8dd92891 | 320 | cpumask_set_cpu(cpu, &cpu_coherent_mask); |
e545a614 MS |
321 | notify_cpu_starting(cpu); |
322 | ||
b9a09a06 YZ |
323 | set_cpu_online(cpu, true); |
324 | ||
0ab7aefc | 325 | set_cpu_sibling_map(cpu); |
bda4584c | 326 | set_cpu_core_map(cpu); |
1da177e4 | 327 | |
cccf34e9 MC |
328 | calculate_cpu_foreign_map(); |
329 | ||
8dd92891 | 330 | cpumask_set_cpu(cpu, &cpu_callin_map); |
1da177e4 | 331 | |
cf9bfe55 | 332 | synchronise_count_slave(cpu); |
39b8d525 | 333 | |
b789ad63 YZ |
334 | /* |
335 | * irq will be enabled in ->smp_finish(), enabling it too early | |
336 | * is dangerous. | |
337 | */ | |
338 | WARN_ON_ONCE(!irqs_disabled()); | |
5309bdac YZ |
339 | mp_ops->smp_finish(); |
340 | ||
fc6d73d6 | 341 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
1da177e4 LT |
342 | } |
343 | ||
1da177e4 LT |
344 | static void stop_this_cpu(void *dummy) |
345 | { | |
346 | /* | |
cccf34e9 MC |
347 | * Remove this CPU. Be a bit slow here and |
348 | * set the bits for every online CPU so we don't miss | |
349 | * any IPI whilst taking this VPE down. | |
1da177e4 | 350 | */ |
cccf34e9 MC |
351 | |
352 | cpumask_copy(&cpu_foreign_map, cpu_online_mask); | |
353 | ||
354 | /* Make it visible to every other CPU */ | |
355 | smp_mb(); | |
356 | ||
0b5f9c00 | 357 | set_cpu_online(smp_processor_id(), false); |
cccf34e9 | 358 | calculate_cpu_foreign_map(); |
ea925a72 AB |
359 | local_irq_disable(); |
360 | while (1); | |
1da177e4 LT |
361 | } |
362 | ||
363 | void smp_send_stop(void) | |
364 | { | |
8691e5a8 | 365 | smp_call_function(stop_this_cpu, NULL, 0); |
1da177e4 LT |
366 | } |
367 | ||
368 | void __init smp_cpus_done(unsigned int max_cpus) | |
369 | { | |
1da177e4 LT |
370 | } |
371 | ||
372 | /* called from main before smp_init() */ | |
373 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
374 | { | |
1da177e4 LT |
375 | init_new_context(current, &init_mm); |
376 | current_thread_info()->cpu = 0; | |
87353d8a | 377 | mp_ops->prepare_cpus(max_cpus); |
0ab7aefc | 378 | set_cpu_sibling_map(0); |
bda4584c | 379 | set_cpu_core_map(0); |
cccf34e9 | 380 | calculate_cpu_foreign_map(); |
320e6aba | 381 | #ifndef CONFIG_HOTPLUG_CPU |
0b5f9c00 | 382 | init_cpu_present(cpu_possible_mask); |
320e6aba | 383 | #endif |
76306f42 | 384 | cpumask_copy(&cpu_coherent_mask, cpu_possible_mask); |
1da177e4 LT |
385 | } |
386 | ||
387 | /* preload SMP state for boot cpu */ | |
28eb0e46 | 388 | void smp_prepare_boot_cpu(void) |
1da177e4 | 389 | { |
4037ac6e RR |
390 | set_cpu_possible(0, true); |
391 | set_cpu_online(0, true); | |
8dd92891 | 392 | cpumask_set_cpu(0, &cpu_callin_map); |
1da177e4 LT |
393 | } |
394 | ||
078a55fc | 395 | int __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 396 | { |
360014a3 | 397 | mp_ops->boot_secondary(cpu, tidle); |
1da177e4 | 398 | |
b727a602 RB |
399 | /* |
400 | * Trust is futile. We should really have timeouts ... | |
401 | */ | |
cafb45b2 | 402 | while (!cpumask_test_cpu(cpu, &cpu_callin_map)) { |
1da177e4 | 403 | udelay(100); |
cafb45b2 RB |
404 | schedule(); |
405 | } | |
1da177e4 | 406 | |
cf9bfe55 | 407 | synchronise_count_master(cpu); |
1da177e4 LT |
408 | return 0; |
409 | } | |
410 | ||
1da177e4 LT |
411 | /* Not really SMP stuff ... */ |
412 | int setup_profiling_timer(unsigned int multiplier) | |
413 | { | |
414 | return 0; | |
415 | } | |
416 | ||
417 | static void flush_tlb_all_ipi(void *info) | |
418 | { | |
419 | local_flush_tlb_all(); | |
420 | } | |
421 | ||
422 | void flush_tlb_all(void) | |
423 | { | |
15c8b6c1 | 424 | on_each_cpu(flush_tlb_all_ipi, NULL, 1); |
1da177e4 LT |
425 | } |
426 | ||
427 | static void flush_tlb_mm_ipi(void *mm) | |
428 | { | |
429 | local_flush_tlb_mm((struct mm_struct *)mm); | |
430 | } | |
431 | ||
25969354 RB |
432 | /* |
433 | * Special Variant of smp_call_function for use by TLB functions: | |
434 | * | |
435 | * o No return value | |
436 | * o collapses to normal function call on UP kernels | |
437 | * o collapses to normal function call on systems with a single shared | |
438 | * primary cache. | |
25969354 RB |
439 | */ |
440 | static inline void smp_on_other_tlbs(void (*func) (void *info), void *info) | |
441 | { | |
8691e5a8 | 442 | smp_call_function(func, info, 1); |
25969354 RB |
443 | } |
444 | ||
445 | static inline void smp_on_each_tlb(void (*func) (void *info), void *info) | |
446 | { | |
447 | preempt_disable(); | |
448 | ||
449 | smp_on_other_tlbs(func, info); | |
450 | func(info); | |
451 | ||
452 | preempt_enable(); | |
453 | } | |
454 | ||
1da177e4 LT |
455 | /* |
456 | * The following tlb flush calls are invoked when old translations are | |
457 | * being torn down, or pte attributes are changing. For single threaded | |
458 | * address spaces, a new context is obtained on the current cpu, and tlb | |
459 | * context on other cpus are invalidated to force a new context allocation | |
460 | * at switch_mm time, should the mm ever be used on other cpus. For | |
461 | * multithreaded address spaces, intercpu interrupts have to be sent. | |
462 | * Another case where intercpu interrupts are required is when the target | |
463 | * mm might be active on another cpu (eg debuggers doing the flushes on | |
464 | * behalf of debugees, kswapd stealing pages from another process etc). | |
465 | * Kanoj 07/00. | |
466 | */ | |
467 | ||
468 | void flush_tlb_mm(struct mm_struct *mm) | |
469 | { | |
470 | preempt_disable(); | |
471 | ||
472 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
c50cade9 | 473 | smp_on_other_tlbs(flush_tlb_mm_ipi, mm); |
1da177e4 | 474 | } else { |
b5eb5511 RB |
475 | unsigned int cpu; |
476 | ||
0b5f9c00 RR |
477 | for_each_online_cpu(cpu) { |
478 | if (cpu != smp_processor_id() && cpu_context(cpu, mm)) | |
b5eb5511 | 479 | cpu_context(cpu, mm) = 0; |
0b5f9c00 | 480 | } |
1da177e4 LT |
481 | } |
482 | local_flush_tlb_mm(mm); | |
483 | ||
484 | preempt_enable(); | |
485 | } | |
486 | ||
487 | struct flush_tlb_data { | |
488 | struct vm_area_struct *vma; | |
489 | unsigned long addr1; | |
490 | unsigned long addr2; | |
491 | }; | |
492 | ||
493 | static void flush_tlb_range_ipi(void *info) | |
494 | { | |
c50cade9 | 495 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
496 | |
497 | local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2); | |
498 | } | |
499 | ||
500 | void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) | |
501 | { | |
502 | struct mm_struct *mm = vma->vm_mm; | |
503 | ||
504 | preempt_disable(); | |
505 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
89a8a5a6 RB |
506 | struct flush_tlb_data fd = { |
507 | .vma = vma, | |
508 | .addr1 = start, | |
509 | .addr2 = end, | |
510 | }; | |
1da177e4 | 511 | |
c50cade9 | 512 | smp_on_other_tlbs(flush_tlb_range_ipi, &fd); |
1da177e4 | 513 | } else { |
b5eb5511 RB |
514 | unsigned int cpu; |
515 | ||
0b5f9c00 RR |
516 | for_each_online_cpu(cpu) { |
517 | if (cpu != smp_processor_id() && cpu_context(cpu, mm)) | |
b5eb5511 | 518 | cpu_context(cpu, mm) = 0; |
0b5f9c00 | 519 | } |
1da177e4 LT |
520 | } |
521 | local_flush_tlb_range(vma, start, end); | |
522 | preempt_enable(); | |
523 | } | |
524 | ||
525 | static void flush_tlb_kernel_range_ipi(void *info) | |
526 | { | |
c50cade9 | 527 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
528 | |
529 | local_flush_tlb_kernel_range(fd->addr1, fd->addr2); | |
530 | } | |
531 | ||
532 | void flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
533 | { | |
89a8a5a6 RB |
534 | struct flush_tlb_data fd = { |
535 | .addr1 = start, | |
536 | .addr2 = end, | |
537 | }; | |
1da177e4 | 538 | |
15c8b6c1 | 539 | on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1); |
1da177e4 LT |
540 | } |
541 | ||
542 | static void flush_tlb_page_ipi(void *info) | |
543 | { | |
c50cade9 | 544 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
545 | |
546 | local_flush_tlb_page(fd->vma, fd->addr1); | |
547 | } | |
548 | ||
549 | void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) | |
550 | { | |
551 | preempt_disable(); | |
552 | if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) { | |
89a8a5a6 RB |
553 | struct flush_tlb_data fd = { |
554 | .vma = vma, | |
555 | .addr1 = page, | |
556 | }; | |
1da177e4 | 557 | |
c50cade9 | 558 | smp_on_other_tlbs(flush_tlb_page_ipi, &fd); |
1da177e4 | 559 | } else { |
b5eb5511 RB |
560 | unsigned int cpu; |
561 | ||
0b5f9c00 RR |
562 | for_each_online_cpu(cpu) { |
563 | if (cpu != smp_processor_id() && cpu_context(cpu, vma->vm_mm)) | |
b5eb5511 | 564 | cpu_context(cpu, vma->vm_mm) = 0; |
0b5f9c00 | 565 | } |
1da177e4 LT |
566 | } |
567 | local_flush_tlb_page(vma, page); | |
568 | preempt_enable(); | |
569 | } | |
570 | ||
571 | static void flush_tlb_one_ipi(void *info) | |
572 | { | |
573 | unsigned long vaddr = (unsigned long) info; | |
574 | ||
575 | local_flush_tlb_one(vaddr); | |
576 | } | |
577 | ||
578 | void flush_tlb_one(unsigned long vaddr) | |
579 | { | |
25969354 | 580 | smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr); |
1da177e4 LT |
581 | } |
582 | ||
583 | EXPORT_SYMBOL(flush_tlb_page); | |
584 | EXPORT_SYMBOL(flush_tlb_one); | |
7aa1c8f4 RB |
585 | |
586 | #if defined(CONFIG_KEXEC) | |
587 | void (*dump_ipi_function_ptr)(void *) = NULL; | |
588 | void dump_send_ipi(void (*dump_ipi_callback)(void *)) | |
589 | { | |
590 | int i; | |
591 | int cpu = smp_processor_id(); | |
592 | ||
593 | dump_ipi_function_ptr = dump_ipi_callback; | |
594 | smp_mb(); | |
595 | for_each_online_cpu(i) | |
596 | if (i != cpu) | |
597 | mp_ops->send_ipi_single(i, SMP_DUMP); | |
598 | ||
599 | } | |
600 | EXPORT_SYMBOL(dump_send_ipi); | |
601 | #endif | |
cc7964af PB |
602 | |
603 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST | |
604 | ||
605 | static DEFINE_PER_CPU(atomic_t, tick_broadcast_count); | |
606 | static DEFINE_PER_CPU(struct call_single_data, tick_broadcast_csd); | |
607 | ||
608 | void tick_broadcast(const struct cpumask *mask) | |
609 | { | |
610 | atomic_t *count; | |
611 | struct call_single_data *csd; | |
612 | int cpu; | |
613 | ||
614 | for_each_cpu(cpu, mask) { | |
615 | count = &per_cpu(tick_broadcast_count, cpu); | |
616 | csd = &per_cpu(tick_broadcast_csd, cpu); | |
617 | ||
618 | if (atomic_inc_return(count) == 1) | |
619 | smp_call_function_single_async(cpu, csd); | |
620 | } | |
621 | } | |
622 | ||
623 | static void tick_broadcast_callee(void *info) | |
624 | { | |
625 | int cpu = smp_processor_id(); | |
626 | tick_receive_broadcast(); | |
627 | atomic_set(&per_cpu(tick_broadcast_count, cpu), 0); | |
628 | } | |
629 | ||
630 | static int __init tick_broadcast_init(void) | |
631 | { | |
632 | struct call_single_data *csd; | |
633 | int cpu; | |
634 | ||
635 | for (cpu = 0; cpu < NR_CPUS; cpu++) { | |
636 | csd = &per_cpu(tick_broadcast_csd, cpu); | |
637 | csd->func = tick_broadcast_callee; | |
638 | } | |
639 | ||
640 | return 0; | |
641 | } | |
642 | early_initcall(tick_broadcast_init); | |
643 | ||
644 | #endif /* CONFIG_GENERIC_CLOCKEVENTS_BROADCAST */ |