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1da177e4 LT |
1 | /* |
2 | * This program is free software; you can redistribute it and/or | |
3 | * modify it under the terms of the GNU General Public License | |
4 | * as published by the Free Software Foundation; either version 2 | |
5 | * of the License, or (at your option) any later version. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | * | |
12 | * You should have received a copy of the GNU General Public License | |
13 | * along with this program; if not, write to the Free Software | |
14 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
15 | * | |
16 | * Copyright (C) 2000, 2001 Kanoj Sarcar | |
17 | * Copyright (C) 2000, 2001 Ralf Baechle | |
18 | * Copyright (C) 2000, 2001 Silicon Graphics, Inc. | |
19 | * Copyright (C) 2000, 2001, 2003 Broadcom Corporation | |
20 | */ | |
21 | #include <linux/cache.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/interrupt.h> | |
631330f5 | 25 | #include <linux/smp.h> |
1da177e4 LT |
26 | #include <linux/spinlock.h> |
27 | #include <linux/threads.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/time.h> | |
30 | #include <linux/timex.h> | |
31 | #include <linux/sched.h> | |
32 | #include <linux/cpumask.h> | |
1e35aaba | 33 | #include <linux/cpu.h> |
4e950f6f | 34 | #include <linux/err.h> |
8f99a162 | 35 | #include <linux/ftrace.h> |
1da177e4 | 36 | |
60063497 | 37 | #include <linux/atomic.h> |
1da177e4 LT |
38 | #include <asm/cpu.h> |
39 | #include <asm/processor.h> | |
bdc92d74 | 40 | #include <asm/idle.h> |
39b8d525 | 41 | #include <asm/r4k-timer.h> |
1da177e4 | 42 | #include <asm/mmu_context.h> |
7bcf7717 | 43 | #include <asm/time.h> |
b81947c6 | 44 | #include <asm/setup.h> |
e060f6ed | 45 | #include <asm/maar.h> |
1da177e4 | 46 | |
cafb45b2 | 47 | cpumask_t cpu_callin_map; /* Bitmask of started secondaries */ |
2dc2ae34 | 48 | |
1da177e4 | 49 | int __cpu_number_map[NR_CPUS]; /* Map physical to logical */ |
2dc2ae34 DD |
50 | EXPORT_SYMBOL(__cpu_number_map); |
51 | ||
1da177e4 | 52 | int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */ |
2dc2ae34 | 53 | EXPORT_SYMBOL(__cpu_logical_map); |
1da177e4 | 54 | |
0ab7aefc RB |
55 | /* Number of TCs (or siblings in Intel speak) per CPU core */ |
56 | int smp_num_siblings = 1; | |
57 | EXPORT_SYMBOL(smp_num_siblings); | |
58 | ||
59 | /* representing the TCs (or siblings in Intel speak) of each logical CPU */ | |
60 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; | |
61 | EXPORT_SYMBOL(cpu_sibling_map); | |
62 | ||
bda4584c HC |
63 | /* representing the core map of multi-core chips of each logical CPU */ |
64 | cpumask_t cpu_core_map[NR_CPUS] __read_mostly; | |
65 | EXPORT_SYMBOL(cpu_core_map); | |
66 | ||
cccf34e9 MC |
67 | /* |
68 | * A logcal cpu mask containing only one VPE per core to | |
69 | * reduce the number of IPIs on large MT systems. | |
70 | */ | |
71 | cpumask_t cpu_foreign_map __read_mostly; | |
72 | EXPORT_SYMBOL(cpu_foreign_map); | |
73 | ||
0ab7aefc RB |
74 | /* representing cpus for which sibling maps can be computed */ |
75 | static cpumask_t cpu_sibling_setup_map; | |
76 | ||
bda4584c HC |
77 | /* representing cpus for which core maps can be computed */ |
78 | static cpumask_t cpu_core_setup_map; | |
79 | ||
76306f42 PB |
80 | cpumask_t cpu_coherent_mask; |
81 | ||
0ab7aefc RB |
82 | static inline void set_cpu_sibling_map(int cpu) |
83 | { | |
84 | int i; | |
85 | ||
8dd92891 | 86 | cpumask_set_cpu(cpu, &cpu_sibling_setup_map); |
0ab7aefc RB |
87 | |
88 | if (smp_num_siblings > 1) { | |
8dd92891 | 89 | for_each_cpu(i, &cpu_sibling_setup_map) { |
bda4584c HC |
90 | if (cpu_data[cpu].package == cpu_data[i].package && |
91 | cpu_data[cpu].core == cpu_data[i].core) { | |
8dd92891 RR |
92 | cpumask_set_cpu(i, &cpu_sibling_map[cpu]); |
93 | cpumask_set_cpu(cpu, &cpu_sibling_map[i]); | |
0ab7aefc RB |
94 | } |
95 | } | |
96 | } else | |
8dd92891 | 97 | cpumask_set_cpu(cpu, &cpu_sibling_map[cpu]); |
0ab7aefc RB |
98 | } |
99 | ||
bda4584c HC |
100 | static inline void set_cpu_core_map(int cpu) |
101 | { | |
102 | int i; | |
103 | ||
8dd92891 | 104 | cpumask_set_cpu(cpu, &cpu_core_setup_map); |
bda4584c | 105 | |
8dd92891 | 106 | for_each_cpu(i, &cpu_core_setup_map) { |
bda4584c | 107 | if (cpu_data[cpu].package == cpu_data[i].package) { |
8dd92891 RR |
108 | cpumask_set_cpu(i, &cpu_core_map[cpu]); |
109 | cpumask_set_cpu(cpu, &cpu_core_map[i]); | |
bda4584c HC |
110 | } |
111 | } | |
112 | } | |
113 | ||
cccf34e9 MC |
114 | /* |
115 | * Calculate a new cpu_foreign_map mask whenever a | |
116 | * new cpu appears or disappears. | |
117 | */ | |
118 | static inline void calculate_cpu_foreign_map(void) | |
119 | { | |
120 | int i, k, core_present; | |
121 | cpumask_t temp_foreign_map; | |
122 | ||
123 | /* Re-calculate the mask */ | |
124 | for_each_online_cpu(i) { | |
125 | core_present = 0; | |
126 | for_each_cpu(k, &temp_foreign_map) | |
127 | if (cpu_data[i].package == cpu_data[k].package && | |
128 | cpu_data[i].core == cpu_data[k].core) | |
129 | core_present = 1; | |
130 | if (!core_present) | |
131 | cpumask_set_cpu(i, &temp_foreign_map); | |
132 | } | |
133 | ||
134 | cpumask_copy(&cpu_foreign_map, &temp_foreign_map); | |
135 | } | |
136 | ||
87353d8a | 137 | struct plat_smp_ops *mp_ops; |
82d45de6 | 138 | EXPORT_SYMBOL(mp_ops); |
87353d8a | 139 | |
078a55fc | 140 | void register_smp_ops(struct plat_smp_ops *ops) |
87353d8a | 141 | { |
83738e30 TS |
142 | if (mp_ops) |
143 | printk(KERN_WARNING "Overriding previously set SMP ops\n"); | |
87353d8a RB |
144 | |
145 | mp_ops = ops; | |
146 | } | |
147 | ||
1da177e4 LT |
148 | /* |
149 | * First C code run on the secondary CPUs after being started up by | |
150 | * the master. | |
151 | */ | |
078a55fc | 152 | asmlinkage void start_secondary(void) |
1da177e4 | 153 | { |
5bfb5d69 | 154 | unsigned int cpu; |
1da177e4 LT |
155 | |
156 | cpu_probe(); | |
6650df3c | 157 | per_cpu_trap_init(false); |
7bcf7717 | 158 | mips_clockevent_init(); |
87353d8a | 159 | mp_ops->init_secondary(); |
c7754e75 | 160 | cpu_report(); |
e060f6ed | 161 | maar_init(); |
1da177e4 LT |
162 | |
163 | /* | |
164 | * XXX parity protection should be folded in here when it's converted | |
165 | * to an option instead of something based on .cputype | |
166 | */ | |
167 | ||
168 | calibrate_delay(); | |
5bfb5d69 NP |
169 | preempt_disable(); |
170 | cpu = smp_processor_id(); | |
1da177e4 LT |
171 | cpu_data[cpu].udelay_val = loops_per_jiffy; |
172 | ||
8dd92891 | 173 | cpumask_set_cpu(cpu, &cpu_coherent_mask); |
e545a614 MS |
174 | notify_cpu_starting(cpu); |
175 | ||
b9a09a06 YZ |
176 | set_cpu_online(cpu, true); |
177 | ||
0ab7aefc | 178 | set_cpu_sibling_map(cpu); |
bda4584c | 179 | set_cpu_core_map(cpu); |
1da177e4 | 180 | |
cccf34e9 MC |
181 | calculate_cpu_foreign_map(); |
182 | ||
8dd92891 | 183 | cpumask_set_cpu(cpu, &cpu_callin_map); |
1da177e4 | 184 | |
cf9bfe55 | 185 | synchronise_count_slave(cpu); |
39b8d525 | 186 | |
b789ad63 YZ |
187 | /* |
188 | * irq will be enabled in ->smp_finish(), enabling it too early | |
189 | * is dangerous. | |
190 | */ | |
191 | WARN_ON_ONCE(!irqs_disabled()); | |
5309bdac YZ |
192 | mp_ops->smp_finish(); |
193 | ||
cdbedc61 | 194 | cpu_startup_entry(CPUHP_ONLINE); |
1da177e4 LT |
195 | } |
196 | ||
1da177e4 LT |
197 | static void stop_this_cpu(void *dummy) |
198 | { | |
199 | /* | |
cccf34e9 MC |
200 | * Remove this CPU. Be a bit slow here and |
201 | * set the bits for every online CPU so we don't miss | |
202 | * any IPI whilst taking this VPE down. | |
1da177e4 | 203 | */ |
cccf34e9 MC |
204 | |
205 | cpumask_copy(&cpu_foreign_map, cpu_online_mask); | |
206 | ||
207 | /* Make it visible to every other CPU */ | |
208 | smp_mb(); | |
209 | ||
0b5f9c00 | 210 | set_cpu_online(smp_processor_id(), false); |
cccf34e9 | 211 | calculate_cpu_foreign_map(); |
ea925a72 AB |
212 | local_irq_disable(); |
213 | while (1); | |
1da177e4 LT |
214 | } |
215 | ||
216 | void smp_send_stop(void) | |
217 | { | |
8691e5a8 | 218 | smp_call_function(stop_this_cpu, NULL, 0); |
1da177e4 LT |
219 | } |
220 | ||
221 | void __init smp_cpus_done(unsigned int max_cpus) | |
222 | { | |
1da177e4 LT |
223 | } |
224 | ||
225 | /* called from main before smp_init() */ | |
226 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
227 | { | |
1da177e4 LT |
228 | init_new_context(current, &init_mm); |
229 | current_thread_info()->cpu = 0; | |
87353d8a | 230 | mp_ops->prepare_cpus(max_cpus); |
0ab7aefc | 231 | set_cpu_sibling_map(0); |
bda4584c | 232 | set_cpu_core_map(0); |
cccf34e9 | 233 | calculate_cpu_foreign_map(); |
320e6aba | 234 | #ifndef CONFIG_HOTPLUG_CPU |
0b5f9c00 | 235 | init_cpu_present(cpu_possible_mask); |
320e6aba | 236 | #endif |
76306f42 | 237 | cpumask_copy(&cpu_coherent_mask, cpu_possible_mask); |
1da177e4 LT |
238 | } |
239 | ||
240 | /* preload SMP state for boot cpu */ | |
28eb0e46 | 241 | void smp_prepare_boot_cpu(void) |
1da177e4 | 242 | { |
4037ac6e RR |
243 | set_cpu_possible(0, true); |
244 | set_cpu_online(0, true); | |
8dd92891 | 245 | cpumask_set_cpu(0, &cpu_callin_map); |
1da177e4 LT |
246 | } |
247 | ||
078a55fc | 248 | int __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 249 | { |
360014a3 | 250 | mp_ops->boot_secondary(cpu, tidle); |
1da177e4 | 251 | |
b727a602 RB |
252 | /* |
253 | * Trust is futile. We should really have timeouts ... | |
254 | */ | |
cafb45b2 | 255 | while (!cpumask_test_cpu(cpu, &cpu_callin_map)) { |
1da177e4 | 256 | udelay(100); |
cafb45b2 RB |
257 | schedule(); |
258 | } | |
1da177e4 | 259 | |
cf9bfe55 | 260 | synchronise_count_master(cpu); |
1da177e4 LT |
261 | return 0; |
262 | } | |
263 | ||
1da177e4 LT |
264 | /* Not really SMP stuff ... */ |
265 | int setup_profiling_timer(unsigned int multiplier) | |
266 | { | |
267 | return 0; | |
268 | } | |
269 | ||
270 | static void flush_tlb_all_ipi(void *info) | |
271 | { | |
272 | local_flush_tlb_all(); | |
273 | } | |
274 | ||
275 | void flush_tlb_all(void) | |
276 | { | |
15c8b6c1 | 277 | on_each_cpu(flush_tlb_all_ipi, NULL, 1); |
1da177e4 LT |
278 | } |
279 | ||
280 | static void flush_tlb_mm_ipi(void *mm) | |
281 | { | |
282 | local_flush_tlb_mm((struct mm_struct *)mm); | |
283 | } | |
284 | ||
25969354 RB |
285 | /* |
286 | * Special Variant of smp_call_function for use by TLB functions: | |
287 | * | |
288 | * o No return value | |
289 | * o collapses to normal function call on UP kernels | |
290 | * o collapses to normal function call on systems with a single shared | |
291 | * primary cache. | |
25969354 RB |
292 | */ |
293 | static inline void smp_on_other_tlbs(void (*func) (void *info), void *info) | |
294 | { | |
8691e5a8 | 295 | smp_call_function(func, info, 1); |
25969354 RB |
296 | } |
297 | ||
298 | static inline void smp_on_each_tlb(void (*func) (void *info), void *info) | |
299 | { | |
300 | preempt_disable(); | |
301 | ||
302 | smp_on_other_tlbs(func, info); | |
303 | func(info); | |
304 | ||
305 | preempt_enable(); | |
306 | } | |
307 | ||
1da177e4 LT |
308 | /* |
309 | * The following tlb flush calls are invoked when old translations are | |
310 | * being torn down, or pte attributes are changing. For single threaded | |
311 | * address spaces, a new context is obtained on the current cpu, and tlb | |
312 | * context on other cpus are invalidated to force a new context allocation | |
313 | * at switch_mm time, should the mm ever be used on other cpus. For | |
314 | * multithreaded address spaces, intercpu interrupts have to be sent. | |
315 | * Another case where intercpu interrupts are required is when the target | |
316 | * mm might be active on another cpu (eg debuggers doing the flushes on | |
317 | * behalf of debugees, kswapd stealing pages from another process etc). | |
318 | * Kanoj 07/00. | |
319 | */ | |
320 | ||
321 | void flush_tlb_mm(struct mm_struct *mm) | |
322 | { | |
323 | preempt_disable(); | |
324 | ||
325 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
c50cade9 | 326 | smp_on_other_tlbs(flush_tlb_mm_ipi, mm); |
1da177e4 | 327 | } else { |
b5eb5511 RB |
328 | unsigned int cpu; |
329 | ||
0b5f9c00 RR |
330 | for_each_online_cpu(cpu) { |
331 | if (cpu != smp_processor_id() && cpu_context(cpu, mm)) | |
b5eb5511 | 332 | cpu_context(cpu, mm) = 0; |
0b5f9c00 | 333 | } |
1da177e4 LT |
334 | } |
335 | local_flush_tlb_mm(mm); | |
336 | ||
337 | preempt_enable(); | |
338 | } | |
339 | ||
340 | struct flush_tlb_data { | |
341 | struct vm_area_struct *vma; | |
342 | unsigned long addr1; | |
343 | unsigned long addr2; | |
344 | }; | |
345 | ||
346 | static void flush_tlb_range_ipi(void *info) | |
347 | { | |
c50cade9 | 348 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
349 | |
350 | local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2); | |
351 | } | |
352 | ||
353 | void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) | |
354 | { | |
355 | struct mm_struct *mm = vma->vm_mm; | |
356 | ||
357 | preempt_disable(); | |
358 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
89a8a5a6 RB |
359 | struct flush_tlb_data fd = { |
360 | .vma = vma, | |
361 | .addr1 = start, | |
362 | .addr2 = end, | |
363 | }; | |
1da177e4 | 364 | |
c50cade9 | 365 | smp_on_other_tlbs(flush_tlb_range_ipi, &fd); |
1da177e4 | 366 | } else { |
b5eb5511 RB |
367 | unsigned int cpu; |
368 | ||
0b5f9c00 RR |
369 | for_each_online_cpu(cpu) { |
370 | if (cpu != smp_processor_id() && cpu_context(cpu, mm)) | |
b5eb5511 | 371 | cpu_context(cpu, mm) = 0; |
0b5f9c00 | 372 | } |
1da177e4 LT |
373 | } |
374 | local_flush_tlb_range(vma, start, end); | |
375 | preempt_enable(); | |
376 | } | |
377 | ||
378 | static void flush_tlb_kernel_range_ipi(void *info) | |
379 | { | |
c50cade9 | 380 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
381 | |
382 | local_flush_tlb_kernel_range(fd->addr1, fd->addr2); | |
383 | } | |
384 | ||
385 | void flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
386 | { | |
89a8a5a6 RB |
387 | struct flush_tlb_data fd = { |
388 | .addr1 = start, | |
389 | .addr2 = end, | |
390 | }; | |
1da177e4 | 391 | |
15c8b6c1 | 392 | on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1); |
1da177e4 LT |
393 | } |
394 | ||
395 | static void flush_tlb_page_ipi(void *info) | |
396 | { | |
c50cade9 | 397 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
398 | |
399 | local_flush_tlb_page(fd->vma, fd->addr1); | |
400 | } | |
401 | ||
402 | void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) | |
403 | { | |
404 | preempt_disable(); | |
405 | if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) { | |
89a8a5a6 RB |
406 | struct flush_tlb_data fd = { |
407 | .vma = vma, | |
408 | .addr1 = page, | |
409 | }; | |
1da177e4 | 410 | |
c50cade9 | 411 | smp_on_other_tlbs(flush_tlb_page_ipi, &fd); |
1da177e4 | 412 | } else { |
b5eb5511 RB |
413 | unsigned int cpu; |
414 | ||
0b5f9c00 RR |
415 | for_each_online_cpu(cpu) { |
416 | if (cpu != smp_processor_id() && cpu_context(cpu, vma->vm_mm)) | |
b5eb5511 | 417 | cpu_context(cpu, vma->vm_mm) = 0; |
0b5f9c00 | 418 | } |
1da177e4 LT |
419 | } |
420 | local_flush_tlb_page(vma, page); | |
421 | preempt_enable(); | |
422 | } | |
423 | ||
424 | static void flush_tlb_one_ipi(void *info) | |
425 | { | |
426 | unsigned long vaddr = (unsigned long) info; | |
427 | ||
428 | local_flush_tlb_one(vaddr); | |
429 | } | |
430 | ||
431 | void flush_tlb_one(unsigned long vaddr) | |
432 | { | |
25969354 | 433 | smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr); |
1da177e4 LT |
434 | } |
435 | ||
436 | EXPORT_SYMBOL(flush_tlb_page); | |
437 | EXPORT_SYMBOL(flush_tlb_one); | |
7aa1c8f4 RB |
438 | |
439 | #if defined(CONFIG_KEXEC) | |
440 | void (*dump_ipi_function_ptr)(void *) = NULL; | |
441 | void dump_send_ipi(void (*dump_ipi_callback)(void *)) | |
442 | { | |
443 | int i; | |
444 | int cpu = smp_processor_id(); | |
445 | ||
446 | dump_ipi_function_ptr = dump_ipi_callback; | |
447 | smp_mb(); | |
448 | for_each_online_cpu(i) | |
449 | if (i != cpu) | |
450 | mp_ops->send_ipi_single(i, SMP_DUMP); | |
451 | ||
452 | } | |
453 | EXPORT_SYMBOL(dump_send_ipi); | |
454 | #endif | |
cc7964af PB |
455 | |
456 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST | |
457 | ||
458 | static DEFINE_PER_CPU(atomic_t, tick_broadcast_count); | |
459 | static DEFINE_PER_CPU(struct call_single_data, tick_broadcast_csd); | |
460 | ||
461 | void tick_broadcast(const struct cpumask *mask) | |
462 | { | |
463 | atomic_t *count; | |
464 | struct call_single_data *csd; | |
465 | int cpu; | |
466 | ||
467 | for_each_cpu(cpu, mask) { | |
468 | count = &per_cpu(tick_broadcast_count, cpu); | |
469 | csd = &per_cpu(tick_broadcast_csd, cpu); | |
470 | ||
471 | if (atomic_inc_return(count) == 1) | |
472 | smp_call_function_single_async(cpu, csd); | |
473 | } | |
474 | } | |
475 | ||
476 | static void tick_broadcast_callee(void *info) | |
477 | { | |
478 | int cpu = smp_processor_id(); | |
479 | tick_receive_broadcast(); | |
480 | atomic_set(&per_cpu(tick_broadcast_count, cpu), 0); | |
481 | } | |
482 | ||
483 | static int __init tick_broadcast_init(void) | |
484 | { | |
485 | struct call_single_data *csd; | |
486 | int cpu; | |
487 | ||
488 | for (cpu = 0; cpu < NR_CPUS; cpu++) { | |
489 | csd = &per_cpu(tick_broadcast_csd, cpu); | |
490 | csd->func = tick_broadcast_callee; | |
491 | } | |
492 | ||
493 | return 0; | |
494 | } | |
495 | early_initcall(tick_broadcast_init); | |
496 | ||
497 | #endif /* CONFIG_GENERIC_CLOCKEVENTS_BROADCAST */ |