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1da177e4 LT |
1 | /* |
2 | * This program is free software; you can redistribute it and/or | |
3 | * modify it under the terms of the GNU General Public License | |
4 | * as published by the Free Software Foundation; either version 2 | |
5 | * of the License, or (at your option) any later version. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | * | |
12 | * You should have received a copy of the GNU General Public License | |
13 | * along with this program; if not, write to the Free Software | |
14 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
15 | * | |
16 | * Copyright (C) 2000, 2001 Kanoj Sarcar | |
17 | * Copyright (C) 2000, 2001 Ralf Baechle | |
18 | * Copyright (C) 2000, 2001 Silicon Graphics, Inc. | |
19 | * Copyright (C) 2000, 2001, 2003 Broadcom Corporation | |
20 | */ | |
21 | #include <linux/cache.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/interrupt.h> | |
631330f5 | 25 | #include <linux/smp.h> |
1da177e4 LT |
26 | #include <linux/spinlock.h> |
27 | #include <linux/threads.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/time.h> | |
30 | #include <linux/timex.h> | |
31 | #include <linux/sched.h> | |
32 | #include <linux/cpumask.h> | |
1e35aaba | 33 | #include <linux/cpu.h> |
4e950f6f | 34 | #include <linux/err.h> |
1da177e4 LT |
35 | |
36 | #include <asm/atomic.h> | |
37 | #include <asm/cpu.h> | |
38 | #include <asm/processor.h> | |
39b8d525 | 39 | #include <asm/r4k-timer.h> |
1da177e4 LT |
40 | #include <asm/system.h> |
41 | #include <asm/mmu_context.h> | |
7bcf7717 | 42 | #include <asm/time.h> |
1da177e4 | 43 | |
41c594ab RB |
44 | #ifdef CONFIG_MIPS_MT_SMTC |
45 | #include <asm/mipsmtregs.h> | |
46 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
47 | ||
1b2bc75c | 48 | volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */ |
1da177e4 LT |
49 | int __cpu_number_map[NR_CPUS]; /* Map physical to logical */ |
50 | int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */ | |
51 | ||
0ab7aefc RB |
52 | /* Number of TCs (or siblings in Intel speak) per CPU core */ |
53 | int smp_num_siblings = 1; | |
54 | EXPORT_SYMBOL(smp_num_siblings); | |
55 | ||
56 | /* representing the TCs (or siblings in Intel speak) of each logical CPU */ | |
57 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; | |
58 | EXPORT_SYMBOL(cpu_sibling_map); | |
59 | ||
60 | /* representing cpus for which sibling maps can be computed */ | |
61 | static cpumask_t cpu_sibling_setup_map; | |
62 | ||
63 | static inline void set_cpu_sibling_map(int cpu) | |
64 | { | |
65 | int i; | |
66 | ||
67 | cpu_set(cpu, cpu_sibling_setup_map); | |
68 | ||
69 | if (smp_num_siblings > 1) { | |
70 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
71 | if (cpu_data[cpu].core == cpu_data[i].core) { | |
72 | cpu_set(i, cpu_sibling_map[cpu]); | |
73 | cpu_set(cpu, cpu_sibling_map[i]); | |
74 | } | |
75 | } | |
76 | } else | |
77 | cpu_set(cpu, cpu_sibling_map[cpu]); | |
78 | } | |
79 | ||
87353d8a RB |
80 | struct plat_smp_ops *mp_ops; |
81 | ||
82 | __cpuinit void register_smp_ops(struct plat_smp_ops *ops) | |
83 | { | |
83738e30 TS |
84 | if (mp_ops) |
85 | printk(KERN_WARNING "Overriding previously set SMP ops\n"); | |
87353d8a RB |
86 | |
87 | mp_ops = ops; | |
88 | } | |
89 | ||
1da177e4 LT |
90 | /* |
91 | * First C code run on the secondary CPUs after being started up by | |
92 | * the master. | |
93 | */ | |
4ebd5233 | 94 | asmlinkage __cpuinit void start_secondary(void) |
1da177e4 | 95 | { |
5bfb5d69 | 96 | unsigned int cpu; |
1da177e4 | 97 | |
41c594ab RB |
98 | #ifdef CONFIG_MIPS_MT_SMTC |
99 | /* Only do cpu_probe for first TC of CPU */ | |
100 | if ((read_c0_tcbind() & TCBIND_CURTC) == 0) | |
101 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
102 | cpu_probe(); |
103 | cpu_report(); | |
104 | per_cpu_trap_init(); | |
7bcf7717 | 105 | mips_clockevent_init(); |
87353d8a | 106 | mp_ops->init_secondary(); |
1da177e4 LT |
107 | |
108 | /* | |
109 | * XXX parity protection should be folded in here when it's converted | |
110 | * to an option instead of something based on .cputype | |
111 | */ | |
112 | ||
113 | calibrate_delay(); | |
5bfb5d69 NP |
114 | preempt_disable(); |
115 | cpu = smp_processor_id(); | |
1da177e4 LT |
116 | cpu_data[cpu].udelay_val = loops_per_jiffy; |
117 | ||
e545a614 MS |
118 | notify_cpu_starting(cpu); |
119 | ||
87353d8a | 120 | mp_ops->smp_finish(); |
0ab7aefc | 121 | set_cpu_sibling_map(cpu); |
1da177e4 LT |
122 | |
123 | cpu_set(cpu, cpu_callin_map); | |
124 | ||
39b8d525 RB |
125 | synchronise_count_slave(); |
126 | ||
1da177e4 LT |
127 | cpu_idle(); |
128 | } | |
129 | ||
48a048fe | 130 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
1da177e4 | 131 | { |
87353d8a | 132 | mp_ops->send_ipi_mask(mask, SMP_CALL_FUNCTION); |
1da177e4 LT |
133 | } |
134 | ||
2f304c0a JA |
135 | /* |
136 | * We reuse the same vector for the single IPI | |
137 | */ | |
138 | void arch_send_call_function_single_ipi(int cpu) | |
bd6aeeff | 139 | { |
b533e652 | 140 | mp_ops->send_ipi_mask(&cpumask_of_cpu(cpu), SMP_CALL_FUNCTION); |
bd6aeeff | 141 | } |
41c594ab | 142 | |
2f304c0a JA |
143 | /* |
144 | * Call into both interrupt handlers, as we share the IPI for them | |
145 | */ | |
1da177e4 LT |
146 | void smp_call_function_interrupt(void) |
147 | { | |
1da177e4 | 148 | irq_enter(); |
2f304c0a JA |
149 | generic_smp_call_function_single_interrupt(); |
150 | generic_smp_call_function_interrupt(); | |
1da177e4 | 151 | irq_exit(); |
b4b2917c PW |
152 | } |
153 | ||
1da177e4 LT |
154 | static void stop_this_cpu(void *dummy) |
155 | { | |
156 | /* | |
157 | * Remove this CPU: | |
158 | */ | |
159 | cpu_clear(smp_processor_id(), cpu_online_map); | |
7920c4d6 RB |
160 | for (;;) { |
161 | if (cpu_wait) | |
162 | (*cpu_wait)(); /* Wait if available. */ | |
163 | } | |
1da177e4 LT |
164 | } |
165 | ||
166 | void smp_send_stop(void) | |
167 | { | |
8691e5a8 | 168 | smp_call_function(stop_this_cpu, NULL, 0); |
1da177e4 LT |
169 | } |
170 | ||
171 | void __init smp_cpus_done(unsigned int max_cpus) | |
172 | { | |
87353d8a | 173 | mp_ops->cpus_done(); |
39b8d525 | 174 | synchronise_count_master(); |
1da177e4 LT |
175 | } |
176 | ||
177 | /* called from main before smp_init() */ | |
178 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
179 | { | |
1da177e4 LT |
180 | init_new_context(current, &init_mm); |
181 | current_thread_info()->cpu = 0; | |
87353d8a | 182 | mp_ops->prepare_cpus(max_cpus); |
0ab7aefc | 183 | set_cpu_sibling_map(0); |
320e6aba | 184 | #ifndef CONFIG_HOTPLUG_CPU |
4037ac6e | 185 | init_cpu_present(&cpu_possible_map); |
320e6aba | 186 | #endif |
1da177e4 LT |
187 | } |
188 | ||
189 | /* preload SMP state for boot cpu */ | |
190 | void __devinit smp_prepare_boot_cpu(void) | |
191 | { | |
4037ac6e RR |
192 | set_cpu_possible(0, true); |
193 | set_cpu_online(0, true); | |
1da177e4 LT |
194 | cpu_set(0, cpu_callin_map); |
195 | } | |
196 | ||
197 | /* | |
b727a602 RB |
198 | * Called once for each "cpu_possible(cpu)". Needs to spin up the cpu |
199 | * and keep control until "cpu_online(cpu)" is set. Note: cpu is | |
200 | * physical, not logical. | |
1da177e4 | 201 | */ |
1b2bc75c RB |
202 | static struct task_struct *cpu_idle_thread[NR_CPUS]; |
203 | ||
b282b6f8 | 204 | int __cpuinit __cpu_up(unsigned int cpu) |
1da177e4 LT |
205 | { |
206 | struct task_struct *idle; | |
207 | ||
208 | /* | |
b727a602 | 209 | * Processor goes to start_secondary(), sets online flag |
1da177e4 LT |
210 | * The following code is purely to make sure |
211 | * Linux can schedule processes on this slave. | |
212 | */ | |
1b2bc75c RB |
213 | if (!cpu_idle_thread[cpu]) { |
214 | idle = fork_idle(cpu); | |
215 | cpu_idle_thread[cpu] = idle; | |
216 | ||
217 | if (IS_ERR(idle)) | |
218 | panic(KERN_ERR "Fork failed for CPU %d", cpu); | |
219 | } else { | |
220 | idle = cpu_idle_thread[cpu]; | |
221 | init_idle(idle, cpu); | |
222 | } | |
1da177e4 | 223 | |
87353d8a | 224 | mp_ops->boot_secondary(cpu, idle); |
1da177e4 | 225 | |
b727a602 RB |
226 | /* |
227 | * Trust is futile. We should really have timeouts ... | |
228 | */ | |
1da177e4 LT |
229 | while (!cpu_isset(cpu, cpu_callin_map)) |
230 | udelay(100); | |
231 | ||
232 | cpu_set(cpu, cpu_online_map); | |
233 | ||
234 | return 0; | |
235 | } | |
236 | ||
1da177e4 LT |
237 | /* Not really SMP stuff ... */ |
238 | int setup_profiling_timer(unsigned int multiplier) | |
239 | { | |
240 | return 0; | |
241 | } | |
242 | ||
243 | static void flush_tlb_all_ipi(void *info) | |
244 | { | |
245 | local_flush_tlb_all(); | |
246 | } | |
247 | ||
248 | void flush_tlb_all(void) | |
249 | { | |
15c8b6c1 | 250 | on_each_cpu(flush_tlb_all_ipi, NULL, 1); |
1da177e4 LT |
251 | } |
252 | ||
253 | static void flush_tlb_mm_ipi(void *mm) | |
254 | { | |
255 | local_flush_tlb_mm((struct mm_struct *)mm); | |
256 | } | |
257 | ||
25969354 RB |
258 | /* |
259 | * Special Variant of smp_call_function for use by TLB functions: | |
260 | * | |
261 | * o No return value | |
262 | * o collapses to normal function call on UP kernels | |
263 | * o collapses to normal function call on systems with a single shared | |
264 | * primary cache. | |
265 | * o CONFIG_MIPS_MT_SMTC currently implies there is only one physical core. | |
266 | */ | |
267 | static inline void smp_on_other_tlbs(void (*func) (void *info), void *info) | |
268 | { | |
269 | #ifndef CONFIG_MIPS_MT_SMTC | |
8691e5a8 | 270 | smp_call_function(func, info, 1); |
25969354 RB |
271 | #endif |
272 | } | |
273 | ||
274 | static inline void smp_on_each_tlb(void (*func) (void *info), void *info) | |
275 | { | |
276 | preempt_disable(); | |
277 | ||
278 | smp_on_other_tlbs(func, info); | |
279 | func(info); | |
280 | ||
281 | preempt_enable(); | |
282 | } | |
283 | ||
1da177e4 LT |
284 | /* |
285 | * The following tlb flush calls are invoked when old translations are | |
286 | * being torn down, or pte attributes are changing. For single threaded | |
287 | * address spaces, a new context is obtained on the current cpu, and tlb | |
288 | * context on other cpus are invalidated to force a new context allocation | |
289 | * at switch_mm time, should the mm ever be used on other cpus. For | |
290 | * multithreaded address spaces, intercpu interrupts have to be sent. | |
291 | * Another case where intercpu interrupts are required is when the target | |
292 | * mm might be active on another cpu (eg debuggers doing the flushes on | |
293 | * behalf of debugees, kswapd stealing pages from another process etc). | |
294 | * Kanoj 07/00. | |
295 | */ | |
296 | ||
297 | void flush_tlb_mm(struct mm_struct *mm) | |
298 | { | |
299 | preempt_disable(); | |
300 | ||
301 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
c50cade9 | 302 | smp_on_other_tlbs(flush_tlb_mm_ipi, mm); |
1da177e4 | 303 | } else { |
b5eb5511 RB |
304 | cpumask_t mask = cpu_online_map; |
305 | unsigned int cpu; | |
306 | ||
307 | cpu_clear(smp_processor_id(), mask); | |
ece8a9e4 | 308 | for_each_cpu_mask(cpu, mask) |
b5eb5511 RB |
309 | if (cpu_context(cpu, mm)) |
310 | cpu_context(cpu, mm) = 0; | |
1da177e4 LT |
311 | } |
312 | local_flush_tlb_mm(mm); | |
313 | ||
314 | preempt_enable(); | |
315 | } | |
316 | ||
317 | struct flush_tlb_data { | |
318 | struct vm_area_struct *vma; | |
319 | unsigned long addr1; | |
320 | unsigned long addr2; | |
321 | }; | |
322 | ||
323 | static void flush_tlb_range_ipi(void *info) | |
324 | { | |
c50cade9 | 325 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
326 | |
327 | local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2); | |
328 | } | |
329 | ||
330 | void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) | |
331 | { | |
332 | struct mm_struct *mm = vma->vm_mm; | |
333 | ||
334 | preempt_disable(); | |
335 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
89a8a5a6 RB |
336 | struct flush_tlb_data fd = { |
337 | .vma = vma, | |
338 | .addr1 = start, | |
339 | .addr2 = end, | |
340 | }; | |
1da177e4 | 341 | |
c50cade9 | 342 | smp_on_other_tlbs(flush_tlb_range_ipi, &fd); |
1da177e4 | 343 | } else { |
b5eb5511 RB |
344 | cpumask_t mask = cpu_online_map; |
345 | unsigned int cpu; | |
346 | ||
347 | cpu_clear(smp_processor_id(), mask); | |
ece8a9e4 | 348 | for_each_cpu_mask(cpu, mask) |
b5eb5511 RB |
349 | if (cpu_context(cpu, mm)) |
350 | cpu_context(cpu, mm) = 0; | |
1da177e4 LT |
351 | } |
352 | local_flush_tlb_range(vma, start, end); | |
353 | preempt_enable(); | |
354 | } | |
355 | ||
356 | static void flush_tlb_kernel_range_ipi(void *info) | |
357 | { | |
c50cade9 | 358 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
359 | |
360 | local_flush_tlb_kernel_range(fd->addr1, fd->addr2); | |
361 | } | |
362 | ||
363 | void flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
364 | { | |
89a8a5a6 RB |
365 | struct flush_tlb_data fd = { |
366 | .addr1 = start, | |
367 | .addr2 = end, | |
368 | }; | |
1da177e4 | 369 | |
15c8b6c1 | 370 | on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1); |
1da177e4 LT |
371 | } |
372 | ||
373 | static void flush_tlb_page_ipi(void *info) | |
374 | { | |
c50cade9 | 375 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
376 | |
377 | local_flush_tlb_page(fd->vma, fd->addr1); | |
378 | } | |
379 | ||
380 | void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) | |
381 | { | |
382 | preempt_disable(); | |
383 | if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) { | |
89a8a5a6 RB |
384 | struct flush_tlb_data fd = { |
385 | .vma = vma, | |
386 | .addr1 = page, | |
387 | }; | |
1da177e4 | 388 | |
c50cade9 | 389 | smp_on_other_tlbs(flush_tlb_page_ipi, &fd); |
1da177e4 | 390 | } else { |
b5eb5511 RB |
391 | cpumask_t mask = cpu_online_map; |
392 | unsigned int cpu; | |
393 | ||
394 | cpu_clear(smp_processor_id(), mask); | |
ece8a9e4 | 395 | for_each_cpu_mask(cpu, mask) |
b5eb5511 RB |
396 | if (cpu_context(cpu, vma->vm_mm)) |
397 | cpu_context(cpu, vma->vm_mm) = 0; | |
1da177e4 LT |
398 | } |
399 | local_flush_tlb_page(vma, page); | |
400 | preempt_enable(); | |
401 | } | |
402 | ||
403 | static void flush_tlb_one_ipi(void *info) | |
404 | { | |
405 | unsigned long vaddr = (unsigned long) info; | |
406 | ||
407 | local_flush_tlb_one(vaddr); | |
408 | } | |
409 | ||
410 | void flush_tlb_one(unsigned long vaddr) | |
411 | { | |
25969354 | 412 | smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr); |
1da177e4 LT |
413 | } |
414 | ||
415 | EXPORT_SYMBOL(flush_tlb_page); | |
416 | EXPORT_SYMBOL(flush_tlb_one); |