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340ee4b9 RB |
1 | /* |
2 | * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. | |
3 | * | |
4 | * Elizabeth Clarke (beth@mips.com) | |
5 | * | |
6 | * This program is free software; you can distribute it and/or modify it | |
7 | * under the terms of the GNU General Public License (Version 2) as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
13 | * for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along | |
16 | * with this program; if not, write to the Free Software Foundation, Inc., | |
17 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
18 | * | |
19 | */ | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/sched.h> | |
22 | #include <linux/cpumask.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/compiler.h> | |
25 | ||
26 | #include <asm/atomic.h> | |
27 | #include <asm/cpu.h> | |
28 | #include <asm/processor.h> | |
29 | #include <asm/system.h> | |
30 | #include <asm/hardirq.h> | |
31 | #include <asm/mmu_context.h> | |
32 | #include <asm/smp.h> | |
33 | #include <asm/time.h> | |
34 | #include <asm/mipsregs.h> | |
35 | #include <asm/mipsmtregs.h> | |
36 | #include <asm/cacheflush.h> | |
37 | #include <asm/mips-boards/maltaint.h> | |
38 | ||
39 | #define MIPS_CPU_IPI_RESCHED_IRQ 0 | |
40 | #define MIPS_CPU_IPI_CALL_IRQ 1 | |
41 | ||
42 | static int cpu_ipi_resched_irq, cpu_ipi_call_irq; | |
43 | ||
44 | #if 0 | |
45 | static void dump_mtregisters(int vpe, int tc) | |
46 | { | |
47 | printk("vpe %d tc %d\n", vpe, tc); | |
48 | ||
49 | settc(tc); | |
50 | ||
51 | printk(" c0 status 0x%lx\n", read_vpe_c0_status()); | |
52 | printk(" vpecontrol 0x%lx\n", read_vpe_c0_vpecontrol()); | |
53 | printk(" vpeconf0 0x%lx\n", read_vpe_c0_vpeconf0()); | |
54 | printk(" tcstatus 0x%lx\n", read_tc_c0_tcstatus()); | |
55 | printk(" tcrestart 0x%lx\n", read_tc_c0_tcrestart()); | |
56 | printk(" tcbind 0x%lx\n", read_tc_c0_tcbind()); | |
57 | printk(" tchalt 0x%lx\n", read_tc_c0_tchalt()); | |
58 | } | |
59 | #endif | |
60 | ||
61 | void __init sanitize_tlb_entries(void) | |
62 | { | |
63 | int i, tlbsiz; | |
64 | unsigned long mvpconf0, ncpu; | |
65 | ||
66 | if (!cpu_has_mipsmt) | |
67 | return; | |
68 | ||
69 | set_c0_mvpcontrol(MVPCONTROL_VPC); | |
70 | ||
fdc9bb16 RB |
71 | back_to_back_c0_hazard(); |
72 | ||
340ee4b9 RB |
73 | /* Disable TLB sharing */ |
74 | clear_c0_mvpcontrol(MVPCONTROL_STLB); | |
75 | ||
76 | mvpconf0 = read_c0_mvpconf0(); | |
77 | ||
78 | printk(KERN_INFO "MVPConf0 0x%lx TLBS %lx PTLBE %ld\n", mvpconf0, | |
79 | (mvpconf0 & MVPCONF0_TLBS) >> MVPCONF0_TLBS_SHIFT, | |
80 | (mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT); | |
81 | ||
82 | tlbsiz = (mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT; | |
83 | ncpu = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; | |
84 | ||
85 | printk(" tlbsiz %d ncpu %ld\n", tlbsiz, ncpu); | |
86 | ||
87 | if (tlbsiz > 0) { | |
88 | /* share them out across the vpe's */ | |
89 | tlbsiz /= ncpu; | |
90 | ||
91 | printk(KERN_INFO "setting Config1.MMU_size to %d\n", tlbsiz); | |
92 | ||
93 | for (i = 0; i < ncpu; i++) { | |
94 | settc(i); | |
95 | ||
96 | if (i == 0) | |
97 | write_c0_config1((read_c0_config1() & ~(0x3f << 25)) | (tlbsiz << 25)); | |
98 | else | |
99 | write_vpe_c0_config1((read_vpe_c0_config1() & ~(0x3f << 25)) | | |
100 | (tlbsiz << 25)); | |
101 | } | |
102 | } | |
103 | ||
104 | clear_c0_mvpcontrol(MVPCONTROL_VPC); | |
105 | } | |
106 | ||
340ee4b9 RB |
107 | static void ipi_resched_dispatch (struct pt_regs *regs) |
108 | { | |
109 | do_IRQ(MIPS_CPU_IPI_RESCHED_IRQ, regs); | |
110 | } | |
111 | ||
112 | static void ipi_call_dispatch (struct pt_regs *regs) | |
113 | { | |
114 | do_IRQ(MIPS_CPU_IPI_CALL_IRQ, regs); | |
115 | } | |
116 | ||
117 | irqreturn_t ipi_resched_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |
118 | { | |
119 | return IRQ_HANDLED; | |
120 | } | |
121 | ||
122 | irqreturn_t ipi_call_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |
123 | { | |
124 | smp_call_function_interrupt(); | |
125 | ||
126 | return IRQ_HANDLED; | |
127 | } | |
128 | ||
129 | static struct irqaction irq_resched = { | |
130 | .handler = ipi_resched_interrupt, | |
131 | .flags = SA_INTERRUPT, | |
132 | .name = "IPI_resched" | |
133 | }; | |
134 | ||
135 | static struct irqaction irq_call = { | |
136 | .handler = ipi_call_interrupt, | |
137 | .flags = SA_INTERRUPT, | |
138 | .name = "IPI_call" | |
139 | }; | |
140 | ||
141 | /* | |
142 | * Common setup before any secondaries are started | |
143 | * Make sure all CPU's are in a sensible state before we boot any of the | |
144 | * secondarys | |
145 | */ | |
9b6695a8 | 146 | void plat_smp_setup(void) |
340ee4b9 RB |
147 | { |
148 | unsigned long val; | |
149 | int i, num; | |
150 | ||
151 | if (!cpu_has_mipsmt) | |
152 | return; | |
153 | ||
154 | /* disable MT so we can configure */ | |
155 | dvpe(); | |
156 | dmt(); | |
157 | ||
158 | /* Put MVPE's into 'configuration state' */ | |
159 | set_c0_mvpcontrol(MVPCONTROL_VPC); | |
160 | ||
161 | val = read_c0_mvpconf0(); | |
162 | ||
163 | /* we'll always have more TC's than VPE's, so loop setting everything | |
164 | to a sensible state */ | |
165 | for (i = 0, num = 0; i <= ((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT); i++) { | |
166 | settc(i); | |
167 | ||
168 | /* VPE's */ | |
169 | if (i <= ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)) { | |
170 | ||
171 | /* deactivate all but vpe0 */ | |
172 | if (i != 0) { | |
173 | unsigned long tmp = read_vpe_c0_vpeconf0(); | |
174 | ||
175 | tmp &= ~VPECONF0_VPA; | |
176 | ||
177 | /* master VPE */ | |
178 | tmp |= VPECONF0_MVP; | |
179 | write_vpe_c0_vpeconf0(tmp); | |
180 | ||
181 | /* Record this as available CPU */ | |
9b6695a8 RB |
182 | cpu_set(i, phys_cpu_present_map); |
183 | __cpu_number_map[i] = ++num; | |
184 | __cpu_logical_map[num] = i; | |
340ee4b9 RB |
185 | } |
186 | ||
187 | /* disable multi-threading with TC's */ | |
188 | write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE); | |
189 | ||
190 | if (i != 0) { | |
191 | write_vpe_c0_status((read_c0_status() & ~(ST0_IM | ST0_IE | ST0_KSU)) | ST0_CU0); | |
192 | write_vpe_c0_cause(read_vpe_c0_cause() & ~CAUSEF_IP); | |
193 | ||
194 | /* set config to be the same as vpe0, particularly kseg0 coherency alg */ | |
195 | write_vpe_c0_config( read_c0_config()); | |
74a96d94 RB |
196 | |
197 | /* Propagate Config7 */ | |
198 | write_vpe_c0_config7(read_c0_config7()); | |
340ee4b9 RB |
199 | } |
200 | ||
201 | } | |
202 | ||
203 | /* TC's */ | |
204 | ||
205 | if (i != 0) { | |
206 | unsigned long tmp; | |
207 | ||
208 | /* bind a TC to each VPE, May as well put all excess TC's | |
209 | on the last VPE */ | |
210 | if ( i >= (((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1) ) | |
211 | write_tc_c0_tcbind(read_tc_c0_tcbind() | ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) ); | |
212 | else { | |
213 | write_tc_c0_tcbind( read_tc_c0_tcbind() | i); | |
214 | ||
215 | /* and set XTC */ | |
216 | write_vpe_c0_vpeconf0( read_vpe_c0_vpeconf0() | (i << VPECONF0_XTC_SHIFT)); | |
217 | } | |
218 | ||
219 | tmp = read_tc_c0_tcstatus(); | |
220 | ||
221 | /* mark not allocated and not dynamically allocatable */ | |
222 | tmp &= ~(TCSTATUS_A | TCSTATUS_DA); | |
223 | tmp |= TCSTATUS_IXMT; /* interrupt exempt */ | |
224 | write_tc_c0_tcstatus(tmp); | |
225 | ||
226 | write_tc_c0_tchalt(TCHALT_H); | |
227 | } | |
228 | } | |
229 | ||
230 | /* Release config state */ | |
231 | clear_c0_mvpcontrol(MVPCONTROL_VPC); | |
232 | ||
233 | /* We'll wait until starting the secondaries before starting MVPE */ | |
234 | ||
235 | printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num); | |
236 | ||
237 | /* set up ipi interrupts */ | |
238 | if (cpu_has_vint) { | |
239 | set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch); | |
240 | set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); | |
241 | } | |
9b6695a8 | 242 | } |
340ee4b9 | 243 | |
9b6695a8 RB |
244 | void __init plat_prepare_cpus(unsigned int max_cpus) |
245 | { | |
340ee4b9 RB |
246 | cpu_ipi_resched_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ; |
247 | cpu_ipi_call_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ; | |
248 | ||
249 | setup_irq(cpu_ipi_resched_irq, &irq_resched); | |
250 | setup_irq(cpu_ipi_call_irq, &irq_call); | |
251 | ||
252 | /* need to mark IPI's as IRQ_PER_CPU */ | |
253 | irq_desc[cpu_ipi_resched_irq].status |= IRQ_PER_CPU; | |
254 | irq_desc[cpu_ipi_call_irq].status |= IRQ_PER_CPU; | |
255 | } | |
256 | ||
257 | /* | |
258 | * Setup the PC, SP, and GP of a secondary processor and start it | |
259 | * running! | |
260 | * smp_bootstrap is the place to resume from | |
261 | * __KSTK_TOS(idle) is apparently the stack pointer | |
262 | * (unsigned long)idle->thread_info the gp | |
263 | * assumes a 1:1 mapping of TC => VPE | |
264 | */ | |
265 | void prom_boot_secondary(int cpu, struct task_struct *idle) | |
266 | { | |
dc8f6029 | 267 | struct thread_info *gp = task_thread_info(idle); |
340ee4b9 RB |
268 | dvpe(); |
269 | set_c0_mvpcontrol(MVPCONTROL_VPC); | |
270 | ||
271 | settc(cpu); | |
272 | ||
273 | /* restart */ | |
274 | write_tc_c0_tcrestart((unsigned long)&smp_bootstrap); | |
275 | ||
276 | /* enable the tc this vpe/cpu will be running */ | |
277 | write_tc_c0_tcstatus((read_tc_c0_tcstatus() & ~TCSTATUS_IXMT) | TCSTATUS_A); | |
278 | ||
279 | write_tc_c0_tchalt(0); | |
280 | ||
281 | /* enable the VPE */ | |
282 | write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA); | |
283 | ||
284 | /* stack pointer */ | |
285 | write_tc_gpr_sp( __KSTK_TOS(idle)); | |
286 | ||
287 | /* global pointer */ | |
dc8f6029 | 288 | write_tc_gpr_gp((unsigned long)gp); |
340ee4b9 | 289 | |
dc8f6029 | 290 | flush_icache_range((unsigned long)gp, (unsigned long)(gp + 1)); |
340ee4b9 RB |
291 | |
292 | /* finally out of configuration and into chaos */ | |
293 | clear_c0_mvpcontrol(MVPCONTROL_VPC); | |
294 | ||
295 | evpe(EVPE_ENABLE); | |
296 | } | |
297 | ||
298 | void prom_init_secondary(void) | |
299 | { | |
300 | write_c0_status((read_c0_status() & ~ST0_IM ) | | |
301 | (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP7)); | |
302 | } | |
303 | ||
304 | void prom_smp_finish(void) | |
305 | { | |
306 | write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ)); | |
307 | ||
308 | local_irq_enable(); | |
309 | } | |
310 | ||
311 | void prom_cpus_done(void) | |
312 | { | |
313 | } | |
314 | ||
315 | void core_send_ipi(int cpu, unsigned int action) | |
316 | { | |
317 | int i; | |
318 | unsigned long flags; | |
319 | int vpflags; | |
320 | ||
321 | local_irq_save (flags); | |
322 | ||
323 | vpflags = dvpe(); /* cant access the other CPU's registers whilst MVPE enabled */ | |
324 | ||
325 | switch (action) { | |
326 | case SMP_CALL_FUNCTION: | |
327 | i = C_SW1; | |
328 | break; | |
329 | ||
330 | case SMP_RESCHEDULE_YOURSELF: | |
331 | default: | |
332 | i = C_SW0; | |
333 | break; | |
334 | } | |
335 | ||
336 | /* 1:1 mapping of vpe and tc... */ | |
337 | settc(cpu); | |
338 | write_vpe_c0_cause(read_vpe_c0_cause() | i); | |
339 | evpe(vpflags); | |
340 | ||
341 | local_irq_restore(flags); | |
342 | } |