Commit | Line | Data |
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41c594ab RB |
1 | /* Copyright (C) 2004 Mips Technologies, Inc */ |
2 | ||
ea580401 | 3 | #include <linux/clockchips.h> |
41c594ab RB |
4 | #include <linux/kernel.h> |
5 | #include <linux/sched.h> | |
6 | #include <linux/cpumask.h> | |
7 | #include <linux/interrupt.h> | |
ae036b79 | 8 | #include <linux/kernel_stat.h> |
ec43c014 | 9 | #include <linux/module.h> |
41c594ab RB |
10 | |
11 | #include <asm/cpu.h> | |
12 | #include <asm/processor.h> | |
13 | #include <asm/atomic.h> | |
14 | #include <asm/system.h> | |
15 | #include <asm/hardirq.h> | |
16 | #include <asm/hazards.h> | |
3b1d4ed5 | 17 | #include <asm/irq.h> |
41c594ab | 18 | #include <asm/mmu_context.h> |
41c594ab RB |
19 | #include <asm/mipsregs.h> |
20 | #include <asm/cacheflush.h> | |
21 | #include <asm/time.h> | |
22 | #include <asm/addrspace.h> | |
23 | #include <asm/smtc.h> | |
24 | #include <asm/smtc_ipi.h> | |
25 | #include <asm/smtc_proc.h> | |
26 | ||
27 | /* | |
1146fe30 RB |
28 | * SMTC Kernel needs to manipulate low-level CPU interrupt mask |
29 | * in do_IRQ. These are passed in setup_irq_smtc() and stored | |
30 | * in this table. | |
41c594ab | 31 | */ |
1146fe30 | 32 | unsigned long irq_hwmask[NR_IRQS]; |
41c594ab | 33 | |
41c594ab RB |
34 | #define LOCK_MT_PRA() \ |
35 | local_irq_save(flags); \ | |
36 | mtflags = dmt() | |
37 | ||
38 | #define UNLOCK_MT_PRA() \ | |
39 | emt(mtflags); \ | |
40 | local_irq_restore(flags) | |
41 | ||
42 | #define LOCK_CORE_PRA() \ | |
43 | local_irq_save(flags); \ | |
44 | mtflags = dvpe() | |
45 | ||
46 | #define UNLOCK_CORE_PRA() \ | |
47 | evpe(mtflags); \ | |
48 | local_irq_restore(flags) | |
49 | ||
50 | /* | |
51 | * Data structures purely associated with SMTC parallelism | |
52 | */ | |
53 | ||
54 | ||
55 | /* | |
56 | * Table for tracking ASIDs whose lifetime is prolonged. | |
57 | */ | |
58 | ||
59 | asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS]; | |
60 | ||
61 | /* | |
62 | * Clock interrupt "latch" buffers, per "CPU" | |
63 | */ | |
64 | ||
ea580401 | 65 | static atomic_t ipi_timer_latch[NR_CPUS]; |
41c594ab RB |
66 | |
67 | /* | |
603e82ed | 68 | * Number of InterProcessor Interrupt (IPI) message buffers to allocate |
41c594ab RB |
69 | */ |
70 | ||
71 | #define IPIBUF_PER_CPU 4 | |
72 | ||
d2bb01b0 | 73 | struct smtc_ipi_q IPIQ[NR_CPUS]; |
5868756d | 74 | static struct smtc_ipi_q freeIPIq; |
41c594ab RB |
75 | |
76 | ||
77 | /* Forward declarations */ | |
78 | ||
937a8015 | 79 | void ipi_decode(struct smtc_ipi *); |
5868756d | 80 | static void post_direct_ipi(int cpu, struct smtc_ipi *pipi); |
20bb25d1 | 81 | static void setup_cross_vpe_interrupts(unsigned int nvpe); |
41c594ab RB |
82 | void init_smtc_stats(void); |
83 | ||
84 | /* Global SMTC Status */ | |
85 | ||
86 | unsigned int smtc_status = 0; | |
87 | ||
88 | /* Boot command line configuration overrides */ | |
89 | ||
be5f1f21 | 90 | static int vpe0limit; |
41c594ab RB |
91 | static int ipibuffers = 0; |
92 | static int nostlb = 0; | |
93 | static int asidmask = 0; | |
94 | unsigned long smtc_asid_mask = 0xff; | |
95 | ||
be5f1f21 KK |
96 | static int __init vpe0tcs(char *str) |
97 | { | |
98 | get_option(&str, &vpe0limit); | |
99 | ||
100 | return 1; | |
101 | } | |
102 | ||
41c594ab RB |
103 | static int __init ipibufs(char *str) |
104 | { | |
105 | get_option(&str, &ipibuffers); | |
106 | return 1; | |
107 | } | |
108 | ||
109 | static int __init stlb_disable(char *s) | |
110 | { | |
111 | nostlb = 1; | |
112 | return 1; | |
113 | } | |
114 | ||
115 | static int __init asidmask_set(char *str) | |
116 | { | |
117 | get_option(&str, &asidmask); | |
4bf42d42 | 118 | switch (asidmask) { |
41c594ab RB |
119 | case 0x1: |
120 | case 0x3: | |
121 | case 0x7: | |
122 | case 0xf: | |
123 | case 0x1f: | |
124 | case 0x3f: | |
125 | case 0x7f: | |
126 | case 0xff: | |
127 | smtc_asid_mask = (unsigned long)asidmask; | |
128 | break; | |
129 | default: | |
130 | printk("ILLEGAL ASID mask 0x%x from command line\n", asidmask); | |
131 | } | |
132 | return 1; | |
133 | } | |
134 | ||
be5f1f21 | 135 | __setup("vpe0tcs=", vpe0tcs); |
41c594ab RB |
136 | __setup("ipibufs=", ipibufs); |
137 | __setup("nostlb", stlb_disable); | |
138 | __setup("asidmask=", asidmask_set); | |
139 | ||
c68644d3 | 140 | #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG |
41c594ab RB |
141 | |
142 | static int hang_trig = 0; | |
143 | ||
144 | static int __init hangtrig_enable(char *s) | |
145 | { | |
146 | hang_trig = 1; | |
147 | return 1; | |
148 | } | |
149 | ||
150 | ||
151 | __setup("hangtrig", hangtrig_enable); | |
152 | ||
153 | #define DEFAULT_BLOCKED_IPI_LIMIT 32 | |
154 | ||
155 | static int timerq_limit = DEFAULT_BLOCKED_IPI_LIMIT; | |
156 | ||
157 | static int __init tintq(char *str) | |
158 | { | |
159 | get_option(&str, &timerq_limit); | |
160 | return 1; | |
161 | } | |
162 | ||
163 | __setup("tintq=", tintq); | |
164 | ||
97aef63c | 165 | static int imstuckcount[2][8]; |
41c594ab | 166 | /* vpemask represents IM/IE bits of per-VPE Status registers, low-to-high */ |
97aef63c | 167 | static int vpemask[2][8] = { |
20bb25d1 RB |
168 | {0, 0, 1, 0, 0, 0, 0, 1}, |
169 | {0, 0, 0, 0, 0, 0, 0, 1} | |
170 | }; | |
41c594ab RB |
171 | int tcnoprog[NR_CPUS]; |
172 | static atomic_t idle_hook_initialized = {0}; | |
173 | static int clock_hang_reported[NR_CPUS]; | |
174 | ||
c68644d3 | 175 | #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */ |
41c594ab | 176 | |
41c594ab RB |
177 | /* |
178 | * Configure shared TLB - VPC configuration bit must be set by caller | |
179 | */ | |
180 | ||
5868756d | 181 | static void smtc_configure_tlb(void) |
41c594ab | 182 | { |
21a151d8 | 183 | int i, tlbsiz, vpes; |
41c594ab RB |
184 | unsigned long mvpconf0; |
185 | unsigned long config1val; | |
186 | ||
187 | /* Set up ASID preservation table */ | |
188 | for (vpes=0; vpes<MAX_SMTC_TLBS; vpes++) { | |
189 | for(i = 0; i < MAX_SMTC_ASIDS; i++) { | |
190 | smtc_live_asid[vpes][i] = 0; | |
191 | } | |
192 | } | |
193 | mvpconf0 = read_c0_mvpconf0(); | |
194 | ||
195 | if ((vpes = ((mvpconf0 & MVPCONF0_PVPE) | |
196 | >> MVPCONF0_PVPE_SHIFT) + 1) > 1) { | |
197 | /* If we have multiple VPEs, try to share the TLB */ | |
198 | if ((mvpconf0 & MVPCONF0_TLBS) && !nostlb) { | |
199 | /* | |
200 | * If TLB sizing is programmable, shared TLB | |
201 | * size is the total available complement. | |
202 | * Otherwise, we have to take the sum of all | |
203 | * static VPE TLB entries. | |
204 | */ | |
205 | if ((tlbsiz = ((mvpconf0 & MVPCONF0_PTLBE) | |
206 | >> MVPCONF0_PTLBE_SHIFT)) == 0) { | |
207 | /* | |
208 | * If there's more than one VPE, there had better | |
209 | * be more than one TC, because we need one to bind | |
210 | * to each VPE in turn to be able to read | |
211 | * its configuration state! | |
212 | */ | |
213 | settc(1); | |
214 | /* Stop the TC from doing anything foolish */ | |
215 | write_tc_c0_tchalt(TCHALT_H); | |
216 | mips_ihb(); | |
217 | /* No need to un-Halt - that happens later anyway */ | |
218 | for (i=0; i < vpes; i++) { | |
219 | write_tc_c0_tcbind(i); | |
220 | /* | |
221 | * To be 100% sure we're really getting the right | |
222 | * information, we exit the configuration state | |
223 | * and do an IHB after each rebinding. | |
224 | */ | |
225 | write_c0_mvpcontrol( | |
226 | read_c0_mvpcontrol() & ~ MVPCONTROL_VPC ); | |
227 | mips_ihb(); | |
228 | /* | |
229 | * Only count if the MMU Type indicated is TLB | |
230 | */ | |
4bf42d42 | 231 | if (((read_vpe_c0_config() & MIPS_CONF_MT) >> 7) == 1) { |
41c594ab RB |
232 | config1val = read_vpe_c0_config1(); |
233 | tlbsiz += ((config1val >> 25) & 0x3f) + 1; | |
234 | } | |
235 | ||
236 | /* Put core back in configuration state */ | |
237 | write_c0_mvpcontrol( | |
238 | read_c0_mvpcontrol() | MVPCONTROL_VPC ); | |
239 | mips_ihb(); | |
240 | } | |
241 | } | |
242 | write_c0_mvpcontrol(read_c0_mvpcontrol() | MVPCONTROL_STLB); | |
c80697b3 | 243 | ehb(); |
41c594ab RB |
244 | |
245 | /* | |
246 | * Setup kernel data structures to use software total, | |
247 | * rather than read the per-VPE Config1 value. The values | |
248 | * for "CPU 0" gets copied to all the other CPUs as part | |
249 | * of their initialization in smtc_cpu_setup(). | |
250 | */ | |
251 | ||
a0b62180 RB |
252 | /* MIPS32 limits TLB indices to 64 */ |
253 | if (tlbsiz > 64) | |
254 | tlbsiz = 64; | |
255 | cpu_data[0].tlbsize = current_cpu_data.tlbsize = tlbsiz; | |
41c594ab | 256 | smtc_status |= SMTC_TLB_SHARED; |
a0b62180 | 257 | local_flush_tlb_all(); |
41c594ab RB |
258 | |
259 | printk("TLB of %d entry pairs shared by %d VPEs\n", | |
260 | tlbsiz, vpes); | |
261 | } else { | |
262 | printk("WARNING: TLB Not Sharable on SMTC Boot!\n"); | |
263 | } | |
264 | } | |
265 | } | |
266 | ||
267 | ||
268 | /* | |
269 | * Incrementally build the CPU map out of constituent MIPS MT cores, | |
270 | * using the specified available VPEs and TCs. Plaform code needs | |
271 | * to ensure that each MIPS MT core invokes this routine on reset, | |
272 | * one at a time(!). | |
273 | * | |
274 | * This version of the build_cpu_map and prepare_cpus routines assumes | |
275 | * that *all* TCs of a MIPS MT core will be used for Linux, and that | |
276 | * they will be spread across *all* available VPEs (to minimise the | |
277 | * loss of efficiency due to exception service serialization). | |
278 | * An improved version would pick up configuration information and | |
279 | * possibly leave some TCs/VPEs as "slave" processors. | |
280 | * | |
281 | * Use c0_MVPConf0 to find out how many TCs are available, setting up | |
282 | * phys_cpu_present_map and the logical/physical mappings. | |
283 | */ | |
284 | ||
285 | int __init mipsmt_build_cpu_map(int start_cpu_slot) | |
286 | { | |
287 | int i, ntcs; | |
288 | ||
289 | /* | |
290 | * The CPU map isn't actually used for anything at this point, | |
291 | * so it's not clear what else we should do apart from set | |
292 | * everything up so that "logical" = "physical". | |
293 | */ | |
294 | ntcs = ((read_c0_mvpconf0() & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1; | |
295 | for (i=start_cpu_slot; i<NR_CPUS && i<ntcs; i++) { | |
296 | cpu_set(i, phys_cpu_present_map); | |
297 | __cpu_number_map[i] = i; | |
298 | __cpu_logical_map[i] = i; | |
299 | } | |
ea580401 | 300 | #ifdef CONFIG_MIPS_MT_FPAFF |
41c594ab RB |
301 | /* Initialize map of CPUs with FPUs */ |
302 | cpus_clear(mt_fpu_cpumask); | |
ea580401 | 303 | #endif |
41c594ab RB |
304 | |
305 | /* One of those TC's is the one booting, and not a secondary... */ | |
306 | printk("%i available secondary CPU TC(s)\n", i - 1); | |
307 | ||
308 | return i; | |
309 | } | |
310 | ||
311 | /* | |
312 | * Common setup before any secondaries are started | |
313 | * Make sure all CPU's are in a sensible state before we boot any of the | |
314 | * secondaries. | |
315 | * | |
316 | * For MIPS MT "SMTC" operation, we set up all TCs, spread as evenly | |
317 | * as possible across the available VPEs. | |
318 | */ | |
319 | ||
320 | static void smtc_tc_setup(int vpe, int tc, int cpu) | |
321 | { | |
322 | settc(tc); | |
323 | write_tc_c0_tchalt(TCHALT_H); | |
324 | mips_ihb(); | |
325 | write_tc_c0_tcstatus((read_tc_c0_tcstatus() | |
326 | & ~(TCSTATUS_TKSU | TCSTATUS_DA | TCSTATUS_IXMT)) | |
327 | | TCSTATUS_A); | |
328 | write_tc_c0_tccontext(0); | |
329 | /* Bind tc to vpe */ | |
330 | write_tc_c0_tcbind(vpe); | |
331 | /* In general, all TCs should have the same cpu_data indications */ | |
332 | memcpy(&cpu_data[cpu], &cpu_data[0], sizeof(struct cpuinfo_mips)); | |
333 | /* For 34Kf, start with TC/CPU 0 as sole owner of single FPU context */ | |
39b8d525 RB |
334 | if (cpu_data[0].cputype == CPU_34K || |
335 | cpu_data[0].cputype == CPU_1004K) | |
41c594ab RB |
336 | cpu_data[cpu].options &= ~MIPS_CPU_FPU; |
337 | cpu_data[cpu].vpe_id = vpe; | |
338 | cpu_data[cpu].tc_id = tc; | |
339 | } | |
340 | ||
341 | ||
342 | void mipsmt_prepare_cpus(void) | |
343 | { | |
be5f1f21 | 344 | int i, vpe, tc, ntc, nvpe, tcpervpe[NR_CPUS], slop, cpu; |
41c594ab RB |
345 | unsigned long flags; |
346 | unsigned long val; | |
347 | int nipi; | |
348 | struct smtc_ipi *pipi; | |
349 | ||
350 | /* disable interrupts so we can disable MT */ | |
351 | local_irq_save(flags); | |
352 | /* disable MT so we can configure */ | |
353 | dvpe(); | |
354 | dmt(); | |
355 | ||
34af946a | 356 | spin_lock_init(&freeIPIq.lock); |
41c594ab RB |
357 | |
358 | /* | |
359 | * We probably don't have as many VPEs as we do SMP "CPUs", | |
360 | * but it's possible - and in any case we'll never use more! | |
361 | */ | |
362 | for (i=0; i<NR_CPUS; i++) { | |
363 | IPIQ[i].head = IPIQ[i].tail = NULL; | |
34af946a | 364 | spin_lock_init(&IPIQ[i].lock); |
41c594ab | 365 | IPIQ[i].depth = 0; |
ea580401 | 366 | atomic_set(&ipi_timer_latch[i], 0); |
41c594ab RB |
367 | } |
368 | ||
369 | /* cpu_data index starts at zero */ | |
370 | cpu = 0; | |
371 | cpu_data[cpu].vpe_id = 0; | |
372 | cpu_data[cpu].tc_id = 0; | |
373 | cpu++; | |
374 | ||
375 | /* Report on boot-time options */ | |
49a89efb | 376 | mips_mt_set_cpuoptions(); |
41c594ab RB |
377 | if (vpelimit > 0) |
378 | printk("Limit of %d VPEs set\n", vpelimit); | |
379 | if (tclimit > 0) | |
380 | printk("Limit of %d TCs set\n", tclimit); | |
381 | if (nostlb) { | |
382 | printk("Shared TLB Use Inhibited - UNSAFE for Multi-VPE Operation\n"); | |
383 | } | |
384 | if (asidmask) | |
385 | printk("ASID mask value override to 0x%x\n", asidmask); | |
386 | ||
387 | /* Temporary */ | |
c68644d3 | 388 | #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG |
41c594ab RB |
389 | if (hang_trig) |
390 | printk("Logic Analyser Trigger on suspected TC hang\n"); | |
c68644d3 | 391 | #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */ |
41c594ab RB |
392 | |
393 | /* Put MVPE's into 'configuration state' */ | |
394 | write_c0_mvpcontrol( read_c0_mvpcontrol() | MVPCONTROL_VPC ); | |
395 | ||
396 | val = read_c0_mvpconf0(); | |
397 | nvpe = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; | |
398 | if (vpelimit > 0 && nvpe > vpelimit) | |
399 | nvpe = vpelimit; | |
400 | ntc = ((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1; | |
401 | if (ntc > NR_CPUS) | |
402 | ntc = NR_CPUS; | |
403 | if (tclimit > 0 && ntc > tclimit) | |
404 | ntc = tclimit; | |
be5f1f21 KK |
405 | slop = ntc % nvpe; |
406 | for (i = 0; i < nvpe; i++) { | |
407 | tcpervpe[i] = ntc / nvpe; | |
408 | if (slop) { | |
409 | if((slop - i) > 0) tcpervpe[i]++; | |
410 | } | |
411 | } | |
412 | /* Handle command line override for VPE0 */ | |
413 | if (vpe0limit > ntc) vpe0limit = ntc; | |
414 | if (vpe0limit > 0) { | |
415 | int slopslop; | |
416 | if (vpe0limit < tcpervpe[0]) { | |
417 | /* Reducing TC count - distribute to others */ | |
418 | slop = tcpervpe[0] - vpe0limit; | |
419 | slopslop = slop % (nvpe - 1); | |
420 | tcpervpe[0] = vpe0limit; | |
421 | for (i = 1; i < nvpe; i++) { | |
422 | tcpervpe[i] += slop / (nvpe - 1); | |
423 | if(slopslop && ((slopslop - (i - 1) > 0))) | |
424 | tcpervpe[i]++; | |
425 | } | |
426 | } else if (vpe0limit > tcpervpe[0]) { | |
427 | /* Increasing TC count - steal from others */ | |
428 | slop = vpe0limit - tcpervpe[0]; | |
429 | slopslop = slop % (nvpe - 1); | |
430 | tcpervpe[0] = vpe0limit; | |
431 | for (i = 1; i < nvpe; i++) { | |
432 | tcpervpe[i] -= slop / (nvpe - 1); | |
433 | if(slopslop && ((slopslop - (i - 1) > 0))) | |
434 | tcpervpe[i]--; | |
435 | } | |
436 | } | |
437 | } | |
41c594ab RB |
438 | |
439 | /* Set up shared TLB */ | |
440 | smtc_configure_tlb(); | |
441 | ||
442 | for (tc = 0, vpe = 0 ; (vpe < nvpe) && (tc < ntc) ; vpe++) { | |
443 | /* | |
444 | * Set the MVP bits. | |
445 | */ | |
446 | settc(tc); | |
447 | write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_MVP); | |
448 | if (vpe != 0) | |
449 | printk(", "); | |
450 | printk("VPE %d: TC", vpe); | |
be5f1f21 | 451 | for (i = 0; i < tcpervpe[vpe]; i++) { |
41c594ab RB |
452 | /* |
453 | * TC 0 is bound to VPE 0 at reset, | |
454 | * and is presumably executing this | |
455 | * code. Leave it alone! | |
456 | */ | |
457 | if (tc != 0) { | |
21a151d8 | 458 | smtc_tc_setup(vpe, tc, cpu); |
41c594ab RB |
459 | cpu++; |
460 | } | |
461 | printk(" %d", tc); | |
462 | tc++; | |
463 | } | |
41c594ab RB |
464 | if (vpe != 0) { |
465 | /* | |
466 | * Clear any stale software interrupts from VPE's Cause | |
467 | */ | |
468 | write_vpe_c0_cause(0); | |
469 | ||
470 | /* | |
471 | * Clear ERL/EXL of VPEs other than 0 | |
472 | * and set restricted interrupt enable/mask. | |
473 | */ | |
474 | write_vpe_c0_status((read_vpe_c0_status() | |
475 | & ~(ST0_BEV | ST0_ERL | ST0_EXL | ST0_IM)) | |
476 | | (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP7 | |
477 | | ST0_IE)); | |
478 | /* | |
479 | * set config to be the same as vpe0, | |
480 | * particularly kseg0 coherency alg | |
481 | */ | |
482 | write_vpe_c0_config(read_c0_config()); | |
483 | /* Clear any pending timer interrupt */ | |
484 | write_vpe_c0_compare(0); | |
485 | /* Propagate Config7 */ | |
486 | write_vpe_c0_config7(read_c0_config7()); | |
64c590b7 | 487 | write_vpe_c0_count(read_c0_count()); |
41c594ab RB |
488 | } |
489 | /* enable multi-threading within VPE */ | |
490 | write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() | VPECONTROL_TE); | |
491 | /* enable the VPE */ | |
492 | write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA); | |
493 | } | |
494 | ||
495 | /* | |
496 | * Pull any physically present but unused TCs out of circulation. | |
497 | */ | |
498 | while (tc < (((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1)) { | |
499 | cpu_clear(tc, phys_cpu_present_map); | |
500 | cpu_clear(tc, cpu_present_map); | |
501 | tc++; | |
502 | } | |
503 | ||
504 | /* release config state */ | |
505 | write_c0_mvpcontrol( read_c0_mvpcontrol() & ~ MVPCONTROL_VPC ); | |
506 | ||
507 | printk("\n"); | |
508 | ||
509 | /* Set up coprocessor affinity CPU mask(s) */ | |
510 | ||
ea580401 | 511 | #ifdef CONFIG_MIPS_MT_FPAFF |
41c594ab | 512 | for (tc = 0; tc < ntc; tc++) { |
4bf42d42 | 513 | if (cpu_data[tc].options & MIPS_CPU_FPU) |
41c594ab RB |
514 | cpu_set(tc, mt_fpu_cpumask); |
515 | } | |
ea580401 | 516 | #endif |
41c594ab RB |
517 | |
518 | /* set up ipi interrupts... */ | |
519 | ||
520 | /* If we have multiple VPEs running, set up the cross-VPE interrupt */ | |
521 | ||
20bb25d1 | 522 | setup_cross_vpe_interrupts(nvpe); |
41c594ab RB |
523 | |
524 | /* Set up queue of free IPI "messages". */ | |
525 | nipi = NR_CPUS * IPIBUF_PER_CPU; | |
526 | if (ipibuffers > 0) | |
527 | nipi = ipibuffers; | |
528 | ||
529 | pipi = kmalloc(nipi *sizeof(struct smtc_ipi), GFP_KERNEL); | |
530 | if (pipi == NULL) | |
531 | panic("kmalloc of IPI message buffers failed\n"); | |
532 | else | |
533 | printk("IPI buffer pool of %d buffers\n", nipi); | |
534 | for (i = 0; i < nipi; i++) { | |
535 | smtc_ipi_nq(&freeIPIq, pipi); | |
536 | pipi++; | |
537 | } | |
538 | ||
539 | /* Arm multithreading and enable other VPEs - but all TCs are Halted */ | |
540 | emt(EMT_ENABLE); | |
541 | evpe(EVPE_ENABLE); | |
542 | local_irq_restore(flags); | |
543 | /* Initialize SMTC /proc statistics/diagnostics */ | |
544 | init_smtc_stats(); | |
545 | } | |
546 | ||
547 | ||
548 | /* | |
549 | * Setup the PC, SP, and GP of a secondary processor and start it | |
550 | * running! | |
551 | * smp_bootstrap is the place to resume from | |
552 | * __KSTK_TOS(idle) is apparently the stack pointer | |
553 | * (unsigned long)idle->thread_info the gp | |
554 | * | |
555 | */ | |
e119d49a | 556 | void __cpuinit smtc_boot_secondary(int cpu, struct task_struct *idle) |
41c594ab RB |
557 | { |
558 | extern u32 kernelsp[NR_CPUS]; | |
b7e4226e | 559 | unsigned long flags; |
41c594ab RB |
560 | int mtflags; |
561 | ||
562 | LOCK_MT_PRA(); | |
563 | if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) { | |
564 | dvpe(); | |
565 | } | |
566 | settc(cpu_data[cpu].tc_id); | |
567 | ||
568 | /* pc */ | |
569 | write_tc_c0_tcrestart((unsigned long)&smp_bootstrap); | |
570 | ||
571 | /* stack pointer */ | |
572 | kernelsp[cpu] = __KSTK_TOS(idle); | |
573 | write_tc_gpr_sp(__KSTK_TOS(idle)); | |
574 | ||
575 | /* global pointer */ | |
c9f4f06d | 576 | write_tc_gpr_gp((unsigned long)task_thread_info(idle)); |
41c594ab RB |
577 | |
578 | smtc_status |= SMTC_MTC_ACTIVE; | |
579 | write_tc_c0_tchalt(0); | |
580 | if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) { | |
581 | evpe(EVPE_ENABLE); | |
582 | } | |
583 | UNLOCK_MT_PRA(); | |
584 | } | |
585 | ||
586 | void smtc_init_secondary(void) | |
587 | { | |
588 | /* | |
589 | * Start timer on secondary VPEs if necessary. | |
54d0a216 | 590 | * plat_timer_setup has already have been invoked by init/main |
41c594ab RB |
591 | * on "boot" TC. Like per_cpu_trap_init() hack, this assumes that |
592 | * SMTC init code assigns TCs consdecutively and in ascending order | |
593 | * to across available VPEs. | |
594 | */ | |
4bf42d42 RB |
595 | if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && |
596 | ((read_c0_tcbind() & TCBIND_CURVPE) | |
41c594ab | 597 | != cpu_data[smp_processor_id() - 1].vpe_id)){ |
49a89efb | 598 | write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ); |
41c594ab RB |
599 | } |
600 | ||
601 | local_irq_enable(); | |
602 | } | |
603 | ||
604 | void smtc_smp_finish(void) | |
605 | { | |
606 | printk("TC %d going on-line as CPU %d\n", | |
607 | cpu_data[smp_processor_id()].tc_id, smp_processor_id()); | |
608 | } | |
609 | ||
610 | void smtc_cpus_done(void) | |
611 | { | |
612 | } | |
613 | ||
614 | /* | |
615 | * Support for SMTC-optimized driver IRQ registration | |
616 | */ | |
617 | ||
618 | /* | |
619 | * SMTC Kernel needs to manipulate low-level CPU interrupt mask | |
620 | * in do_IRQ. These are passed in setup_irq_smtc() and stored | |
621 | * in this table. | |
622 | */ | |
623 | ||
624 | int setup_irq_smtc(unsigned int irq, struct irqaction * new, | |
625 | unsigned long hwmask) | |
626 | { | |
ef36fc3c | 627 | #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG |
20bb25d1 RB |
628 | unsigned int vpe = current_cpu_data.vpe_id; |
629 | ||
3b1d4ed5 | 630 | vpemask[vpe][irq - MIPS_CPU_IRQ_BASE] = 1; |
20bb25d1 | 631 | #endif |
ef36fc3c | 632 | irq_hwmask[irq] = hwmask; |
41c594ab RB |
633 | |
634 | return setup_irq(irq, new); | |
635 | } | |
636 | ||
f571eff0 KK |
637 | #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF |
638 | /* | |
639 | * Support for IRQ affinity to TCs | |
640 | */ | |
641 | ||
642 | void smtc_set_irq_affinity(unsigned int irq, cpumask_t affinity) | |
643 | { | |
644 | /* | |
645 | * If a "fast path" cache of quickly decodable affinity state | |
646 | * is maintained, this is where it gets done, on a call up | |
647 | * from the platform affinity code. | |
648 | */ | |
649 | } | |
650 | ||
651 | void smtc_forward_irq(unsigned int irq) | |
652 | { | |
653 | int target; | |
654 | ||
655 | /* | |
656 | * OK wise guy, now figure out how to get the IRQ | |
657 | * to be serviced on an authorized "CPU". | |
658 | * | |
659 | * Ideally, to handle the situation where an IRQ has multiple | |
660 | * eligible CPUS, we would maintain state per IRQ that would | |
661 | * allow a fair distribution of service requests. Since the | |
662 | * expected use model is any-or-only-one, for simplicity | |
663 | * and efficiency, we just pick the easiest one to find. | |
664 | */ | |
665 | ||
666 | target = first_cpu(irq_desc[irq].affinity); | |
667 | ||
668 | /* | |
669 | * We depend on the platform code to have correctly processed | |
670 | * IRQ affinity change requests to ensure that the IRQ affinity | |
671 | * mask has been purged of bits corresponding to nonexistent and | |
672 | * offline "CPUs", and to TCs bound to VPEs other than the VPE | |
673 | * connected to the physical interrupt input for the interrupt | |
674 | * in question. Otherwise we have a nasty problem with interrupt | |
675 | * mask management. This is best handled in non-performance-critical | |
676 | * platform IRQ affinity setting code, to minimize interrupt-time | |
677 | * checks. | |
678 | */ | |
679 | ||
680 | /* If no one is eligible, service locally */ | |
681 | if (target >= NR_CPUS) { | |
682 | do_IRQ_no_affinity(irq); | |
683 | return; | |
684 | } | |
685 | ||
686 | smtc_send_ipi(target, IRQ_AFFINITY_IPI, irq); | |
687 | } | |
688 | ||
689 | #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ | |
690 | ||
41c594ab RB |
691 | /* |
692 | * IPI model for SMTC is tricky, because interrupts aren't TC-specific. | |
693 | * Within a VPE one TC can interrupt another by different approaches. | |
694 | * The easiest to get right would probably be to make all TCs except | |
695 | * the target IXMT and set a software interrupt, but an IXMT-based | |
696 | * scheme requires that a handler must run before a new IPI could | |
697 | * be sent, which would break the "broadcast" loops in MIPS MT. | |
698 | * A more gonzo approach within a VPE is to halt the TC, extract | |
699 | * its Restart, Status, and a couple of GPRs, and program the Restart | |
700 | * address to emulate an interrupt. | |
701 | * | |
702 | * Within a VPE, one can be confident that the target TC isn't in | |
703 | * a critical EXL state when halted, since the write to the Halt | |
704 | * register could not have issued on the writing thread if the | |
705 | * halting thread had EXL set. So k0 and k1 of the target TC | |
706 | * can be used by the injection code. Across VPEs, one can't | |
707 | * be certain that the target TC isn't in a critical exception | |
708 | * state. So we try a two-step process of sending a software | |
709 | * interrupt to the target VPE, which either handles the event | |
710 | * itself (if it was the target) or injects the event within | |
711 | * the VPE. | |
712 | */ | |
713 | ||
5868756d | 714 | static void smtc_ipi_qdump(void) |
41c594ab RB |
715 | { |
716 | int i; | |
717 | ||
718 | for (i = 0; i < NR_CPUS ;i++) { | |
719 | printk("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n", | |
720 | i, (unsigned)IPIQ[i].head, (unsigned)IPIQ[i].tail, | |
721 | IPIQ[i].depth); | |
722 | } | |
723 | } | |
724 | ||
725 | /* | |
726 | * The standard atomic.h primitives don't quite do what we want | |
727 | * here: We need an atomic add-and-return-previous-value (which | |
728 | * could be done with atomic_add_return and a decrement) and an | |
729 | * atomic set/zero-and-return-previous-value (which can't really | |
730 | * be done with the atomic.h primitives). And since this is | |
731 | * MIPS MT, we can assume that we have LL/SC. | |
732 | */ | |
ea580401 | 733 | static inline int atomic_postincrement(atomic_t *v) |
41c594ab RB |
734 | { |
735 | unsigned long result; | |
736 | ||
737 | unsigned long temp; | |
738 | ||
739 | __asm__ __volatile__( | |
740 | "1: ll %0, %2 \n" | |
741 | " addu %1, %0, 1 \n" | |
742 | " sc %1, %2 \n" | |
743 | " beqz %1, 1b \n" | |
d87d0c93 | 744 | __WEAK_LLSC_MB |
ea580401 RB |
745 | : "=&r" (result), "=&r" (temp), "=m" (v->counter) |
746 | : "m" (v->counter) | |
41c594ab RB |
747 | : "memory"); |
748 | ||
749 | return result; | |
750 | } | |
751 | ||
41c594ab RB |
752 | void smtc_send_ipi(int cpu, int type, unsigned int action) |
753 | { | |
754 | int tcstatus; | |
755 | struct smtc_ipi *pipi; | |
b7e4226e | 756 | unsigned long flags; |
41c594ab RB |
757 | int mtflags; |
758 | ||
759 | if (cpu == smp_processor_id()) { | |
760 | printk("Cannot Send IPI to self!\n"); | |
761 | return; | |
762 | } | |
763 | /* Set up a descriptor, to be delivered either promptly or queued */ | |
764 | pipi = smtc_ipi_dq(&freeIPIq); | |
765 | if (pipi == NULL) { | |
766 | bust_spinlocks(1); | |
767 | mips_mt_regdump(dvpe()); | |
768 | panic("IPI Msg. Buffers Depleted\n"); | |
769 | } | |
770 | pipi->type = type; | |
771 | pipi->arg = (void *)action; | |
772 | pipi->dest = cpu; | |
773 | if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) { | |
ea580401 RB |
774 | if (type == SMTC_CLOCK_TICK) |
775 | atomic_inc(&ipi_timer_latch[cpu]); | |
603e82ed | 776 | /* If not on same VPE, enqueue and send cross-VPE interrupt */ |
41c594ab RB |
777 | smtc_ipi_nq(&IPIQ[cpu], pipi); |
778 | LOCK_CORE_PRA(); | |
779 | settc(cpu_data[cpu].tc_id); | |
780 | write_vpe_c0_cause(read_vpe_c0_cause() | C_SW1); | |
781 | UNLOCK_CORE_PRA(); | |
782 | } else { | |
783 | /* | |
784 | * Not sufficient to do a LOCK_MT_PRA (dmt) here, | |
785 | * since ASID shootdown on the other VPE may | |
786 | * collide with this operation. | |
787 | */ | |
788 | LOCK_CORE_PRA(); | |
789 | settc(cpu_data[cpu].tc_id); | |
790 | /* Halt the targeted TC */ | |
791 | write_tc_c0_tchalt(TCHALT_H); | |
792 | mips_ihb(); | |
793 | ||
794 | /* | |
795 | * Inspect TCStatus - if IXMT is set, we have to queue | |
796 | * a message. Otherwise, we set up the "interrupt" | |
797 | * of the other TC | |
798 | */ | |
799 | tcstatus = read_tc_c0_tcstatus(); | |
800 | ||
801 | if ((tcstatus & TCSTATUS_IXMT) != 0) { | |
802 | /* | |
803 | * Spin-waiting here can deadlock, | |
804 | * so we queue the message for the target TC. | |
805 | */ | |
806 | write_tc_c0_tchalt(0); | |
807 | UNLOCK_CORE_PRA(); | |
808 | /* Try to reduce redundant timer interrupt messages */ | |
4bf42d42 RB |
809 | if (type == SMTC_CLOCK_TICK) { |
810 | if (atomic_postincrement(&ipi_timer_latch[cpu])!=0){ | |
41c594ab RB |
811 | smtc_ipi_nq(&freeIPIq, pipi); |
812 | return; | |
813 | } | |
814 | } | |
815 | smtc_ipi_nq(&IPIQ[cpu], pipi); | |
816 | } else { | |
ea580401 RB |
817 | if (type == SMTC_CLOCK_TICK) |
818 | atomic_inc(&ipi_timer_latch[cpu]); | |
41c594ab RB |
819 | post_direct_ipi(cpu, pipi); |
820 | write_tc_c0_tchalt(0); | |
821 | UNLOCK_CORE_PRA(); | |
822 | } | |
823 | } | |
824 | } | |
825 | ||
826 | /* | |
827 | * Send IPI message to Halted TC, TargTC/TargVPE already having been set | |
828 | */ | |
5868756d | 829 | static void post_direct_ipi(int cpu, struct smtc_ipi *pipi) |
41c594ab RB |
830 | { |
831 | struct pt_regs *kstack; | |
832 | unsigned long tcstatus; | |
833 | unsigned long tcrestart; | |
834 | extern u32 kernelsp[NR_CPUS]; | |
835 | extern void __smtc_ipi_vector(void); | |
ea580401 | 836 | //printk("%s: on %d for %d\n", __func__, smp_processor_id(), cpu); |
41c594ab RB |
837 | |
838 | /* Extract Status, EPC from halted TC */ | |
839 | tcstatus = read_tc_c0_tcstatus(); | |
840 | tcrestart = read_tc_c0_tcrestart(); | |
841 | /* If TCRestart indicates a WAIT instruction, advance the PC */ | |
842 | if ((tcrestart & 0x80000000) | |
843 | && ((*(unsigned int *)tcrestart & 0xfe00003f) == 0x42000020)) { | |
844 | tcrestart += 4; | |
845 | } | |
846 | /* | |
847 | * Save on TC's future kernel stack | |
848 | * | |
849 | * CU bit of Status is indicator that TC was | |
850 | * already running on a kernel stack... | |
851 | */ | |
4bf42d42 | 852 | if (tcstatus & ST0_CU0) { |
41c594ab RB |
853 | /* Note that this "- 1" is pointer arithmetic */ |
854 | kstack = ((struct pt_regs *)read_tc_gpr_sp()) - 1; | |
855 | } else { | |
856 | kstack = ((struct pt_regs *)kernelsp[cpu]) - 1; | |
857 | } | |
858 | ||
859 | kstack->cp0_epc = (long)tcrestart; | |
860 | /* Save TCStatus */ | |
861 | kstack->cp0_tcstatus = tcstatus; | |
862 | /* Pass token of operation to be performed kernel stack pad area */ | |
863 | kstack->pad0[4] = (unsigned long)pipi; | |
864 | /* Pass address of function to be called likewise */ | |
865 | kstack->pad0[5] = (unsigned long)&ipi_decode; | |
866 | /* Set interrupt exempt and kernel mode */ | |
867 | tcstatus |= TCSTATUS_IXMT; | |
868 | tcstatus &= ~TCSTATUS_TKSU; | |
869 | write_tc_c0_tcstatus(tcstatus); | |
870 | ehb(); | |
871 | /* Set TC Restart address to be SMTC IPI vector */ | |
872 | write_tc_c0_tcrestart(__smtc_ipi_vector); | |
873 | } | |
874 | ||
937a8015 | 875 | static void ipi_resched_interrupt(void) |
41c594ab RB |
876 | { |
877 | /* Return from interrupt should be enough to cause scheduler check */ | |
878 | } | |
879 | ||
937a8015 | 880 | static void ipi_call_interrupt(void) |
41c594ab RB |
881 | { |
882 | /* Invoke generic function invocation code in smp.c */ | |
883 | smp_call_function_interrupt(); | |
884 | } | |
885 | ||
ea580401 RB |
886 | DECLARE_PER_CPU(struct clock_event_device, smtc_dummy_clockevent_device); |
887 | ||
937a8015 | 888 | void ipi_decode(struct smtc_ipi *pipi) |
41c594ab | 889 | { |
ea580401 RB |
890 | unsigned int cpu = smp_processor_id(); |
891 | struct clock_event_device *cd; | |
41c594ab RB |
892 | void *arg_copy = pipi->arg; |
893 | int type_copy = pipi->type; | |
ea580401 | 894 | int ticks; |
41c594ab RB |
895 | |
896 | smtc_ipi_nq(&freeIPIq, pipi); | |
897 | switch (type_copy) { | |
4bf42d42 | 898 | case SMTC_CLOCK_TICK: |
ae036b79 | 899 | irq_enter(); |
ea580401 RB |
900 | kstat_this_cpu.irqs[MIPS_CPU_IRQ_BASE + 1]++; |
901 | cd = &per_cpu(smtc_dummy_clockevent_device, cpu); | |
902 | ticks = atomic_read(&ipi_timer_latch[cpu]); | |
903 | atomic_sub(ticks, &ipi_timer_latch[cpu]); | |
904 | while (ticks) { | |
905 | cd->event_handler(cd); | |
906 | ticks--; | |
907 | } | |
ae036b79 | 908 | irq_exit(); |
4bf42d42 | 909 | break; |
ea580401 | 910 | |
4bf42d42 RB |
911 | case LINUX_SMP_IPI: |
912 | switch ((int)arg_copy) { | |
913 | case SMP_RESCHEDULE_YOURSELF: | |
937a8015 | 914 | ipi_resched_interrupt(); |
41c594ab | 915 | break; |
4bf42d42 | 916 | case SMP_CALL_FUNCTION: |
937a8015 | 917 | ipi_call_interrupt(); |
41c594ab RB |
918 | break; |
919 | default: | |
4bf42d42 RB |
920 | printk("Impossible SMTC IPI Argument 0x%x\n", |
921 | (int)arg_copy); | |
41c594ab | 922 | break; |
4bf42d42 RB |
923 | } |
924 | break; | |
f571eff0 KK |
925 | #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF |
926 | case IRQ_AFFINITY_IPI: | |
927 | /* | |
928 | * Accept a "forwarded" interrupt that was initially | |
929 | * taken by a TC who doesn't have affinity for the IRQ. | |
930 | */ | |
931 | do_IRQ_no_affinity((int)arg_copy); | |
932 | break; | |
933 | #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ | |
4bf42d42 RB |
934 | default: |
935 | printk("Impossible SMTC IPI Type 0x%x\n", type_copy); | |
936 | break; | |
41c594ab RB |
937 | } |
938 | } | |
939 | ||
937a8015 | 940 | void deferred_smtc_ipi(void) |
41c594ab RB |
941 | { |
942 | struct smtc_ipi *pipi; | |
943 | unsigned long flags; | |
944 | /* DEBUG */ | |
945 | int q = smp_processor_id(); | |
946 | ||
947 | /* | |
948 | * Test is not atomic, but much faster than a dequeue, | |
949 | * and the vast majority of invocations will have a null queue. | |
950 | */ | |
4bf42d42 | 951 | if (IPIQ[q].head != NULL) { |
41c594ab RB |
952 | while((pipi = smtc_ipi_dq(&IPIQ[q])) != NULL) { |
953 | /* ipi_decode() should be called with interrupts off */ | |
954 | local_irq_save(flags); | |
937a8015 | 955 | ipi_decode(pipi); |
41c594ab RB |
956 | local_irq_restore(flags); |
957 | } | |
958 | } | |
959 | } | |
960 | ||
41c594ab RB |
961 | /* |
962 | * Cross-VPE interrupts in the SMTC prototype use "software interrupts" | |
963 | * set via cross-VPE MTTR manipulation of the Cause register. It would be | |
964 | * in some regards preferable to have external logic for "doorbell" hardware | |
965 | * interrupts. | |
966 | */ | |
967 | ||
97dcb82d | 968 | static int cpu_ipi_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_IRQ; |
41c594ab | 969 | |
937a8015 | 970 | static irqreturn_t ipi_interrupt(int irq, void *dev_idm) |
41c594ab RB |
971 | { |
972 | int my_vpe = cpu_data[smp_processor_id()].vpe_id; | |
973 | int my_tc = cpu_data[smp_processor_id()].tc_id; | |
974 | int cpu; | |
975 | struct smtc_ipi *pipi; | |
976 | unsigned long tcstatus; | |
977 | int sent; | |
b7e4226e | 978 | unsigned long flags; |
41c594ab RB |
979 | unsigned int mtflags; |
980 | unsigned int vpflags; | |
981 | ||
982 | /* | |
983 | * So long as cross-VPE interrupts are done via | |
984 | * MFTR/MTTR read-modify-writes of Cause, we need | |
985 | * to stop other VPEs whenever the local VPE does | |
986 | * anything similar. | |
987 | */ | |
988 | local_irq_save(flags); | |
989 | vpflags = dvpe(); | |
990 | clear_c0_cause(0x100 << MIPS_CPU_IPI_IRQ); | |
991 | set_c0_status(0x100 << MIPS_CPU_IPI_IRQ); | |
992 | irq_enable_hazard(); | |
993 | evpe(vpflags); | |
994 | local_irq_restore(flags); | |
995 | ||
996 | /* | |
997 | * Cross-VPE Interrupt handler: Try to directly deliver IPIs | |
998 | * queued for TCs on this VPE other than the current one. | |
999 | * Return-from-interrupt should cause us to drain the queue | |
1000 | * for the current TC, so we ought not to have to do it explicitly here. | |
1001 | */ | |
1002 | ||
1003 | for_each_online_cpu(cpu) { | |
1004 | if (cpu_data[cpu].vpe_id != my_vpe) | |
1005 | continue; | |
1006 | ||
1007 | pipi = smtc_ipi_dq(&IPIQ[cpu]); | |
1008 | if (pipi != NULL) { | |
1009 | if (cpu_data[cpu].tc_id != my_tc) { | |
1010 | sent = 0; | |
1011 | LOCK_MT_PRA(); | |
1012 | settc(cpu_data[cpu].tc_id); | |
1013 | write_tc_c0_tchalt(TCHALT_H); | |
1014 | mips_ihb(); | |
1015 | tcstatus = read_tc_c0_tcstatus(); | |
1016 | if ((tcstatus & TCSTATUS_IXMT) == 0) { | |
1017 | post_direct_ipi(cpu, pipi); | |
1018 | sent = 1; | |
1019 | } | |
1020 | write_tc_c0_tchalt(0); | |
1021 | UNLOCK_MT_PRA(); | |
1022 | if (!sent) { | |
1023 | smtc_ipi_req(&IPIQ[cpu], pipi); | |
1024 | } | |
1025 | } else { | |
1026 | /* | |
1027 | * ipi_decode() should be called | |
1028 | * with interrupts off | |
1029 | */ | |
1030 | local_irq_save(flags); | |
937a8015 | 1031 | ipi_decode(pipi); |
41c594ab RB |
1032 | local_irq_restore(flags); |
1033 | } | |
1034 | } | |
1035 | } | |
1036 | ||
1037 | return IRQ_HANDLED; | |
1038 | } | |
1039 | ||
937a8015 | 1040 | static void ipi_irq_dispatch(void) |
41c594ab | 1041 | { |
937a8015 | 1042 | do_IRQ(cpu_ipi_irq); |
41c594ab RB |
1043 | } |
1044 | ||
033890b0 RB |
1045 | static struct irqaction irq_ipi = { |
1046 | .handler = ipi_interrupt, | |
1047 | .flags = IRQF_DISABLED, | |
1048 | .name = "SMTC_IPI", | |
1049 | .flags = IRQF_PERCPU | |
1050 | }; | |
41c594ab | 1051 | |
20bb25d1 | 1052 | static void setup_cross_vpe_interrupts(unsigned int nvpe) |
41c594ab | 1053 | { |
20bb25d1 RB |
1054 | if (nvpe < 1) |
1055 | return; | |
1056 | ||
41c594ab | 1057 | if (!cpu_has_vint) |
603e82ed | 1058 | panic("SMTC Kernel requires Vectored Interrupt support"); |
41c594ab RB |
1059 | |
1060 | set_vi_handler(MIPS_CPU_IPI_IRQ, ipi_irq_dispatch); | |
1061 | ||
41c594ab RB |
1062 | setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ)); |
1063 | ||
1417836e | 1064 | set_irq_handler(cpu_ipi_irq, handle_percpu_irq); |
41c594ab RB |
1065 | } |
1066 | ||
1067 | /* | |
1068 | * SMTC-specific hacks invoked from elsewhere in the kernel. | |
8a1e97ee RB |
1069 | * |
1070 | * smtc_ipi_replay is called from raw_local_irq_restore which is only ever | |
1071 | * called with interrupts disabled. We do rely on interrupts being disabled | |
1072 | * here because using spin_lock_irqsave()/spin_unlock_irqrestore() would | |
1073 | * result in a recursive call to raw_local_irq_restore(). | |
41c594ab RB |
1074 | */ |
1075 | ||
8a1e97ee | 1076 | static void __smtc_ipi_replay(void) |
ac8be955 | 1077 | { |
8a1e97ee RB |
1078 | unsigned int cpu = smp_processor_id(); |
1079 | ||
ac8be955 RB |
1080 | /* |
1081 | * To the extent that we've ever turned interrupts off, | |
1082 | * we may have accumulated deferred IPIs. This is subtle. | |
1083 | * If we use the smtc_ipi_qdepth() macro, we'll get an | |
1084 | * exact number - but we'll also disable interrupts | |
1085 | * and create a window of failure where a new IPI gets | |
1086 | * queued after we test the depth but before we re-enable | |
1087 | * interrupts. So long as IXMT never gets set, however, | |
1088 | * we should be OK: If we pick up something and dispatch | |
1089 | * it here, that's great. If we see nothing, but concurrent | |
1090 | * with this operation, another TC sends us an IPI, IXMT | |
1091 | * is clear, and we'll handle it as a real pseudo-interrupt | |
1092 | * and not a pseudo-pseudo interrupt. | |
1093 | */ | |
8a1e97ee RB |
1094 | if (IPIQ[cpu].depth > 0) { |
1095 | while (1) { | |
1096 | struct smtc_ipi_q *q = &IPIQ[cpu]; | |
1097 | struct smtc_ipi *pipi; | |
1098 | extern void self_ipi(struct smtc_ipi *); | |
1099 | ||
1100 | spin_lock(&q->lock); | |
1101 | pipi = __smtc_ipi_dq(q); | |
1102 | spin_unlock(&q->lock); | |
1103 | if (!pipi) | |
1104 | break; | |
ac8be955 | 1105 | |
ac8be955 | 1106 | self_ipi(pipi); |
8a1e97ee | 1107 | smtc_cpu_stats[cpu].selfipis++; |
ac8be955 RB |
1108 | } |
1109 | } | |
1110 | } | |
1111 | ||
8a1e97ee RB |
1112 | void smtc_ipi_replay(void) |
1113 | { | |
1114 | raw_local_irq_disable(); | |
1115 | __smtc_ipi_replay(); | |
1116 | } | |
1117 | ||
ec43c014 RB |
1118 | EXPORT_SYMBOL(smtc_ipi_replay); |
1119 | ||
41c594ab RB |
1120 | void smtc_idle_loop_hook(void) |
1121 | { | |
c68644d3 | 1122 | #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG |
41c594ab RB |
1123 | int im; |
1124 | int flags; | |
1125 | int mtflags; | |
1126 | int bit; | |
1127 | int vpe; | |
1128 | int tc; | |
1129 | int hook_ntcs; | |
1130 | /* | |
1131 | * printk within DMT-protected regions can deadlock, | |
1132 | * so buffer diagnostic messages for later output. | |
1133 | */ | |
1134 | char *pdb_msg; | |
1135 | char id_ho_db_msg[768]; /* worst-case use should be less than 700 */ | |
1136 | ||
1137 | if (atomic_read(&idle_hook_initialized) == 0) { /* fast test */ | |
1138 | if (atomic_add_return(1, &idle_hook_initialized) == 1) { | |
1139 | int mvpconf0; | |
1140 | /* Tedious stuff to just do once */ | |
1141 | mvpconf0 = read_c0_mvpconf0(); | |
1142 | hook_ntcs = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1; | |
1143 | if (hook_ntcs > NR_CPUS) | |
1144 | hook_ntcs = NR_CPUS; | |
1145 | for (tc = 0; tc < hook_ntcs; tc++) { | |
1146 | tcnoprog[tc] = 0; | |
1147 | clock_hang_reported[tc] = 0; | |
1148 | } | |
1149 | for (vpe = 0; vpe < 2; vpe++) | |
1150 | for (im = 0; im < 8; im++) | |
1151 | imstuckcount[vpe][im] = 0; | |
1152 | printk("Idle loop test hook initialized for %d TCs\n", hook_ntcs); | |
1153 | atomic_set(&idle_hook_initialized, 1000); | |
1154 | } else { | |
1155 | /* Someone else is initializing in parallel - let 'em finish */ | |
1156 | while (atomic_read(&idle_hook_initialized) < 1000) | |
1157 | ; | |
1158 | } | |
1159 | } | |
1160 | ||
1161 | /* Have we stupidly left IXMT set somewhere? */ | |
1162 | if (read_c0_tcstatus() & 0x400) { | |
1163 | write_c0_tcstatus(read_c0_tcstatus() & ~0x400); | |
1164 | ehb(); | |
1165 | printk("Dangling IXMT in cpu_idle()\n"); | |
1166 | } | |
1167 | ||
1168 | /* Have we stupidly left an IM bit turned off? */ | |
1169 | #define IM_LIMIT 2000 | |
1170 | local_irq_save(flags); | |
1171 | mtflags = dmt(); | |
1172 | pdb_msg = &id_ho_db_msg[0]; | |
1173 | im = read_c0_status(); | |
8f8771a0 | 1174 | vpe = current_cpu_data.vpe_id; |
41c594ab RB |
1175 | for (bit = 0; bit < 8; bit++) { |
1176 | /* | |
1177 | * In current prototype, I/O interrupts | |
1178 | * are masked for VPE > 0 | |
1179 | */ | |
1180 | if (vpemask[vpe][bit]) { | |
1181 | if (!(im & (0x100 << bit))) | |
1182 | imstuckcount[vpe][bit]++; | |
1183 | else | |
1184 | imstuckcount[vpe][bit] = 0; | |
1185 | if (imstuckcount[vpe][bit] > IM_LIMIT) { | |
1186 | set_c0_status(0x100 << bit); | |
1187 | ehb(); | |
1188 | imstuckcount[vpe][bit] = 0; | |
1189 | pdb_msg += sprintf(pdb_msg, | |
1190 | "Dangling IM %d fixed for VPE %d\n", bit, | |
1191 | vpe); | |
1192 | } | |
1193 | } | |
1194 | } | |
1195 | ||
1196 | /* | |
1197 | * Now that we limit outstanding timer IPIs, check for hung TC | |
1198 | */ | |
1199 | for (tc = 0; tc < NR_CPUS; tc++) { | |
1200 | /* Don't check ourself - we'll dequeue IPIs just below */ | |
1201 | if ((tc != smp_processor_id()) && | |
ea580401 | 1202 | atomic_read(&ipi_timer_latch[tc]) > timerq_limit) { |
41c594ab RB |
1203 | if (clock_hang_reported[tc] == 0) { |
1204 | pdb_msg += sprintf(pdb_msg, | |
1205 | "TC %d looks hung with timer latch at %d\n", | |
ea580401 | 1206 | tc, atomic_read(&ipi_timer_latch[tc])); |
41c594ab RB |
1207 | clock_hang_reported[tc]++; |
1208 | } | |
1209 | } | |
1210 | } | |
1211 | emt(mtflags); | |
1212 | local_irq_restore(flags); | |
1213 | if (pdb_msg != &id_ho_db_msg[0]) | |
1214 | printk("CPU%d: %s", smp_processor_id(), id_ho_db_msg); | |
c68644d3 | 1215 | #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */ |
ac8be955 | 1216 | |
41c594ab | 1217 | /* |
ac8be955 RB |
1218 | * Replay any accumulated deferred IPIs. If "Instant Replay" |
1219 | * is in use, there should never be any. | |
41c594ab | 1220 | */ |
ac8be955 | 1221 | #ifndef CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY |
8a1e97ee RB |
1222 | { |
1223 | unsigned long flags; | |
1224 | ||
1225 | local_irq_save(flags); | |
1226 | __smtc_ipi_replay(); | |
1227 | local_irq_restore(flags); | |
1228 | } | |
ac8be955 | 1229 | #endif /* CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY */ |
41c594ab RB |
1230 | } |
1231 | ||
1232 | void smtc_soft_dump(void) | |
1233 | { | |
1234 | int i; | |
1235 | ||
1236 | printk("Counter Interrupts taken per CPU (TC)\n"); | |
1237 | for (i=0; i < NR_CPUS; i++) { | |
1238 | printk("%d: %ld\n", i, smtc_cpu_stats[i].timerints); | |
1239 | } | |
1240 | printk("Self-IPI invocations:\n"); | |
1241 | for (i=0; i < NR_CPUS; i++) { | |
1242 | printk("%d: %ld\n", i, smtc_cpu_stats[i].selfipis); | |
1243 | } | |
1244 | smtc_ipi_qdump(); | |
1245 | printk("Timer IPI Backlogs:\n"); | |
1246 | for (i=0; i < NR_CPUS; i++) { | |
ea580401 | 1247 | printk("%d: %d\n", i, atomic_read(&ipi_timer_latch[i])); |
41c594ab RB |
1248 | } |
1249 | printk("%d Recoveries of \"stolen\" FPU\n", | |
1250 | atomic_read(&smtc_fpu_recoveries)); | |
1251 | } | |
1252 | ||
1253 | ||
1254 | /* | |
1255 | * TLB management routines special to SMTC | |
1256 | */ | |
1257 | ||
1258 | void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) | |
1259 | { | |
1260 | unsigned long flags, mtflags, tcstat, prevhalt, asid; | |
1261 | int tlb, i; | |
1262 | ||
1263 | /* | |
1264 | * It would be nice to be able to use a spinlock here, | |
1265 | * but this is invoked from within TLB flush routines | |
1266 | * that protect themselves with DVPE, so if a lock is | |
e0daad44 | 1267 | * held by another TC, it'll never be freed. |
41c594ab RB |
1268 | * |
1269 | * DVPE/DMT must not be done with interrupts enabled, | |
1270 | * so even so most callers will already have disabled | |
1271 | * them, let's be really careful... | |
1272 | */ | |
1273 | ||
1274 | local_irq_save(flags); | |
1275 | if (smtc_status & SMTC_TLB_SHARED) { | |
1276 | mtflags = dvpe(); | |
1277 | tlb = 0; | |
1278 | } else { | |
1279 | mtflags = dmt(); | |
1280 | tlb = cpu_data[cpu].vpe_id; | |
1281 | } | |
1282 | asid = asid_cache(cpu); | |
1283 | ||
1284 | do { | |
1285 | if (!((asid += ASID_INC) & ASID_MASK) ) { | |
1286 | if (cpu_has_vtag_icache) | |
1287 | flush_icache_all(); | |
1288 | /* Traverse all online CPUs (hack requires contigous range) */ | |
b5eb5511 | 1289 | for_each_online_cpu(i) { |
41c594ab RB |
1290 | /* |
1291 | * We don't need to worry about our own CPU, nor those of | |
1292 | * CPUs who don't share our TLB. | |
1293 | */ | |
1294 | if ((i != smp_processor_id()) && | |
1295 | ((smtc_status & SMTC_TLB_SHARED) || | |
1296 | (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))) { | |
1297 | settc(cpu_data[i].tc_id); | |
1298 | prevhalt = read_tc_c0_tchalt() & TCHALT_H; | |
1299 | if (!prevhalt) { | |
1300 | write_tc_c0_tchalt(TCHALT_H); | |
1301 | mips_ihb(); | |
1302 | } | |
1303 | tcstat = read_tc_c0_tcstatus(); | |
1304 | smtc_live_asid[tlb][(tcstat & ASID_MASK)] |= (asiduse)(0x1 << i); | |
1305 | if (!prevhalt) | |
1306 | write_tc_c0_tchalt(0); | |
1307 | } | |
1308 | } | |
1309 | if (!asid) /* fix version if needed */ | |
1310 | asid = ASID_FIRST_VERSION; | |
1311 | local_flush_tlb_all(); /* start new asid cycle */ | |
1312 | } | |
1313 | } while (smtc_live_asid[tlb][(asid & ASID_MASK)]); | |
1314 | ||
1315 | /* | |
1316 | * SMTC shares the TLB within VPEs and possibly across all VPEs. | |
1317 | */ | |
b5eb5511 | 1318 | for_each_online_cpu(i) { |
41c594ab RB |
1319 | if ((smtc_status & SMTC_TLB_SHARED) || |
1320 | (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id)) | |
1321 | cpu_context(i, mm) = asid_cache(i) = asid; | |
1322 | } | |
1323 | ||
1324 | if (smtc_status & SMTC_TLB_SHARED) | |
1325 | evpe(mtflags); | |
1326 | else | |
1327 | emt(mtflags); | |
1328 | local_irq_restore(flags); | |
1329 | } | |
1330 | ||
1331 | /* | |
1332 | * Invoked from macros defined in mmu_context.h | |
1333 | * which must already have disabled interrupts | |
1334 | * and done a DVPE or DMT as appropriate. | |
1335 | */ | |
1336 | ||
1337 | void smtc_flush_tlb_asid(unsigned long asid) | |
1338 | { | |
1339 | int entry; | |
1340 | unsigned long ehi; | |
1341 | ||
1342 | entry = read_c0_wired(); | |
1343 | ||
1344 | /* Traverse all non-wired entries */ | |
1345 | while (entry < current_cpu_data.tlbsize) { | |
1346 | write_c0_index(entry); | |
1347 | ehb(); | |
1348 | tlb_read(); | |
1349 | ehb(); | |
1350 | ehi = read_c0_entryhi(); | |
4bf42d42 | 1351 | if ((ehi & ASID_MASK) == asid) { |
41c594ab RB |
1352 | /* |
1353 | * Invalidate only entries with specified ASID, | |
1354 | * makiing sure all entries differ. | |
1355 | */ | |
1356 | write_c0_entryhi(CKSEG0 + (entry << (PAGE_SHIFT + 1))); | |
1357 | write_c0_entrylo0(0); | |
1358 | write_c0_entrylo1(0); | |
1359 | mtc0_tlbw_hazard(); | |
1360 | tlb_write_indexed(); | |
1361 | } | |
1362 | entry++; | |
1363 | } | |
1364 | write_c0_index(PARKED_INDEX); | |
1365 | tlbw_use_hazard(); | |
1366 | } | |
1367 | ||
1368 | /* | |
1369 | * Support for single-threading cache flush operations. | |
1370 | */ | |
1371 | ||
5868756d | 1372 | static int halt_state_save[NR_CPUS]; |
41c594ab RB |
1373 | |
1374 | /* | |
1375 | * To really, really be sure that nothing is being done | |
1376 | * by other TCs, halt them all. This code assumes that | |
1377 | * a DVPE has already been done, so while their Halted | |
1378 | * state is theoretically architecturally unstable, in | |
1379 | * practice, it's not going to change while we're looking | |
1380 | * at it. | |
1381 | */ | |
1382 | ||
1383 | void smtc_cflush_lockdown(void) | |
1384 | { | |
1385 | int cpu; | |
1386 | ||
1387 | for_each_online_cpu(cpu) { | |
1388 | if (cpu != smp_processor_id()) { | |
1389 | settc(cpu_data[cpu].tc_id); | |
1390 | halt_state_save[cpu] = read_tc_c0_tchalt(); | |
1391 | write_tc_c0_tchalt(TCHALT_H); | |
1392 | } | |
1393 | } | |
1394 | mips_ihb(); | |
1395 | } | |
1396 | ||
1397 | /* It would be cheating to change the cpu_online states during a flush! */ | |
1398 | ||
1399 | void smtc_cflush_release(void) | |
1400 | { | |
1401 | int cpu; | |
1402 | ||
1403 | /* | |
1404 | * Start with a hazard barrier to ensure | |
1405 | * that all CACHE ops have played through. | |
1406 | */ | |
1407 | mips_ihb(); | |
1408 | ||
1409 | for_each_online_cpu(cpu) { | |
1410 | if (cpu != smp_processor_id()) { | |
1411 | settc(cpu_data[cpu].tc_id); | |
1412 | write_tc_c0_tchalt(halt_state_save[cpu]); | |
1413 | } | |
1414 | } | |
1415 | mips_ihb(); | |
1416 | } |