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1da177e4 LT |
1 | /* |
2 | * Copyright 2001 MontaVista Software Inc. | |
3 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net | |
4 | * Copyright (c) 2003, 2004 Maciej W. Rozycki | |
5 | * | |
d9eec1a5 | 6 | * Common time service routines for MIPS machines. |
1da177e4 | 7 | * |
70342287 RB |
8 | * This program is free software; you can redistribute it and/or modify it |
9 | * under the terms of the GNU General Public License as published by the | |
1da177e4 LT |
10 | * Free Software Foundation; either version 2 of the License, or (at your |
11 | * option) any later version. | |
12 | */ | |
656db506 | 13 | #include <linux/bug.h> |
7bcf7717 | 14 | #include <linux/clockchips.h> |
1da177e4 LT |
15 | #include <linux/types.h> |
16 | #include <linux/kernel.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/sched.h> | |
19 | #include <linux/param.h> | |
20 | #include <linux/time.h> | |
21 | #include <linux/timex.h> | |
22 | #include <linux/smp.h> | |
1da177e4 | 23 | #include <linux/spinlock.h> |
73bc256d | 24 | #include <linux/export.h> |
1da177e4 | 25 | |
1da177e4 | 26 | #include <asm/cpu-features.h> |
69f24d17 | 27 | #include <asm/cpu-type.h> |
1da177e4 | 28 | #include <asm/div64.h> |
ea580401 | 29 | #include <asm/smtc_ipi.h> |
1da177e4 LT |
30 | #include <asm/time.h> |
31 | ||
1da177e4 LT |
32 | /* |
33 | * forward reference | |
34 | */ | |
1da177e4 | 35 | DEFINE_SPINLOCK(rtc_lock); |
4b550488 | 36 | EXPORT_SYMBOL(rtc_lock); |
1da177e4 | 37 | |
4b550488 | 38 | int __weak rtc_mips_set_time(unsigned long sec) |
1da177e4 | 39 | { |
4b550488 | 40 | return 0; |
1da177e4 LT |
41 | } |
42 | ||
4b550488 | 43 | int __weak rtc_mips_set_mmss(unsigned long nowtime) |
1da177e4 | 44 | { |
4b550488 | 45 | return rtc_mips_set_time(nowtime); |
1da177e4 LT |
46 | } |
47 | ||
f5ff0a28 RB |
48 | int update_persistent_clock(struct timespec now) |
49 | { | |
50 | return rtc_mips_set_mmss(now.tv_sec); | |
51 | } | |
1da177e4 | 52 | |
46684734 | 53 | static int null_perf_irq(void) |
ba339c03 RB |
54 | { |
55 | return 0; | |
56 | } | |
57 | ||
7d12e780 | 58 | int (*perf_irq)(void) = null_perf_irq; |
ba339c03 | 59 | |
ba339c03 RB |
60 | EXPORT_SYMBOL(perf_irq); |
61 | ||
1da177e4 LT |
62 | /* |
63 | * time_init() - it does the following things. | |
64 | * | |
4b550488 | 65 | * 1) plat_time_init() - |
70342287 RB |
66 | * a) (optional) set up RTC routines, |
67 | * b) (optional) calibrate and set the mips_hpt_frequency | |
16b7b2ac AN |
68 | * (only needed if you intended to use cpu counter as timer interrupt |
69 | * source) | |
4b550488 | 70 | * 2) calculate a couple of cached variables for later usage |
1da177e4 LT |
71 | */ |
72 | ||
1da177e4 LT |
73 | unsigned int mips_hpt_frequency; |
74 | ||
656db506 RB |
75 | /* |
76 | * This function exists in order to cause an error due to a duplicate | |
77 | * definition if platform code should have its own implementation. The hook | |
78 | * to use instead is plat_time_init. plat_time_init does not receive the | |
70342287 | 79 | * irqaction pointer argument anymore. This is because any function which |
656db506 RB |
80 | * initializes an interrupt timer now takes care of its own request_irq rsp. |
81 | * setup_irq calls and each clock_event_device should use its own | |
82 | * struct irqrequest. | |
83 | */ | |
d9eec1a5 | 84 | void __init plat_timer_setup(void) |
7bcf7717 | 85 | { |
656db506 | 86 | BUG(); |
7bcf7717 RB |
87 | } |
88 | ||
5aa85c9f RB |
89 | static __init int cpu_has_mfc0_count_bug(void) |
90 | { | |
91 | switch (current_cpu_type()) { | |
92 | case CPU_R4000PC: | |
93 | case CPU_R4000SC: | |
94 | case CPU_R4000MC: | |
95 | /* | |
96 | * V3.0 is documented as suffering from the mfc0 from count bug. | |
70342287 | 97 | * Afaik this is the last version of the R4000. Later versions |
5aa85c9f RB |
98 | * were marketed as R4400. |
99 | */ | |
100 | return 1; | |
101 | ||
102 | case CPU_R4400PC: | |
103 | case CPU_R4400SC: | |
104 | case CPU_R4400MC: | |
105 | /* | |
25985edc | 106 | * The published errata for the R4400 up to 3.0 say the CPU |
5aa85c9f RB |
107 | * has the mfc0 from count bug. |
108 | */ | |
109 | if ((current_cpu_data.processor_id & 0xff) <= 0x30) | |
110 | return 1; | |
111 | ||
112 | /* | |
ce202cbb | 113 | * we assume newer revisions are ok |
5aa85c9f | 114 | */ |
ce202cbb | 115 | return 0; |
5aa85c9f RB |
116 | } |
117 | ||
118 | return 0; | |
119 | } | |
120 | ||
4b550488 RB |
121 | void __init time_init(void) |
122 | { | |
123 | plat_time_init(); | |
1da177e4 | 124 | |
afddce0c MR |
125 | /* |
126 | * The use of the R4k timer as a clock event takes precedence; | |
127 | * if reading the Count register might interfere with the timer | |
128 | * interrupt, then we don't use the timer as a clock source. | |
129 | * We may still use the timer as a clock source though if the | |
130 | * timer interrupt isn't reliable; the interference doesn't | |
131 | * matter then, because we don't use the interrupt. | |
132 | */ | |
133 | if (mips_clockevent_init() != 0 || !cpu_has_mfc0_count_bug()) | |
d9eec1a5 | 134 | init_mips_clocksource(); |
1da177e4 | 135 | } |