Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
36ccf1c0 | 6 | * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle |
1da177e4 LT |
7 | * Copyright (C) 1995, 1996 Paul M. Antoine |
8 | * Copyright (C) 1998 Ulf Carlsson | |
9 | * Copyright (C) 1999 Silicon Graphics, Inc. | |
10 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
11 | * Copyright (C) 2000, 01 MIPS Technologies, Inc. | |
60b0d655 | 12 | * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki |
1da177e4 | 13 | */ |
8e8a52ed | 14 | #include <linux/bug.h> |
60b0d655 | 15 | #include <linux/compiler.h> |
7aa1c8f4 | 16 | #include <linux/kexec.h> |
1da177e4 | 17 | #include <linux/init.h> |
8742cd23 | 18 | #include <linux/kernel.h> |
f9ded569 | 19 | #include <linux/module.h> |
1da177e4 | 20 | #include <linux/mm.h> |
1da177e4 LT |
21 | #include <linux/sched.h> |
22 | #include <linux/smp.h> | |
1da177e4 LT |
23 | #include <linux/spinlock.h> |
24 | #include <linux/kallsyms.h> | |
e01402b1 | 25 | #include <linux/bootmem.h> |
d4fd1989 | 26 | #include <linux/interrupt.h> |
39b8d525 | 27 | #include <linux/ptrace.h> |
88547001 JW |
28 | #include <linux/kgdb.h> |
29 | #include <linux/kdebug.h> | |
c1bf207d | 30 | #include <linux/kprobes.h> |
69f3a7de | 31 | #include <linux/notifier.h> |
5dd11d5d | 32 | #include <linux/kdb.h> |
ca4d3e67 | 33 | #include <linux/irq.h> |
7f788d2d | 34 | #include <linux/perf_event.h> |
1da177e4 LT |
35 | |
36 | #include <asm/bootinfo.h> | |
37 | #include <asm/branch.h> | |
38 | #include <asm/break.h> | |
69f3a7de | 39 | #include <asm/cop2.h> |
1da177e4 | 40 | #include <asm/cpu.h> |
e50c0a8f | 41 | #include <asm/dsp.h> |
1da177e4 | 42 | #include <asm/fpu.h> |
ba3049ed | 43 | #include <asm/fpu_emulator.h> |
340ee4b9 RB |
44 | #include <asm/mipsregs.h> |
45 | #include <asm/mipsmtregs.h> | |
1da177e4 LT |
46 | #include <asm/module.h> |
47 | #include <asm/pgtable.h> | |
48 | #include <asm/ptrace.h> | |
49 | #include <asm/sections.h> | |
1da177e4 LT |
50 | #include <asm/tlbdebug.h> |
51 | #include <asm/traps.h> | |
52 | #include <asm/uaccess.h> | |
b67b2b70 | 53 | #include <asm/watch.h> |
1da177e4 | 54 | #include <asm/mmu_context.h> |
1da177e4 | 55 | #include <asm/types.h> |
1df0f0ff | 56 | #include <asm/stacktrace.h> |
92bbe1b9 | 57 | #include <asm/uasm.h> |
1da177e4 | 58 | |
c65a5480 AN |
59 | extern void check_wait(void); |
60 | extern asmlinkage void r4k_wait(void); | |
61 | extern asmlinkage void rollback_handle_int(void); | |
e4ac58af | 62 | extern asmlinkage void handle_int(void); |
1da177e4 LT |
63 | extern asmlinkage void handle_tlbm(void); |
64 | extern asmlinkage void handle_tlbl(void); | |
65 | extern asmlinkage void handle_tlbs(void); | |
66 | extern asmlinkage void handle_adel(void); | |
67 | extern asmlinkage void handle_ades(void); | |
68 | extern asmlinkage void handle_ibe(void); | |
69 | extern asmlinkage void handle_dbe(void); | |
70 | extern asmlinkage void handle_sys(void); | |
71 | extern asmlinkage void handle_bp(void); | |
72 | extern asmlinkage void handle_ri(void); | |
5b10496b AN |
73 | extern asmlinkage void handle_ri_rdhwr_vivt(void); |
74 | extern asmlinkage void handle_ri_rdhwr(void); | |
1da177e4 LT |
75 | extern asmlinkage void handle_cpu(void); |
76 | extern asmlinkage void handle_ov(void); | |
77 | extern asmlinkage void handle_tr(void); | |
78 | extern asmlinkage void handle_fpe(void); | |
79 | extern asmlinkage void handle_mdmx(void); | |
80 | extern asmlinkage void handle_watch(void); | |
340ee4b9 | 81 | extern asmlinkage void handle_mt(void); |
e50c0a8f | 82 | extern asmlinkage void handle_dsp(void); |
1da177e4 LT |
83 | extern asmlinkage void handle_mcheck(void); |
84 | extern asmlinkage void handle_reserved(void); | |
85 | ||
12616ed2 | 86 | extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, |
515b029d DD |
87 | struct mips_fpu_struct *ctx, int has_fpu, |
88 | void *__user *fault_addr); | |
1da177e4 LT |
89 | |
90 | void (*board_be_init)(void); | |
91 | int (*board_be_handler)(struct pt_regs *regs, int is_fixup); | |
e01402b1 RB |
92 | void (*board_nmi_handler_setup)(void); |
93 | void (*board_ejtag_handler_setup)(void); | |
94 | void (*board_bind_eic_interrupt)(int irq, int regset); | |
6fb97eff | 95 | void (*board_ebase_setup)(void); |
fcbf1dfd | 96 | void __cpuinitdata(*board_cache_error_setup)(void); |
1da177e4 | 97 | |
4d157d5e | 98 | static void show_raw_backtrace(unsigned long reg29) |
e889d78f | 99 | { |
39b8d525 | 100 | unsigned long *sp = (unsigned long *)(reg29 & ~3); |
e889d78f AN |
101 | unsigned long addr; |
102 | ||
103 | printk("Call Trace:"); | |
104 | #ifdef CONFIG_KALLSYMS | |
105 | printk("\n"); | |
106 | #endif | |
10220c88 TB |
107 | while (!kstack_end(sp)) { |
108 | unsigned long __user *p = | |
109 | (unsigned long __user *)(unsigned long)sp++; | |
110 | if (__get_user(addr, p)) { | |
111 | printk(" (Bad stack address)"); | |
112 | break; | |
39b8d525 | 113 | } |
10220c88 TB |
114 | if (__kernel_text_address(addr)) |
115 | print_ip_sym(addr); | |
e889d78f | 116 | } |
10220c88 | 117 | printk("\n"); |
e889d78f AN |
118 | } |
119 | ||
f66686f7 | 120 | #ifdef CONFIG_KALLSYMS |
1df0f0ff | 121 | int raw_show_trace; |
f66686f7 AN |
122 | static int __init set_raw_show_trace(char *str) |
123 | { | |
124 | raw_show_trace = 1; | |
125 | return 1; | |
126 | } | |
127 | __setup("raw_show_trace", set_raw_show_trace); | |
1df0f0ff | 128 | #endif |
4d157d5e | 129 | |
eae23f2c | 130 | static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) |
f66686f7 | 131 | { |
4d157d5e FBH |
132 | unsigned long sp = regs->regs[29]; |
133 | unsigned long ra = regs->regs[31]; | |
f66686f7 | 134 | unsigned long pc = regs->cp0_epc; |
f66686f7 | 135 | |
e909be82 VW |
136 | if (!task) |
137 | task = current; | |
138 | ||
f66686f7 | 139 | if (raw_show_trace || !__kernel_text_address(pc)) { |
87151ae3 | 140 | show_raw_backtrace(sp); |
f66686f7 AN |
141 | return; |
142 | } | |
143 | printk("Call Trace:\n"); | |
4d157d5e | 144 | do { |
87151ae3 | 145 | print_ip_sym(pc); |
1924600c | 146 | pc = unwind_stack(task, &sp, pc, &ra); |
4d157d5e | 147 | } while (pc); |
f66686f7 AN |
148 | printk("\n"); |
149 | } | |
f66686f7 | 150 | |
1da177e4 LT |
151 | /* |
152 | * This routine abuses get_user()/put_user() to reference pointers | |
153 | * with at least a bit of error checking ... | |
154 | */ | |
eae23f2c RB |
155 | static void show_stacktrace(struct task_struct *task, |
156 | const struct pt_regs *regs) | |
1da177e4 LT |
157 | { |
158 | const int field = 2 * sizeof(unsigned long); | |
159 | long stackdata; | |
160 | int i; | |
5e0373b8 | 161 | unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; |
1da177e4 LT |
162 | |
163 | printk("Stack :"); | |
164 | i = 0; | |
165 | while ((unsigned long) sp & (PAGE_SIZE - 1)) { | |
166 | if (i && ((i % (64 / field)) == 0)) | |
70342287 | 167 | printk("\n "); |
1da177e4 LT |
168 | if (i > 39) { |
169 | printk(" ..."); | |
170 | break; | |
171 | } | |
172 | ||
173 | if (__get_user(stackdata, sp++)) { | |
174 | printk(" (Bad stack address)"); | |
175 | break; | |
176 | } | |
177 | ||
178 | printk(" %0*lx", field, stackdata); | |
179 | i++; | |
180 | } | |
181 | printk("\n"); | |
87151ae3 | 182 | show_backtrace(task, regs); |
f66686f7 AN |
183 | } |
184 | ||
f66686f7 AN |
185 | void show_stack(struct task_struct *task, unsigned long *sp) |
186 | { | |
187 | struct pt_regs regs; | |
188 | if (sp) { | |
189 | regs.regs[29] = (unsigned long)sp; | |
190 | regs.regs[31] = 0; | |
191 | regs.cp0_epc = 0; | |
192 | } else { | |
193 | if (task && task != current) { | |
194 | regs.regs[29] = task->thread.reg29; | |
195 | regs.regs[31] = 0; | |
196 | regs.cp0_epc = task->thread.reg31; | |
5dd11d5d JW |
197 | #ifdef CONFIG_KGDB_KDB |
198 | } else if (atomic_read(&kgdb_active) != -1 && | |
199 | kdb_current_regs) { | |
200 | memcpy(®s, kdb_current_regs, sizeof(regs)); | |
201 | #endif /* CONFIG_KGDB_KDB */ | |
f66686f7 AN |
202 | } else { |
203 | prepare_frametrace(®s); | |
204 | } | |
205 | } | |
206 | show_stacktrace(task, ®s); | |
1da177e4 LT |
207 | } |
208 | ||
209 | /* | |
210 | * The architecture-independent dump_stack generator | |
211 | */ | |
212 | void dump_stack(void) | |
213 | { | |
1666a6fc | 214 | struct pt_regs regs; |
1da177e4 | 215 | |
1666a6fc FBH |
216 | prepare_frametrace(®s); |
217 | show_backtrace(current, ®s); | |
1da177e4 LT |
218 | } |
219 | ||
220 | EXPORT_SYMBOL(dump_stack); | |
221 | ||
e1bb8289 | 222 | static void show_code(unsigned int __user *pc) |
1da177e4 LT |
223 | { |
224 | long i; | |
39b8d525 | 225 | unsigned short __user *pc16 = NULL; |
1da177e4 LT |
226 | |
227 | printk("\nCode:"); | |
228 | ||
39b8d525 RB |
229 | if ((unsigned long)pc & 1) |
230 | pc16 = (unsigned short __user *)((unsigned long)pc & ~1); | |
1da177e4 LT |
231 | for(i = -3 ; i < 6 ; i++) { |
232 | unsigned int insn; | |
39b8d525 | 233 | if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { |
1da177e4 LT |
234 | printk(" (Bad address in epc)\n"); |
235 | break; | |
236 | } | |
39b8d525 | 237 | printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); |
1da177e4 LT |
238 | } |
239 | } | |
240 | ||
eae23f2c | 241 | static void __show_regs(const struct pt_regs *regs) |
1da177e4 LT |
242 | { |
243 | const int field = 2 * sizeof(unsigned long); | |
244 | unsigned int cause = regs->cp0_cause; | |
245 | int i; | |
246 | ||
247 | printk("Cpu %d\n", smp_processor_id()); | |
248 | ||
249 | /* | |
250 | * Saved main processor registers | |
251 | */ | |
252 | for (i = 0; i < 32; ) { | |
253 | if ((i % 4) == 0) | |
254 | printk("$%2d :", i); | |
255 | if (i == 0) | |
256 | printk(" %0*lx", field, 0UL); | |
257 | else if (i == 26 || i == 27) | |
258 | printk(" %*s", field, ""); | |
259 | else | |
260 | printk(" %0*lx", field, regs->regs[i]); | |
261 | ||
262 | i++; | |
263 | if ((i % 4) == 0) | |
264 | printk("\n"); | |
265 | } | |
266 | ||
9693a853 FBH |
267 | #ifdef CONFIG_CPU_HAS_SMARTMIPS |
268 | printk("Acx : %0*lx\n", field, regs->acx); | |
269 | #endif | |
1da177e4 LT |
270 | printk("Hi : %0*lx\n", field, regs->hi); |
271 | printk("Lo : %0*lx\n", field, regs->lo); | |
272 | ||
273 | /* | |
274 | * Saved cp0 registers | |
275 | */ | |
b012cffe RB |
276 | printk("epc : %0*lx %pS\n", field, regs->cp0_epc, |
277 | (void *) regs->cp0_epc); | |
1da177e4 | 278 | printk(" %s\n", print_tainted()); |
b012cffe RB |
279 | printk("ra : %0*lx %pS\n", field, regs->regs[31], |
280 | (void *) regs->regs[31]); | |
1da177e4 | 281 | |
70342287 | 282 | printk("Status: %08x ", (uint32_t) regs->cp0_status); |
1da177e4 | 283 | |
3b2396d9 MR |
284 | if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { |
285 | if (regs->cp0_status & ST0_KUO) | |
286 | printk("KUo "); | |
287 | if (regs->cp0_status & ST0_IEO) | |
288 | printk("IEo "); | |
289 | if (regs->cp0_status & ST0_KUP) | |
290 | printk("KUp "); | |
291 | if (regs->cp0_status & ST0_IEP) | |
292 | printk("IEp "); | |
293 | if (regs->cp0_status & ST0_KUC) | |
294 | printk("KUc "); | |
295 | if (regs->cp0_status & ST0_IEC) | |
296 | printk("IEc "); | |
297 | } else { | |
298 | if (regs->cp0_status & ST0_KX) | |
299 | printk("KX "); | |
300 | if (regs->cp0_status & ST0_SX) | |
301 | printk("SX "); | |
302 | if (regs->cp0_status & ST0_UX) | |
303 | printk("UX "); | |
304 | switch (regs->cp0_status & ST0_KSU) { | |
305 | case KSU_USER: | |
306 | printk("USER "); | |
307 | break; | |
308 | case KSU_SUPERVISOR: | |
309 | printk("SUPERVISOR "); | |
310 | break; | |
311 | case KSU_KERNEL: | |
312 | printk("KERNEL "); | |
313 | break; | |
314 | default: | |
315 | printk("BAD_MODE "); | |
316 | break; | |
317 | } | |
318 | if (regs->cp0_status & ST0_ERL) | |
319 | printk("ERL "); | |
320 | if (regs->cp0_status & ST0_EXL) | |
321 | printk("EXL "); | |
322 | if (regs->cp0_status & ST0_IE) | |
323 | printk("IE "); | |
1da177e4 | 324 | } |
1da177e4 LT |
325 | printk("\n"); |
326 | ||
327 | printk("Cause : %08x\n", cause); | |
328 | ||
329 | cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; | |
330 | if (1 <= cause && cause <= 5) | |
331 | printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); | |
332 | ||
9966db25 RB |
333 | printk("PrId : %08x (%s)\n", read_c0_prid(), |
334 | cpu_name_string()); | |
1da177e4 LT |
335 | } |
336 | ||
eae23f2c RB |
337 | /* |
338 | * FIXME: really the generic show_regs should take a const pointer argument. | |
339 | */ | |
340 | void show_regs(struct pt_regs *regs) | |
341 | { | |
342 | __show_regs((struct pt_regs *)regs); | |
343 | } | |
344 | ||
c1bf207d | 345 | void show_registers(struct pt_regs *regs) |
1da177e4 | 346 | { |
39b8d525 RB |
347 | const int field = 2 * sizeof(unsigned long); |
348 | ||
eae23f2c | 349 | __show_regs(regs); |
1da177e4 | 350 | print_modules(); |
39b8d525 RB |
351 | printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", |
352 | current->comm, current->pid, current_thread_info(), current, | |
353 | field, current_thread_info()->tp_value); | |
354 | if (cpu_has_userlocal) { | |
355 | unsigned long tls; | |
356 | ||
357 | tls = read_c0_userlocal(); | |
358 | if (tls != current_thread_info()->tp_value) | |
359 | printk("*HwTLS: %0*lx\n", field, tls); | |
360 | } | |
361 | ||
f66686f7 | 362 | show_stacktrace(current, regs); |
e1bb8289 | 363 | show_code((unsigned int __user *) regs->cp0_epc); |
1da177e4 LT |
364 | printk("\n"); |
365 | } | |
366 | ||
70dc6f04 DD |
367 | static int regs_to_trapnr(struct pt_regs *regs) |
368 | { | |
369 | return (regs->cp0_cause >> 2) & 0x1f; | |
370 | } | |
371 | ||
4d85f6af | 372 | static DEFINE_RAW_SPINLOCK(die_lock); |
1da177e4 | 373 | |
70dc6f04 | 374 | void __noreturn die(const char *str, struct pt_regs *regs) |
1da177e4 LT |
375 | { |
376 | static int die_counter; | |
ce384d83 | 377 | int sig = SIGSEGV; |
41c594ab | 378 | #ifdef CONFIG_MIPS_MT_SMTC |
8742cd23 | 379 | unsigned long dvpret; |
41c594ab | 380 | #endif /* CONFIG_MIPS_MT_SMTC */ |
1da177e4 | 381 | |
8742cd23 NL |
382 | oops_enter(); |
383 | ||
10423c91 RB |
384 | if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP) |
385 | sig = 0; | |
5dd11d5d | 386 | |
1da177e4 | 387 | console_verbose(); |
4d85f6af | 388 | raw_spin_lock_irq(&die_lock); |
8742cd23 NL |
389 | #ifdef CONFIG_MIPS_MT_SMTC |
390 | dvpret = dvpe(); | |
391 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
41c594ab RB |
392 | bust_spinlocks(1); |
393 | #ifdef CONFIG_MIPS_MT_SMTC | |
394 | mips_mt_regdump(dvpret); | |
395 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
ce384d83 | 396 | |
178086c8 | 397 | printk("%s[#%d]:\n", str, ++die_counter); |
1da177e4 | 398 | show_registers(regs); |
373d4d09 | 399 | add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); |
4d85f6af | 400 | raw_spin_unlock_irq(&die_lock); |
d4fd1989 | 401 | |
8742cd23 NL |
402 | oops_exit(); |
403 | ||
d4fd1989 MB |
404 | if (in_interrupt()) |
405 | panic("Fatal exception in interrupt"); | |
406 | ||
407 | if (panic_on_oops) { | |
ab75dc02 | 408 | printk(KERN_EMERG "Fatal exception: panic in 5 seconds"); |
d4fd1989 MB |
409 | ssleep(5); |
410 | panic("Fatal exception"); | |
411 | } | |
412 | ||
7aa1c8f4 RB |
413 | if (regs && kexec_should_crash(current)) |
414 | crash_kexec(regs); | |
415 | ||
ce384d83 | 416 | do_exit(sig); |
1da177e4 LT |
417 | } |
418 | ||
0510617b TB |
419 | extern struct exception_table_entry __start___dbe_table[]; |
420 | extern struct exception_table_entry __stop___dbe_table[]; | |
1da177e4 | 421 | |
b6dcec9b RB |
422 | __asm__( |
423 | " .section __dbe_table, \"a\"\n" | |
424 | " .previous \n"); | |
1da177e4 LT |
425 | |
426 | /* Given an address, look for it in the exception tables. */ | |
427 | static const struct exception_table_entry *search_dbe_tables(unsigned long addr) | |
428 | { | |
429 | const struct exception_table_entry *e; | |
430 | ||
431 | e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); | |
432 | if (!e) | |
433 | e = search_module_dbetables(addr); | |
434 | return e; | |
435 | } | |
436 | ||
437 | asmlinkage void do_be(struct pt_regs *regs) | |
438 | { | |
439 | const int field = 2 * sizeof(unsigned long); | |
440 | const struct exception_table_entry *fixup = NULL; | |
441 | int data = regs->cp0_cause & 4; | |
442 | int action = MIPS_BE_FATAL; | |
443 | ||
70342287 | 444 | /* XXX For now. Fixme, this searches the wrong table ... */ |
1da177e4 LT |
445 | if (data && !user_mode(regs)) |
446 | fixup = search_dbe_tables(exception_epc(regs)); | |
447 | ||
448 | if (fixup) | |
449 | action = MIPS_BE_FIXUP; | |
450 | ||
451 | if (board_be_handler) | |
28fc582c | 452 | action = board_be_handler(regs, fixup != NULL); |
1da177e4 LT |
453 | |
454 | switch (action) { | |
455 | case MIPS_BE_DISCARD: | |
456 | return; | |
457 | case MIPS_BE_FIXUP: | |
458 | if (fixup) { | |
459 | regs->cp0_epc = fixup->nextinsn; | |
460 | return; | |
461 | } | |
462 | break; | |
463 | default: | |
464 | break; | |
465 | } | |
466 | ||
467 | /* | |
468 | * Assume it would be too dangerous to continue ... | |
469 | */ | |
470 | printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", | |
471 | data ? "Data" : "Instruction", | |
472 | field, regs->cp0_epc, field, regs->regs[31]); | |
70dc6f04 | 473 | if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS) |
88547001 JW |
474 | == NOTIFY_STOP) |
475 | return; | |
476 | ||
1da177e4 LT |
477 | die_if_kernel("Oops", regs); |
478 | force_sig(SIGBUS, current); | |
479 | } | |
480 | ||
1da177e4 | 481 | /* |
60b0d655 | 482 | * ll/sc, rdhwr, sync emulation |
1da177e4 LT |
483 | */ |
484 | ||
485 | #define OPCODE 0xfc000000 | |
486 | #define BASE 0x03e00000 | |
487 | #define RT 0x001f0000 | |
488 | #define OFFSET 0x0000ffff | |
489 | #define LL 0xc0000000 | |
490 | #define SC 0xe0000000 | |
60b0d655 | 491 | #define SPEC0 0x00000000 |
3c37026d RB |
492 | #define SPEC3 0x7c000000 |
493 | #define RD 0x0000f800 | |
494 | #define FUNC 0x0000003f | |
60b0d655 | 495 | #define SYNC 0x0000000f |
3c37026d | 496 | #define RDHWR 0x0000003b |
1da177e4 LT |
497 | |
498 | /* | |
499 | * The ll_bit is cleared by r*_switch.S | |
500 | */ | |
501 | ||
f1e39a4a RB |
502 | unsigned int ll_bit; |
503 | struct task_struct *ll_task; | |
1da177e4 | 504 | |
60b0d655 | 505 | static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 506 | { |
fe00f943 | 507 | unsigned long value, __user *vaddr; |
1da177e4 | 508 | long offset; |
1da177e4 LT |
509 | |
510 | /* | |
511 | * analyse the ll instruction that just caused a ri exception | |
512 | * and put the referenced address to addr. | |
513 | */ | |
514 | ||
515 | /* sign extend offset */ | |
516 | offset = opcode & OFFSET; | |
517 | offset <<= 16; | |
518 | offset >>= 16; | |
519 | ||
fe00f943 | 520 | vaddr = (unsigned long __user *) |
b9688310 | 521 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); |
1da177e4 | 522 | |
60b0d655 MR |
523 | if ((unsigned long)vaddr & 3) |
524 | return SIGBUS; | |
525 | if (get_user(value, vaddr)) | |
526 | return SIGSEGV; | |
1da177e4 LT |
527 | |
528 | preempt_disable(); | |
529 | ||
530 | if (ll_task == NULL || ll_task == current) { | |
531 | ll_bit = 1; | |
532 | } else { | |
533 | ll_bit = 0; | |
534 | } | |
535 | ll_task = current; | |
536 | ||
537 | preempt_enable(); | |
538 | ||
539 | regs->regs[(opcode & RT) >> 16] = value; | |
540 | ||
60b0d655 | 541 | return 0; |
1da177e4 LT |
542 | } |
543 | ||
60b0d655 | 544 | static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 545 | { |
fe00f943 RB |
546 | unsigned long __user *vaddr; |
547 | unsigned long reg; | |
1da177e4 | 548 | long offset; |
1da177e4 LT |
549 | |
550 | /* | |
551 | * analyse the sc instruction that just caused a ri exception | |
552 | * and put the referenced address to addr. | |
553 | */ | |
554 | ||
555 | /* sign extend offset */ | |
556 | offset = opcode & OFFSET; | |
557 | offset <<= 16; | |
558 | offset >>= 16; | |
559 | ||
fe00f943 | 560 | vaddr = (unsigned long __user *) |
b9688310 | 561 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); |
1da177e4 LT |
562 | reg = (opcode & RT) >> 16; |
563 | ||
60b0d655 MR |
564 | if ((unsigned long)vaddr & 3) |
565 | return SIGBUS; | |
1da177e4 LT |
566 | |
567 | preempt_disable(); | |
568 | ||
569 | if (ll_bit == 0 || ll_task != current) { | |
570 | regs->regs[reg] = 0; | |
571 | preempt_enable(); | |
60b0d655 | 572 | return 0; |
1da177e4 LT |
573 | } |
574 | ||
575 | preempt_enable(); | |
576 | ||
60b0d655 MR |
577 | if (put_user(regs->regs[reg], vaddr)) |
578 | return SIGSEGV; | |
1da177e4 LT |
579 | |
580 | regs->regs[reg] = 1; | |
581 | ||
60b0d655 | 582 | return 0; |
1da177e4 LT |
583 | } |
584 | ||
585 | /* | |
586 | * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both | |
587 | * opcodes are supposed to result in coprocessor unusable exceptions if | |
588 | * executed on ll/sc-less processors. That's the theory. In practice a | |
589 | * few processors such as NEC's VR4100 throw reserved instruction exceptions | |
590 | * instead, so we're doing the emulation thing in both exception handlers. | |
591 | */ | |
60b0d655 | 592 | static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 593 | { |
7f788d2d DCZ |
594 | if ((opcode & OPCODE) == LL) { |
595 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 596 | 1, regs, 0); |
60b0d655 | 597 | return simulate_ll(regs, opcode); |
7f788d2d DCZ |
598 | } |
599 | if ((opcode & OPCODE) == SC) { | |
600 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 601 | 1, regs, 0); |
60b0d655 | 602 | return simulate_sc(regs, opcode); |
7f788d2d | 603 | } |
1da177e4 | 604 | |
60b0d655 | 605 | return -1; /* Must be something else ... */ |
1da177e4 LT |
606 | } |
607 | ||
3c37026d RB |
608 | /* |
609 | * Simulate trapping 'rdhwr' instructions to provide user accessible | |
1f5826bd | 610 | * registers not implemented in hardware. |
3c37026d | 611 | */ |
60b0d655 | 612 | static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode) |
3c37026d | 613 | { |
dc8f6029 | 614 | struct thread_info *ti = task_thread_info(current); |
3c37026d RB |
615 | |
616 | if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { | |
617 | int rd = (opcode & RD) >> 11; | |
618 | int rt = (opcode & RT) >> 16; | |
7f788d2d | 619 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, |
a8b0ca17 | 620 | 1, regs, 0); |
3c37026d | 621 | switch (rd) { |
1f5826bd CD |
622 | case 0: /* CPU number */ |
623 | regs->regs[rt] = smp_processor_id(); | |
624 | return 0; | |
625 | case 1: /* SYNCI length */ | |
626 | regs->regs[rt] = min(current_cpu_data.dcache.linesz, | |
627 | current_cpu_data.icache.linesz); | |
628 | return 0; | |
629 | case 2: /* Read count register */ | |
630 | regs->regs[rt] = read_c0_count(); | |
631 | return 0; | |
632 | case 3: /* Count register resolution */ | |
633 | switch (current_cpu_data.cputype) { | |
634 | case CPU_20KC: | |
635 | case CPU_25KF: | |
636 | regs->regs[rt] = 1; | |
637 | break; | |
3c37026d | 638 | default: |
1f5826bd CD |
639 | regs->regs[rt] = 2; |
640 | } | |
641 | return 0; | |
642 | case 29: | |
643 | regs->regs[rt] = ti->tp_value; | |
644 | return 0; | |
645 | default: | |
646 | return -1; | |
3c37026d RB |
647 | } |
648 | } | |
649 | ||
56ebd51b | 650 | /* Not ours. */ |
60b0d655 MR |
651 | return -1; |
652 | } | |
e5679882 | 653 | |
60b0d655 MR |
654 | static int simulate_sync(struct pt_regs *regs, unsigned int opcode) |
655 | { | |
7f788d2d DCZ |
656 | if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) { |
657 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 658 | 1, regs, 0); |
60b0d655 | 659 | return 0; |
7f788d2d | 660 | } |
60b0d655 MR |
661 | |
662 | return -1; /* Must be something else ... */ | |
3c37026d RB |
663 | } |
664 | ||
1da177e4 LT |
665 | asmlinkage void do_ov(struct pt_regs *regs) |
666 | { | |
667 | siginfo_t info; | |
668 | ||
36ccf1c0 RB |
669 | die_if_kernel("Integer overflow", regs); |
670 | ||
1da177e4 LT |
671 | info.si_code = FPE_INTOVF; |
672 | info.si_signo = SIGFPE; | |
673 | info.si_errno = 0; | |
fe00f943 | 674 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
675 | force_sig_info(SIGFPE, &info, current); |
676 | } | |
677 | ||
102cedc3 | 678 | int process_fpemu_return(int sig, void __user *fault_addr) |
515b029d DD |
679 | { |
680 | if (sig == SIGSEGV || sig == SIGBUS) { | |
681 | struct siginfo si = {0}; | |
682 | si.si_addr = fault_addr; | |
683 | si.si_signo = sig; | |
684 | if (sig == SIGSEGV) { | |
685 | if (find_vma(current->mm, (unsigned long)fault_addr)) | |
686 | si.si_code = SEGV_ACCERR; | |
687 | else | |
688 | si.si_code = SEGV_MAPERR; | |
689 | } else { | |
690 | si.si_code = BUS_ADRERR; | |
691 | } | |
692 | force_sig_info(sig, &si, current); | |
693 | return 1; | |
694 | } else if (sig) { | |
695 | force_sig(sig, current); | |
696 | return 1; | |
697 | } else { | |
698 | return 0; | |
699 | } | |
700 | } | |
701 | ||
1da177e4 LT |
702 | /* |
703 | * XXX Delayed fp exceptions when doing a lazy ctx switch XXX | |
704 | */ | |
705 | asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) | |
706 | { | |
515b029d | 707 | siginfo_t info = {0}; |
948a34cf | 708 | |
70dc6f04 | 709 | if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE) |
88547001 JW |
710 | == NOTIFY_STOP) |
711 | return; | |
57725f9e CD |
712 | die_if_kernel("FP exception in kernel code", regs); |
713 | ||
1da177e4 LT |
714 | if (fcr31 & FPU_CSR_UNI_X) { |
715 | int sig; | |
515b029d | 716 | void __user *fault_addr = NULL; |
1da177e4 | 717 | |
1da177e4 | 718 | /* |
a3dddd56 | 719 | * Unimplemented operation exception. If we've got the full |
1da177e4 LT |
720 | * software emulator on-board, let's use it... |
721 | * | |
722 | * Force FPU to dump state into task/thread context. We're | |
723 | * moving a lot of data here for what is probably a single | |
724 | * instruction, but the alternative is to pre-decode the FP | |
725 | * register operands before invoking the emulator, which seems | |
726 | * a bit extreme for what should be an infrequent event. | |
727 | */ | |
cd21dfcf | 728 | /* Ensure 'resume' not overwrite saved fp context again. */ |
53dc8028 | 729 | lose_fpu(1); |
1da177e4 LT |
730 | |
731 | /* Run the emulator */ | |
515b029d DD |
732 | sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, |
733 | &fault_addr); | |
1da177e4 LT |
734 | |
735 | /* | |
736 | * We can't allow the emulated instruction to leave any of | |
737 | * the cause bit set in $fcr31. | |
738 | */ | |
eae89076 | 739 | current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; |
1da177e4 LT |
740 | |
741 | /* Restore the hardware register state */ | |
70342287 | 742 | own_fpu(1); /* Using the FPU again. */ |
1da177e4 LT |
743 | |
744 | /* If something went wrong, signal */ | |
515b029d | 745 | process_fpemu_return(sig, fault_addr); |
1da177e4 LT |
746 | |
747 | return; | |
948a34cf TS |
748 | } else if (fcr31 & FPU_CSR_INV_X) |
749 | info.si_code = FPE_FLTINV; | |
750 | else if (fcr31 & FPU_CSR_DIV_X) | |
751 | info.si_code = FPE_FLTDIV; | |
752 | else if (fcr31 & FPU_CSR_OVF_X) | |
753 | info.si_code = FPE_FLTOVF; | |
754 | else if (fcr31 & FPU_CSR_UDF_X) | |
755 | info.si_code = FPE_FLTUND; | |
756 | else if (fcr31 & FPU_CSR_INE_X) | |
757 | info.si_code = FPE_FLTRES; | |
758 | else | |
759 | info.si_code = __SI_FAULT; | |
760 | info.si_signo = SIGFPE; | |
761 | info.si_errno = 0; | |
762 | info.si_addr = (void __user *) regs->cp0_epc; | |
763 | force_sig_info(SIGFPE, &info, current); | |
1da177e4 LT |
764 | } |
765 | ||
df270051 RB |
766 | static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, |
767 | const char *str) | |
1da177e4 | 768 | { |
1da177e4 | 769 | siginfo_t info; |
df270051 | 770 | char b[40]; |
1da177e4 | 771 | |
5dd11d5d | 772 | #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP |
70dc6f04 | 773 | if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) |
5dd11d5d JW |
774 | return; |
775 | #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ | |
776 | ||
70dc6f04 | 777 | if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) |
88547001 JW |
778 | return; |
779 | ||
1da177e4 | 780 | /* |
df270051 RB |
781 | * A short test says that IRIX 5.3 sends SIGTRAP for all trap |
782 | * insns, even for trap and break codes that indicate arithmetic | |
783 | * failures. Weird ... | |
1da177e4 LT |
784 | * But should we continue the brokenness??? --macro |
785 | */ | |
df270051 RB |
786 | switch (code) { |
787 | case BRK_OVERFLOW: | |
788 | case BRK_DIVZERO: | |
789 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); | |
790 | die_if_kernel(b, regs); | |
791 | if (code == BRK_DIVZERO) | |
1da177e4 LT |
792 | info.si_code = FPE_INTDIV; |
793 | else | |
794 | info.si_code = FPE_INTOVF; | |
795 | info.si_signo = SIGFPE; | |
796 | info.si_errno = 0; | |
fe00f943 | 797 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
798 | force_sig_info(SIGFPE, &info, current); |
799 | break; | |
63dc68a8 | 800 | case BRK_BUG: |
df270051 RB |
801 | die_if_kernel("Kernel bug detected", regs); |
802 | force_sig(SIGTRAP, current); | |
63dc68a8 | 803 | break; |
ba3049ed RB |
804 | case BRK_MEMU: |
805 | /* | |
806 | * Address errors may be deliberately induced by the FPU | |
807 | * emulator to retake control of the CPU after executing the | |
808 | * instruction in the delay slot of an emulated branch. | |
809 | * | |
810 | * Terminate if exception was recognized as a delay slot return | |
811 | * otherwise handle as normal. | |
812 | */ | |
813 | if (do_dsemulret(regs)) | |
814 | return; | |
815 | ||
816 | die_if_kernel("Math emu break/trap", regs); | |
817 | force_sig(SIGTRAP, current); | |
818 | break; | |
1da177e4 | 819 | default: |
df270051 RB |
820 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); |
821 | die_if_kernel(b, regs); | |
1da177e4 LT |
822 | force_sig(SIGTRAP, current); |
823 | } | |
df270051 RB |
824 | } |
825 | ||
826 | asmlinkage void do_bp(struct pt_regs *regs) | |
827 | { | |
828 | unsigned int opcode, bcode; | |
829 | ||
830 | if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) | |
831 | goto out_sigsegv; | |
832 | ||
833 | /* | |
834 | * There is the ancient bug in the MIPS assemblers that the break | |
835 | * code starts left to bit 16 instead to bit 6 in the opcode. | |
836 | * Gas is bug-compatible, but not always, grrr... | |
837 | * We handle both cases with a simple heuristics. --macro | |
838 | */ | |
839 | bcode = ((opcode >> 6) & ((1 << 20) - 1)); | |
840 | if (bcode >= (1 << 10)) | |
841 | bcode >>= 10; | |
842 | ||
c1bf207d DD |
843 | /* |
844 | * notify the kprobe handlers, if instruction is likely to | |
845 | * pertain to them. | |
846 | */ | |
847 | switch (bcode) { | |
848 | case BRK_KPROBE_BP: | |
70dc6f04 | 849 | if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) |
c1bf207d DD |
850 | return; |
851 | else | |
852 | break; | |
853 | case BRK_KPROBE_SSTEPBP: | |
70dc6f04 | 854 | if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) |
c1bf207d DD |
855 | return; |
856 | else | |
857 | break; | |
858 | default: | |
859 | break; | |
860 | } | |
861 | ||
df270051 | 862 | do_trap_or_bp(regs, bcode, "Break"); |
90fccb13 | 863 | return; |
e5679882 RB |
864 | |
865 | out_sigsegv: | |
866 | force_sig(SIGSEGV, current); | |
1da177e4 LT |
867 | } |
868 | ||
869 | asmlinkage void do_tr(struct pt_regs *regs) | |
870 | { | |
871 | unsigned int opcode, tcode = 0; | |
1da177e4 | 872 | |
ba755f8e | 873 | if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) |
e5679882 | 874 | goto out_sigsegv; |
1da177e4 LT |
875 | |
876 | /* Immediate versions don't provide a code. */ | |
877 | if (!(opcode & OPCODE)) | |
878 | tcode = ((opcode >> 6) & ((1 << 10) - 1)); | |
879 | ||
df270051 | 880 | do_trap_or_bp(regs, tcode, "Trap"); |
90fccb13 | 881 | return; |
e5679882 RB |
882 | |
883 | out_sigsegv: | |
884 | force_sig(SIGSEGV, current); | |
1da177e4 LT |
885 | } |
886 | ||
887 | asmlinkage void do_ri(struct pt_regs *regs) | |
888 | { | |
60b0d655 MR |
889 | unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); |
890 | unsigned long old_epc = regs->cp0_epc; | |
891 | unsigned int opcode = 0; | |
892 | int status = -1; | |
1da177e4 | 893 | |
70dc6f04 | 894 | if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL) |
88547001 JW |
895 | == NOTIFY_STOP) |
896 | return; | |
897 | ||
60b0d655 | 898 | die_if_kernel("Reserved instruction in kernel code", regs); |
1da177e4 | 899 | |
60b0d655 | 900 | if (unlikely(compute_return_epc(regs) < 0)) |
3c37026d RB |
901 | return; |
902 | ||
60b0d655 MR |
903 | if (unlikely(get_user(opcode, epc) < 0)) |
904 | status = SIGSEGV; | |
905 | ||
906 | if (!cpu_has_llsc && status < 0) | |
907 | status = simulate_llsc(regs, opcode); | |
908 | ||
909 | if (status < 0) | |
910 | status = simulate_rdhwr(regs, opcode); | |
911 | ||
912 | if (status < 0) | |
913 | status = simulate_sync(regs, opcode); | |
914 | ||
915 | if (status < 0) | |
916 | status = SIGILL; | |
917 | ||
918 | if (unlikely(status > 0)) { | |
919 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
920 | force_sig(status, current); | |
921 | } | |
1da177e4 LT |
922 | } |
923 | ||
d223a861 RB |
924 | /* |
925 | * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've | |
926 | * emulated more than some threshold number of instructions, force migration to | |
927 | * a "CPU" that has FP support. | |
928 | */ | |
929 | static void mt_ase_fp_affinity(void) | |
930 | { | |
931 | #ifdef CONFIG_MIPS_MT_FPAFF | |
932 | if (mt_fpemul_threshold > 0 && | |
933 | ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { | |
934 | /* | |
935 | * If there's no FPU present, or if the application has already | |
936 | * restricted the allowed set to exclude any CPUs with FPUs, | |
937 | * we'll skip the procedure. | |
938 | */ | |
939 | if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { | |
940 | cpumask_t tmask; | |
941 | ||
9cc12363 KK |
942 | current->thread.user_cpus_allowed |
943 | = current->cpus_allowed; | |
944 | cpus_and(tmask, current->cpus_allowed, | |
945 | mt_fpu_cpumask); | |
ed1bbdef | 946 | set_cpus_allowed_ptr(current, &tmask); |
293c5bd1 | 947 | set_thread_flag(TIF_FPUBOUND); |
d223a861 RB |
948 | } |
949 | } | |
950 | #endif /* CONFIG_MIPS_MT_FPAFF */ | |
951 | } | |
952 | ||
69f3a7de RB |
953 | /* |
954 | * No lock; only written during early bootup by CPU 0. | |
955 | */ | |
956 | static RAW_NOTIFIER_HEAD(cu2_chain); | |
957 | ||
958 | int __ref register_cu2_notifier(struct notifier_block *nb) | |
959 | { | |
960 | return raw_notifier_chain_register(&cu2_chain, nb); | |
961 | } | |
962 | ||
963 | int cu2_notifier_call_chain(unsigned long val, void *v) | |
964 | { | |
965 | return raw_notifier_call_chain(&cu2_chain, val, v); | |
966 | } | |
967 | ||
968 | static int default_cu2_call(struct notifier_block *nfb, unsigned long action, | |
70342287 | 969 | void *data) |
69f3a7de RB |
970 | { |
971 | struct pt_regs *regs = data; | |
972 | ||
973 | switch (action) { | |
974 | default: | |
975 | die_if_kernel("Unhandled kernel unaligned access or invalid " | |
976 | "instruction", regs); | |
70342287 | 977 | /* Fall through */ |
69f3a7de RB |
978 | |
979 | case CU2_EXCEPTION: | |
980 | force_sig(SIGILL, current); | |
981 | } | |
982 | ||
983 | return NOTIFY_OK; | |
984 | } | |
985 | ||
1da177e4 LT |
986 | asmlinkage void do_cpu(struct pt_regs *regs) |
987 | { | |
60b0d655 MR |
988 | unsigned int __user *epc; |
989 | unsigned long old_epc; | |
990 | unsigned int opcode; | |
1da177e4 | 991 | unsigned int cpid; |
60b0d655 | 992 | int status; |
f9bb4cf3 | 993 | unsigned long __maybe_unused flags; |
1da177e4 | 994 | |
5323180d AN |
995 | die_if_kernel("do_cpu invoked from kernel context!", regs); |
996 | ||
1da177e4 LT |
997 | cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; |
998 | ||
999 | switch (cpid) { | |
1000 | case 0: | |
60b0d655 MR |
1001 | epc = (unsigned int __user *)exception_epc(regs); |
1002 | old_epc = regs->cp0_epc; | |
1003 | opcode = 0; | |
1004 | status = -1; | |
1da177e4 | 1005 | |
60b0d655 | 1006 | if (unlikely(compute_return_epc(regs) < 0)) |
1da177e4 | 1007 | return; |
3c37026d | 1008 | |
60b0d655 MR |
1009 | if (unlikely(get_user(opcode, epc) < 0)) |
1010 | status = SIGSEGV; | |
1011 | ||
1012 | if (!cpu_has_llsc && status < 0) | |
1013 | status = simulate_llsc(regs, opcode); | |
1014 | ||
1015 | if (status < 0) | |
1016 | status = simulate_rdhwr(regs, opcode); | |
1017 | ||
1018 | if (status < 0) | |
1019 | status = SIGILL; | |
1020 | ||
1021 | if (unlikely(status > 0)) { | |
1022 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
1023 | force_sig(status, current); | |
1024 | } | |
1025 | ||
1026 | return; | |
1da177e4 | 1027 | |
051ff44a MR |
1028 | case 3: |
1029 | /* | |
1030 | * Old (MIPS I and MIPS II) processors will set this code | |
1031 | * for COP1X opcode instructions that replaced the original | |
70342287 | 1032 | * COP3 space. We don't limit COP1 space instructions in |
051ff44a MR |
1033 | * the emulator according to the CPU ISA, so we want to |
1034 | * treat COP1X instructions consistently regardless of which | |
70342287 | 1035 | * code the CPU chose. Therefore we redirect this trap to |
051ff44a MR |
1036 | * the FP emulator too. |
1037 | * | |
1038 | * Then some newer FPU-less processors use this code | |
1039 | * erroneously too, so they are covered by this choice | |
1040 | * as well. | |
1041 | */ | |
1042 | if (raw_cpu_has_fpu) | |
1043 | break; | |
1044 | /* Fall through. */ | |
1045 | ||
1da177e4 | 1046 | case 1: |
70342287 | 1047 | if (used_math()) /* Using the FPU again. */ |
53dc8028 | 1048 | own_fpu(1); |
70342287 | 1049 | else { /* First time FPU user. */ |
1da177e4 LT |
1050 | init_fpu(); |
1051 | set_used_math(); | |
1052 | } | |
1053 | ||
5323180d | 1054 | if (!raw_cpu_has_fpu) { |
e04582b7 | 1055 | int sig; |
515b029d | 1056 | void __user *fault_addr = NULL; |
e04582b7 | 1057 | sig = fpu_emulator_cop1Handler(regs, |
515b029d DD |
1058 | ¤t->thread.fpu, |
1059 | 0, &fault_addr); | |
1060 | if (!process_fpemu_return(sig, fault_addr)) | |
d223a861 | 1061 | mt_ase_fp_affinity(); |
1da177e4 LT |
1062 | } |
1063 | ||
1da177e4 LT |
1064 | return; |
1065 | ||
1066 | case 2: | |
69f3a7de | 1067 | raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); |
55dc9d51 | 1068 | return; |
1da177e4 LT |
1069 | } |
1070 | ||
1071 | force_sig(SIGILL, current); | |
1072 | } | |
1073 | ||
1074 | asmlinkage void do_mdmx(struct pt_regs *regs) | |
1075 | { | |
1076 | force_sig(SIGILL, current); | |
1077 | } | |
1078 | ||
8bc6d05b DD |
1079 | /* |
1080 | * Called with interrupts disabled. | |
1081 | */ | |
1da177e4 LT |
1082 | asmlinkage void do_watch(struct pt_regs *regs) |
1083 | { | |
b67b2b70 DD |
1084 | u32 cause; |
1085 | ||
1da177e4 | 1086 | /* |
b67b2b70 DD |
1087 | * Clear WP (bit 22) bit of cause register so we don't loop |
1088 | * forever. | |
1da177e4 | 1089 | */ |
b67b2b70 DD |
1090 | cause = read_c0_cause(); |
1091 | cause &= ~(1 << 22); | |
1092 | write_c0_cause(cause); | |
1093 | ||
1094 | /* | |
1095 | * If the current thread has the watch registers loaded, save | |
1096 | * their values and send SIGTRAP. Otherwise another thread | |
1097 | * left the registers set, clear them and continue. | |
1098 | */ | |
1099 | if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { | |
1100 | mips_read_watch_registers(); | |
8bc6d05b | 1101 | local_irq_enable(); |
b67b2b70 | 1102 | force_sig(SIGTRAP, current); |
8bc6d05b | 1103 | } else { |
b67b2b70 | 1104 | mips_clear_watch_registers(); |
8bc6d05b DD |
1105 | local_irq_enable(); |
1106 | } | |
1da177e4 LT |
1107 | } |
1108 | ||
1109 | asmlinkage void do_mcheck(struct pt_regs *regs) | |
1110 | { | |
cac4bcbc RB |
1111 | const int field = 2 * sizeof(unsigned long); |
1112 | int multi_match = regs->cp0_status & ST0_TS; | |
1113 | ||
1da177e4 | 1114 | show_regs(regs); |
cac4bcbc RB |
1115 | |
1116 | if (multi_match) { | |
70342287 | 1117 | printk("Index : %0x\n", read_c0_index()); |
cac4bcbc RB |
1118 | printk("Pagemask: %0x\n", read_c0_pagemask()); |
1119 | printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); | |
1120 | printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); | |
1121 | printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); | |
1122 | printk("\n"); | |
1123 | dump_tlb_all(); | |
1124 | } | |
1125 | ||
e1bb8289 | 1126 | show_code((unsigned int __user *) regs->cp0_epc); |
cac4bcbc | 1127 | |
1da177e4 LT |
1128 | /* |
1129 | * Some chips may have other causes of machine check (e.g. SB1 | |
1130 | * graduation timer) | |
1131 | */ | |
1132 | panic("Caught Machine Check exception - %scaused by multiple " | |
1133 | "matching entries in the TLB.", | |
cac4bcbc | 1134 | (multi_match) ? "" : "not "); |
1da177e4 LT |
1135 | } |
1136 | ||
340ee4b9 RB |
1137 | asmlinkage void do_mt(struct pt_regs *regs) |
1138 | { | |
41c594ab RB |
1139 | int subcode; |
1140 | ||
41c594ab RB |
1141 | subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) |
1142 | >> VPECONTROL_EXCPT_SHIFT; | |
1143 | switch (subcode) { | |
1144 | case 0: | |
e35a5e35 | 1145 | printk(KERN_DEBUG "Thread Underflow\n"); |
41c594ab RB |
1146 | break; |
1147 | case 1: | |
e35a5e35 | 1148 | printk(KERN_DEBUG "Thread Overflow\n"); |
41c594ab RB |
1149 | break; |
1150 | case 2: | |
e35a5e35 | 1151 | printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); |
41c594ab RB |
1152 | break; |
1153 | case 3: | |
e35a5e35 | 1154 | printk(KERN_DEBUG "Gating Storage Exception\n"); |
41c594ab RB |
1155 | break; |
1156 | case 4: | |
e35a5e35 | 1157 | printk(KERN_DEBUG "YIELD Scheduler Exception\n"); |
41c594ab RB |
1158 | break; |
1159 | case 5: | |
f232c7e8 | 1160 | printk(KERN_DEBUG "Gating Storage Scheduler Exception\n"); |
41c594ab RB |
1161 | break; |
1162 | default: | |
e35a5e35 | 1163 | printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", |
41c594ab RB |
1164 | subcode); |
1165 | break; | |
1166 | } | |
340ee4b9 RB |
1167 | die_if_kernel("MIPS MT Thread exception in kernel", regs); |
1168 | ||
1169 | force_sig(SIGILL, current); | |
1170 | } | |
1171 | ||
1172 | ||
e50c0a8f RB |
1173 | asmlinkage void do_dsp(struct pt_regs *regs) |
1174 | { | |
1175 | if (cpu_has_dsp) | |
ab75dc02 | 1176 | panic("Unexpected DSP exception"); |
e50c0a8f RB |
1177 | |
1178 | force_sig(SIGILL, current); | |
1179 | } | |
1180 | ||
1da177e4 LT |
1181 | asmlinkage void do_reserved(struct pt_regs *regs) |
1182 | { | |
1183 | /* | |
70342287 | 1184 | * Game over - no way to handle this if it ever occurs. Most probably |
1da177e4 LT |
1185 | * caused by a new unknown cpu type or after another deadly |
1186 | * hard/software error. | |
1187 | */ | |
1188 | show_regs(regs); | |
1189 | panic("Caught reserved exception %ld - should not happen.", | |
1190 | (regs->cp0_cause & 0x7f) >> 2); | |
1191 | } | |
1192 | ||
39b8d525 RB |
1193 | static int __initdata l1parity = 1; |
1194 | static int __init nol1parity(char *s) | |
1195 | { | |
1196 | l1parity = 0; | |
1197 | return 1; | |
1198 | } | |
1199 | __setup("nol1par", nol1parity); | |
1200 | static int __initdata l2parity = 1; | |
1201 | static int __init nol2parity(char *s) | |
1202 | { | |
1203 | l2parity = 0; | |
1204 | return 1; | |
1205 | } | |
1206 | __setup("nol2par", nol2parity); | |
1207 | ||
1da177e4 LT |
1208 | /* |
1209 | * Some MIPS CPUs can enable/disable for cache parity detection, but do | |
1210 | * it different ways. | |
1211 | */ | |
1212 | static inline void parity_protection_init(void) | |
1213 | { | |
10cc3529 | 1214 | switch (current_cpu_type()) { |
1da177e4 | 1215 | case CPU_24K: |
98a41de9 | 1216 | case CPU_34K: |
39b8d525 RB |
1217 | case CPU_74K: |
1218 | case CPU_1004K: | |
1219 | { | |
1220 | #define ERRCTL_PE 0x80000000 | |
1221 | #define ERRCTL_L2P 0x00800000 | |
1222 | unsigned long errctl; | |
1223 | unsigned int l1parity_present, l2parity_present; | |
1224 | ||
1225 | errctl = read_c0_ecc(); | |
1226 | errctl &= ~(ERRCTL_PE|ERRCTL_L2P); | |
1227 | ||
1228 | /* probe L1 parity support */ | |
1229 | write_c0_ecc(errctl | ERRCTL_PE); | |
1230 | back_to_back_c0_hazard(); | |
1231 | l1parity_present = (read_c0_ecc() & ERRCTL_PE); | |
1232 | ||
1233 | /* probe L2 parity support */ | |
1234 | write_c0_ecc(errctl|ERRCTL_L2P); | |
1235 | back_to_back_c0_hazard(); | |
1236 | l2parity_present = (read_c0_ecc() & ERRCTL_L2P); | |
1237 | ||
1238 | if (l1parity_present && l2parity_present) { | |
1239 | if (l1parity) | |
1240 | errctl |= ERRCTL_PE; | |
1241 | if (l1parity ^ l2parity) | |
1242 | errctl |= ERRCTL_L2P; | |
1243 | } else if (l1parity_present) { | |
1244 | if (l1parity) | |
1245 | errctl |= ERRCTL_PE; | |
1246 | } else if (l2parity_present) { | |
1247 | if (l2parity) | |
1248 | errctl |= ERRCTL_L2P; | |
1249 | } else { | |
1250 | /* No parity available */ | |
1251 | } | |
1252 | ||
1253 | printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); | |
1254 | ||
1255 | write_c0_ecc(errctl); | |
1256 | back_to_back_c0_hazard(); | |
1257 | errctl = read_c0_ecc(); | |
1258 | printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); | |
1259 | ||
1260 | if (l1parity_present) | |
1261 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1262 | (errctl & ERRCTL_PE) ? "en" : "dis"); | |
1263 | ||
1264 | if (l2parity_present) { | |
1265 | if (l1parity_present && l1parity) | |
1266 | errctl ^= ERRCTL_L2P; | |
1267 | printk(KERN_INFO "L2 cache parity protection %sabled\n", | |
1268 | (errctl & ERRCTL_L2P) ? "en" : "dis"); | |
1269 | } | |
1270 | } | |
1271 | break; | |
1272 | ||
1da177e4 | 1273 | case CPU_5KC: |
78d4803f | 1274 | case CPU_5KE: |
2fa36399 | 1275 | case CPU_LOONGSON1: |
14f18b7f RB |
1276 | write_c0_ecc(0x80000000); |
1277 | back_to_back_c0_hazard(); | |
1278 | /* Set the PE bit (bit 31) in the c0_errctl register. */ | |
1279 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1280 | (read_c0_ecc() & 0x80000000) ? "en" : "dis"); | |
1da177e4 LT |
1281 | break; |
1282 | case CPU_20KC: | |
1283 | case CPU_25KF: | |
1284 | /* Clear the DE bit (bit 16) in the c0_status register. */ | |
1285 | printk(KERN_INFO "Enable cache parity protection for " | |
1286 | "MIPS 20KC/25KF CPUs.\n"); | |
1287 | clear_c0_status(ST0_DE); | |
1288 | break; | |
1289 | default: | |
1290 | break; | |
1291 | } | |
1292 | } | |
1293 | ||
1294 | asmlinkage void cache_parity_error(void) | |
1295 | { | |
1296 | const int field = 2 * sizeof(unsigned long); | |
1297 | unsigned int reg_val; | |
1298 | ||
1299 | /* For the moment, report the problem and hang. */ | |
1300 | printk("Cache error exception:\n"); | |
1301 | printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); | |
1302 | reg_val = read_c0_cacheerr(); | |
1303 | printk("c0_cacheerr == %08x\n", reg_val); | |
1304 | ||
1305 | printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", | |
1306 | reg_val & (1<<30) ? "secondary" : "primary", | |
1307 | reg_val & (1<<31) ? "data" : "insn"); | |
1308 | printk("Error bits: %s%s%s%s%s%s%s\n", | |
1309 | reg_val & (1<<29) ? "ED " : "", | |
1310 | reg_val & (1<<28) ? "ET " : "", | |
1311 | reg_val & (1<<26) ? "EE " : "", | |
1312 | reg_val & (1<<25) ? "EB " : "", | |
1313 | reg_val & (1<<24) ? "EI " : "", | |
1314 | reg_val & (1<<23) ? "E1 " : "", | |
1315 | reg_val & (1<<22) ? "E0 " : ""); | |
1316 | printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); | |
1317 | ||
ec917c2c | 1318 | #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) |
1da177e4 LT |
1319 | if (reg_val & (1<<22)) |
1320 | printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); | |
1321 | ||
1322 | if (reg_val & (1<<23)) | |
1323 | printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); | |
1324 | #endif | |
1325 | ||
1326 | panic("Can't handle the cache error!"); | |
1327 | } | |
1328 | ||
1329 | /* | |
1330 | * SDBBP EJTAG debug exception handler. | |
1331 | * We skip the instruction and return to the next instruction. | |
1332 | */ | |
1333 | void ejtag_exception_handler(struct pt_regs *regs) | |
1334 | { | |
1335 | const int field = 2 * sizeof(unsigned long); | |
1336 | unsigned long depc, old_epc; | |
1337 | unsigned int debug; | |
1338 | ||
70ae6126 | 1339 | printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); |
1da177e4 LT |
1340 | depc = read_c0_depc(); |
1341 | debug = read_c0_debug(); | |
70ae6126 | 1342 | printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); |
1da177e4 LT |
1343 | if (debug & 0x80000000) { |
1344 | /* | |
1345 | * In branch delay slot. | |
1346 | * We cheat a little bit here and use EPC to calculate the | |
1347 | * debug return address (DEPC). EPC is restored after the | |
1348 | * calculation. | |
1349 | */ | |
1350 | old_epc = regs->cp0_epc; | |
1351 | regs->cp0_epc = depc; | |
1352 | __compute_return_epc(regs); | |
1353 | depc = regs->cp0_epc; | |
1354 | regs->cp0_epc = old_epc; | |
1355 | } else | |
1356 | depc += 4; | |
1357 | write_c0_depc(depc); | |
1358 | ||
1359 | #if 0 | |
70ae6126 | 1360 | printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); |
1da177e4 LT |
1361 | write_c0_debug(debug | 0x100); |
1362 | #endif | |
1363 | } | |
1364 | ||
1365 | /* | |
1366 | * NMI exception handler. | |
34bd92e2 | 1367 | * No lock; only written during early bootup by CPU 0. |
1da177e4 | 1368 | */ |
34bd92e2 KC |
1369 | static RAW_NOTIFIER_HEAD(nmi_chain); |
1370 | ||
1371 | int register_nmi_notifier(struct notifier_block *nb) | |
1372 | { | |
1373 | return raw_notifier_chain_register(&nmi_chain, nb); | |
1374 | } | |
1375 | ||
ff2d8b19 | 1376 | void __noreturn nmi_exception_handler(struct pt_regs *regs) |
1da177e4 | 1377 | { |
34bd92e2 | 1378 | raw_notifier_call_chain(&nmi_chain, 0, regs); |
41c594ab | 1379 | bust_spinlocks(1); |
1da177e4 LT |
1380 | printk("NMI taken!!!!\n"); |
1381 | die("NMI", regs); | |
1da177e4 LT |
1382 | } |
1383 | ||
e01402b1 RB |
1384 | #define VECTORSPACING 0x100 /* for EI/VI mode */ |
1385 | ||
1386 | unsigned long ebase; | |
1da177e4 | 1387 | unsigned long exception_handlers[32]; |
e01402b1 | 1388 | unsigned long vi_handlers[64]; |
1da177e4 | 1389 | |
2d1b6e95 | 1390 | void __init *set_except_vector(int n, void *addr) |
1da177e4 LT |
1391 | { |
1392 | unsigned long handler = (unsigned long) addr; | |
1393 | unsigned long old_handler = exception_handlers[n]; | |
1394 | ||
1395 | exception_handlers[n] = handler; | |
1396 | if (n == 0 && cpu_has_divec) { | |
92bbe1b9 FF |
1397 | unsigned long jump_mask = ~((1 << 28) - 1); |
1398 | u32 *buf = (u32 *)(ebase + 0x200); | |
1399 | unsigned int k0 = 26; | |
1400 | if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { | |
1401 | uasm_i_j(&buf, handler & ~jump_mask); | |
1402 | uasm_i_nop(&buf); | |
1403 | } else { | |
1404 | UASM_i_LA(&buf, k0, handler); | |
1405 | uasm_i_jr(&buf, k0); | |
1406 | uasm_i_nop(&buf); | |
1407 | } | |
1408 | local_flush_icache_range(ebase + 0x200, (unsigned long)buf); | |
e01402b1 RB |
1409 | } |
1410 | return (void *)old_handler; | |
1411 | } | |
1412 | ||
6ba07e59 AN |
1413 | static asmlinkage void do_default_vi(void) |
1414 | { | |
1415 | show_regs(get_irq_regs()); | |
1416 | panic("Caught unexpected vectored interrupt."); | |
1417 | } | |
1418 | ||
ef300e42 | 1419 | static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) |
e01402b1 RB |
1420 | { |
1421 | unsigned long handler; | |
1422 | unsigned long old_handler = vi_handlers[n]; | |
f6771dbb | 1423 | int srssets = current_cpu_data.srsets; |
e01402b1 RB |
1424 | u32 *w; |
1425 | unsigned char *b; | |
1426 | ||
b72b7092 | 1427 | BUG_ON(!cpu_has_veic && !cpu_has_vint); |
e01402b1 RB |
1428 | |
1429 | if (addr == NULL) { | |
1430 | handler = (unsigned long) do_default_vi; | |
1431 | srs = 0; | |
41c594ab | 1432 | } else |
e01402b1 RB |
1433 | handler = (unsigned long) addr; |
1434 | vi_handlers[n] = (unsigned long) addr; | |
1435 | ||
1436 | b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); | |
1437 | ||
f6771dbb | 1438 | if (srs >= srssets) |
e01402b1 RB |
1439 | panic("Shadow register set %d not supported", srs); |
1440 | ||
1441 | if (cpu_has_veic) { | |
1442 | if (board_bind_eic_interrupt) | |
49a89efb | 1443 | board_bind_eic_interrupt(n, srs); |
41c594ab | 1444 | } else if (cpu_has_vint) { |
e01402b1 | 1445 | /* SRSMap is only defined if shadow sets are implemented */ |
f6771dbb | 1446 | if (srssets > 1) |
49a89efb | 1447 | change_c0_srsmap(0xf << n*4, srs << n*4); |
e01402b1 RB |
1448 | } |
1449 | ||
1450 | if (srs == 0) { | |
1451 | /* | |
1452 | * If no shadow set is selected then use the default handler | |
1453 | * that does normal register saving and a standard interrupt exit | |
1454 | */ | |
1455 | ||
1456 | extern char except_vec_vi, except_vec_vi_lui; | |
1457 | extern char except_vec_vi_ori, except_vec_vi_end; | |
c65a5480 AN |
1458 | extern char rollback_except_vec_vi; |
1459 | char *vec_start = (cpu_wait == r4k_wait) ? | |
1460 | &rollback_except_vec_vi : &except_vec_vi; | |
41c594ab RB |
1461 | #ifdef CONFIG_MIPS_MT_SMTC |
1462 | /* | |
1463 | * We need to provide the SMTC vectored interrupt handler | |
1464 | * not only with the address of the handler, but with the | |
1465 | * Status.IM bit to be masked before going there. | |
1466 | */ | |
1467 | extern char except_vec_vi_mori; | |
c65a5480 | 1468 | const int mori_offset = &except_vec_vi_mori - vec_start; |
41c594ab | 1469 | #endif /* CONFIG_MIPS_MT_SMTC */ |
c65a5480 AN |
1470 | const int handler_len = &except_vec_vi_end - vec_start; |
1471 | const int lui_offset = &except_vec_vi_lui - vec_start; | |
1472 | const int ori_offset = &except_vec_vi_ori - vec_start; | |
e01402b1 RB |
1473 | |
1474 | if (handler_len > VECTORSPACING) { | |
1475 | /* | |
1476 | * Sigh... panicing won't help as the console | |
1477 | * is probably not configured :( | |
1478 | */ | |
49a89efb | 1479 | panic("VECTORSPACING too small"); |
e01402b1 RB |
1480 | } |
1481 | ||
c65a5480 | 1482 | memcpy(b, vec_start, handler_len); |
41c594ab | 1483 | #ifdef CONFIG_MIPS_MT_SMTC |
8e8a52ed RB |
1484 | BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ |
1485 | ||
41c594ab RB |
1486 | w = (u32 *)(b + mori_offset); |
1487 | *w = (*w & 0xffff0000) | (0x100 << n); | |
1488 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
e01402b1 RB |
1489 | w = (u32 *)(b + lui_offset); |
1490 | *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); | |
1491 | w = (u32 *)(b + ori_offset); | |
1492 | *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); | |
e0cee3ee TB |
1493 | local_flush_icache_range((unsigned long)b, |
1494 | (unsigned long)(b+handler_len)); | |
e01402b1 RB |
1495 | } |
1496 | else { | |
1497 | /* | |
1498 | * In other cases jump directly to the interrupt handler | |
1499 | * | |
1500 | * It is the handlers responsibility to save registers if required | |
1501 | * (eg hi/lo) and return from the exception using "eret" | |
1502 | */ | |
1503 | w = (u32 *)b; | |
1504 | *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ | |
1505 | *w = 0; | |
e0cee3ee TB |
1506 | local_flush_icache_range((unsigned long)b, |
1507 | (unsigned long)(b+8)); | |
1da177e4 | 1508 | } |
e01402b1 | 1509 | |
1da177e4 LT |
1510 | return (void *)old_handler; |
1511 | } | |
1512 | ||
ef300e42 | 1513 | void *set_vi_handler(int n, vi_handler_t addr) |
e01402b1 | 1514 | { |
ff3eab2a | 1515 | return set_vi_srs_handler(n, addr, 0); |
e01402b1 | 1516 | } |
f41ae0b2 | 1517 | |
1da177e4 | 1518 | extern void tlb_init(void); |
1d40cfcd | 1519 | extern void flush_tlb_handlers(void); |
1da177e4 | 1520 | |
42f77542 RB |
1521 | /* |
1522 | * Timer interrupt | |
1523 | */ | |
1524 | int cp0_compare_irq; | |
68b6352c | 1525 | EXPORT_SYMBOL_GPL(cp0_compare_irq); |
010c108d | 1526 | int cp0_compare_irq_shift; |
42f77542 RB |
1527 | |
1528 | /* | |
1529 | * Performance counter IRQ or -1 if shared with timer | |
1530 | */ | |
1531 | int cp0_perfcount_irq; | |
1532 | EXPORT_SYMBOL_GPL(cp0_perfcount_irq); | |
1533 | ||
bdc94eb4 CD |
1534 | static int __cpuinitdata noulri; |
1535 | ||
1536 | static int __init ulri_disable(char *s) | |
1537 | { | |
1538 | pr_info("Disabling ulri\n"); | |
1539 | noulri = 1; | |
1540 | ||
1541 | return 1; | |
1542 | } | |
1543 | __setup("noulri", ulri_disable); | |
1544 | ||
6650df3c | 1545 | void __cpuinit per_cpu_trap_init(bool is_boot_cpu) |
1da177e4 LT |
1546 | { |
1547 | unsigned int cpu = smp_processor_id(); | |
1548 | unsigned int status_set = ST0_CU0; | |
18d693b3 | 1549 | unsigned int hwrena = cpu_hwrena_impl_bits; |
d532f3d2 | 1550 | unsigned long asid = 0; |
41c594ab RB |
1551 | #ifdef CONFIG_MIPS_MT_SMTC |
1552 | int secondaryTC = 0; | |
1553 | int bootTC = (cpu == 0); | |
1554 | ||
1555 | /* | |
1556 | * Only do per_cpu_trap_init() for first TC of Each VPE. | |
1557 | * Note that this hack assumes that the SMTC init code | |
1558 | * assigns TCs consecutively and in ascending order. | |
1559 | */ | |
1560 | ||
1561 | if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && | |
1562 | ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) | |
1563 | secondaryTC = 1; | |
1564 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
1565 | |
1566 | /* | |
1567 | * Disable coprocessors and select 32-bit or 64-bit addressing | |
1568 | * and the 16/32 or 32/32 FPR register model. Reset the BEV | |
1569 | * flag that some firmware may have left set and the TS bit (for | |
1570 | * IP27). Set XX for ISA IV code to work. | |
1571 | */ | |
875d43e7 | 1572 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1573 | status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; |
1574 | #endif | |
adb37892 | 1575 | if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV) |
1da177e4 | 1576 | status_set |= ST0_XX; |
bbaf238b CD |
1577 | if (cpu_has_dsp) |
1578 | status_set |= ST0_MX; | |
1579 | ||
b38c7399 | 1580 | change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, |
1da177e4 LT |
1581 | status_set); |
1582 | ||
18d693b3 KC |
1583 | if (cpu_has_mips_r2) |
1584 | hwrena |= 0x0000000f; | |
a3692020 | 1585 | |
18d693b3 KC |
1586 | if (!noulri && cpu_has_userlocal) |
1587 | hwrena |= (1 << 29); | |
a3692020 | 1588 | |
18d693b3 KC |
1589 | if (hwrena) |
1590 | write_c0_hwrena(hwrena); | |
e01402b1 | 1591 | |
41c594ab RB |
1592 | #ifdef CONFIG_MIPS_MT_SMTC |
1593 | if (!secondaryTC) { | |
1594 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1595 | ||
e01402b1 | 1596 | if (cpu_has_veic || cpu_has_vint) { |
9fb4c2b9 | 1597 | unsigned long sr = set_c0_status(ST0_BEV); |
49a89efb | 1598 | write_c0_ebase(ebase); |
9fb4c2b9 | 1599 | write_c0_status(sr); |
e01402b1 | 1600 | /* Setting vector spacing enables EI/VI mode */ |
49a89efb | 1601 | change_c0_intctl(0x3e0, VECTORSPACING); |
e01402b1 | 1602 | } |
d03d0a57 RB |
1603 | if (cpu_has_divec) { |
1604 | if (cpu_has_mipsmt) { | |
1605 | unsigned int vpflags = dvpe(); | |
1606 | set_c0_cause(CAUSEF_IV); | |
1607 | evpe(vpflags); | |
1608 | } else | |
1609 | set_c0_cause(CAUSEF_IV); | |
1610 | } | |
3b1d4ed5 RB |
1611 | |
1612 | /* | |
1613 | * Before R2 both interrupt numbers were fixed to 7, so on R2 only: | |
1614 | * | |
1615 | * o read IntCtl.IPTI to determine the timer interrupt | |
1616 | * o read IntCtl.IPPCI to determine the performance counter interrupt | |
1617 | */ | |
1618 | if (cpu_has_mips_r2) { | |
010c108d DV |
1619 | cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; |
1620 | cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; | |
1621 | cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; | |
c3e838a2 | 1622 | if (cp0_perfcount_irq == cp0_compare_irq) |
3b1d4ed5 | 1623 | cp0_perfcount_irq = -1; |
c3e838a2 CD |
1624 | } else { |
1625 | cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; | |
c6a4ebb9 | 1626 | cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ; |
c3e838a2 | 1627 | cp0_perfcount_irq = -1; |
3b1d4ed5 RB |
1628 | } |
1629 | ||
41c594ab RB |
1630 | #ifdef CONFIG_MIPS_MT_SMTC |
1631 | } | |
1632 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 | 1633 | |
d532f3d2 SH |
1634 | asid = ASID_FIRST_VERSION; |
1635 | cpu_data[cpu].asid_cache = asid; | |
1636 | TLBMISS_HANDLER_SETUP(); | |
1da177e4 LT |
1637 | |
1638 | atomic_inc(&init_mm.mm_count); | |
1639 | current->active_mm = &init_mm; | |
1640 | BUG_ON(current->mm); | |
1641 | enter_lazy_tlb(&init_mm, current); | |
1642 | ||
41c594ab RB |
1643 | #ifdef CONFIG_MIPS_MT_SMTC |
1644 | if (bootTC) { | |
1645 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
6650df3c DD |
1646 | /* Boot CPU's cache setup in setup_arch(). */ |
1647 | if (!is_boot_cpu) | |
1648 | cpu_cache_init(); | |
41c594ab RB |
1649 | tlb_init(); |
1650 | #ifdef CONFIG_MIPS_MT_SMTC | |
6a05888d RB |
1651 | } else if (!secondaryTC) { |
1652 | /* | |
1653 | * First TC in non-boot VPE must do subset of tlb_init() | |
1654 | * for MMU countrol registers. | |
1655 | */ | |
1656 | write_c0_pagemask(PM_DEFAULT_MASK); | |
1657 | write_c0_wired(0); | |
41c594ab RB |
1658 | } |
1659 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
3d8bfdd0 | 1660 | TLBMISS_HANDLER_SETUP(); |
1da177e4 LT |
1661 | } |
1662 | ||
e01402b1 | 1663 | /* Install CPU exception handler */ |
e3dc81f2 | 1664 | void __cpuinit set_handler(unsigned long offset, void *addr, unsigned long size) |
e01402b1 RB |
1665 | { |
1666 | memcpy((void *)(ebase + offset), addr, size); | |
e0cee3ee | 1667 | local_flush_icache_range(ebase + offset, ebase + offset + size); |
e01402b1 RB |
1668 | } |
1669 | ||
234fcd14 | 1670 | static char panic_null_cerr[] __cpuinitdata = |
641e97f3 RB |
1671 | "Trying to set NULL cache error exception handler"; |
1672 | ||
42fe7ee3 RB |
1673 | /* |
1674 | * Install uncached CPU exception handler. | |
1675 | * This is suitable only for the cache error exception which is the only | |
1676 | * exception handler that is being run uncached. | |
1677 | */ | |
234fcd14 RB |
1678 | void __cpuinit set_uncached_handler(unsigned long offset, void *addr, |
1679 | unsigned long size) | |
e01402b1 | 1680 | { |
4f81b01a | 1681 | unsigned long uncached_ebase = CKSEG1ADDR(ebase); |
e01402b1 | 1682 | |
641e97f3 RB |
1683 | if (!addr) |
1684 | panic(panic_null_cerr); | |
1685 | ||
e01402b1 RB |
1686 | memcpy((void *)(uncached_ebase + offset), addr, size); |
1687 | } | |
1688 | ||
5b10496b AN |
1689 | static int __initdata rdhwr_noopt; |
1690 | static int __init set_rdhwr_noopt(char *str) | |
1691 | { | |
1692 | rdhwr_noopt = 1; | |
1693 | return 1; | |
1694 | } | |
1695 | ||
1696 | __setup("rdhwr_noopt", set_rdhwr_noopt); | |
1697 | ||
1da177e4 LT |
1698 | void __init trap_init(void) |
1699 | { | |
1700 | extern char except_vec3_generic, except_vec3_r4000; | |
1da177e4 LT |
1701 | extern char except_vec4; |
1702 | unsigned long i; | |
c65a5480 AN |
1703 | int rollback; |
1704 | ||
1705 | check_wait(); | |
1706 | rollback = (cpu_wait == r4k_wait); | |
1da177e4 | 1707 | |
88547001 JW |
1708 | #if defined(CONFIG_KGDB) |
1709 | if (kgdb_early_setup) | |
70342287 | 1710 | return; /* Already done */ |
88547001 JW |
1711 | #endif |
1712 | ||
9fb4c2b9 CD |
1713 | if (cpu_has_veic || cpu_has_vint) { |
1714 | unsigned long size = 0x200 + VECTORSPACING*64; | |
1715 | ebase = (unsigned long) | |
1716 | __alloc_bootmem(size, 1 << fls(size), 0); | |
1717 | } else { | |
f6be75d0 | 1718 | ebase = CKSEG0; |
566f74f6 DD |
1719 | if (cpu_has_mips_r2) |
1720 | ebase += (read_c0_ebase() & 0x3ffff000); | |
1721 | } | |
e01402b1 | 1722 | |
6fb97eff KC |
1723 | if (board_ebase_setup) |
1724 | board_ebase_setup(); | |
6650df3c | 1725 | per_cpu_trap_init(true); |
1da177e4 LT |
1726 | |
1727 | /* | |
1728 | * Copy the generic exception handlers to their final destination. | |
1729 | * This will be overriden later as suitable for a particular | |
1730 | * configuration. | |
1731 | */ | |
e01402b1 | 1732 | set_handler(0x180, &except_vec3_generic, 0x80); |
1da177e4 LT |
1733 | |
1734 | /* | |
1735 | * Setup default vectors | |
1736 | */ | |
1737 | for (i = 0; i <= 31; i++) | |
1738 | set_except_vector(i, handle_reserved); | |
1739 | ||
1740 | /* | |
1741 | * Copy the EJTAG debug exception vector handler code to it's final | |
1742 | * destination. | |
1743 | */ | |
e01402b1 | 1744 | if (cpu_has_ejtag && board_ejtag_handler_setup) |
49a89efb | 1745 | board_ejtag_handler_setup(); |
1da177e4 LT |
1746 | |
1747 | /* | |
1748 | * Only some CPUs have the watch exceptions. | |
1749 | */ | |
1750 | if (cpu_has_watch) | |
1751 | set_except_vector(23, handle_watch); | |
1752 | ||
1753 | /* | |
e01402b1 | 1754 | * Initialise interrupt handlers |
1da177e4 | 1755 | */ |
e01402b1 RB |
1756 | if (cpu_has_veic || cpu_has_vint) { |
1757 | int nvec = cpu_has_veic ? 64 : 8; | |
1758 | for (i = 0; i < nvec; i++) | |
ff3eab2a | 1759 | set_vi_handler(i, NULL); |
e01402b1 RB |
1760 | } |
1761 | else if (cpu_has_divec) | |
1762 | set_handler(0x200, &except_vec4, 0x8); | |
1da177e4 LT |
1763 | |
1764 | /* | |
1765 | * Some CPUs can enable/disable for cache parity detection, but does | |
1766 | * it different ways. | |
1767 | */ | |
1768 | parity_protection_init(); | |
1769 | ||
1770 | /* | |
1771 | * The Data Bus Errors / Instruction Bus Errors are signaled | |
1772 | * by external hardware. Therefore these two exceptions | |
1773 | * may have board specific handlers. | |
1774 | */ | |
1775 | if (board_be_init) | |
1776 | board_be_init(); | |
1777 | ||
c65a5480 | 1778 | set_except_vector(0, rollback ? rollback_handle_int : handle_int); |
1da177e4 LT |
1779 | set_except_vector(1, handle_tlbm); |
1780 | set_except_vector(2, handle_tlbl); | |
1781 | set_except_vector(3, handle_tlbs); | |
1782 | ||
1783 | set_except_vector(4, handle_adel); | |
1784 | set_except_vector(5, handle_ades); | |
1785 | ||
1786 | set_except_vector(6, handle_ibe); | |
1787 | set_except_vector(7, handle_dbe); | |
1788 | ||
1789 | set_except_vector(8, handle_sys); | |
1790 | set_except_vector(9, handle_bp); | |
5b10496b AN |
1791 | set_except_vector(10, rdhwr_noopt ? handle_ri : |
1792 | (cpu_has_vtag_icache ? | |
1793 | handle_ri_rdhwr_vivt : handle_ri_rdhwr)); | |
1da177e4 LT |
1794 | set_except_vector(11, handle_cpu); |
1795 | set_except_vector(12, handle_ov); | |
1796 | set_except_vector(13, handle_tr); | |
1da177e4 | 1797 | |
10cc3529 RB |
1798 | if (current_cpu_type() == CPU_R6000 || |
1799 | current_cpu_type() == CPU_R6000A) { | |
1da177e4 LT |
1800 | /* |
1801 | * The R6000 is the only R-series CPU that features a machine | |
1802 | * check exception (similar to the R4000 cache error) and | |
1803 | * unaligned ldc1/sdc1 exception. The handlers have not been | |
70342287 | 1804 | * written yet. Well, anyway there is no R6000 machine on the |
1da177e4 LT |
1805 | * current list of targets for Linux/MIPS. |
1806 | * (Duh, crap, there is someone with a triple R6k machine) | |
1807 | */ | |
1808 | //set_except_vector(14, handle_mc); | |
1809 | //set_except_vector(15, handle_ndc); | |
1810 | } | |
1811 | ||
e01402b1 RB |
1812 | |
1813 | if (board_nmi_handler_setup) | |
1814 | board_nmi_handler_setup(); | |
1815 | ||
e50c0a8f RB |
1816 | if (cpu_has_fpu && !cpu_has_nofpuex) |
1817 | set_except_vector(15, handle_fpe); | |
1818 | ||
1819 | set_except_vector(22, handle_mdmx); | |
1820 | ||
1821 | if (cpu_has_mcheck) | |
1822 | set_except_vector(24, handle_mcheck); | |
1823 | ||
340ee4b9 RB |
1824 | if (cpu_has_mipsmt) |
1825 | set_except_vector(25, handle_mt); | |
1826 | ||
acaec427 | 1827 | set_except_vector(26, handle_dsp); |
e50c0a8f | 1828 | |
fcbf1dfd DD |
1829 | if (board_cache_error_setup) |
1830 | board_cache_error_setup(); | |
1831 | ||
e50c0a8f RB |
1832 | if (cpu_has_vce) |
1833 | /* Special exception: R4[04]00 uses also the divec space. */ | |
566f74f6 | 1834 | memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100); |
e50c0a8f | 1835 | else if (cpu_has_4kex) |
566f74f6 | 1836 | memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80); |
e50c0a8f | 1837 | else |
566f74f6 | 1838 | memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80); |
e50c0a8f | 1839 | |
e0cee3ee | 1840 | local_flush_icache_range(ebase, ebase + 0x400); |
1d40cfcd | 1841 | flush_tlb_handlers(); |
0510617b TB |
1842 | |
1843 | sort_extable(__start___dbe_table, __stop___dbe_table); | |
69f3a7de | 1844 | |
4483b159 | 1845 | cu2_notifier(default_cu2_call, 0x80000000); /* Run last */ |
1da177e4 | 1846 | } |