Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
36ccf1c0 | 6 | * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle |
1da177e4 LT |
7 | * Copyright (C) 1995, 1996 Paul M. Antoine |
8 | * Copyright (C) 1998 Ulf Carlsson | |
9 | * Copyright (C) 1999 Silicon Graphics, Inc. | |
10 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
60b0d655 | 11 | * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki |
2a0b24f5 | 12 | * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved. |
b08a9c95 | 13 | * Copyright (C) 2014, Imagination Technologies Ltd. |
1da177e4 | 14 | */ |
ed2d72c1 | 15 | #include <linux/bitops.h> |
8e8a52ed | 16 | #include <linux/bug.h> |
60b0d655 | 17 | #include <linux/compiler.h> |
c3fc5cd5 | 18 | #include <linux/context_tracking.h> |
ae4ce454 | 19 | #include <linux/cpu_pm.h> |
7aa1c8f4 | 20 | #include <linux/kexec.h> |
1da177e4 | 21 | #include <linux/init.h> |
8742cd23 | 22 | #include <linux/kernel.h> |
f9ded569 | 23 | #include <linux/module.h> |
1da177e4 | 24 | #include <linux/mm.h> |
1da177e4 LT |
25 | #include <linux/sched.h> |
26 | #include <linux/smp.h> | |
1da177e4 LT |
27 | #include <linux/spinlock.h> |
28 | #include <linux/kallsyms.h> | |
e01402b1 | 29 | #include <linux/bootmem.h> |
d4fd1989 | 30 | #include <linux/interrupt.h> |
39b8d525 | 31 | #include <linux/ptrace.h> |
88547001 JW |
32 | #include <linux/kgdb.h> |
33 | #include <linux/kdebug.h> | |
c1bf207d | 34 | #include <linux/kprobes.h> |
69f3a7de | 35 | #include <linux/notifier.h> |
5dd11d5d | 36 | #include <linux/kdb.h> |
ca4d3e67 | 37 | #include <linux/irq.h> |
7f788d2d | 38 | #include <linux/perf_event.h> |
1da177e4 | 39 | |
a13c9962 | 40 | #include <asm/addrspace.h> |
1da177e4 LT |
41 | #include <asm/bootinfo.h> |
42 | #include <asm/branch.h> | |
43 | #include <asm/break.h> | |
69f3a7de | 44 | #include <asm/cop2.h> |
1da177e4 | 45 | #include <asm/cpu.h> |
69f24d17 | 46 | #include <asm/cpu-type.h> |
e50c0a8f | 47 | #include <asm/dsp.h> |
1da177e4 | 48 | #include <asm/fpu.h> |
ba3049ed | 49 | #include <asm/fpu_emulator.h> |
bdc92d74 | 50 | #include <asm/idle.h> |
b0a668fb | 51 | #include <asm/mips-r2-to-r6-emul.h> |
340ee4b9 RB |
52 | #include <asm/mipsregs.h> |
53 | #include <asm/mipsmtregs.h> | |
1da177e4 | 54 | #include <asm/module.h> |
1db1af84 | 55 | #include <asm/msa.h> |
1da177e4 LT |
56 | #include <asm/pgtable.h> |
57 | #include <asm/ptrace.h> | |
58 | #include <asm/sections.h> | |
3b143cca | 59 | #include <asm/siginfo.h> |
1da177e4 LT |
60 | #include <asm/tlbdebug.h> |
61 | #include <asm/traps.h> | |
62 | #include <asm/uaccess.h> | |
b67b2b70 | 63 | #include <asm/watch.h> |
1da177e4 | 64 | #include <asm/mmu_context.h> |
1da177e4 | 65 | #include <asm/types.h> |
1df0f0ff | 66 | #include <asm/stacktrace.h> |
92bbe1b9 | 67 | #include <asm/uasm.h> |
1da177e4 | 68 | |
c65a5480 | 69 | extern void check_wait(void); |
c65a5480 | 70 | extern asmlinkage void rollback_handle_int(void); |
e4ac58af | 71 | extern asmlinkage void handle_int(void); |
86a1708a RB |
72 | extern u32 handle_tlbl[]; |
73 | extern u32 handle_tlbs[]; | |
74 | extern u32 handle_tlbm[]; | |
1da177e4 LT |
75 | extern asmlinkage void handle_adel(void); |
76 | extern asmlinkage void handle_ades(void); | |
77 | extern asmlinkage void handle_ibe(void); | |
78 | extern asmlinkage void handle_dbe(void); | |
79 | extern asmlinkage void handle_sys(void); | |
80 | extern asmlinkage void handle_bp(void); | |
81 | extern asmlinkage void handle_ri(void); | |
5b10496b AN |
82 | extern asmlinkage void handle_ri_rdhwr_vivt(void); |
83 | extern asmlinkage void handle_ri_rdhwr(void); | |
1da177e4 LT |
84 | extern asmlinkage void handle_cpu(void); |
85 | extern asmlinkage void handle_ov(void); | |
86 | extern asmlinkage void handle_tr(void); | |
2bcb3fbc | 87 | extern asmlinkage void handle_msa_fpe(void); |
1da177e4 | 88 | extern asmlinkage void handle_fpe(void); |
75b5b5e0 | 89 | extern asmlinkage void handle_ftlb(void); |
1db1af84 | 90 | extern asmlinkage void handle_msa(void); |
1da177e4 LT |
91 | extern asmlinkage void handle_mdmx(void); |
92 | extern asmlinkage void handle_watch(void); | |
340ee4b9 | 93 | extern asmlinkage void handle_mt(void); |
e50c0a8f | 94 | extern asmlinkage void handle_dsp(void); |
1da177e4 LT |
95 | extern asmlinkage void handle_mcheck(void); |
96 | extern asmlinkage void handle_reserved(void); | |
5890f70f | 97 | extern void tlb_do_page_fault_0(void); |
1da177e4 | 98 | |
1da177e4 LT |
99 | void (*board_be_init)(void); |
100 | int (*board_be_handler)(struct pt_regs *regs, int is_fixup); | |
e01402b1 RB |
101 | void (*board_nmi_handler_setup)(void); |
102 | void (*board_ejtag_handler_setup)(void); | |
103 | void (*board_bind_eic_interrupt)(int irq, int regset); | |
6fb97eff | 104 | void (*board_ebase_setup)(void); |
078a55fc | 105 | void(*board_cache_error_setup)(void); |
1da177e4 | 106 | |
4d157d5e | 107 | static void show_raw_backtrace(unsigned long reg29) |
e889d78f | 108 | { |
39b8d525 | 109 | unsigned long *sp = (unsigned long *)(reg29 & ~3); |
e889d78f AN |
110 | unsigned long addr; |
111 | ||
112 | printk("Call Trace:"); | |
113 | #ifdef CONFIG_KALLSYMS | |
114 | printk("\n"); | |
115 | #endif | |
10220c88 TB |
116 | while (!kstack_end(sp)) { |
117 | unsigned long __user *p = | |
118 | (unsigned long __user *)(unsigned long)sp++; | |
119 | if (__get_user(addr, p)) { | |
120 | printk(" (Bad stack address)"); | |
121 | break; | |
39b8d525 | 122 | } |
10220c88 TB |
123 | if (__kernel_text_address(addr)) |
124 | print_ip_sym(addr); | |
e889d78f | 125 | } |
10220c88 | 126 | printk("\n"); |
e889d78f AN |
127 | } |
128 | ||
f66686f7 | 129 | #ifdef CONFIG_KALLSYMS |
1df0f0ff | 130 | int raw_show_trace; |
f66686f7 AN |
131 | static int __init set_raw_show_trace(char *str) |
132 | { | |
133 | raw_show_trace = 1; | |
134 | return 1; | |
135 | } | |
136 | __setup("raw_show_trace", set_raw_show_trace); | |
1df0f0ff | 137 | #endif |
4d157d5e | 138 | |
eae23f2c | 139 | static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) |
f66686f7 | 140 | { |
4d157d5e FBH |
141 | unsigned long sp = regs->regs[29]; |
142 | unsigned long ra = regs->regs[31]; | |
f66686f7 | 143 | unsigned long pc = regs->cp0_epc; |
f66686f7 | 144 | |
e909be82 VW |
145 | if (!task) |
146 | task = current; | |
147 | ||
81a76d71 | 148 | if (raw_show_trace || user_mode(regs) || !__kernel_text_address(pc)) { |
87151ae3 | 149 | show_raw_backtrace(sp); |
f66686f7 AN |
150 | return; |
151 | } | |
152 | printk("Call Trace:\n"); | |
4d157d5e | 153 | do { |
87151ae3 | 154 | print_ip_sym(pc); |
1924600c | 155 | pc = unwind_stack(task, &sp, pc, &ra); |
4d157d5e | 156 | } while (pc); |
f66686f7 AN |
157 | printk("\n"); |
158 | } | |
f66686f7 | 159 | |
1da177e4 LT |
160 | /* |
161 | * This routine abuses get_user()/put_user() to reference pointers | |
162 | * with at least a bit of error checking ... | |
163 | */ | |
eae23f2c RB |
164 | static void show_stacktrace(struct task_struct *task, |
165 | const struct pt_regs *regs) | |
1da177e4 LT |
166 | { |
167 | const int field = 2 * sizeof(unsigned long); | |
168 | long stackdata; | |
169 | int i; | |
5e0373b8 | 170 | unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; |
1da177e4 LT |
171 | |
172 | printk("Stack :"); | |
173 | i = 0; | |
174 | while ((unsigned long) sp & (PAGE_SIZE - 1)) { | |
175 | if (i && ((i % (64 / field)) == 0)) | |
70342287 | 176 | printk("\n "); |
1da177e4 LT |
177 | if (i > 39) { |
178 | printk(" ..."); | |
179 | break; | |
180 | } | |
181 | ||
182 | if (__get_user(stackdata, sp++)) { | |
183 | printk(" (Bad stack address)"); | |
184 | break; | |
185 | } | |
186 | ||
187 | printk(" %0*lx", field, stackdata); | |
188 | i++; | |
189 | } | |
190 | printk("\n"); | |
87151ae3 | 191 | show_backtrace(task, regs); |
f66686f7 AN |
192 | } |
193 | ||
f66686f7 AN |
194 | void show_stack(struct task_struct *task, unsigned long *sp) |
195 | { | |
196 | struct pt_regs regs; | |
1e77863a | 197 | mm_segment_t old_fs = get_fs(); |
f66686f7 AN |
198 | if (sp) { |
199 | regs.regs[29] = (unsigned long)sp; | |
200 | regs.regs[31] = 0; | |
201 | regs.cp0_epc = 0; | |
202 | } else { | |
203 | if (task && task != current) { | |
204 | regs.regs[29] = task->thread.reg29; | |
205 | regs.regs[31] = 0; | |
206 | regs.cp0_epc = task->thread.reg31; | |
5dd11d5d JW |
207 | #ifdef CONFIG_KGDB_KDB |
208 | } else if (atomic_read(&kgdb_active) != -1 && | |
209 | kdb_current_regs) { | |
210 | memcpy(®s, kdb_current_regs, sizeof(regs)); | |
211 | #endif /* CONFIG_KGDB_KDB */ | |
f66686f7 AN |
212 | } else { |
213 | prepare_frametrace(®s); | |
214 | } | |
215 | } | |
1e77863a JH |
216 | /* |
217 | * show_stack() deals exclusively with kernel mode, so be sure to access | |
218 | * the stack in the kernel (not user) address space. | |
219 | */ | |
220 | set_fs(KERNEL_DS); | |
f66686f7 | 221 | show_stacktrace(task, ®s); |
1e77863a | 222 | set_fs(old_fs); |
1da177e4 LT |
223 | } |
224 | ||
e1bb8289 | 225 | static void show_code(unsigned int __user *pc) |
1da177e4 LT |
226 | { |
227 | long i; | |
39b8d525 | 228 | unsigned short __user *pc16 = NULL; |
1da177e4 LT |
229 | |
230 | printk("\nCode:"); | |
231 | ||
39b8d525 RB |
232 | if ((unsigned long)pc & 1) |
233 | pc16 = (unsigned short __user *)((unsigned long)pc & ~1); | |
1da177e4 LT |
234 | for(i = -3 ; i < 6 ; i++) { |
235 | unsigned int insn; | |
39b8d525 | 236 | if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { |
1da177e4 LT |
237 | printk(" (Bad address in epc)\n"); |
238 | break; | |
239 | } | |
39b8d525 | 240 | printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); |
1da177e4 LT |
241 | } |
242 | } | |
243 | ||
eae23f2c | 244 | static void __show_regs(const struct pt_regs *regs) |
1da177e4 LT |
245 | { |
246 | const int field = 2 * sizeof(unsigned long); | |
247 | unsigned int cause = regs->cp0_cause; | |
37dd3818 | 248 | unsigned int exccode; |
1da177e4 LT |
249 | int i; |
250 | ||
a43cb95d | 251 | show_regs_print_info(KERN_DEFAULT); |
1da177e4 LT |
252 | |
253 | /* | |
254 | * Saved main processor registers | |
255 | */ | |
256 | for (i = 0; i < 32; ) { | |
257 | if ((i % 4) == 0) | |
258 | printk("$%2d :", i); | |
259 | if (i == 0) | |
260 | printk(" %0*lx", field, 0UL); | |
261 | else if (i == 26 || i == 27) | |
262 | printk(" %*s", field, ""); | |
263 | else | |
264 | printk(" %0*lx", field, regs->regs[i]); | |
265 | ||
266 | i++; | |
267 | if ((i % 4) == 0) | |
268 | printk("\n"); | |
269 | } | |
270 | ||
9693a853 FBH |
271 | #ifdef CONFIG_CPU_HAS_SMARTMIPS |
272 | printk("Acx : %0*lx\n", field, regs->acx); | |
273 | #endif | |
1da177e4 LT |
274 | printk("Hi : %0*lx\n", field, regs->hi); |
275 | printk("Lo : %0*lx\n", field, regs->lo); | |
276 | ||
277 | /* | |
278 | * Saved cp0 registers | |
279 | */ | |
b012cffe RB |
280 | printk("epc : %0*lx %pS\n", field, regs->cp0_epc, |
281 | (void *) regs->cp0_epc); | |
b012cffe RB |
282 | printk("ra : %0*lx %pS\n", field, regs->regs[31], |
283 | (void *) regs->regs[31]); | |
1da177e4 | 284 | |
70342287 | 285 | printk("Status: %08x ", (uint32_t) regs->cp0_status); |
1da177e4 | 286 | |
1990e542 | 287 | if (cpu_has_3kex) { |
3b2396d9 MR |
288 | if (regs->cp0_status & ST0_KUO) |
289 | printk("KUo "); | |
290 | if (regs->cp0_status & ST0_IEO) | |
291 | printk("IEo "); | |
292 | if (regs->cp0_status & ST0_KUP) | |
293 | printk("KUp "); | |
294 | if (regs->cp0_status & ST0_IEP) | |
295 | printk("IEp "); | |
296 | if (regs->cp0_status & ST0_KUC) | |
297 | printk("KUc "); | |
298 | if (regs->cp0_status & ST0_IEC) | |
299 | printk("IEc "); | |
1990e542 | 300 | } else if (cpu_has_4kex) { |
3b2396d9 MR |
301 | if (regs->cp0_status & ST0_KX) |
302 | printk("KX "); | |
303 | if (regs->cp0_status & ST0_SX) | |
304 | printk("SX "); | |
305 | if (regs->cp0_status & ST0_UX) | |
306 | printk("UX "); | |
307 | switch (regs->cp0_status & ST0_KSU) { | |
308 | case KSU_USER: | |
309 | printk("USER "); | |
310 | break; | |
311 | case KSU_SUPERVISOR: | |
312 | printk("SUPERVISOR "); | |
313 | break; | |
314 | case KSU_KERNEL: | |
315 | printk("KERNEL "); | |
316 | break; | |
317 | default: | |
318 | printk("BAD_MODE "); | |
319 | break; | |
320 | } | |
321 | if (regs->cp0_status & ST0_ERL) | |
322 | printk("ERL "); | |
323 | if (regs->cp0_status & ST0_EXL) | |
324 | printk("EXL "); | |
325 | if (regs->cp0_status & ST0_IE) | |
326 | printk("IE "); | |
1da177e4 | 327 | } |
1da177e4 LT |
328 | printk("\n"); |
329 | ||
37dd3818 PG |
330 | exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; |
331 | printk("Cause : %08x (ExcCode %02x)\n", cause, exccode); | |
1da177e4 | 332 | |
37dd3818 | 333 | if (1 <= exccode && exccode <= 5) |
1da177e4 LT |
334 | printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); |
335 | ||
9966db25 RB |
336 | printk("PrId : %08x (%s)\n", read_c0_prid(), |
337 | cpu_name_string()); | |
1da177e4 LT |
338 | } |
339 | ||
eae23f2c RB |
340 | /* |
341 | * FIXME: really the generic show_regs should take a const pointer argument. | |
342 | */ | |
343 | void show_regs(struct pt_regs *regs) | |
344 | { | |
345 | __show_regs((struct pt_regs *)regs); | |
346 | } | |
347 | ||
c1bf207d | 348 | void show_registers(struct pt_regs *regs) |
1da177e4 | 349 | { |
39b8d525 | 350 | const int field = 2 * sizeof(unsigned long); |
83e4da1e | 351 | mm_segment_t old_fs = get_fs(); |
39b8d525 | 352 | |
eae23f2c | 353 | __show_regs(regs); |
1da177e4 | 354 | print_modules(); |
39b8d525 RB |
355 | printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", |
356 | current->comm, current->pid, current_thread_info(), current, | |
357 | field, current_thread_info()->tp_value); | |
358 | if (cpu_has_userlocal) { | |
359 | unsigned long tls; | |
360 | ||
361 | tls = read_c0_userlocal(); | |
362 | if (tls != current_thread_info()->tp_value) | |
363 | printk("*HwTLS: %0*lx\n", field, tls); | |
364 | } | |
365 | ||
83e4da1e LY |
366 | if (!user_mode(regs)) |
367 | /* Necessary for getting the correct stack content */ | |
368 | set_fs(KERNEL_DS); | |
f66686f7 | 369 | show_stacktrace(current, regs); |
e1bb8289 | 370 | show_code((unsigned int __user *) regs->cp0_epc); |
1da177e4 | 371 | printk("\n"); |
83e4da1e | 372 | set_fs(old_fs); |
1da177e4 LT |
373 | } |
374 | ||
4d85f6af | 375 | static DEFINE_RAW_SPINLOCK(die_lock); |
1da177e4 | 376 | |
70dc6f04 | 377 | void __noreturn die(const char *str, struct pt_regs *regs) |
1da177e4 LT |
378 | { |
379 | static int die_counter; | |
ce384d83 | 380 | int sig = SIGSEGV; |
1da177e4 | 381 | |
8742cd23 NL |
382 | oops_enter(); |
383 | ||
e3b28831 | 384 | if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr, |
dc73e4c1 | 385 | SIGSEGV) == NOTIFY_STOP) |
10423c91 | 386 | sig = 0; |
5dd11d5d | 387 | |
1da177e4 | 388 | console_verbose(); |
4d85f6af | 389 | raw_spin_lock_irq(&die_lock); |
41c594ab | 390 | bust_spinlocks(1); |
ce384d83 | 391 | |
178086c8 | 392 | printk("%s[#%d]:\n", str, ++die_counter); |
1da177e4 | 393 | show_registers(regs); |
373d4d09 | 394 | add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); |
4d85f6af | 395 | raw_spin_unlock_irq(&die_lock); |
d4fd1989 | 396 | |
8742cd23 NL |
397 | oops_exit(); |
398 | ||
d4fd1989 MB |
399 | if (in_interrupt()) |
400 | panic("Fatal exception in interrupt"); | |
401 | ||
99a7a234 | 402 | if (panic_on_oops) |
d4fd1989 | 403 | panic("Fatal exception"); |
d4fd1989 | 404 | |
7aa1c8f4 RB |
405 | if (regs && kexec_should_crash(current)) |
406 | crash_kexec(regs); | |
407 | ||
ce384d83 | 408 | do_exit(sig); |
1da177e4 LT |
409 | } |
410 | ||
0510617b TB |
411 | extern struct exception_table_entry __start___dbe_table[]; |
412 | extern struct exception_table_entry __stop___dbe_table[]; | |
1da177e4 | 413 | |
b6dcec9b RB |
414 | __asm__( |
415 | " .section __dbe_table, \"a\"\n" | |
416 | " .previous \n"); | |
1da177e4 LT |
417 | |
418 | /* Given an address, look for it in the exception tables. */ | |
419 | static const struct exception_table_entry *search_dbe_tables(unsigned long addr) | |
420 | { | |
421 | const struct exception_table_entry *e; | |
422 | ||
423 | e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); | |
424 | if (!e) | |
425 | e = search_module_dbetables(addr); | |
426 | return e; | |
427 | } | |
428 | ||
429 | asmlinkage void do_be(struct pt_regs *regs) | |
430 | { | |
431 | const int field = 2 * sizeof(unsigned long); | |
432 | const struct exception_table_entry *fixup = NULL; | |
433 | int data = regs->cp0_cause & 4; | |
434 | int action = MIPS_BE_FATAL; | |
c3fc5cd5 | 435 | enum ctx_state prev_state; |
1da177e4 | 436 | |
c3fc5cd5 | 437 | prev_state = exception_enter(); |
70342287 | 438 | /* XXX For now. Fixme, this searches the wrong table ... */ |
1da177e4 LT |
439 | if (data && !user_mode(regs)) |
440 | fixup = search_dbe_tables(exception_epc(regs)); | |
441 | ||
442 | if (fixup) | |
443 | action = MIPS_BE_FIXUP; | |
444 | ||
445 | if (board_be_handler) | |
28fc582c | 446 | action = board_be_handler(regs, fixup != NULL); |
1da177e4 LT |
447 | |
448 | switch (action) { | |
449 | case MIPS_BE_DISCARD: | |
c3fc5cd5 | 450 | goto out; |
1da177e4 LT |
451 | case MIPS_BE_FIXUP: |
452 | if (fixup) { | |
453 | regs->cp0_epc = fixup->nextinsn; | |
c3fc5cd5 | 454 | goto out; |
1da177e4 LT |
455 | } |
456 | break; | |
457 | default: | |
458 | break; | |
459 | } | |
460 | ||
461 | /* | |
462 | * Assume it would be too dangerous to continue ... | |
463 | */ | |
464 | printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", | |
465 | data ? "Data" : "Instruction", | |
466 | field, regs->cp0_epc, field, regs->regs[31]); | |
e3b28831 | 467 | if (notify_die(DIE_OOPS, "bus error", regs, 0, current->thread.trap_nr, |
dc73e4c1 | 468 | SIGBUS) == NOTIFY_STOP) |
c3fc5cd5 | 469 | goto out; |
88547001 | 470 | |
1da177e4 LT |
471 | die_if_kernel("Oops", regs); |
472 | force_sig(SIGBUS, current); | |
c3fc5cd5 RB |
473 | |
474 | out: | |
475 | exception_exit(prev_state); | |
1da177e4 LT |
476 | } |
477 | ||
1da177e4 | 478 | /* |
60b0d655 | 479 | * ll/sc, rdhwr, sync emulation |
1da177e4 LT |
480 | */ |
481 | ||
482 | #define OPCODE 0xfc000000 | |
483 | #define BASE 0x03e00000 | |
484 | #define RT 0x001f0000 | |
485 | #define OFFSET 0x0000ffff | |
486 | #define LL 0xc0000000 | |
487 | #define SC 0xe0000000 | |
60b0d655 | 488 | #define SPEC0 0x00000000 |
3c37026d RB |
489 | #define SPEC3 0x7c000000 |
490 | #define RD 0x0000f800 | |
491 | #define FUNC 0x0000003f | |
60b0d655 | 492 | #define SYNC 0x0000000f |
3c37026d | 493 | #define RDHWR 0x0000003b |
1da177e4 | 494 | |
2a0b24f5 SH |
495 | /* microMIPS definitions */ |
496 | #define MM_POOL32A_FUNC 0xfc00ffff | |
497 | #define MM_RDHWR 0x00006b3c | |
498 | #define MM_RS 0x001f0000 | |
499 | #define MM_RT 0x03e00000 | |
500 | ||
1da177e4 LT |
501 | /* |
502 | * The ll_bit is cleared by r*_switch.S | |
503 | */ | |
504 | ||
f1e39a4a RB |
505 | unsigned int ll_bit; |
506 | struct task_struct *ll_task; | |
1da177e4 | 507 | |
60b0d655 | 508 | static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 509 | { |
fe00f943 | 510 | unsigned long value, __user *vaddr; |
1da177e4 | 511 | long offset; |
1da177e4 LT |
512 | |
513 | /* | |
514 | * analyse the ll instruction that just caused a ri exception | |
515 | * and put the referenced address to addr. | |
516 | */ | |
517 | ||
518 | /* sign extend offset */ | |
519 | offset = opcode & OFFSET; | |
520 | offset <<= 16; | |
521 | offset >>= 16; | |
522 | ||
fe00f943 | 523 | vaddr = (unsigned long __user *) |
b9688310 | 524 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); |
1da177e4 | 525 | |
60b0d655 MR |
526 | if ((unsigned long)vaddr & 3) |
527 | return SIGBUS; | |
528 | if (get_user(value, vaddr)) | |
529 | return SIGSEGV; | |
1da177e4 LT |
530 | |
531 | preempt_disable(); | |
532 | ||
533 | if (ll_task == NULL || ll_task == current) { | |
534 | ll_bit = 1; | |
535 | } else { | |
536 | ll_bit = 0; | |
537 | } | |
538 | ll_task = current; | |
539 | ||
540 | preempt_enable(); | |
541 | ||
542 | regs->regs[(opcode & RT) >> 16] = value; | |
543 | ||
60b0d655 | 544 | return 0; |
1da177e4 LT |
545 | } |
546 | ||
60b0d655 | 547 | static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 548 | { |
fe00f943 RB |
549 | unsigned long __user *vaddr; |
550 | unsigned long reg; | |
1da177e4 | 551 | long offset; |
1da177e4 LT |
552 | |
553 | /* | |
554 | * analyse the sc instruction that just caused a ri exception | |
555 | * and put the referenced address to addr. | |
556 | */ | |
557 | ||
558 | /* sign extend offset */ | |
559 | offset = opcode & OFFSET; | |
560 | offset <<= 16; | |
561 | offset >>= 16; | |
562 | ||
fe00f943 | 563 | vaddr = (unsigned long __user *) |
b9688310 | 564 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); |
1da177e4 LT |
565 | reg = (opcode & RT) >> 16; |
566 | ||
60b0d655 MR |
567 | if ((unsigned long)vaddr & 3) |
568 | return SIGBUS; | |
1da177e4 LT |
569 | |
570 | preempt_disable(); | |
571 | ||
572 | if (ll_bit == 0 || ll_task != current) { | |
573 | regs->regs[reg] = 0; | |
574 | preempt_enable(); | |
60b0d655 | 575 | return 0; |
1da177e4 LT |
576 | } |
577 | ||
578 | preempt_enable(); | |
579 | ||
60b0d655 MR |
580 | if (put_user(regs->regs[reg], vaddr)) |
581 | return SIGSEGV; | |
1da177e4 LT |
582 | |
583 | regs->regs[reg] = 1; | |
584 | ||
60b0d655 | 585 | return 0; |
1da177e4 LT |
586 | } |
587 | ||
588 | /* | |
589 | * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both | |
590 | * opcodes are supposed to result in coprocessor unusable exceptions if | |
591 | * executed on ll/sc-less processors. That's the theory. In practice a | |
592 | * few processors such as NEC's VR4100 throw reserved instruction exceptions | |
593 | * instead, so we're doing the emulation thing in both exception handlers. | |
594 | */ | |
60b0d655 | 595 | static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 596 | { |
7f788d2d DCZ |
597 | if ((opcode & OPCODE) == LL) { |
598 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 599 | 1, regs, 0); |
60b0d655 | 600 | return simulate_ll(regs, opcode); |
7f788d2d DCZ |
601 | } |
602 | if ((opcode & OPCODE) == SC) { | |
603 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 604 | 1, regs, 0); |
60b0d655 | 605 | return simulate_sc(regs, opcode); |
7f788d2d | 606 | } |
1da177e4 | 607 | |
60b0d655 | 608 | return -1; /* Must be something else ... */ |
1da177e4 LT |
609 | } |
610 | ||
3c37026d RB |
611 | /* |
612 | * Simulate trapping 'rdhwr' instructions to provide user accessible | |
1f5826bd | 613 | * registers not implemented in hardware. |
3c37026d | 614 | */ |
2a0b24f5 | 615 | static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt) |
3c37026d | 616 | { |
dc8f6029 | 617 | struct thread_info *ti = task_thread_info(current); |
3c37026d | 618 | |
2a0b24f5 SH |
619 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, |
620 | 1, regs, 0); | |
621 | switch (rd) { | |
622 | case 0: /* CPU number */ | |
623 | regs->regs[rt] = smp_processor_id(); | |
624 | return 0; | |
625 | case 1: /* SYNCI length */ | |
626 | regs->regs[rt] = min(current_cpu_data.dcache.linesz, | |
627 | current_cpu_data.icache.linesz); | |
628 | return 0; | |
629 | case 2: /* Read count register */ | |
630 | regs->regs[rt] = read_c0_count(); | |
631 | return 0; | |
632 | case 3: /* Count register resolution */ | |
69f24d17 | 633 | switch (current_cpu_type()) { |
2a0b24f5 SH |
634 | case CPU_20KC: |
635 | case CPU_25KF: | |
636 | regs->regs[rt] = 1; | |
637 | break; | |
638 | default: | |
639 | regs->regs[rt] = 2; | |
640 | } | |
641 | return 0; | |
642 | case 29: | |
643 | regs->regs[rt] = ti->tp_value; | |
644 | return 0; | |
645 | default: | |
646 | return -1; | |
647 | } | |
648 | } | |
649 | ||
650 | static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode) | |
651 | { | |
3c37026d RB |
652 | if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { |
653 | int rd = (opcode & RD) >> 11; | |
654 | int rt = (opcode & RT) >> 16; | |
2a0b24f5 SH |
655 | |
656 | simulate_rdhwr(regs, rd, rt); | |
657 | return 0; | |
658 | } | |
659 | ||
660 | /* Not ours. */ | |
661 | return -1; | |
662 | } | |
663 | ||
7aa70471 | 664 | static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode) |
2a0b24f5 SH |
665 | { |
666 | if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) { | |
667 | int rd = (opcode & MM_RS) >> 16; | |
668 | int rt = (opcode & MM_RT) >> 21; | |
669 | simulate_rdhwr(regs, rd, rt); | |
670 | return 0; | |
3c37026d RB |
671 | } |
672 | ||
56ebd51b | 673 | /* Not ours. */ |
60b0d655 MR |
674 | return -1; |
675 | } | |
e5679882 | 676 | |
60b0d655 MR |
677 | static int simulate_sync(struct pt_regs *regs, unsigned int opcode) |
678 | { | |
7f788d2d DCZ |
679 | if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) { |
680 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 681 | 1, regs, 0); |
60b0d655 | 682 | return 0; |
7f788d2d | 683 | } |
60b0d655 MR |
684 | |
685 | return -1; /* Must be something else ... */ | |
3c37026d RB |
686 | } |
687 | ||
1da177e4 LT |
688 | asmlinkage void do_ov(struct pt_regs *regs) |
689 | { | |
c3fc5cd5 | 690 | enum ctx_state prev_state; |
e723e3f7 MR |
691 | siginfo_t info = { |
692 | .si_signo = SIGFPE, | |
693 | .si_code = FPE_INTOVF, | |
694 | .si_addr = (void __user *)regs->cp0_epc, | |
695 | }; | |
1da177e4 | 696 | |
c3fc5cd5 | 697 | prev_state = exception_enter(); |
36ccf1c0 RB |
698 | die_if_kernel("Integer overflow", regs); |
699 | ||
1da177e4 | 700 | force_sig_info(SIGFPE, &info, current); |
c3fc5cd5 | 701 | exception_exit(prev_state); |
1da177e4 LT |
702 | } |
703 | ||
304acb71 | 704 | int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31) |
515b029d | 705 | { |
304acb71 MR |
706 | struct siginfo si = { 0 }; |
707 | ||
708 | switch (sig) { | |
709 | case 0: | |
710 | return 0; | |
ad70c13a | 711 | |
304acb71 | 712 | case SIGFPE: |
515b029d DD |
713 | si.si_addr = fault_addr; |
714 | si.si_signo = sig; | |
304acb71 MR |
715 | /* |
716 | * Inexact can happen together with Overflow or Underflow. | |
717 | * Respect the mask to deliver the correct exception. | |
718 | */ | |
719 | fcr31 &= (fcr31 & FPU_CSR_ALL_E) << | |
720 | (ffs(FPU_CSR_ALL_X) - ffs(FPU_CSR_ALL_E)); | |
721 | if (fcr31 & FPU_CSR_INV_X) | |
722 | si.si_code = FPE_FLTINV; | |
723 | else if (fcr31 & FPU_CSR_DIV_X) | |
724 | si.si_code = FPE_FLTDIV; | |
725 | else if (fcr31 & FPU_CSR_OVF_X) | |
726 | si.si_code = FPE_FLTOVF; | |
727 | else if (fcr31 & FPU_CSR_UDF_X) | |
728 | si.si_code = FPE_FLTUND; | |
729 | else if (fcr31 & FPU_CSR_INE_X) | |
730 | si.si_code = FPE_FLTRES; | |
731 | else | |
732 | si.si_code = __SI_FAULT; | |
515b029d DD |
733 | force_sig_info(sig, &si, current); |
734 | return 1; | |
304acb71 MR |
735 | |
736 | case SIGBUS: | |
737 | si.si_addr = fault_addr; | |
738 | si.si_signo = sig; | |
739 | si.si_code = BUS_ADRERR; | |
740 | force_sig_info(sig, &si, current); | |
741 | return 1; | |
742 | ||
743 | case SIGSEGV: | |
744 | si.si_addr = fault_addr; | |
745 | si.si_signo = sig; | |
746 | down_read(¤t->mm->mmap_sem); | |
747 | if (find_vma(current->mm, (unsigned long)fault_addr)) | |
748 | si.si_code = SEGV_ACCERR; | |
749 | else | |
750 | si.si_code = SEGV_MAPERR; | |
751 | up_read(¤t->mm->mmap_sem); | |
752 | force_sig_info(sig, &si, current); | |
753 | return 1; | |
754 | ||
755 | default: | |
515b029d DD |
756 | force_sig(sig, current); |
757 | return 1; | |
515b029d DD |
758 | } |
759 | } | |
760 | ||
4227a2d4 PB |
761 | static int simulate_fp(struct pt_regs *regs, unsigned int opcode, |
762 | unsigned long old_epc, unsigned long old_ra) | |
763 | { | |
764 | union mips_instruction inst = { .word = opcode }; | |
304acb71 MR |
765 | void __user *fault_addr; |
766 | unsigned long fcr31; | |
4227a2d4 PB |
767 | int sig; |
768 | ||
769 | /* If it's obviously not an FP instruction, skip it */ | |
770 | switch (inst.i_format.opcode) { | |
771 | case cop1_op: | |
772 | case cop1x_op: | |
773 | case lwc1_op: | |
774 | case ldc1_op: | |
775 | case swc1_op: | |
776 | case sdc1_op: | |
777 | break; | |
778 | ||
779 | default: | |
780 | return -1; | |
781 | } | |
782 | ||
783 | /* | |
784 | * do_ri skipped over the instruction via compute_return_epc, undo | |
785 | * that for the FPU emulator. | |
786 | */ | |
787 | regs->cp0_epc = old_epc; | |
788 | regs->regs[31] = old_ra; | |
789 | ||
790 | /* Save the FP context to struct thread_struct */ | |
791 | lose_fpu(1); | |
792 | ||
793 | /* Run the emulator */ | |
794 | sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, | |
795 | &fault_addr); | |
304acb71 | 796 | fcr31 = current->thread.fpu.fcr31; |
4227a2d4 | 797 | |
443c4403 MR |
798 | /* |
799 | * We can't allow the emulated instruction to leave any of | |
800 | * the cause bits set in $fcr31. | |
801 | */ | |
802 | current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; | |
4227a2d4 PB |
803 | |
804 | /* Restore the hardware register state */ | |
805 | own_fpu(1); | |
806 | ||
304acb71 MR |
807 | /* Send a signal if required. */ |
808 | process_fpemu_return(sig, fault_addr, fcr31); | |
809 | ||
4227a2d4 PB |
810 | return 0; |
811 | } | |
812 | ||
1da177e4 LT |
813 | /* |
814 | * XXX Delayed fp exceptions when doing a lazy ctx switch XXX | |
815 | */ | |
816 | asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) | |
817 | { | |
c3fc5cd5 | 818 | enum ctx_state prev_state; |
304acb71 MR |
819 | void __user *fault_addr; |
820 | int sig; | |
948a34cf | 821 | |
c3fc5cd5 | 822 | prev_state = exception_enter(); |
e3b28831 | 823 | if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr, |
dc73e4c1 | 824 | SIGFPE) == NOTIFY_STOP) |
c3fc5cd5 | 825 | goto out; |
64bedffe JH |
826 | |
827 | /* Clear FCSR.Cause before enabling interrupts */ | |
828 | write_32bit_cp1_register(CP1_STATUS, fcr31 & ~FPU_CSR_ALL_X); | |
829 | local_irq_enable(); | |
830 | ||
57725f9e CD |
831 | die_if_kernel("FP exception in kernel code", regs); |
832 | ||
1da177e4 | 833 | if (fcr31 & FPU_CSR_UNI_X) { |
1da177e4 | 834 | /* |
a3dddd56 | 835 | * Unimplemented operation exception. If we've got the full |
1da177e4 LT |
836 | * software emulator on-board, let's use it... |
837 | * | |
838 | * Force FPU to dump state into task/thread context. We're | |
839 | * moving a lot of data here for what is probably a single | |
840 | * instruction, but the alternative is to pre-decode the FP | |
841 | * register operands before invoking the emulator, which seems | |
842 | * a bit extreme for what should be an infrequent event. | |
843 | */ | |
cd21dfcf | 844 | /* Ensure 'resume' not overwrite saved fp context again. */ |
53dc8028 | 845 | lose_fpu(1); |
1da177e4 LT |
846 | |
847 | /* Run the emulator */ | |
515b029d DD |
848 | sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, |
849 | &fault_addr); | |
304acb71 | 850 | fcr31 = current->thread.fpu.fcr31; |
1da177e4 LT |
851 | |
852 | /* | |
853 | * We can't allow the emulated instruction to leave any of | |
443c4403 | 854 | * the cause bits set in $fcr31. |
1da177e4 | 855 | */ |
eae89076 | 856 | current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; |
1da177e4 LT |
857 | |
858 | /* Restore the hardware register state */ | |
70342287 | 859 | own_fpu(1); /* Using the FPU again. */ |
304acb71 MR |
860 | } else { |
861 | sig = SIGFPE; | |
862 | fault_addr = (void __user *) regs->cp0_epc; | |
ed2d72c1 | 863 | } |
1da177e4 | 864 | |
304acb71 MR |
865 | /* Send a signal if required. */ |
866 | process_fpemu_return(sig, fault_addr, fcr31); | |
c3fc5cd5 RB |
867 | |
868 | out: | |
869 | exception_exit(prev_state); | |
1da177e4 LT |
870 | } |
871 | ||
3b143cca | 872 | void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code, |
df270051 | 873 | const char *str) |
1da177e4 | 874 | { |
e723e3f7 | 875 | siginfo_t info = { 0 }; |
df270051 | 876 | char b[40]; |
1da177e4 | 877 | |
5dd11d5d | 878 | #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP |
e3b28831 RB |
879 | if (kgdb_ll_trap(DIE_TRAP, str, regs, code, current->thread.trap_nr, |
880 | SIGTRAP) == NOTIFY_STOP) | |
5dd11d5d JW |
881 | return; |
882 | #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ | |
883 | ||
e3b28831 | 884 | if (notify_die(DIE_TRAP, str, regs, code, current->thread.trap_nr, |
dc73e4c1 | 885 | SIGTRAP) == NOTIFY_STOP) |
88547001 JW |
886 | return; |
887 | ||
1da177e4 | 888 | /* |
df270051 RB |
889 | * A short test says that IRIX 5.3 sends SIGTRAP for all trap |
890 | * insns, even for trap and break codes that indicate arithmetic | |
891 | * failures. Weird ... | |
1da177e4 LT |
892 | * But should we continue the brokenness??? --macro |
893 | */ | |
df270051 RB |
894 | switch (code) { |
895 | case BRK_OVERFLOW: | |
896 | case BRK_DIVZERO: | |
897 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); | |
898 | die_if_kernel(b, regs); | |
899 | if (code == BRK_DIVZERO) | |
1da177e4 LT |
900 | info.si_code = FPE_INTDIV; |
901 | else | |
902 | info.si_code = FPE_INTOVF; | |
903 | info.si_signo = SIGFPE; | |
fe00f943 | 904 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
905 | force_sig_info(SIGFPE, &info, current); |
906 | break; | |
63dc68a8 | 907 | case BRK_BUG: |
df270051 RB |
908 | die_if_kernel("Kernel bug detected", regs); |
909 | force_sig(SIGTRAP, current); | |
63dc68a8 | 910 | break; |
ba3049ed RB |
911 | case BRK_MEMU: |
912 | /* | |
1f443779 MR |
913 | * This breakpoint code is used by the FPU emulator to retake |
914 | * control of the CPU after executing the instruction from the | |
915 | * delay slot of an emulated branch. | |
ba3049ed RB |
916 | * |
917 | * Terminate if exception was recognized as a delay slot return | |
918 | * otherwise handle as normal. | |
919 | */ | |
920 | if (do_dsemulret(regs)) | |
921 | return; | |
922 | ||
923 | die_if_kernel("Math emu break/trap", regs); | |
924 | force_sig(SIGTRAP, current); | |
925 | break; | |
1da177e4 | 926 | default: |
df270051 RB |
927 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); |
928 | die_if_kernel(b, regs); | |
3b143cca MR |
929 | if (si_code) { |
930 | info.si_signo = SIGTRAP; | |
931 | info.si_code = si_code; | |
932 | force_sig_info(SIGTRAP, &info, current); | |
933 | } else { | |
934 | force_sig(SIGTRAP, current); | |
935 | } | |
1da177e4 | 936 | } |
df270051 RB |
937 | } |
938 | ||
939 | asmlinkage void do_bp(struct pt_regs *regs) | |
940 | { | |
f6a31da5 | 941 | unsigned long epc = msk_isa16_mode(exception_epc(regs)); |
df270051 | 942 | unsigned int opcode, bcode; |
c3fc5cd5 | 943 | enum ctx_state prev_state; |
078dde5e LY |
944 | mm_segment_t seg; |
945 | ||
946 | seg = get_fs(); | |
947 | if (!user_mode(regs)) | |
948 | set_fs(KERNEL_DS); | |
2a0b24f5 | 949 | |
c3fc5cd5 | 950 | prev_state = exception_enter(); |
e3b28831 | 951 | current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; |
2a0b24f5 | 952 | if (get_isa16_mode(regs->cp0_epc)) { |
f6a31da5 MR |
953 | u16 instr[2]; |
954 | ||
955 | if (__get_user(instr[0], (u16 __user *)epc)) | |
956 | goto out_sigsegv; | |
957 | ||
958 | if (!cpu_has_mmips) { | |
b08a9c95 | 959 | /* MIPS16e mode */ |
68893e00 | 960 | bcode = (instr[0] >> 5) & 0x3f; |
f6a31da5 MR |
961 | } else if (mm_insn_16bit(instr[0])) { |
962 | /* 16-bit microMIPS BREAK */ | |
963 | bcode = instr[0] & 0xf; | |
964 | } else { | |
965 | /* 32-bit microMIPS BREAK */ | |
966 | if (__get_user(instr[1], (u16 __user *)(epc + 2))) | |
2a0b24f5 | 967 | goto out_sigsegv; |
f6a31da5 MR |
968 | opcode = (instr[0] << 16) | instr[1]; |
969 | bcode = (opcode >> 6) & ((1 << 20) - 1); | |
2a0b24f5 SH |
970 | } |
971 | } else { | |
f6a31da5 | 972 | if (__get_user(opcode, (unsigned int __user *)epc)) |
2a0b24f5 | 973 | goto out_sigsegv; |
f6a31da5 | 974 | bcode = (opcode >> 6) & ((1 << 20) - 1); |
2a0b24f5 | 975 | } |
df270051 RB |
976 | |
977 | /* | |
978 | * There is the ancient bug in the MIPS assemblers that the break | |
979 | * code starts left to bit 16 instead to bit 6 in the opcode. | |
980 | * Gas is bug-compatible, but not always, grrr... | |
981 | * We handle both cases with a simple heuristics. --macro | |
982 | */ | |
df270051 | 983 | if (bcode >= (1 << 10)) |
c9875032 | 984 | bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10); |
df270051 | 985 | |
c1bf207d DD |
986 | /* |
987 | * notify the kprobe handlers, if instruction is likely to | |
988 | * pertain to them. | |
989 | */ | |
990 | switch (bcode) { | |
40e084a5 RB |
991 | case BRK_UPROBE: |
992 | if (notify_die(DIE_UPROBE, "uprobe", regs, bcode, | |
993 | current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) | |
994 | goto out; | |
995 | else | |
996 | break; | |
997 | case BRK_UPROBE_XOL: | |
998 | if (notify_die(DIE_UPROBE_XOL, "uprobe_xol", regs, bcode, | |
999 | current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) | |
1000 | goto out; | |
1001 | else | |
1002 | break; | |
c1bf207d | 1003 | case BRK_KPROBE_BP: |
dc73e4c1 | 1004 | if (notify_die(DIE_BREAK, "debug", regs, bcode, |
e3b28831 | 1005 | current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) |
c3fc5cd5 | 1006 | goto out; |
c1bf207d DD |
1007 | else |
1008 | break; | |
1009 | case BRK_KPROBE_SSTEPBP: | |
dc73e4c1 | 1010 | if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, |
e3b28831 | 1011 | current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) |
c3fc5cd5 | 1012 | goto out; |
c1bf207d DD |
1013 | else |
1014 | break; | |
1015 | default: | |
1016 | break; | |
1017 | } | |
1018 | ||
3b143cca | 1019 | do_trap_or_bp(regs, bcode, TRAP_BRKPT, "Break"); |
c3fc5cd5 RB |
1020 | |
1021 | out: | |
078dde5e | 1022 | set_fs(seg); |
c3fc5cd5 | 1023 | exception_exit(prev_state); |
90fccb13 | 1024 | return; |
e5679882 RB |
1025 | |
1026 | out_sigsegv: | |
1027 | force_sig(SIGSEGV, current); | |
c3fc5cd5 | 1028 | goto out; |
1da177e4 LT |
1029 | } |
1030 | ||
1031 | asmlinkage void do_tr(struct pt_regs *regs) | |
1032 | { | |
a9a6e7a0 | 1033 | u32 opcode, tcode = 0; |
c3fc5cd5 | 1034 | enum ctx_state prev_state; |
2a0b24f5 | 1035 | u16 instr[2]; |
078dde5e | 1036 | mm_segment_t seg; |
a9a6e7a0 | 1037 | unsigned long epc = msk_isa16_mode(exception_epc(regs)); |
1da177e4 | 1038 | |
078dde5e LY |
1039 | seg = get_fs(); |
1040 | if (!user_mode(regs)) | |
1041 | set_fs(get_ds()); | |
1042 | ||
c3fc5cd5 | 1043 | prev_state = exception_enter(); |
e3b28831 | 1044 | current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; |
a9a6e7a0 MR |
1045 | if (get_isa16_mode(regs->cp0_epc)) { |
1046 | if (__get_user(instr[0], (u16 __user *)(epc + 0)) || | |
1047 | __get_user(instr[1], (u16 __user *)(epc + 2))) | |
2a0b24f5 | 1048 | goto out_sigsegv; |
a9a6e7a0 MR |
1049 | opcode = (instr[0] << 16) | instr[1]; |
1050 | /* Immediate versions don't provide a code. */ | |
1051 | if (!(opcode & OPCODE)) | |
1052 | tcode = (opcode >> 12) & ((1 << 4) - 1); | |
1053 | } else { | |
1054 | if (__get_user(opcode, (u32 __user *)epc)) | |
1055 | goto out_sigsegv; | |
1056 | /* Immediate versions don't provide a code. */ | |
1057 | if (!(opcode & OPCODE)) | |
1058 | tcode = (opcode >> 6) & ((1 << 10) - 1); | |
2a0b24f5 | 1059 | } |
1da177e4 | 1060 | |
3b143cca | 1061 | do_trap_or_bp(regs, tcode, 0, "Trap"); |
c3fc5cd5 RB |
1062 | |
1063 | out: | |
078dde5e | 1064 | set_fs(seg); |
c3fc5cd5 | 1065 | exception_exit(prev_state); |
90fccb13 | 1066 | return; |
e5679882 RB |
1067 | |
1068 | out_sigsegv: | |
1069 | force_sig(SIGSEGV, current); | |
c3fc5cd5 | 1070 | goto out; |
1da177e4 LT |
1071 | } |
1072 | ||
1073 | asmlinkage void do_ri(struct pt_regs *regs) | |
1074 | { | |
60b0d655 MR |
1075 | unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); |
1076 | unsigned long old_epc = regs->cp0_epc; | |
2a0b24f5 | 1077 | unsigned long old31 = regs->regs[31]; |
c3fc5cd5 | 1078 | enum ctx_state prev_state; |
60b0d655 MR |
1079 | unsigned int opcode = 0; |
1080 | int status = -1; | |
1da177e4 | 1081 | |
b0a668fb LY |
1082 | /* |
1083 | * Avoid any kernel code. Just emulate the R2 instruction | |
1084 | * as quickly as possible. | |
1085 | */ | |
1086 | if (mipsr2_emulation && cpu_has_mips_r6 && | |
4a7c2371 MR |
1087 | likely(user_mode(regs)) && |
1088 | likely(get_user(opcode, epc) >= 0)) { | |
304acb71 MR |
1089 | unsigned long fcr31 = 0; |
1090 | ||
1091 | status = mipsr2_decoder(regs, opcode, &fcr31); | |
4a7c2371 MR |
1092 | switch (status) { |
1093 | case 0: | |
1094 | case SIGEMT: | |
1095 | task_thread_info(current)->r2_emul_return = 1; | |
1096 | return; | |
1097 | case SIGILL: | |
1098 | goto no_r2_instr; | |
1099 | default: | |
1100 | process_fpemu_return(status, | |
304acb71 MR |
1101 | ¤t->thread.cp0_baduaddr, |
1102 | fcr31); | |
4a7c2371 MR |
1103 | task_thread_info(current)->r2_emul_return = 1; |
1104 | return; | |
b0a668fb LY |
1105 | } |
1106 | } | |
1107 | ||
1108 | no_r2_instr: | |
1109 | ||
c3fc5cd5 | 1110 | prev_state = exception_enter(); |
e3b28831 | 1111 | current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; |
b0a668fb | 1112 | |
e3b28831 | 1113 | if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr, |
dc73e4c1 | 1114 | SIGILL) == NOTIFY_STOP) |
c3fc5cd5 | 1115 | goto out; |
88547001 | 1116 | |
60b0d655 | 1117 | die_if_kernel("Reserved instruction in kernel code", regs); |
1da177e4 | 1118 | |
60b0d655 | 1119 | if (unlikely(compute_return_epc(regs) < 0)) |
c3fc5cd5 | 1120 | goto out; |
3c37026d | 1121 | |
3d50a7fb | 1122 | if (!get_isa16_mode(regs->cp0_epc)) { |
2a0b24f5 SH |
1123 | if (unlikely(get_user(opcode, epc) < 0)) |
1124 | status = SIGSEGV; | |
60b0d655 | 1125 | |
2a0b24f5 SH |
1126 | if (!cpu_has_llsc && status < 0) |
1127 | status = simulate_llsc(regs, opcode); | |
1128 | ||
1129 | if (status < 0) | |
1130 | status = simulate_rdhwr_normal(regs, opcode); | |
1131 | ||
1132 | if (status < 0) | |
1133 | status = simulate_sync(regs, opcode); | |
4227a2d4 PB |
1134 | |
1135 | if (status < 0) | |
1136 | status = simulate_fp(regs, opcode, old_epc, old31); | |
3d50a7fb MR |
1137 | } else if (cpu_has_mmips) { |
1138 | unsigned short mmop[2] = { 0 }; | |
1139 | ||
1140 | if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0)) | |
1141 | status = SIGSEGV; | |
1142 | if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0)) | |
1143 | status = SIGSEGV; | |
1144 | opcode = mmop[0]; | |
1145 | opcode = (opcode << 16) | mmop[1]; | |
1146 | ||
1147 | if (status < 0) | |
1148 | status = simulate_rdhwr_mm(regs, opcode); | |
2a0b24f5 | 1149 | } |
60b0d655 MR |
1150 | |
1151 | if (status < 0) | |
1152 | status = SIGILL; | |
1153 | ||
1154 | if (unlikely(status > 0)) { | |
1155 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
2a0b24f5 | 1156 | regs->regs[31] = old31; |
60b0d655 MR |
1157 | force_sig(status, current); |
1158 | } | |
c3fc5cd5 RB |
1159 | |
1160 | out: | |
1161 | exception_exit(prev_state); | |
1da177e4 LT |
1162 | } |
1163 | ||
d223a861 RB |
1164 | /* |
1165 | * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've | |
1166 | * emulated more than some threshold number of instructions, force migration to | |
1167 | * a "CPU" that has FP support. | |
1168 | */ | |
1169 | static void mt_ase_fp_affinity(void) | |
1170 | { | |
1171 | #ifdef CONFIG_MIPS_MT_FPAFF | |
1172 | if (mt_fpemul_threshold > 0 && | |
1173 | ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { | |
1174 | /* | |
1175 | * If there's no FPU present, or if the application has already | |
1176 | * restricted the allowed set to exclude any CPUs with FPUs, | |
1177 | * we'll skip the procedure. | |
1178 | */ | |
8dd92891 | 1179 | if (cpumask_intersects(¤t->cpus_allowed, &mt_fpu_cpumask)) { |
d223a861 RB |
1180 | cpumask_t tmask; |
1181 | ||
9cc12363 KK |
1182 | current->thread.user_cpus_allowed |
1183 | = current->cpus_allowed; | |
8dd92891 RR |
1184 | cpumask_and(&tmask, ¤t->cpus_allowed, |
1185 | &mt_fpu_cpumask); | |
ed1bbdef | 1186 | set_cpus_allowed_ptr(current, &tmask); |
293c5bd1 | 1187 | set_thread_flag(TIF_FPUBOUND); |
d223a861 RB |
1188 | } |
1189 | } | |
1190 | #endif /* CONFIG_MIPS_MT_FPAFF */ | |
1191 | } | |
1192 | ||
69f3a7de RB |
1193 | /* |
1194 | * No lock; only written during early bootup by CPU 0. | |
1195 | */ | |
1196 | static RAW_NOTIFIER_HEAD(cu2_chain); | |
1197 | ||
1198 | int __ref register_cu2_notifier(struct notifier_block *nb) | |
1199 | { | |
1200 | return raw_notifier_chain_register(&cu2_chain, nb); | |
1201 | } | |
1202 | ||
1203 | int cu2_notifier_call_chain(unsigned long val, void *v) | |
1204 | { | |
1205 | return raw_notifier_call_chain(&cu2_chain, val, v); | |
1206 | } | |
1207 | ||
1208 | static int default_cu2_call(struct notifier_block *nfb, unsigned long action, | |
70342287 | 1209 | void *data) |
69f3a7de RB |
1210 | { |
1211 | struct pt_regs *regs = data; | |
1212 | ||
83bee792 | 1213 | die_if_kernel("COP2: Unhandled kernel unaligned access or invalid " |
69f3a7de | 1214 | "instruction", regs); |
83bee792 | 1215 | force_sig(SIGILL, current); |
69f3a7de RB |
1216 | |
1217 | return NOTIFY_OK; | |
1218 | } | |
1219 | ||
9791554b PB |
1220 | static int wait_on_fp_mode_switch(atomic_t *p) |
1221 | { | |
1222 | /* | |
1223 | * The FP mode for this task is currently being switched. That may | |
1224 | * involve modifications to the format of this tasks FP context which | |
1225 | * make it unsafe to proceed with execution for the moment. Instead, | |
1226 | * schedule some other task. | |
1227 | */ | |
1228 | schedule(); | |
1229 | return 0; | |
1230 | } | |
1231 | ||
1db1af84 PB |
1232 | static int enable_restore_fp_context(int msa) |
1233 | { | |
c9017757 | 1234 | int err, was_fpu_owner, prior_msa; |
1db1af84 | 1235 | |
9791554b PB |
1236 | /* |
1237 | * If an FP mode switch is currently underway, wait for it to | |
1238 | * complete before proceeding. | |
1239 | */ | |
1240 | wait_on_atomic_t(¤t->mm->context.fp_mode_switching, | |
1241 | wait_on_fp_mode_switch, TASK_KILLABLE); | |
1242 | ||
1db1af84 PB |
1243 | if (!used_math()) { |
1244 | /* First time FP context user. */ | |
762a1f43 | 1245 | preempt_disable(); |
1db1af84 | 1246 | err = init_fpu(); |
c9017757 | 1247 | if (msa && !err) { |
1db1af84 | 1248 | enable_msa(); |
e49d3848 | 1249 | init_msa_upper(); |
732c0c3c PB |
1250 | set_thread_flag(TIF_USEDMSA); |
1251 | set_thread_flag(TIF_MSA_CTX_LIVE); | |
c9017757 | 1252 | } |
762a1f43 | 1253 | preempt_enable(); |
1db1af84 PB |
1254 | if (!err) |
1255 | set_used_math(); | |
1256 | return err; | |
1257 | } | |
1258 | ||
1259 | /* | |
1260 | * This task has formerly used the FP context. | |
1261 | * | |
1262 | * If this thread has no live MSA vector context then we can simply | |
1263 | * restore the scalar FP context. If it has live MSA vector context | |
1264 | * (that is, it has or may have used MSA since last performing a | |
1265 | * function call) then we'll need to restore the vector context. This | |
1266 | * applies even if we're currently only executing a scalar FP | |
1267 | * instruction. This is because if we were to later execute an MSA | |
1268 | * instruction then we'd either have to: | |
1269 | * | |
1270 | * - Restore the vector context & clobber any registers modified by | |
1271 | * scalar FP instructions between now & then. | |
1272 | * | |
1273 | * or | |
1274 | * | |
1275 | * - Not restore the vector context & lose the most significant bits | |
1276 | * of all vector registers. | |
1277 | * | |
1278 | * Neither of those options is acceptable. We cannot restore the least | |
1279 | * significant bits of the registers now & only restore the most | |
1280 | * significant bits later because the most significant bits of any | |
1281 | * vector registers whose aliased FP register is modified now will have | |
1282 | * been zeroed. We'd have no way to know that when restoring the vector | |
1283 | * context & thus may load an outdated value for the most significant | |
1284 | * bits of a vector register. | |
1285 | */ | |
1286 | if (!msa && !thread_msa_context_live()) | |
1287 | return own_fpu(1); | |
1288 | ||
1289 | /* | |
1290 | * This task is using or has previously used MSA. Thus we require | |
1291 | * that Status.FR == 1. | |
1292 | */ | |
762a1f43 | 1293 | preempt_disable(); |
1db1af84 | 1294 | was_fpu_owner = is_fpu_owner(); |
762a1f43 | 1295 | err = own_fpu_inatomic(0); |
1db1af84 | 1296 | if (err) |
762a1f43 | 1297 | goto out; |
1db1af84 PB |
1298 | |
1299 | enable_msa(); | |
1300 | write_msa_csr(current->thread.fpu.msacsr); | |
1301 | set_thread_flag(TIF_USEDMSA); | |
1302 | ||
1303 | /* | |
1304 | * If this is the first time that the task is using MSA and it has | |
1305 | * previously used scalar FP in this time slice then we already nave | |
c9017757 PB |
1306 | * FP context which we shouldn't clobber. We do however need to clear |
1307 | * the upper 64b of each vector register so that this task has no | |
1308 | * opportunity to see data left behind by another. | |
1db1af84 | 1309 | */ |
c9017757 PB |
1310 | prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE); |
1311 | if (!prior_msa && was_fpu_owner) { | |
e49d3848 | 1312 | init_msa_upper(); |
762a1f43 PB |
1313 | |
1314 | goto out; | |
c9017757 | 1315 | } |
1db1af84 | 1316 | |
c9017757 PB |
1317 | if (!prior_msa) { |
1318 | /* | |
1319 | * Restore the least significant 64b of each vector register | |
1320 | * from the existing scalar FP context. | |
1321 | */ | |
1322 | _restore_fp(current); | |
b8340673 | 1323 | |
c9017757 PB |
1324 | /* |
1325 | * The task has not formerly used MSA, so clear the upper 64b | |
1326 | * of each vector register such that it cannot see data left | |
1327 | * behind by another task. | |
1328 | */ | |
e49d3848 | 1329 | init_msa_upper(); |
c9017757 PB |
1330 | } else { |
1331 | /* We need to restore the vector context. */ | |
1332 | restore_msa(current); | |
b8340673 | 1333 | |
c9017757 PB |
1334 | /* Restore the scalar FP control & status register */ |
1335 | if (!was_fpu_owner) | |
d76e9b9f JH |
1336 | write_32bit_cp1_register(CP1_STATUS, |
1337 | current->thread.fpu.fcr31); | |
c9017757 | 1338 | } |
762a1f43 PB |
1339 | |
1340 | out: | |
1341 | preempt_enable(); | |
1342 | ||
1db1af84 PB |
1343 | return 0; |
1344 | } | |
1345 | ||
1da177e4 LT |
1346 | asmlinkage void do_cpu(struct pt_regs *regs) |
1347 | { | |
c3fc5cd5 | 1348 | enum ctx_state prev_state; |
60b0d655 | 1349 | unsigned int __user *epc; |
2a0b24f5 | 1350 | unsigned long old_epc, old31; |
304acb71 | 1351 | void __user *fault_addr; |
60b0d655 | 1352 | unsigned int opcode; |
304acb71 | 1353 | unsigned long fcr31; |
1da177e4 | 1354 | unsigned int cpid; |
597ce172 | 1355 | int status, err; |
304acb71 | 1356 | int sig; |
1da177e4 | 1357 | |
c3fc5cd5 | 1358 | prev_state = exception_enter(); |
1da177e4 LT |
1359 | cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; |
1360 | ||
83bee792 J |
1361 | if (cpid != 2) |
1362 | die_if_kernel("do_cpu invoked from kernel context!", regs); | |
1363 | ||
1da177e4 LT |
1364 | switch (cpid) { |
1365 | case 0: | |
60b0d655 MR |
1366 | epc = (unsigned int __user *)exception_epc(regs); |
1367 | old_epc = regs->cp0_epc; | |
2a0b24f5 | 1368 | old31 = regs->regs[31]; |
60b0d655 MR |
1369 | opcode = 0; |
1370 | status = -1; | |
1da177e4 | 1371 | |
60b0d655 | 1372 | if (unlikely(compute_return_epc(regs) < 0)) |
27e28e8e | 1373 | break; |
3c37026d | 1374 | |
10f6d99f | 1375 | if (!get_isa16_mode(regs->cp0_epc)) { |
2a0b24f5 SH |
1376 | if (unlikely(get_user(opcode, epc) < 0)) |
1377 | status = SIGSEGV; | |
1378 | ||
1379 | if (!cpu_has_llsc && status < 0) | |
1380 | status = simulate_llsc(regs, opcode); | |
2a0b24f5 | 1381 | } |
60b0d655 MR |
1382 | |
1383 | if (status < 0) | |
1384 | status = SIGILL; | |
1385 | ||
1386 | if (unlikely(status > 0)) { | |
1387 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
2a0b24f5 | 1388 | regs->regs[31] = old31; |
60b0d655 MR |
1389 | force_sig(status, current); |
1390 | } | |
1391 | ||
27e28e8e | 1392 | break; |
1da177e4 | 1393 | |
051ff44a MR |
1394 | case 3: |
1395 | /* | |
2d83fea7 MR |
1396 | * The COP3 opcode space and consequently the CP0.Status.CU3 |
1397 | * bit and the CP0.Cause.CE=3 encoding have been removed as | |
1398 | * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs | |
1399 | * up the space has been reused for COP1X instructions, that | |
1400 | * are enabled by the CP0.Status.CU1 bit and consequently | |
1401 | * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable | |
1402 | * exceptions. Some FPU-less processors that implement one | |
1403 | * of these ISAs however use this code erroneously for COP1X | |
1404 | * instructions. Therefore we redirect this trap to the FP | |
1405 | * emulator too. | |
051ff44a | 1406 | */ |
2d83fea7 | 1407 | if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) { |
27e28e8e | 1408 | force_sig(SIGILL, current); |
051ff44a | 1409 | break; |
27e28e8e | 1410 | } |
051ff44a MR |
1411 | /* Fall through. */ |
1412 | ||
1da177e4 | 1413 | case 1: |
1db1af84 | 1414 | err = enable_restore_fp_context(0); |
1da177e4 | 1415 | |
304acb71 MR |
1416 | if (raw_cpu_has_fpu && !err) |
1417 | break; | |
1da177e4 | 1418 | |
304acb71 MR |
1419 | sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0, |
1420 | &fault_addr); | |
1421 | fcr31 = current->thread.fpu.fcr31; | |
1422 | ||
1423 | /* | |
1424 | * We can't allow the emulated instruction to leave | |
1425 | * any of the cause bits set in $fcr31. | |
1426 | */ | |
1427 | current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; | |
1428 | ||
1429 | /* Send a signal if required. */ | |
1430 | if (!process_fpemu_return(sig, fault_addr, fcr31) && !err) | |
1431 | mt_ase_fp_affinity(); | |
1da177e4 | 1432 | |
27e28e8e | 1433 | break; |
1da177e4 LT |
1434 | |
1435 | case 2: | |
69f3a7de | 1436 | raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); |
27e28e8e | 1437 | break; |
1da177e4 LT |
1438 | } |
1439 | ||
c3fc5cd5 | 1440 | exception_exit(prev_state); |
1da177e4 LT |
1441 | } |
1442 | ||
64bedffe | 1443 | asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr) |
2bcb3fbc PB |
1444 | { |
1445 | enum ctx_state prev_state; | |
1446 | ||
1447 | prev_state = exception_enter(); | |
e3b28831 | 1448 | current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; |
64bedffe | 1449 | if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0, |
e3b28831 | 1450 | current->thread.trap_nr, SIGFPE) == NOTIFY_STOP) |
64bedffe JH |
1451 | goto out; |
1452 | ||
1453 | /* Clear MSACSR.Cause before enabling interrupts */ | |
1454 | write_msa_csr(msacsr & ~MSA_CSR_CAUSEF); | |
1455 | local_irq_enable(); | |
1456 | ||
2bcb3fbc PB |
1457 | die_if_kernel("do_msa_fpe invoked from kernel context!", regs); |
1458 | force_sig(SIGFPE, current); | |
64bedffe | 1459 | out: |
2bcb3fbc PB |
1460 | exception_exit(prev_state); |
1461 | } | |
1462 | ||
1db1af84 PB |
1463 | asmlinkage void do_msa(struct pt_regs *regs) |
1464 | { | |
1465 | enum ctx_state prev_state; | |
1466 | int err; | |
1467 | ||
1468 | prev_state = exception_enter(); | |
1469 | ||
1470 | if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) { | |
1471 | force_sig(SIGILL, current); | |
1472 | goto out; | |
1473 | } | |
1474 | ||
1475 | die_if_kernel("do_msa invoked from kernel context!", regs); | |
1476 | ||
1477 | err = enable_restore_fp_context(1); | |
1478 | if (err) | |
1479 | force_sig(SIGILL, current); | |
1480 | out: | |
1481 | exception_exit(prev_state); | |
1482 | } | |
1483 | ||
1da177e4 LT |
1484 | asmlinkage void do_mdmx(struct pt_regs *regs) |
1485 | { | |
c3fc5cd5 RB |
1486 | enum ctx_state prev_state; |
1487 | ||
1488 | prev_state = exception_enter(); | |
1da177e4 | 1489 | force_sig(SIGILL, current); |
c3fc5cd5 | 1490 | exception_exit(prev_state); |
1da177e4 LT |
1491 | } |
1492 | ||
8bc6d05b DD |
1493 | /* |
1494 | * Called with interrupts disabled. | |
1495 | */ | |
1da177e4 LT |
1496 | asmlinkage void do_watch(struct pt_regs *regs) |
1497 | { | |
3b143cca | 1498 | siginfo_t info = { .si_signo = SIGTRAP, .si_code = TRAP_HWBKPT }; |
c3fc5cd5 | 1499 | enum ctx_state prev_state; |
b67b2b70 | 1500 | |
c3fc5cd5 | 1501 | prev_state = exception_enter(); |
1da177e4 | 1502 | /* |
b67b2b70 DD |
1503 | * Clear WP (bit 22) bit of cause register so we don't loop |
1504 | * forever. | |
1da177e4 | 1505 | */ |
e233c733 | 1506 | clear_c0_cause(CAUSEF_WP); |
b67b2b70 DD |
1507 | |
1508 | /* | |
1509 | * If the current thread has the watch registers loaded, save | |
1510 | * their values and send SIGTRAP. Otherwise another thread | |
1511 | * left the registers set, clear them and continue. | |
1512 | */ | |
1513 | if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { | |
1514 | mips_read_watch_registers(); | |
8bc6d05b | 1515 | local_irq_enable(); |
3b143cca | 1516 | force_sig_info(SIGTRAP, &info, current); |
8bc6d05b | 1517 | } else { |
b67b2b70 | 1518 | mips_clear_watch_registers(); |
8bc6d05b DD |
1519 | local_irq_enable(); |
1520 | } | |
c3fc5cd5 | 1521 | exception_exit(prev_state); |
1da177e4 LT |
1522 | } |
1523 | ||
1524 | asmlinkage void do_mcheck(struct pt_regs *regs) | |
1525 | { | |
cac4bcbc | 1526 | int multi_match = regs->cp0_status & ST0_TS; |
c3fc5cd5 | 1527 | enum ctx_state prev_state; |
55c723e1 | 1528 | mm_segment_t old_fs = get_fs(); |
cac4bcbc | 1529 | |
c3fc5cd5 | 1530 | prev_state = exception_enter(); |
1da177e4 | 1531 | show_regs(regs); |
cac4bcbc RB |
1532 | |
1533 | if (multi_match) { | |
3c865dd9 JH |
1534 | dump_tlb_regs(); |
1535 | pr_info("\n"); | |
cac4bcbc RB |
1536 | dump_tlb_all(); |
1537 | } | |
1538 | ||
55c723e1 JH |
1539 | if (!user_mode(regs)) |
1540 | set_fs(KERNEL_DS); | |
1541 | ||
e1bb8289 | 1542 | show_code((unsigned int __user *) regs->cp0_epc); |
cac4bcbc | 1543 | |
55c723e1 JH |
1544 | set_fs(old_fs); |
1545 | ||
1da177e4 LT |
1546 | /* |
1547 | * Some chips may have other causes of machine check (e.g. SB1 | |
1548 | * graduation timer) | |
1549 | */ | |
1550 | panic("Caught Machine Check exception - %scaused by multiple " | |
1551 | "matching entries in the TLB.", | |
cac4bcbc | 1552 | (multi_match) ? "" : "not "); |
1da177e4 LT |
1553 | } |
1554 | ||
340ee4b9 RB |
1555 | asmlinkage void do_mt(struct pt_regs *regs) |
1556 | { | |
41c594ab RB |
1557 | int subcode; |
1558 | ||
41c594ab RB |
1559 | subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) |
1560 | >> VPECONTROL_EXCPT_SHIFT; | |
1561 | switch (subcode) { | |
1562 | case 0: | |
e35a5e35 | 1563 | printk(KERN_DEBUG "Thread Underflow\n"); |
41c594ab RB |
1564 | break; |
1565 | case 1: | |
e35a5e35 | 1566 | printk(KERN_DEBUG "Thread Overflow\n"); |
41c594ab RB |
1567 | break; |
1568 | case 2: | |
e35a5e35 | 1569 | printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); |
41c594ab RB |
1570 | break; |
1571 | case 3: | |
e35a5e35 | 1572 | printk(KERN_DEBUG "Gating Storage Exception\n"); |
41c594ab RB |
1573 | break; |
1574 | case 4: | |
e35a5e35 | 1575 | printk(KERN_DEBUG "YIELD Scheduler Exception\n"); |
41c594ab RB |
1576 | break; |
1577 | case 5: | |
f232c7e8 | 1578 | printk(KERN_DEBUG "Gating Storage Scheduler Exception\n"); |
41c594ab RB |
1579 | break; |
1580 | default: | |
e35a5e35 | 1581 | printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", |
41c594ab RB |
1582 | subcode); |
1583 | break; | |
1584 | } | |
340ee4b9 RB |
1585 | die_if_kernel("MIPS MT Thread exception in kernel", regs); |
1586 | ||
1587 | force_sig(SIGILL, current); | |
1588 | } | |
1589 | ||
1590 | ||
e50c0a8f RB |
1591 | asmlinkage void do_dsp(struct pt_regs *regs) |
1592 | { | |
1593 | if (cpu_has_dsp) | |
ab75dc02 | 1594 | panic("Unexpected DSP exception"); |
e50c0a8f RB |
1595 | |
1596 | force_sig(SIGILL, current); | |
1597 | } | |
1598 | ||
1da177e4 LT |
1599 | asmlinkage void do_reserved(struct pt_regs *regs) |
1600 | { | |
1601 | /* | |
70342287 | 1602 | * Game over - no way to handle this if it ever occurs. Most probably |
1da177e4 LT |
1603 | * caused by a new unknown cpu type or after another deadly |
1604 | * hard/software error. | |
1605 | */ | |
1606 | show_regs(regs); | |
1607 | panic("Caught reserved exception %ld - should not happen.", | |
1608 | (regs->cp0_cause & 0x7f) >> 2); | |
1609 | } | |
1610 | ||
39b8d525 RB |
1611 | static int __initdata l1parity = 1; |
1612 | static int __init nol1parity(char *s) | |
1613 | { | |
1614 | l1parity = 0; | |
1615 | return 1; | |
1616 | } | |
1617 | __setup("nol1par", nol1parity); | |
1618 | static int __initdata l2parity = 1; | |
1619 | static int __init nol2parity(char *s) | |
1620 | { | |
1621 | l2parity = 0; | |
1622 | return 1; | |
1623 | } | |
1624 | __setup("nol2par", nol2parity); | |
1625 | ||
1da177e4 LT |
1626 | /* |
1627 | * Some MIPS CPUs can enable/disable for cache parity detection, but do | |
1628 | * it different ways. | |
1629 | */ | |
1630 | static inline void parity_protection_init(void) | |
1631 | { | |
10cc3529 | 1632 | switch (current_cpu_type()) { |
1da177e4 | 1633 | case CPU_24K: |
98a41de9 | 1634 | case CPU_34K: |
39b8d525 RB |
1635 | case CPU_74K: |
1636 | case CPU_1004K: | |
442e14a2 | 1637 | case CPU_1074K: |
26ab96df | 1638 | case CPU_INTERAPTIV: |
708ac4b8 | 1639 | case CPU_PROAPTIV: |
aced4cbd | 1640 | case CPU_P5600: |
4695089f | 1641 | case CPU_QEMU_GENERIC: |
4e88a862 | 1642 | case CPU_I6400: |
1091bfa2 | 1643 | case CPU_P6600: |
39b8d525 RB |
1644 | { |
1645 | #define ERRCTL_PE 0x80000000 | |
1646 | #define ERRCTL_L2P 0x00800000 | |
1647 | unsigned long errctl; | |
1648 | unsigned int l1parity_present, l2parity_present; | |
1649 | ||
1650 | errctl = read_c0_ecc(); | |
1651 | errctl &= ~(ERRCTL_PE|ERRCTL_L2P); | |
1652 | ||
1653 | /* probe L1 parity support */ | |
1654 | write_c0_ecc(errctl | ERRCTL_PE); | |
1655 | back_to_back_c0_hazard(); | |
1656 | l1parity_present = (read_c0_ecc() & ERRCTL_PE); | |
1657 | ||
1658 | /* probe L2 parity support */ | |
1659 | write_c0_ecc(errctl|ERRCTL_L2P); | |
1660 | back_to_back_c0_hazard(); | |
1661 | l2parity_present = (read_c0_ecc() & ERRCTL_L2P); | |
1662 | ||
1663 | if (l1parity_present && l2parity_present) { | |
1664 | if (l1parity) | |
1665 | errctl |= ERRCTL_PE; | |
1666 | if (l1parity ^ l2parity) | |
1667 | errctl |= ERRCTL_L2P; | |
1668 | } else if (l1parity_present) { | |
1669 | if (l1parity) | |
1670 | errctl |= ERRCTL_PE; | |
1671 | } else if (l2parity_present) { | |
1672 | if (l2parity) | |
1673 | errctl |= ERRCTL_L2P; | |
1674 | } else { | |
1675 | /* No parity available */ | |
1676 | } | |
1677 | ||
1678 | printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); | |
1679 | ||
1680 | write_c0_ecc(errctl); | |
1681 | back_to_back_c0_hazard(); | |
1682 | errctl = read_c0_ecc(); | |
1683 | printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); | |
1684 | ||
1685 | if (l1parity_present) | |
1686 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1687 | (errctl & ERRCTL_PE) ? "en" : "dis"); | |
1688 | ||
1689 | if (l2parity_present) { | |
1690 | if (l1parity_present && l1parity) | |
1691 | errctl ^= ERRCTL_L2P; | |
1692 | printk(KERN_INFO "L2 cache parity protection %sabled\n", | |
1693 | (errctl & ERRCTL_L2P) ? "en" : "dis"); | |
1694 | } | |
1695 | } | |
1696 | break; | |
1697 | ||
1da177e4 | 1698 | case CPU_5KC: |
78d4803f | 1699 | case CPU_5KE: |
2fa36399 | 1700 | case CPU_LOONGSON1: |
14f18b7f RB |
1701 | write_c0_ecc(0x80000000); |
1702 | back_to_back_c0_hazard(); | |
1703 | /* Set the PE bit (bit 31) in the c0_errctl register. */ | |
1704 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1705 | (read_c0_ecc() & 0x80000000) ? "en" : "dis"); | |
1da177e4 LT |
1706 | break; |
1707 | case CPU_20KC: | |
1708 | case CPU_25KF: | |
1709 | /* Clear the DE bit (bit 16) in the c0_status register. */ | |
1710 | printk(KERN_INFO "Enable cache parity protection for " | |
1711 | "MIPS 20KC/25KF CPUs.\n"); | |
1712 | clear_c0_status(ST0_DE); | |
1713 | break; | |
1714 | default: | |
1715 | break; | |
1716 | } | |
1717 | } | |
1718 | ||
1719 | asmlinkage void cache_parity_error(void) | |
1720 | { | |
1721 | const int field = 2 * sizeof(unsigned long); | |
1722 | unsigned int reg_val; | |
1723 | ||
1724 | /* For the moment, report the problem and hang. */ | |
1725 | printk("Cache error exception:\n"); | |
1726 | printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); | |
1727 | reg_val = read_c0_cacheerr(); | |
1728 | printk("c0_cacheerr == %08x\n", reg_val); | |
1729 | ||
1730 | printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", | |
1731 | reg_val & (1<<30) ? "secondary" : "primary", | |
1732 | reg_val & (1<<31) ? "data" : "insn"); | |
9c7d5768 | 1733 | if ((cpu_has_mips_r2_r6) && |
721a9205 | 1734 | ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) { |
6de20451 LY |
1735 | pr_err("Error bits: %s%s%s%s%s%s%s%s\n", |
1736 | reg_val & (1<<29) ? "ED " : "", | |
1737 | reg_val & (1<<28) ? "ET " : "", | |
1738 | reg_val & (1<<27) ? "ES " : "", | |
1739 | reg_val & (1<<26) ? "EE " : "", | |
1740 | reg_val & (1<<25) ? "EB " : "", | |
1741 | reg_val & (1<<24) ? "EI " : "", | |
1742 | reg_val & (1<<23) ? "E1 " : "", | |
1743 | reg_val & (1<<22) ? "E0 " : ""); | |
1744 | } else { | |
1745 | pr_err("Error bits: %s%s%s%s%s%s%s\n", | |
1746 | reg_val & (1<<29) ? "ED " : "", | |
1747 | reg_val & (1<<28) ? "ET " : "", | |
1748 | reg_val & (1<<26) ? "EE " : "", | |
1749 | reg_val & (1<<25) ? "EB " : "", | |
1750 | reg_val & (1<<24) ? "EI " : "", | |
1751 | reg_val & (1<<23) ? "E1 " : "", | |
1752 | reg_val & (1<<22) ? "E0 " : ""); | |
1753 | } | |
1da177e4 LT |
1754 | printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); |
1755 | ||
ec917c2c | 1756 | #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) |
1da177e4 LT |
1757 | if (reg_val & (1<<22)) |
1758 | printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); | |
1759 | ||
1760 | if (reg_val & (1<<23)) | |
1761 | printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); | |
1762 | #endif | |
1763 | ||
1764 | panic("Can't handle the cache error!"); | |
1765 | } | |
1766 | ||
75b5b5e0 LY |
1767 | asmlinkage void do_ftlb(void) |
1768 | { | |
1769 | const int field = 2 * sizeof(unsigned long); | |
1770 | unsigned int reg_val; | |
1771 | ||
1772 | /* For the moment, report the problem and hang. */ | |
9c7d5768 | 1773 | if ((cpu_has_mips_r2_r6) && |
b2edcfc8 HC |
1774 | (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) || |
1775 | ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) { | |
75b5b5e0 LY |
1776 | pr_err("FTLB error exception, cp0_ecc=0x%08x:\n", |
1777 | read_c0_ecc()); | |
1778 | pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); | |
1779 | reg_val = read_c0_cacheerr(); | |
1780 | pr_err("c0_cacheerr == %08x\n", reg_val); | |
1781 | ||
1782 | if ((reg_val & 0xc0000000) == 0xc0000000) { | |
1783 | pr_err("Decoded c0_cacheerr: FTLB parity error\n"); | |
1784 | } else { | |
1785 | pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n", | |
1786 | reg_val & (1<<30) ? "secondary" : "primary", | |
1787 | reg_val & (1<<31) ? "data" : "insn"); | |
1788 | } | |
1789 | } else { | |
1790 | pr_err("FTLB error exception\n"); | |
1791 | } | |
1792 | /* Just print the cacheerr bits for now */ | |
1793 | cache_parity_error(); | |
1794 | } | |
1795 | ||
1da177e4 LT |
1796 | /* |
1797 | * SDBBP EJTAG debug exception handler. | |
1798 | * We skip the instruction and return to the next instruction. | |
1799 | */ | |
1800 | void ejtag_exception_handler(struct pt_regs *regs) | |
1801 | { | |
1802 | const int field = 2 * sizeof(unsigned long); | |
2a0b24f5 | 1803 | unsigned long depc, old_epc, old_ra; |
1da177e4 LT |
1804 | unsigned int debug; |
1805 | ||
70ae6126 | 1806 | printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); |
1da177e4 LT |
1807 | depc = read_c0_depc(); |
1808 | debug = read_c0_debug(); | |
70ae6126 | 1809 | printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); |
1da177e4 LT |
1810 | if (debug & 0x80000000) { |
1811 | /* | |
1812 | * In branch delay slot. | |
1813 | * We cheat a little bit here and use EPC to calculate the | |
1814 | * debug return address (DEPC). EPC is restored after the | |
1815 | * calculation. | |
1816 | */ | |
1817 | old_epc = regs->cp0_epc; | |
2a0b24f5 | 1818 | old_ra = regs->regs[31]; |
1da177e4 | 1819 | regs->cp0_epc = depc; |
2a0b24f5 | 1820 | compute_return_epc(regs); |
1da177e4 LT |
1821 | depc = regs->cp0_epc; |
1822 | regs->cp0_epc = old_epc; | |
2a0b24f5 | 1823 | regs->regs[31] = old_ra; |
1da177e4 LT |
1824 | } else |
1825 | depc += 4; | |
1826 | write_c0_depc(depc); | |
1827 | ||
1828 | #if 0 | |
70ae6126 | 1829 | printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); |
1da177e4 LT |
1830 | write_c0_debug(debug | 0x100); |
1831 | #endif | |
1832 | } | |
1833 | ||
1834 | /* | |
1835 | * NMI exception handler. | |
34bd92e2 | 1836 | * No lock; only written during early bootup by CPU 0. |
1da177e4 | 1837 | */ |
34bd92e2 KC |
1838 | static RAW_NOTIFIER_HEAD(nmi_chain); |
1839 | ||
1840 | int register_nmi_notifier(struct notifier_block *nb) | |
1841 | { | |
1842 | return raw_notifier_chain_register(&nmi_chain, nb); | |
1843 | } | |
1844 | ||
ff2d8b19 | 1845 | void __noreturn nmi_exception_handler(struct pt_regs *regs) |
1da177e4 | 1846 | { |
83e4da1e LY |
1847 | char str[100]; |
1848 | ||
7963b3f1 | 1849 | nmi_enter(); |
34bd92e2 | 1850 | raw_notifier_call_chain(&nmi_chain, 0, regs); |
41c594ab | 1851 | bust_spinlocks(1); |
83e4da1e LY |
1852 | snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n", |
1853 | smp_processor_id(), regs->cp0_epc); | |
1854 | regs->cp0_epc = read_c0_errorepc(); | |
1855 | die(str, regs); | |
7963b3f1 | 1856 | nmi_exit(); |
1da177e4 LT |
1857 | } |
1858 | ||
e01402b1 RB |
1859 | #define VECTORSPACING 0x100 /* for EI/VI mode */ |
1860 | ||
1861 | unsigned long ebase; | |
1da177e4 | 1862 | unsigned long exception_handlers[32]; |
e01402b1 | 1863 | unsigned long vi_handlers[64]; |
1da177e4 | 1864 | |
2d1b6e95 | 1865 | void __init *set_except_vector(int n, void *addr) |
1da177e4 LT |
1866 | { |
1867 | unsigned long handler = (unsigned long) addr; | |
b22d1b6a | 1868 | unsigned long old_handler; |
1da177e4 | 1869 | |
2a0b24f5 SH |
1870 | #ifdef CONFIG_CPU_MICROMIPS |
1871 | /* | |
1872 | * Only the TLB handlers are cache aligned with an even | |
1873 | * address. All other handlers are on an odd address and | |
1874 | * require no modification. Otherwise, MIPS32 mode will | |
1875 | * be entered when handling any TLB exceptions. That | |
1876 | * would be bad...since we must stay in microMIPS mode. | |
1877 | */ | |
1878 | if (!(handler & 0x1)) | |
1879 | handler |= 1; | |
1880 | #endif | |
b22d1b6a | 1881 | old_handler = xchg(&exception_handlers[n], handler); |
1da177e4 | 1882 | |
1da177e4 | 1883 | if (n == 0 && cpu_has_divec) { |
2a0b24f5 SH |
1884 | #ifdef CONFIG_CPU_MICROMIPS |
1885 | unsigned long jump_mask = ~((1 << 27) - 1); | |
1886 | #else | |
92bbe1b9 | 1887 | unsigned long jump_mask = ~((1 << 28) - 1); |
2a0b24f5 | 1888 | #endif |
92bbe1b9 FF |
1889 | u32 *buf = (u32 *)(ebase + 0x200); |
1890 | unsigned int k0 = 26; | |
1891 | if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { | |
1892 | uasm_i_j(&buf, handler & ~jump_mask); | |
1893 | uasm_i_nop(&buf); | |
1894 | } else { | |
1895 | UASM_i_LA(&buf, k0, handler); | |
1896 | uasm_i_jr(&buf, k0); | |
1897 | uasm_i_nop(&buf); | |
1898 | } | |
1899 | local_flush_icache_range(ebase + 0x200, (unsigned long)buf); | |
e01402b1 RB |
1900 | } |
1901 | return (void *)old_handler; | |
1902 | } | |
1903 | ||
86a1708a | 1904 | static void do_default_vi(void) |
6ba07e59 AN |
1905 | { |
1906 | show_regs(get_irq_regs()); | |
1907 | panic("Caught unexpected vectored interrupt."); | |
1908 | } | |
1909 | ||
ef300e42 | 1910 | static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) |
e01402b1 RB |
1911 | { |
1912 | unsigned long handler; | |
1913 | unsigned long old_handler = vi_handlers[n]; | |
f6771dbb | 1914 | int srssets = current_cpu_data.srsets; |
2a0b24f5 | 1915 | u16 *h; |
e01402b1 RB |
1916 | unsigned char *b; |
1917 | ||
b72b7092 | 1918 | BUG_ON(!cpu_has_veic && !cpu_has_vint); |
e01402b1 RB |
1919 | |
1920 | if (addr == NULL) { | |
1921 | handler = (unsigned long) do_default_vi; | |
1922 | srs = 0; | |
41c594ab | 1923 | } else |
e01402b1 | 1924 | handler = (unsigned long) addr; |
2a0b24f5 | 1925 | vi_handlers[n] = handler; |
e01402b1 RB |
1926 | |
1927 | b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); | |
1928 | ||
f6771dbb | 1929 | if (srs >= srssets) |
e01402b1 RB |
1930 | panic("Shadow register set %d not supported", srs); |
1931 | ||
1932 | if (cpu_has_veic) { | |
1933 | if (board_bind_eic_interrupt) | |
49a89efb | 1934 | board_bind_eic_interrupt(n, srs); |
41c594ab | 1935 | } else if (cpu_has_vint) { |
e01402b1 | 1936 | /* SRSMap is only defined if shadow sets are implemented */ |
f6771dbb | 1937 | if (srssets > 1) |
49a89efb | 1938 | change_c0_srsmap(0xf << n*4, srs << n*4); |
e01402b1 RB |
1939 | } |
1940 | ||
1941 | if (srs == 0) { | |
1942 | /* | |
1943 | * If no shadow set is selected then use the default handler | |
2a0b24f5 | 1944 | * that does normal register saving and standard interrupt exit |
e01402b1 | 1945 | */ |
e01402b1 RB |
1946 | extern char except_vec_vi, except_vec_vi_lui; |
1947 | extern char except_vec_vi_ori, except_vec_vi_end; | |
c65a5480 | 1948 | extern char rollback_except_vec_vi; |
f94d9a8e | 1949 | char *vec_start = using_rollback_handler() ? |
c65a5480 | 1950 | &rollback_except_vec_vi : &except_vec_vi; |
2a0b24f5 SH |
1951 | #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) |
1952 | const int lui_offset = &except_vec_vi_lui - vec_start + 2; | |
1953 | const int ori_offset = &except_vec_vi_ori - vec_start + 2; | |
1954 | #else | |
c65a5480 AN |
1955 | const int lui_offset = &except_vec_vi_lui - vec_start; |
1956 | const int ori_offset = &except_vec_vi_ori - vec_start; | |
2a0b24f5 SH |
1957 | #endif |
1958 | const int handler_len = &except_vec_vi_end - vec_start; | |
e01402b1 RB |
1959 | |
1960 | if (handler_len > VECTORSPACING) { | |
1961 | /* | |
1962 | * Sigh... panicing won't help as the console | |
1963 | * is probably not configured :( | |
1964 | */ | |
49a89efb | 1965 | panic("VECTORSPACING too small"); |
e01402b1 RB |
1966 | } |
1967 | ||
2a0b24f5 SH |
1968 | set_handler(((unsigned long)b - ebase), vec_start, |
1969 | #ifdef CONFIG_CPU_MICROMIPS | |
1970 | (handler_len - 1)); | |
1971 | #else | |
1972 | handler_len); | |
1973 | #endif | |
2a0b24f5 SH |
1974 | h = (u16 *)(b + lui_offset); |
1975 | *h = (handler >> 16) & 0xffff; | |
1976 | h = (u16 *)(b + ori_offset); | |
1977 | *h = (handler & 0xffff); | |
e0cee3ee TB |
1978 | local_flush_icache_range((unsigned long)b, |
1979 | (unsigned long)(b+handler_len)); | |
e01402b1 RB |
1980 | } |
1981 | else { | |
1982 | /* | |
2a0b24f5 SH |
1983 | * In other cases jump directly to the interrupt handler. It |
1984 | * is the handler's responsibility to save registers if required | |
1985 | * (eg hi/lo) and return from the exception using "eret". | |
e01402b1 | 1986 | */ |
2a0b24f5 SH |
1987 | u32 insn; |
1988 | ||
1989 | h = (u16 *)b; | |
1990 | /* j handler */ | |
1991 | #ifdef CONFIG_CPU_MICROMIPS | |
1992 | insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1); | |
1993 | #else | |
1994 | insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2); | |
1995 | #endif | |
1996 | h[0] = (insn >> 16) & 0xffff; | |
1997 | h[1] = insn & 0xffff; | |
1998 | h[2] = 0; | |
1999 | h[3] = 0; | |
e0cee3ee TB |
2000 | local_flush_icache_range((unsigned long)b, |
2001 | (unsigned long)(b+8)); | |
1da177e4 | 2002 | } |
e01402b1 | 2003 | |
1da177e4 LT |
2004 | return (void *)old_handler; |
2005 | } | |
2006 | ||
ef300e42 | 2007 | void *set_vi_handler(int n, vi_handler_t addr) |
e01402b1 | 2008 | { |
ff3eab2a | 2009 | return set_vi_srs_handler(n, addr, 0); |
e01402b1 | 2010 | } |
f41ae0b2 | 2011 | |
1da177e4 LT |
2012 | extern void tlb_init(void); |
2013 | ||
42f77542 RB |
2014 | /* |
2015 | * Timer interrupt | |
2016 | */ | |
2017 | int cp0_compare_irq; | |
68b6352c | 2018 | EXPORT_SYMBOL_GPL(cp0_compare_irq); |
010c108d | 2019 | int cp0_compare_irq_shift; |
42f77542 RB |
2020 | |
2021 | /* | |
2022 | * Performance counter IRQ or -1 if shared with timer | |
2023 | */ | |
2024 | int cp0_perfcount_irq; | |
2025 | EXPORT_SYMBOL_GPL(cp0_perfcount_irq); | |
2026 | ||
8f7ff027 JH |
2027 | /* |
2028 | * Fast debug channel IRQ or -1 if not present | |
2029 | */ | |
2030 | int cp0_fdc_irq; | |
2031 | EXPORT_SYMBOL_GPL(cp0_fdc_irq); | |
2032 | ||
078a55fc | 2033 | static int noulri; |
bdc94eb4 CD |
2034 | |
2035 | static int __init ulri_disable(char *s) | |
2036 | { | |
2037 | pr_info("Disabling ulri\n"); | |
2038 | noulri = 1; | |
2039 | ||
2040 | return 1; | |
2041 | } | |
2042 | __setup("noulri", ulri_disable); | |
2043 | ||
ae4ce454 JH |
2044 | /* configure STATUS register */ |
2045 | static void configure_status(void) | |
1da177e4 | 2046 | { |
1da177e4 LT |
2047 | /* |
2048 | * Disable coprocessors and select 32-bit or 64-bit addressing | |
2049 | * and the 16/32 or 32/32 FPR register model. Reset the BEV | |
2050 | * flag that some firmware may have left set and the TS bit (for | |
2051 | * IP27). Set XX for ISA IV code to work. | |
2052 | */ | |
ae4ce454 | 2053 | unsigned int status_set = ST0_CU0; |
875d43e7 | 2054 | #ifdef CONFIG_64BIT |
1da177e4 LT |
2055 | status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; |
2056 | #endif | |
adb37892 | 2057 | if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV) |
1da177e4 | 2058 | status_set |= ST0_XX; |
bbaf238b CD |
2059 | if (cpu_has_dsp) |
2060 | status_set |= ST0_MX; | |
2061 | ||
b38c7399 | 2062 | change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, |
1da177e4 | 2063 | status_set); |
ae4ce454 JH |
2064 | } |
2065 | ||
2066 | /* configure HWRENA register */ | |
2067 | static void configure_hwrena(void) | |
2068 | { | |
2069 | unsigned int hwrena = cpu_hwrena_impl_bits; | |
1da177e4 | 2070 | |
9c7d5768 | 2071 | if (cpu_has_mips_r2_r6) |
18d693b3 | 2072 | hwrena |= 0x0000000f; |
a3692020 | 2073 | |
18d693b3 KC |
2074 | if (!noulri && cpu_has_userlocal) |
2075 | hwrena |= (1 << 29); | |
a3692020 | 2076 | |
18d693b3 KC |
2077 | if (hwrena) |
2078 | write_c0_hwrena(hwrena); | |
ae4ce454 | 2079 | } |
e01402b1 | 2080 | |
ae4ce454 JH |
2081 | static void configure_exception_vector(void) |
2082 | { | |
e01402b1 | 2083 | if (cpu_has_veic || cpu_has_vint) { |
9fb4c2b9 | 2084 | unsigned long sr = set_c0_status(ST0_BEV); |
49a89efb | 2085 | write_c0_ebase(ebase); |
9fb4c2b9 | 2086 | write_c0_status(sr); |
e01402b1 | 2087 | /* Setting vector spacing enables EI/VI mode */ |
49a89efb | 2088 | change_c0_intctl(0x3e0, VECTORSPACING); |
e01402b1 | 2089 | } |
d03d0a57 RB |
2090 | if (cpu_has_divec) { |
2091 | if (cpu_has_mipsmt) { | |
2092 | unsigned int vpflags = dvpe(); | |
2093 | set_c0_cause(CAUSEF_IV); | |
2094 | evpe(vpflags); | |
2095 | } else | |
2096 | set_c0_cause(CAUSEF_IV); | |
2097 | } | |
ae4ce454 JH |
2098 | } |
2099 | ||
2100 | void per_cpu_trap_init(bool is_boot_cpu) | |
2101 | { | |
2102 | unsigned int cpu = smp_processor_id(); | |
ae4ce454 JH |
2103 | |
2104 | configure_status(); | |
2105 | configure_hwrena(); | |
2106 | ||
ae4ce454 | 2107 | configure_exception_vector(); |
3b1d4ed5 RB |
2108 | |
2109 | /* | |
2110 | * Before R2 both interrupt numbers were fixed to 7, so on R2 only: | |
2111 | * | |
2112 | * o read IntCtl.IPTI to determine the timer interrupt | |
2113 | * o read IntCtl.IPPCI to determine the performance counter interrupt | |
8f7ff027 | 2114 | * o read IntCtl.IPFDC to determine the fast debug channel interrupt |
3b1d4ed5 | 2115 | */ |
9c7d5768 | 2116 | if (cpu_has_mips_r2_r6) { |
04d83f94 MC |
2117 | /* |
2118 | * We shouldn't trust a secondary core has a sane EBASE register | |
2119 | * so use the one calculated by the boot CPU. | |
2120 | */ | |
2121 | if (!is_boot_cpu) | |
2122 | write_c0_ebase(ebase); | |
2123 | ||
010c108d DV |
2124 | cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; |
2125 | cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; | |
2126 | cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; | |
8f7ff027 JH |
2127 | cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7; |
2128 | if (!cp0_fdc_irq) | |
2129 | cp0_fdc_irq = -1; | |
2130 | ||
c3e838a2 CD |
2131 | } else { |
2132 | cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; | |
c6a4ebb9 | 2133 | cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ; |
c3e838a2 | 2134 | cp0_perfcount_irq = -1; |
8f7ff027 | 2135 | cp0_fdc_irq = -1; |
3b1d4ed5 RB |
2136 | } |
2137 | ||
48c4ac97 | 2138 | if (!cpu_data[cpu].asid_cache) |
4edf00a4 | 2139 | cpu_data[cpu].asid_cache = asid_first_version(cpu); |
1da177e4 LT |
2140 | |
2141 | atomic_inc(&init_mm.mm_count); | |
2142 | current->active_mm = &init_mm; | |
2143 | BUG_ON(current->mm); | |
2144 | enter_lazy_tlb(&init_mm, current); | |
2145 | ||
761b4493 MC |
2146 | /* Boot CPU's cache setup in setup_arch(). */ |
2147 | if (!is_boot_cpu) | |
2148 | cpu_cache_init(); | |
2149 | tlb_init(); | |
3d8bfdd0 | 2150 | TLBMISS_HANDLER_SETUP(); |
1da177e4 LT |
2151 | } |
2152 | ||
e01402b1 | 2153 | /* Install CPU exception handler */ |
078a55fc | 2154 | void set_handler(unsigned long offset, void *addr, unsigned long size) |
e01402b1 | 2155 | { |
2a0b24f5 SH |
2156 | #ifdef CONFIG_CPU_MICROMIPS |
2157 | memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size); | |
2158 | #else | |
e01402b1 | 2159 | memcpy((void *)(ebase + offset), addr, size); |
2a0b24f5 | 2160 | #endif |
e0cee3ee | 2161 | local_flush_icache_range(ebase + offset, ebase + offset + size); |
e01402b1 RB |
2162 | } |
2163 | ||
078a55fc | 2164 | static char panic_null_cerr[] = |
641e97f3 RB |
2165 | "Trying to set NULL cache error exception handler"; |
2166 | ||
42fe7ee3 RB |
2167 | /* |
2168 | * Install uncached CPU exception handler. | |
2169 | * This is suitable only for the cache error exception which is the only | |
2170 | * exception handler that is being run uncached. | |
2171 | */ | |
078a55fc | 2172 | void set_uncached_handler(unsigned long offset, void *addr, |
234fcd14 | 2173 | unsigned long size) |
e01402b1 | 2174 | { |
4f81b01a | 2175 | unsigned long uncached_ebase = CKSEG1ADDR(ebase); |
e01402b1 | 2176 | |
641e97f3 RB |
2177 | if (!addr) |
2178 | panic(panic_null_cerr); | |
2179 | ||
e01402b1 RB |
2180 | memcpy((void *)(uncached_ebase + offset), addr, size); |
2181 | } | |
2182 | ||
5b10496b AN |
2183 | static int __initdata rdhwr_noopt; |
2184 | static int __init set_rdhwr_noopt(char *str) | |
2185 | { | |
2186 | rdhwr_noopt = 1; | |
2187 | return 1; | |
2188 | } | |
2189 | ||
2190 | __setup("rdhwr_noopt", set_rdhwr_noopt); | |
2191 | ||
1da177e4 LT |
2192 | void __init trap_init(void) |
2193 | { | |
2a0b24f5 | 2194 | extern char except_vec3_generic; |
1da177e4 | 2195 | extern char except_vec4; |
2a0b24f5 | 2196 | extern char except_vec3_r4000; |
1da177e4 | 2197 | unsigned long i; |
c65a5480 AN |
2198 | |
2199 | check_wait(); | |
1da177e4 | 2200 | |
9fb4c2b9 CD |
2201 | if (cpu_has_veic || cpu_has_vint) { |
2202 | unsigned long size = 0x200 + VECTORSPACING*64; | |
2203 | ebase = (unsigned long) | |
2204 | __alloc_bootmem(size, 1 << fls(size), 0); | |
2205 | } else { | |
a13c9962 PB |
2206 | ebase = CAC_BASE; |
2207 | ||
9c7d5768 | 2208 | if (cpu_has_mips_r2_r6) |
566f74f6 DD |
2209 | ebase += (read_c0_ebase() & 0x3ffff000); |
2210 | } | |
e01402b1 | 2211 | |
c6213c6c SH |
2212 | if (cpu_has_mmips) { |
2213 | unsigned int config3 = read_c0_config3(); | |
2214 | ||
2215 | if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) | |
2216 | write_c0_config3(config3 | MIPS_CONF3_ISA_OE); | |
2217 | else | |
2218 | write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE); | |
2219 | } | |
2220 | ||
6fb97eff KC |
2221 | if (board_ebase_setup) |
2222 | board_ebase_setup(); | |
6650df3c | 2223 | per_cpu_trap_init(true); |
1da177e4 LT |
2224 | |
2225 | /* | |
2226 | * Copy the generic exception handlers to their final destination. | |
92a76f6d | 2227 | * This will be overridden later as suitable for a particular |
1da177e4 LT |
2228 | * configuration. |
2229 | */ | |
e01402b1 | 2230 | set_handler(0x180, &except_vec3_generic, 0x80); |
1da177e4 LT |
2231 | |
2232 | /* | |
2233 | * Setup default vectors | |
2234 | */ | |
2235 | for (i = 0; i <= 31; i++) | |
2236 | set_except_vector(i, handle_reserved); | |
2237 | ||
2238 | /* | |
2239 | * Copy the EJTAG debug exception vector handler code to it's final | |
2240 | * destination. | |
2241 | */ | |
e01402b1 | 2242 | if (cpu_has_ejtag && board_ejtag_handler_setup) |
49a89efb | 2243 | board_ejtag_handler_setup(); |
1da177e4 LT |
2244 | |
2245 | /* | |
2246 | * Only some CPUs have the watch exceptions. | |
2247 | */ | |
2248 | if (cpu_has_watch) | |
1b505def | 2249 | set_except_vector(EXCCODE_WATCH, handle_watch); |
1da177e4 LT |
2250 | |
2251 | /* | |
e01402b1 | 2252 | * Initialise interrupt handlers |
1da177e4 | 2253 | */ |
e01402b1 RB |
2254 | if (cpu_has_veic || cpu_has_vint) { |
2255 | int nvec = cpu_has_veic ? 64 : 8; | |
2256 | for (i = 0; i < nvec; i++) | |
ff3eab2a | 2257 | set_vi_handler(i, NULL); |
e01402b1 RB |
2258 | } |
2259 | else if (cpu_has_divec) | |
2260 | set_handler(0x200, &except_vec4, 0x8); | |
1da177e4 LT |
2261 | |
2262 | /* | |
2263 | * Some CPUs can enable/disable for cache parity detection, but does | |
2264 | * it different ways. | |
2265 | */ | |
2266 | parity_protection_init(); | |
2267 | ||
2268 | /* | |
2269 | * The Data Bus Errors / Instruction Bus Errors are signaled | |
2270 | * by external hardware. Therefore these two exceptions | |
2271 | * may have board specific handlers. | |
2272 | */ | |
2273 | if (board_be_init) | |
2274 | board_be_init(); | |
2275 | ||
1b505def JH |
2276 | set_except_vector(EXCCODE_INT, using_rollback_handler() ? |
2277 | rollback_handle_int : handle_int); | |
2278 | set_except_vector(EXCCODE_MOD, handle_tlbm); | |
2279 | set_except_vector(EXCCODE_TLBL, handle_tlbl); | |
2280 | set_except_vector(EXCCODE_TLBS, handle_tlbs); | |
1da177e4 | 2281 | |
1b505def JH |
2282 | set_except_vector(EXCCODE_ADEL, handle_adel); |
2283 | set_except_vector(EXCCODE_ADES, handle_ades); | |
1da177e4 | 2284 | |
1b505def JH |
2285 | set_except_vector(EXCCODE_IBE, handle_ibe); |
2286 | set_except_vector(EXCCODE_DBE, handle_dbe); | |
1da177e4 | 2287 | |
1b505def JH |
2288 | set_except_vector(EXCCODE_SYS, handle_sys); |
2289 | set_except_vector(EXCCODE_BP, handle_bp); | |
2290 | set_except_vector(EXCCODE_RI, rdhwr_noopt ? handle_ri : | |
5b10496b AN |
2291 | (cpu_has_vtag_icache ? |
2292 | handle_ri_rdhwr_vivt : handle_ri_rdhwr)); | |
1b505def JH |
2293 | set_except_vector(EXCCODE_CPU, handle_cpu); |
2294 | set_except_vector(EXCCODE_OV, handle_ov); | |
2295 | set_except_vector(EXCCODE_TR, handle_tr); | |
2296 | set_except_vector(EXCCODE_MSAFPE, handle_msa_fpe); | |
1da177e4 | 2297 | |
10cc3529 RB |
2298 | if (current_cpu_type() == CPU_R6000 || |
2299 | current_cpu_type() == CPU_R6000A) { | |
1da177e4 LT |
2300 | /* |
2301 | * The R6000 is the only R-series CPU that features a machine | |
2302 | * check exception (similar to the R4000 cache error) and | |
2303 | * unaligned ldc1/sdc1 exception. The handlers have not been | |
70342287 | 2304 | * written yet. Well, anyway there is no R6000 machine on the |
1da177e4 LT |
2305 | * current list of targets for Linux/MIPS. |
2306 | * (Duh, crap, there is someone with a triple R6k machine) | |
2307 | */ | |
2308 | //set_except_vector(14, handle_mc); | |
2309 | //set_except_vector(15, handle_ndc); | |
2310 | } | |
2311 | ||
e01402b1 RB |
2312 | |
2313 | if (board_nmi_handler_setup) | |
2314 | board_nmi_handler_setup(); | |
2315 | ||
e50c0a8f | 2316 | if (cpu_has_fpu && !cpu_has_nofpuex) |
1b505def | 2317 | set_except_vector(EXCCODE_FPE, handle_fpe); |
e50c0a8f | 2318 | |
1b505def | 2319 | set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb); |
5890f70f LY |
2320 | |
2321 | if (cpu_has_rixiex) { | |
1b505def JH |
2322 | set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0); |
2323 | set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0); | |
5890f70f LY |
2324 | } |
2325 | ||
1b505def JH |
2326 | set_except_vector(EXCCODE_MSADIS, handle_msa); |
2327 | set_except_vector(EXCCODE_MDMX, handle_mdmx); | |
e50c0a8f RB |
2328 | |
2329 | if (cpu_has_mcheck) | |
1b505def | 2330 | set_except_vector(EXCCODE_MCHECK, handle_mcheck); |
e50c0a8f | 2331 | |
340ee4b9 | 2332 | if (cpu_has_mipsmt) |
1b505def | 2333 | set_except_vector(EXCCODE_THREAD, handle_mt); |
340ee4b9 | 2334 | |
1b505def | 2335 | set_except_vector(EXCCODE_DSPDIS, handle_dsp); |
e50c0a8f | 2336 | |
fcbf1dfd DD |
2337 | if (board_cache_error_setup) |
2338 | board_cache_error_setup(); | |
2339 | ||
e50c0a8f RB |
2340 | if (cpu_has_vce) |
2341 | /* Special exception: R4[04]00 uses also the divec space. */ | |
2a0b24f5 | 2342 | set_handler(0x180, &except_vec3_r4000, 0x100); |
e50c0a8f | 2343 | else if (cpu_has_4kex) |
2a0b24f5 | 2344 | set_handler(0x180, &except_vec3_generic, 0x80); |
e50c0a8f | 2345 | else |
2a0b24f5 | 2346 | set_handler(0x080, &except_vec3_generic, 0x80); |
e50c0a8f | 2347 | |
e0cee3ee | 2348 | local_flush_icache_range(ebase, ebase + 0x400); |
0510617b TB |
2349 | |
2350 | sort_extable(__start___dbe_table, __stop___dbe_table); | |
69f3a7de | 2351 | |
4483b159 | 2352 | cu2_notifier(default_cu2_call, 0x80000000); /* Run last */ |
1da177e4 | 2353 | } |
ae4ce454 JH |
2354 | |
2355 | static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd, | |
2356 | void *v) | |
2357 | { | |
2358 | switch (cmd) { | |
2359 | case CPU_PM_ENTER_FAILED: | |
2360 | case CPU_PM_EXIT: | |
2361 | configure_status(); | |
2362 | configure_hwrena(); | |
2363 | configure_exception_vector(); | |
2364 | ||
2365 | /* Restore register with CPU number for TLB handlers */ | |
2366 | TLBMISS_HANDLER_RESTORE(); | |
2367 | ||
2368 | break; | |
2369 | } | |
2370 | ||
2371 | return NOTIFY_OK; | |
2372 | } | |
2373 | ||
2374 | static struct notifier_block trap_pm_notifier_block = { | |
2375 | .notifier_call = trap_pm_notifier, | |
2376 | }; | |
2377 | ||
2378 | static int __init trap_pm_init(void) | |
2379 | { | |
2380 | return cpu_pm_register_notifier(&trap_pm_notifier_block); | |
2381 | } | |
2382 | arch_initcall(trap_pm_init); |