Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
36ccf1c0 | 6 | * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle |
1da177e4 LT |
7 | * Copyright (C) 1995, 1996 Paul M. Antoine |
8 | * Copyright (C) 1998 Ulf Carlsson | |
9 | * Copyright (C) 1999 Silicon Graphics, Inc. | |
10 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
11 | * Copyright (C) 2000, 01 MIPS Technologies, Inc. | |
60b0d655 | 12 | * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki |
1da177e4 | 13 | */ |
8e8a52ed | 14 | #include <linux/bug.h> |
60b0d655 | 15 | #include <linux/compiler.h> |
1da177e4 | 16 | #include <linux/init.h> |
8742cd23 | 17 | #include <linux/kernel.h> |
1da177e4 | 18 | #include <linux/mm.h> |
1da177e4 LT |
19 | #include <linux/sched.h> |
20 | #include <linux/smp.h> | |
1da177e4 LT |
21 | #include <linux/spinlock.h> |
22 | #include <linux/kallsyms.h> | |
e01402b1 | 23 | #include <linux/bootmem.h> |
d4fd1989 | 24 | #include <linux/interrupt.h> |
39b8d525 | 25 | #include <linux/ptrace.h> |
88547001 JW |
26 | #include <linux/kgdb.h> |
27 | #include <linux/kdebug.h> | |
c1bf207d | 28 | #include <linux/kprobes.h> |
69f3a7de | 29 | #include <linux/notifier.h> |
5dd11d5d | 30 | #include <linux/kdb.h> |
ca4d3e67 | 31 | #include <linux/irq.h> |
7f788d2d | 32 | #include <linux/perf_event.h> |
1da177e4 LT |
33 | |
34 | #include <asm/bootinfo.h> | |
35 | #include <asm/branch.h> | |
36 | #include <asm/break.h> | |
69f3a7de | 37 | #include <asm/cop2.h> |
1da177e4 | 38 | #include <asm/cpu.h> |
e50c0a8f | 39 | #include <asm/dsp.h> |
1da177e4 | 40 | #include <asm/fpu.h> |
ba3049ed | 41 | #include <asm/fpu_emulator.h> |
340ee4b9 RB |
42 | #include <asm/mipsregs.h> |
43 | #include <asm/mipsmtregs.h> | |
1da177e4 LT |
44 | #include <asm/module.h> |
45 | #include <asm/pgtable.h> | |
46 | #include <asm/ptrace.h> | |
47 | #include <asm/sections.h> | |
48 | #include <asm/system.h> | |
49 | #include <asm/tlbdebug.h> | |
50 | #include <asm/traps.h> | |
51 | #include <asm/uaccess.h> | |
b67b2b70 | 52 | #include <asm/watch.h> |
1da177e4 | 53 | #include <asm/mmu_context.h> |
1da177e4 | 54 | #include <asm/types.h> |
1df0f0ff | 55 | #include <asm/stacktrace.h> |
92bbe1b9 | 56 | #include <asm/uasm.h> |
1da177e4 | 57 | |
c65a5480 AN |
58 | extern void check_wait(void); |
59 | extern asmlinkage void r4k_wait(void); | |
60 | extern asmlinkage void rollback_handle_int(void); | |
e4ac58af | 61 | extern asmlinkage void handle_int(void); |
1da177e4 LT |
62 | extern asmlinkage void handle_tlbm(void); |
63 | extern asmlinkage void handle_tlbl(void); | |
64 | extern asmlinkage void handle_tlbs(void); | |
65 | extern asmlinkage void handle_adel(void); | |
66 | extern asmlinkage void handle_ades(void); | |
67 | extern asmlinkage void handle_ibe(void); | |
68 | extern asmlinkage void handle_dbe(void); | |
69 | extern asmlinkage void handle_sys(void); | |
70 | extern asmlinkage void handle_bp(void); | |
71 | extern asmlinkage void handle_ri(void); | |
5b10496b AN |
72 | extern asmlinkage void handle_ri_rdhwr_vivt(void); |
73 | extern asmlinkage void handle_ri_rdhwr(void); | |
1da177e4 LT |
74 | extern asmlinkage void handle_cpu(void); |
75 | extern asmlinkage void handle_ov(void); | |
76 | extern asmlinkage void handle_tr(void); | |
77 | extern asmlinkage void handle_fpe(void); | |
78 | extern asmlinkage void handle_mdmx(void); | |
79 | extern asmlinkage void handle_watch(void); | |
340ee4b9 | 80 | extern asmlinkage void handle_mt(void); |
e50c0a8f | 81 | extern asmlinkage void handle_dsp(void); |
1da177e4 LT |
82 | extern asmlinkage void handle_mcheck(void); |
83 | extern asmlinkage void handle_reserved(void); | |
84 | ||
12616ed2 | 85 | extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, |
515b029d DD |
86 | struct mips_fpu_struct *ctx, int has_fpu, |
87 | void *__user *fault_addr); | |
1da177e4 LT |
88 | |
89 | void (*board_be_init)(void); | |
90 | int (*board_be_handler)(struct pt_regs *regs, int is_fixup); | |
e01402b1 RB |
91 | void (*board_nmi_handler_setup)(void); |
92 | void (*board_ejtag_handler_setup)(void); | |
93 | void (*board_bind_eic_interrupt)(int irq, int regset); | |
1da177e4 | 94 | |
1da177e4 | 95 | |
4d157d5e | 96 | static void show_raw_backtrace(unsigned long reg29) |
e889d78f | 97 | { |
39b8d525 | 98 | unsigned long *sp = (unsigned long *)(reg29 & ~3); |
e889d78f AN |
99 | unsigned long addr; |
100 | ||
101 | printk("Call Trace:"); | |
102 | #ifdef CONFIG_KALLSYMS | |
103 | printk("\n"); | |
104 | #endif | |
10220c88 TB |
105 | while (!kstack_end(sp)) { |
106 | unsigned long __user *p = | |
107 | (unsigned long __user *)(unsigned long)sp++; | |
108 | if (__get_user(addr, p)) { | |
109 | printk(" (Bad stack address)"); | |
110 | break; | |
39b8d525 | 111 | } |
10220c88 TB |
112 | if (__kernel_text_address(addr)) |
113 | print_ip_sym(addr); | |
e889d78f | 114 | } |
10220c88 | 115 | printk("\n"); |
e889d78f AN |
116 | } |
117 | ||
f66686f7 | 118 | #ifdef CONFIG_KALLSYMS |
1df0f0ff | 119 | int raw_show_trace; |
f66686f7 AN |
120 | static int __init set_raw_show_trace(char *str) |
121 | { | |
122 | raw_show_trace = 1; | |
123 | return 1; | |
124 | } | |
125 | __setup("raw_show_trace", set_raw_show_trace); | |
1df0f0ff | 126 | #endif |
4d157d5e | 127 | |
eae23f2c | 128 | static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) |
f66686f7 | 129 | { |
4d157d5e FBH |
130 | unsigned long sp = regs->regs[29]; |
131 | unsigned long ra = regs->regs[31]; | |
f66686f7 | 132 | unsigned long pc = regs->cp0_epc; |
f66686f7 AN |
133 | |
134 | if (raw_show_trace || !__kernel_text_address(pc)) { | |
87151ae3 | 135 | show_raw_backtrace(sp); |
f66686f7 AN |
136 | return; |
137 | } | |
138 | printk("Call Trace:\n"); | |
4d157d5e | 139 | do { |
87151ae3 | 140 | print_ip_sym(pc); |
1924600c | 141 | pc = unwind_stack(task, &sp, pc, &ra); |
4d157d5e | 142 | } while (pc); |
f66686f7 AN |
143 | printk("\n"); |
144 | } | |
f66686f7 | 145 | |
1da177e4 LT |
146 | /* |
147 | * This routine abuses get_user()/put_user() to reference pointers | |
148 | * with at least a bit of error checking ... | |
149 | */ | |
eae23f2c RB |
150 | static void show_stacktrace(struct task_struct *task, |
151 | const struct pt_regs *regs) | |
1da177e4 LT |
152 | { |
153 | const int field = 2 * sizeof(unsigned long); | |
154 | long stackdata; | |
155 | int i; | |
5e0373b8 | 156 | unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; |
1da177e4 LT |
157 | |
158 | printk("Stack :"); | |
159 | i = 0; | |
160 | while ((unsigned long) sp & (PAGE_SIZE - 1)) { | |
161 | if (i && ((i % (64 / field)) == 0)) | |
162 | printk("\n "); | |
163 | if (i > 39) { | |
164 | printk(" ..."); | |
165 | break; | |
166 | } | |
167 | ||
168 | if (__get_user(stackdata, sp++)) { | |
169 | printk(" (Bad stack address)"); | |
170 | break; | |
171 | } | |
172 | ||
173 | printk(" %0*lx", field, stackdata); | |
174 | i++; | |
175 | } | |
176 | printk("\n"); | |
87151ae3 | 177 | show_backtrace(task, regs); |
f66686f7 AN |
178 | } |
179 | ||
f66686f7 AN |
180 | void show_stack(struct task_struct *task, unsigned long *sp) |
181 | { | |
182 | struct pt_regs regs; | |
183 | if (sp) { | |
184 | regs.regs[29] = (unsigned long)sp; | |
185 | regs.regs[31] = 0; | |
186 | regs.cp0_epc = 0; | |
187 | } else { | |
188 | if (task && task != current) { | |
189 | regs.regs[29] = task->thread.reg29; | |
190 | regs.regs[31] = 0; | |
191 | regs.cp0_epc = task->thread.reg31; | |
5dd11d5d JW |
192 | #ifdef CONFIG_KGDB_KDB |
193 | } else if (atomic_read(&kgdb_active) != -1 && | |
194 | kdb_current_regs) { | |
195 | memcpy(®s, kdb_current_regs, sizeof(regs)); | |
196 | #endif /* CONFIG_KGDB_KDB */ | |
f66686f7 AN |
197 | } else { |
198 | prepare_frametrace(®s); | |
199 | } | |
200 | } | |
201 | show_stacktrace(task, ®s); | |
1da177e4 LT |
202 | } |
203 | ||
204 | /* | |
205 | * The architecture-independent dump_stack generator | |
206 | */ | |
207 | void dump_stack(void) | |
208 | { | |
1666a6fc | 209 | struct pt_regs regs; |
1da177e4 | 210 | |
1666a6fc FBH |
211 | prepare_frametrace(®s); |
212 | show_backtrace(current, ®s); | |
1da177e4 LT |
213 | } |
214 | ||
215 | EXPORT_SYMBOL(dump_stack); | |
216 | ||
e1bb8289 | 217 | static void show_code(unsigned int __user *pc) |
1da177e4 LT |
218 | { |
219 | long i; | |
39b8d525 | 220 | unsigned short __user *pc16 = NULL; |
1da177e4 LT |
221 | |
222 | printk("\nCode:"); | |
223 | ||
39b8d525 RB |
224 | if ((unsigned long)pc & 1) |
225 | pc16 = (unsigned short __user *)((unsigned long)pc & ~1); | |
1da177e4 LT |
226 | for(i = -3 ; i < 6 ; i++) { |
227 | unsigned int insn; | |
39b8d525 | 228 | if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { |
1da177e4 LT |
229 | printk(" (Bad address in epc)\n"); |
230 | break; | |
231 | } | |
39b8d525 | 232 | printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); |
1da177e4 LT |
233 | } |
234 | } | |
235 | ||
eae23f2c | 236 | static void __show_regs(const struct pt_regs *regs) |
1da177e4 LT |
237 | { |
238 | const int field = 2 * sizeof(unsigned long); | |
239 | unsigned int cause = regs->cp0_cause; | |
240 | int i; | |
241 | ||
242 | printk("Cpu %d\n", smp_processor_id()); | |
243 | ||
244 | /* | |
245 | * Saved main processor registers | |
246 | */ | |
247 | for (i = 0; i < 32; ) { | |
248 | if ((i % 4) == 0) | |
249 | printk("$%2d :", i); | |
250 | if (i == 0) | |
251 | printk(" %0*lx", field, 0UL); | |
252 | else if (i == 26 || i == 27) | |
253 | printk(" %*s", field, ""); | |
254 | else | |
255 | printk(" %0*lx", field, regs->regs[i]); | |
256 | ||
257 | i++; | |
258 | if ((i % 4) == 0) | |
259 | printk("\n"); | |
260 | } | |
261 | ||
9693a853 FBH |
262 | #ifdef CONFIG_CPU_HAS_SMARTMIPS |
263 | printk("Acx : %0*lx\n", field, regs->acx); | |
264 | #endif | |
1da177e4 LT |
265 | printk("Hi : %0*lx\n", field, regs->hi); |
266 | printk("Lo : %0*lx\n", field, regs->lo); | |
267 | ||
268 | /* | |
269 | * Saved cp0 registers | |
270 | */ | |
b012cffe RB |
271 | printk("epc : %0*lx %pS\n", field, regs->cp0_epc, |
272 | (void *) regs->cp0_epc); | |
1da177e4 | 273 | printk(" %s\n", print_tainted()); |
b012cffe RB |
274 | printk("ra : %0*lx %pS\n", field, regs->regs[31], |
275 | (void *) regs->regs[31]); | |
1da177e4 LT |
276 | |
277 | printk("Status: %08x ", (uint32_t) regs->cp0_status); | |
278 | ||
3b2396d9 MR |
279 | if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { |
280 | if (regs->cp0_status & ST0_KUO) | |
281 | printk("KUo "); | |
282 | if (regs->cp0_status & ST0_IEO) | |
283 | printk("IEo "); | |
284 | if (regs->cp0_status & ST0_KUP) | |
285 | printk("KUp "); | |
286 | if (regs->cp0_status & ST0_IEP) | |
287 | printk("IEp "); | |
288 | if (regs->cp0_status & ST0_KUC) | |
289 | printk("KUc "); | |
290 | if (regs->cp0_status & ST0_IEC) | |
291 | printk("IEc "); | |
292 | } else { | |
293 | if (regs->cp0_status & ST0_KX) | |
294 | printk("KX "); | |
295 | if (regs->cp0_status & ST0_SX) | |
296 | printk("SX "); | |
297 | if (regs->cp0_status & ST0_UX) | |
298 | printk("UX "); | |
299 | switch (regs->cp0_status & ST0_KSU) { | |
300 | case KSU_USER: | |
301 | printk("USER "); | |
302 | break; | |
303 | case KSU_SUPERVISOR: | |
304 | printk("SUPERVISOR "); | |
305 | break; | |
306 | case KSU_KERNEL: | |
307 | printk("KERNEL "); | |
308 | break; | |
309 | default: | |
310 | printk("BAD_MODE "); | |
311 | break; | |
312 | } | |
313 | if (regs->cp0_status & ST0_ERL) | |
314 | printk("ERL "); | |
315 | if (regs->cp0_status & ST0_EXL) | |
316 | printk("EXL "); | |
317 | if (regs->cp0_status & ST0_IE) | |
318 | printk("IE "); | |
1da177e4 | 319 | } |
1da177e4 LT |
320 | printk("\n"); |
321 | ||
322 | printk("Cause : %08x\n", cause); | |
323 | ||
324 | cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; | |
325 | if (1 <= cause && cause <= 5) | |
326 | printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); | |
327 | ||
9966db25 RB |
328 | printk("PrId : %08x (%s)\n", read_c0_prid(), |
329 | cpu_name_string()); | |
1da177e4 LT |
330 | } |
331 | ||
eae23f2c RB |
332 | /* |
333 | * FIXME: really the generic show_regs should take a const pointer argument. | |
334 | */ | |
335 | void show_regs(struct pt_regs *regs) | |
336 | { | |
337 | __show_regs((struct pt_regs *)regs); | |
338 | } | |
339 | ||
c1bf207d | 340 | void show_registers(struct pt_regs *regs) |
1da177e4 | 341 | { |
39b8d525 RB |
342 | const int field = 2 * sizeof(unsigned long); |
343 | ||
eae23f2c | 344 | __show_regs(regs); |
1da177e4 | 345 | print_modules(); |
39b8d525 RB |
346 | printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", |
347 | current->comm, current->pid, current_thread_info(), current, | |
348 | field, current_thread_info()->tp_value); | |
349 | if (cpu_has_userlocal) { | |
350 | unsigned long tls; | |
351 | ||
352 | tls = read_c0_userlocal(); | |
353 | if (tls != current_thread_info()->tp_value) | |
354 | printk("*HwTLS: %0*lx\n", field, tls); | |
355 | } | |
356 | ||
f66686f7 | 357 | show_stacktrace(current, regs); |
e1bb8289 | 358 | show_code((unsigned int __user *) regs->cp0_epc); |
1da177e4 LT |
359 | printk("\n"); |
360 | } | |
361 | ||
70dc6f04 DD |
362 | static int regs_to_trapnr(struct pt_regs *regs) |
363 | { | |
364 | return (regs->cp0_cause >> 2) & 0x1f; | |
365 | } | |
366 | ||
4d85f6af | 367 | static DEFINE_RAW_SPINLOCK(die_lock); |
1da177e4 | 368 | |
70dc6f04 | 369 | void __noreturn die(const char *str, struct pt_regs *regs) |
1da177e4 LT |
370 | { |
371 | static int die_counter; | |
ce384d83 | 372 | int sig = SIGSEGV; |
41c594ab | 373 | #ifdef CONFIG_MIPS_MT_SMTC |
8742cd23 | 374 | unsigned long dvpret; |
41c594ab | 375 | #endif /* CONFIG_MIPS_MT_SMTC */ |
1da177e4 | 376 | |
8742cd23 NL |
377 | oops_enter(); |
378 | ||
10423c91 RB |
379 | if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP) |
380 | sig = 0; | |
5dd11d5d | 381 | |
1da177e4 | 382 | console_verbose(); |
4d85f6af | 383 | raw_spin_lock_irq(&die_lock); |
8742cd23 NL |
384 | #ifdef CONFIG_MIPS_MT_SMTC |
385 | dvpret = dvpe(); | |
386 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
41c594ab RB |
387 | bust_spinlocks(1); |
388 | #ifdef CONFIG_MIPS_MT_SMTC | |
389 | mips_mt_regdump(dvpret); | |
390 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
ce384d83 | 391 | |
178086c8 | 392 | printk("%s[#%d]:\n", str, ++die_counter); |
1da177e4 | 393 | show_registers(regs); |
bcdcd8e7 | 394 | add_taint(TAINT_DIE); |
4d85f6af | 395 | raw_spin_unlock_irq(&die_lock); |
d4fd1989 | 396 | |
8742cd23 NL |
397 | oops_exit(); |
398 | ||
d4fd1989 MB |
399 | if (in_interrupt()) |
400 | panic("Fatal exception in interrupt"); | |
401 | ||
402 | if (panic_on_oops) { | |
403 | printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n"); | |
404 | ssleep(5); | |
405 | panic("Fatal exception"); | |
406 | } | |
407 | ||
ce384d83 | 408 | do_exit(sig); |
1da177e4 LT |
409 | } |
410 | ||
0510617b TB |
411 | extern struct exception_table_entry __start___dbe_table[]; |
412 | extern struct exception_table_entry __stop___dbe_table[]; | |
1da177e4 | 413 | |
b6dcec9b RB |
414 | __asm__( |
415 | " .section __dbe_table, \"a\"\n" | |
416 | " .previous \n"); | |
1da177e4 LT |
417 | |
418 | /* Given an address, look for it in the exception tables. */ | |
419 | static const struct exception_table_entry *search_dbe_tables(unsigned long addr) | |
420 | { | |
421 | const struct exception_table_entry *e; | |
422 | ||
423 | e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); | |
424 | if (!e) | |
425 | e = search_module_dbetables(addr); | |
426 | return e; | |
427 | } | |
428 | ||
429 | asmlinkage void do_be(struct pt_regs *regs) | |
430 | { | |
431 | const int field = 2 * sizeof(unsigned long); | |
432 | const struct exception_table_entry *fixup = NULL; | |
433 | int data = regs->cp0_cause & 4; | |
434 | int action = MIPS_BE_FATAL; | |
435 | ||
436 | /* XXX For now. Fixme, this searches the wrong table ... */ | |
437 | if (data && !user_mode(regs)) | |
438 | fixup = search_dbe_tables(exception_epc(regs)); | |
439 | ||
440 | if (fixup) | |
441 | action = MIPS_BE_FIXUP; | |
442 | ||
443 | if (board_be_handler) | |
28fc582c | 444 | action = board_be_handler(regs, fixup != NULL); |
1da177e4 LT |
445 | |
446 | switch (action) { | |
447 | case MIPS_BE_DISCARD: | |
448 | return; | |
449 | case MIPS_BE_FIXUP: | |
450 | if (fixup) { | |
451 | regs->cp0_epc = fixup->nextinsn; | |
452 | return; | |
453 | } | |
454 | break; | |
455 | default: | |
456 | break; | |
457 | } | |
458 | ||
459 | /* | |
460 | * Assume it would be too dangerous to continue ... | |
461 | */ | |
462 | printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", | |
463 | data ? "Data" : "Instruction", | |
464 | field, regs->cp0_epc, field, regs->regs[31]); | |
70dc6f04 | 465 | if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS) |
88547001 JW |
466 | == NOTIFY_STOP) |
467 | return; | |
468 | ||
1da177e4 LT |
469 | die_if_kernel("Oops", regs); |
470 | force_sig(SIGBUS, current); | |
471 | } | |
472 | ||
1da177e4 | 473 | /* |
60b0d655 | 474 | * ll/sc, rdhwr, sync emulation |
1da177e4 LT |
475 | */ |
476 | ||
477 | #define OPCODE 0xfc000000 | |
478 | #define BASE 0x03e00000 | |
479 | #define RT 0x001f0000 | |
480 | #define OFFSET 0x0000ffff | |
481 | #define LL 0xc0000000 | |
482 | #define SC 0xe0000000 | |
60b0d655 | 483 | #define SPEC0 0x00000000 |
3c37026d RB |
484 | #define SPEC3 0x7c000000 |
485 | #define RD 0x0000f800 | |
486 | #define FUNC 0x0000003f | |
60b0d655 | 487 | #define SYNC 0x0000000f |
3c37026d | 488 | #define RDHWR 0x0000003b |
1da177e4 LT |
489 | |
490 | /* | |
491 | * The ll_bit is cleared by r*_switch.S | |
492 | */ | |
493 | ||
f1e39a4a RB |
494 | unsigned int ll_bit; |
495 | struct task_struct *ll_task; | |
1da177e4 | 496 | |
60b0d655 | 497 | static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 498 | { |
fe00f943 | 499 | unsigned long value, __user *vaddr; |
1da177e4 | 500 | long offset; |
1da177e4 LT |
501 | |
502 | /* | |
503 | * analyse the ll instruction that just caused a ri exception | |
504 | * and put the referenced address to addr. | |
505 | */ | |
506 | ||
507 | /* sign extend offset */ | |
508 | offset = opcode & OFFSET; | |
509 | offset <<= 16; | |
510 | offset >>= 16; | |
511 | ||
fe00f943 RB |
512 | vaddr = (unsigned long __user *) |
513 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); | |
1da177e4 | 514 | |
60b0d655 MR |
515 | if ((unsigned long)vaddr & 3) |
516 | return SIGBUS; | |
517 | if (get_user(value, vaddr)) | |
518 | return SIGSEGV; | |
1da177e4 LT |
519 | |
520 | preempt_disable(); | |
521 | ||
522 | if (ll_task == NULL || ll_task == current) { | |
523 | ll_bit = 1; | |
524 | } else { | |
525 | ll_bit = 0; | |
526 | } | |
527 | ll_task = current; | |
528 | ||
529 | preempt_enable(); | |
530 | ||
531 | regs->regs[(opcode & RT) >> 16] = value; | |
532 | ||
60b0d655 | 533 | return 0; |
1da177e4 LT |
534 | } |
535 | ||
60b0d655 | 536 | static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 537 | { |
fe00f943 RB |
538 | unsigned long __user *vaddr; |
539 | unsigned long reg; | |
1da177e4 | 540 | long offset; |
1da177e4 LT |
541 | |
542 | /* | |
543 | * analyse the sc instruction that just caused a ri exception | |
544 | * and put the referenced address to addr. | |
545 | */ | |
546 | ||
547 | /* sign extend offset */ | |
548 | offset = opcode & OFFSET; | |
549 | offset <<= 16; | |
550 | offset >>= 16; | |
551 | ||
fe00f943 RB |
552 | vaddr = (unsigned long __user *) |
553 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); | |
1da177e4 LT |
554 | reg = (opcode & RT) >> 16; |
555 | ||
60b0d655 MR |
556 | if ((unsigned long)vaddr & 3) |
557 | return SIGBUS; | |
1da177e4 LT |
558 | |
559 | preempt_disable(); | |
560 | ||
561 | if (ll_bit == 0 || ll_task != current) { | |
562 | regs->regs[reg] = 0; | |
563 | preempt_enable(); | |
60b0d655 | 564 | return 0; |
1da177e4 LT |
565 | } |
566 | ||
567 | preempt_enable(); | |
568 | ||
60b0d655 MR |
569 | if (put_user(regs->regs[reg], vaddr)) |
570 | return SIGSEGV; | |
1da177e4 LT |
571 | |
572 | regs->regs[reg] = 1; | |
573 | ||
60b0d655 | 574 | return 0; |
1da177e4 LT |
575 | } |
576 | ||
577 | /* | |
578 | * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both | |
579 | * opcodes are supposed to result in coprocessor unusable exceptions if | |
580 | * executed on ll/sc-less processors. That's the theory. In practice a | |
581 | * few processors such as NEC's VR4100 throw reserved instruction exceptions | |
582 | * instead, so we're doing the emulation thing in both exception handlers. | |
583 | */ | |
60b0d655 | 584 | static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 585 | { |
7f788d2d DCZ |
586 | if ((opcode & OPCODE) == LL) { |
587 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 588 | 1, regs, 0); |
60b0d655 | 589 | return simulate_ll(regs, opcode); |
7f788d2d DCZ |
590 | } |
591 | if ((opcode & OPCODE) == SC) { | |
592 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 593 | 1, regs, 0); |
60b0d655 | 594 | return simulate_sc(regs, opcode); |
7f788d2d | 595 | } |
1da177e4 | 596 | |
60b0d655 | 597 | return -1; /* Must be something else ... */ |
1da177e4 LT |
598 | } |
599 | ||
3c37026d RB |
600 | /* |
601 | * Simulate trapping 'rdhwr' instructions to provide user accessible | |
1f5826bd | 602 | * registers not implemented in hardware. |
3c37026d | 603 | */ |
60b0d655 | 604 | static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode) |
3c37026d | 605 | { |
dc8f6029 | 606 | struct thread_info *ti = task_thread_info(current); |
3c37026d RB |
607 | |
608 | if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { | |
609 | int rd = (opcode & RD) >> 11; | |
610 | int rt = (opcode & RT) >> 16; | |
7f788d2d | 611 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, |
a8b0ca17 | 612 | 1, regs, 0); |
3c37026d | 613 | switch (rd) { |
1f5826bd CD |
614 | case 0: /* CPU number */ |
615 | regs->regs[rt] = smp_processor_id(); | |
616 | return 0; | |
617 | case 1: /* SYNCI length */ | |
618 | regs->regs[rt] = min(current_cpu_data.dcache.linesz, | |
619 | current_cpu_data.icache.linesz); | |
620 | return 0; | |
621 | case 2: /* Read count register */ | |
622 | regs->regs[rt] = read_c0_count(); | |
623 | return 0; | |
624 | case 3: /* Count register resolution */ | |
625 | switch (current_cpu_data.cputype) { | |
626 | case CPU_20KC: | |
627 | case CPU_25KF: | |
628 | regs->regs[rt] = 1; | |
629 | break; | |
3c37026d | 630 | default: |
1f5826bd CD |
631 | regs->regs[rt] = 2; |
632 | } | |
633 | return 0; | |
634 | case 29: | |
635 | regs->regs[rt] = ti->tp_value; | |
636 | return 0; | |
637 | default: | |
638 | return -1; | |
3c37026d RB |
639 | } |
640 | } | |
641 | ||
56ebd51b | 642 | /* Not ours. */ |
60b0d655 MR |
643 | return -1; |
644 | } | |
e5679882 | 645 | |
60b0d655 MR |
646 | static int simulate_sync(struct pt_regs *regs, unsigned int opcode) |
647 | { | |
7f788d2d DCZ |
648 | if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) { |
649 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 650 | 1, regs, 0); |
60b0d655 | 651 | return 0; |
7f788d2d | 652 | } |
60b0d655 MR |
653 | |
654 | return -1; /* Must be something else ... */ | |
3c37026d RB |
655 | } |
656 | ||
1da177e4 LT |
657 | asmlinkage void do_ov(struct pt_regs *regs) |
658 | { | |
659 | siginfo_t info; | |
660 | ||
36ccf1c0 RB |
661 | die_if_kernel("Integer overflow", regs); |
662 | ||
1da177e4 LT |
663 | info.si_code = FPE_INTOVF; |
664 | info.si_signo = SIGFPE; | |
665 | info.si_errno = 0; | |
fe00f943 | 666 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
667 | force_sig_info(SIGFPE, &info, current); |
668 | } | |
669 | ||
515b029d DD |
670 | static int process_fpemu_return(int sig, void __user *fault_addr) |
671 | { | |
672 | if (sig == SIGSEGV || sig == SIGBUS) { | |
673 | struct siginfo si = {0}; | |
674 | si.si_addr = fault_addr; | |
675 | si.si_signo = sig; | |
676 | if (sig == SIGSEGV) { | |
677 | if (find_vma(current->mm, (unsigned long)fault_addr)) | |
678 | si.si_code = SEGV_ACCERR; | |
679 | else | |
680 | si.si_code = SEGV_MAPERR; | |
681 | } else { | |
682 | si.si_code = BUS_ADRERR; | |
683 | } | |
684 | force_sig_info(sig, &si, current); | |
685 | return 1; | |
686 | } else if (sig) { | |
687 | force_sig(sig, current); | |
688 | return 1; | |
689 | } else { | |
690 | return 0; | |
691 | } | |
692 | } | |
693 | ||
1da177e4 LT |
694 | /* |
695 | * XXX Delayed fp exceptions when doing a lazy ctx switch XXX | |
696 | */ | |
697 | asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) | |
698 | { | |
515b029d | 699 | siginfo_t info = {0}; |
948a34cf | 700 | |
70dc6f04 | 701 | if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE) |
88547001 JW |
702 | == NOTIFY_STOP) |
703 | return; | |
57725f9e CD |
704 | die_if_kernel("FP exception in kernel code", regs); |
705 | ||
1da177e4 LT |
706 | if (fcr31 & FPU_CSR_UNI_X) { |
707 | int sig; | |
515b029d | 708 | void __user *fault_addr = NULL; |
1da177e4 | 709 | |
1da177e4 | 710 | /* |
a3dddd56 | 711 | * Unimplemented operation exception. If we've got the full |
1da177e4 LT |
712 | * software emulator on-board, let's use it... |
713 | * | |
714 | * Force FPU to dump state into task/thread context. We're | |
715 | * moving a lot of data here for what is probably a single | |
716 | * instruction, but the alternative is to pre-decode the FP | |
717 | * register operands before invoking the emulator, which seems | |
718 | * a bit extreme for what should be an infrequent event. | |
719 | */ | |
cd21dfcf | 720 | /* Ensure 'resume' not overwrite saved fp context again. */ |
53dc8028 | 721 | lose_fpu(1); |
1da177e4 LT |
722 | |
723 | /* Run the emulator */ | |
515b029d DD |
724 | sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, |
725 | &fault_addr); | |
1da177e4 LT |
726 | |
727 | /* | |
728 | * We can't allow the emulated instruction to leave any of | |
729 | * the cause bit set in $fcr31. | |
730 | */ | |
eae89076 | 731 | current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; |
1da177e4 LT |
732 | |
733 | /* Restore the hardware register state */ | |
53dc8028 | 734 | own_fpu(1); /* Using the FPU again. */ |
1da177e4 LT |
735 | |
736 | /* If something went wrong, signal */ | |
515b029d | 737 | process_fpemu_return(sig, fault_addr); |
1da177e4 LT |
738 | |
739 | return; | |
948a34cf TS |
740 | } else if (fcr31 & FPU_CSR_INV_X) |
741 | info.si_code = FPE_FLTINV; | |
742 | else if (fcr31 & FPU_CSR_DIV_X) | |
743 | info.si_code = FPE_FLTDIV; | |
744 | else if (fcr31 & FPU_CSR_OVF_X) | |
745 | info.si_code = FPE_FLTOVF; | |
746 | else if (fcr31 & FPU_CSR_UDF_X) | |
747 | info.si_code = FPE_FLTUND; | |
748 | else if (fcr31 & FPU_CSR_INE_X) | |
749 | info.si_code = FPE_FLTRES; | |
750 | else | |
751 | info.si_code = __SI_FAULT; | |
752 | info.si_signo = SIGFPE; | |
753 | info.si_errno = 0; | |
754 | info.si_addr = (void __user *) regs->cp0_epc; | |
755 | force_sig_info(SIGFPE, &info, current); | |
1da177e4 LT |
756 | } |
757 | ||
df270051 RB |
758 | static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, |
759 | const char *str) | |
1da177e4 | 760 | { |
1da177e4 | 761 | siginfo_t info; |
df270051 | 762 | char b[40]; |
1da177e4 | 763 | |
5dd11d5d | 764 | #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP |
70dc6f04 | 765 | if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) |
5dd11d5d JW |
766 | return; |
767 | #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ | |
768 | ||
70dc6f04 | 769 | if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) |
88547001 JW |
770 | return; |
771 | ||
1da177e4 | 772 | /* |
df270051 RB |
773 | * A short test says that IRIX 5.3 sends SIGTRAP for all trap |
774 | * insns, even for trap and break codes that indicate arithmetic | |
775 | * failures. Weird ... | |
1da177e4 LT |
776 | * But should we continue the brokenness??? --macro |
777 | */ | |
df270051 RB |
778 | switch (code) { |
779 | case BRK_OVERFLOW: | |
780 | case BRK_DIVZERO: | |
781 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); | |
782 | die_if_kernel(b, regs); | |
783 | if (code == BRK_DIVZERO) | |
1da177e4 LT |
784 | info.si_code = FPE_INTDIV; |
785 | else | |
786 | info.si_code = FPE_INTOVF; | |
787 | info.si_signo = SIGFPE; | |
788 | info.si_errno = 0; | |
fe00f943 | 789 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
790 | force_sig_info(SIGFPE, &info, current); |
791 | break; | |
63dc68a8 | 792 | case BRK_BUG: |
df270051 RB |
793 | die_if_kernel("Kernel bug detected", regs); |
794 | force_sig(SIGTRAP, current); | |
63dc68a8 | 795 | break; |
ba3049ed RB |
796 | case BRK_MEMU: |
797 | /* | |
798 | * Address errors may be deliberately induced by the FPU | |
799 | * emulator to retake control of the CPU after executing the | |
800 | * instruction in the delay slot of an emulated branch. | |
801 | * | |
802 | * Terminate if exception was recognized as a delay slot return | |
803 | * otherwise handle as normal. | |
804 | */ | |
805 | if (do_dsemulret(regs)) | |
806 | return; | |
807 | ||
808 | die_if_kernel("Math emu break/trap", regs); | |
809 | force_sig(SIGTRAP, current); | |
810 | break; | |
1da177e4 | 811 | default: |
df270051 RB |
812 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); |
813 | die_if_kernel(b, regs); | |
1da177e4 LT |
814 | force_sig(SIGTRAP, current); |
815 | } | |
df270051 RB |
816 | } |
817 | ||
818 | asmlinkage void do_bp(struct pt_regs *regs) | |
819 | { | |
820 | unsigned int opcode, bcode; | |
821 | ||
822 | if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) | |
823 | goto out_sigsegv; | |
824 | ||
825 | /* | |
826 | * There is the ancient bug in the MIPS assemblers that the break | |
827 | * code starts left to bit 16 instead to bit 6 in the opcode. | |
828 | * Gas is bug-compatible, but not always, grrr... | |
829 | * We handle both cases with a simple heuristics. --macro | |
830 | */ | |
831 | bcode = ((opcode >> 6) & ((1 << 20) - 1)); | |
832 | if (bcode >= (1 << 10)) | |
833 | bcode >>= 10; | |
834 | ||
c1bf207d DD |
835 | /* |
836 | * notify the kprobe handlers, if instruction is likely to | |
837 | * pertain to them. | |
838 | */ | |
839 | switch (bcode) { | |
840 | case BRK_KPROBE_BP: | |
70dc6f04 | 841 | if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) |
c1bf207d DD |
842 | return; |
843 | else | |
844 | break; | |
845 | case BRK_KPROBE_SSTEPBP: | |
70dc6f04 | 846 | if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) |
c1bf207d DD |
847 | return; |
848 | else | |
849 | break; | |
850 | default: | |
851 | break; | |
852 | } | |
853 | ||
df270051 | 854 | do_trap_or_bp(regs, bcode, "Break"); |
90fccb13 | 855 | return; |
e5679882 RB |
856 | |
857 | out_sigsegv: | |
858 | force_sig(SIGSEGV, current); | |
1da177e4 LT |
859 | } |
860 | ||
861 | asmlinkage void do_tr(struct pt_regs *regs) | |
862 | { | |
863 | unsigned int opcode, tcode = 0; | |
1da177e4 | 864 | |
ba755f8e | 865 | if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) |
e5679882 | 866 | goto out_sigsegv; |
1da177e4 LT |
867 | |
868 | /* Immediate versions don't provide a code. */ | |
869 | if (!(opcode & OPCODE)) | |
870 | tcode = ((opcode >> 6) & ((1 << 10) - 1)); | |
871 | ||
df270051 | 872 | do_trap_or_bp(regs, tcode, "Trap"); |
90fccb13 | 873 | return; |
e5679882 RB |
874 | |
875 | out_sigsegv: | |
876 | force_sig(SIGSEGV, current); | |
1da177e4 LT |
877 | } |
878 | ||
879 | asmlinkage void do_ri(struct pt_regs *regs) | |
880 | { | |
60b0d655 MR |
881 | unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); |
882 | unsigned long old_epc = regs->cp0_epc; | |
883 | unsigned int opcode = 0; | |
884 | int status = -1; | |
1da177e4 | 885 | |
70dc6f04 | 886 | if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL) |
88547001 JW |
887 | == NOTIFY_STOP) |
888 | return; | |
889 | ||
60b0d655 | 890 | die_if_kernel("Reserved instruction in kernel code", regs); |
1da177e4 | 891 | |
60b0d655 | 892 | if (unlikely(compute_return_epc(regs) < 0)) |
3c37026d RB |
893 | return; |
894 | ||
60b0d655 MR |
895 | if (unlikely(get_user(opcode, epc) < 0)) |
896 | status = SIGSEGV; | |
897 | ||
898 | if (!cpu_has_llsc && status < 0) | |
899 | status = simulate_llsc(regs, opcode); | |
900 | ||
901 | if (status < 0) | |
902 | status = simulate_rdhwr(regs, opcode); | |
903 | ||
904 | if (status < 0) | |
905 | status = simulate_sync(regs, opcode); | |
906 | ||
907 | if (status < 0) | |
908 | status = SIGILL; | |
909 | ||
910 | if (unlikely(status > 0)) { | |
911 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
912 | force_sig(status, current); | |
913 | } | |
1da177e4 LT |
914 | } |
915 | ||
d223a861 RB |
916 | /* |
917 | * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've | |
918 | * emulated more than some threshold number of instructions, force migration to | |
919 | * a "CPU" that has FP support. | |
920 | */ | |
921 | static void mt_ase_fp_affinity(void) | |
922 | { | |
923 | #ifdef CONFIG_MIPS_MT_FPAFF | |
924 | if (mt_fpemul_threshold > 0 && | |
925 | ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { | |
926 | /* | |
927 | * If there's no FPU present, or if the application has already | |
928 | * restricted the allowed set to exclude any CPUs with FPUs, | |
929 | * we'll skip the procedure. | |
930 | */ | |
931 | if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { | |
932 | cpumask_t tmask; | |
933 | ||
9cc12363 KK |
934 | current->thread.user_cpus_allowed |
935 | = current->cpus_allowed; | |
936 | cpus_and(tmask, current->cpus_allowed, | |
937 | mt_fpu_cpumask); | |
ed1bbdef | 938 | set_cpus_allowed_ptr(current, &tmask); |
293c5bd1 | 939 | set_thread_flag(TIF_FPUBOUND); |
d223a861 RB |
940 | } |
941 | } | |
942 | #endif /* CONFIG_MIPS_MT_FPAFF */ | |
943 | } | |
944 | ||
69f3a7de RB |
945 | /* |
946 | * No lock; only written during early bootup by CPU 0. | |
947 | */ | |
948 | static RAW_NOTIFIER_HEAD(cu2_chain); | |
949 | ||
950 | int __ref register_cu2_notifier(struct notifier_block *nb) | |
951 | { | |
952 | return raw_notifier_chain_register(&cu2_chain, nb); | |
953 | } | |
954 | ||
955 | int cu2_notifier_call_chain(unsigned long val, void *v) | |
956 | { | |
957 | return raw_notifier_call_chain(&cu2_chain, val, v); | |
958 | } | |
959 | ||
960 | static int default_cu2_call(struct notifier_block *nfb, unsigned long action, | |
961 | void *data) | |
962 | { | |
963 | struct pt_regs *regs = data; | |
964 | ||
965 | switch (action) { | |
966 | default: | |
967 | die_if_kernel("Unhandled kernel unaligned access or invalid " | |
968 | "instruction", regs); | |
969 | /* Fall through */ | |
970 | ||
971 | case CU2_EXCEPTION: | |
972 | force_sig(SIGILL, current); | |
973 | } | |
974 | ||
975 | return NOTIFY_OK; | |
976 | } | |
977 | ||
1da177e4 LT |
978 | asmlinkage void do_cpu(struct pt_regs *regs) |
979 | { | |
60b0d655 MR |
980 | unsigned int __user *epc; |
981 | unsigned long old_epc; | |
982 | unsigned int opcode; | |
1da177e4 | 983 | unsigned int cpid; |
60b0d655 | 984 | int status; |
f9bb4cf3 | 985 | unsigned long __maybe_unused flags; |
1da177e4 | 986 | |
5323180d AN |
987 | die_if_kernel("do_cpu invoked from kernel context!", regs); |
988 | ||
1da177e4 LT |
989 | cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; |
990 | ||
991 | switch (cpid) { | |
992 | case 0: | |
60b0d655 MR |
993 | epc = (unsigned int __user *)exception_epc(regs); |
994 | old_epc = regs->cp0_epc; | |
995 | opcode = 0; | |
996 | status = -1; | |
1da177e4 | 997 | |
60b0d655 | 998 | if (unlikely(compute_return_epc(regs) < 0)) |
1da177e4 | 999 | return; |
3c37026d | 1000 | |
60b0d655 MR |
1001 | if (unlikely(get_user(opcode, epc) < 0)) |
1002 | status = SIGSEGV; | |
1003 | ||
1004 | if (!cpu_has_llsc && status < 0) | |
1005 | status = simulate_llsc(regs, opcode); | |
1006 | ||
1007 | if (status < 0) | |
1008 | status = simulate_rdhwr(regs, opcode); | |
1009 | ||
1010 | if (status < 0) | |
1011 | status = SIGILL; | |
1012 | ||
1013 | if (unlikely(status > 0)) { | |
1014 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
1015 | force_sig(status, current); | |
1016 | } | |
1017 | ||
1018 | return; | |
1da177e4 LT |
1019 | |
1020 | case 1: | |
53dc8028 AN |
1021 | if (used_math()) /* Using the FPU again. */ |
1022 | own_fpu(1); | |
1023 | else { /* First time FPU user. */ | |
1da177e4 LT |
1024 | init_fpu(); |
1025 | set_used_math(); | |
1026 | } | |
1027 | ||
5323180d | 1028 | if (!raw_cpu_has_fpu) { |
e04582b7 | 1029 | int sig; |
515b029d | 1030 | void __user *fault_addr = NULL; |
e04582b7 | 1031 | sig = fpu_emulator_cop1Handler(regs, |
515b029d DD |
1032 | ¤t->thread.fpu, |
1033 | 0, &fault_addr); | |
1034 | if (!process_fpemu_return(sig, fault_addr)) | |
d223a861 | 1035 | mt_ase_fp_affinity(); |
1da177e4 LT |
1036 | } |
1037 | ||
1da177e4 LT |
1038 | return; |
1039 | ||
1040 | case 2: | |
69f3a7de | 1041 | raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); |
55dc9d51 | 1042 | return; |
69f3a7de | 1043 | |
1da177e4 LT |
1044 | case 3: |
1045 | break; | |
1046 | } | |
1047 | ||
1048 | force_sig(SIGILL, current); | |
1049 | } | |
1050 | ||
1051 | asmlinkage void do_mdmx(struct pt_regs *regs) | |
1052 | { | |
1053 | force_sig(SIGILL, current); | |
1054 | } | |
1055 | ||
8bc6d05b DD |
1056 | /* |
1057 | * Called with interrupts disabled. | |
1058 | */ | |
1da177e4 LT |
1059 | asmlinkage void do_watch(struct pt_regs *regs) |
1060 | { | |
b67b2b70 DD |
1061 | u32 cause; |
1062 | ||
1da177e4 | 1063 | /* |
b67b2b70 DD |
1064 | * Clear WP (bit 22) bit of cause register so we don't loop |
1065 | * forever. | |
1da177e4 | 1066 | */ |
b67b2b70 DD |
1067 | cause = read_c0_cause(); |
1068 | cause &= ~(1 << 22); | |
1069 | write_c0_cause(cause); | |
1070 | ||
1071 | /* | |
1072 | * If the current thread has the watch registers loaded, save | |
1073 | * their values and send SIGTRAP. Otherwise another thread | |
1074 | * left the registers set, clear them and continue. | |
1075 | */ | |
1076 | if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { | |
1077 | mips_read_watch_registers(); | |
8bc6d05b | 1078 | local_irq_enable(); |
b67b2b70 | 1079 | force_sig(SIGTRAP, current); |
8bc6d05b | 1080 | } else { |
b67b2b70 | 1081 | mips_clear_watch_registers(); |
8bc6d05b DD |
1082 | local_irq_enable(); |
1083 | } | |
1da177e4 LT |
1084 | } |
1085 | ||
1086 | asmlinkage void do_mcheck(struct pt_regs *regs) | |
1087 | { | |
cac4bcbc RB |
1088 | const int field = 2 * sizeof(unsigned long); |
1089 | int multi_match = regs->cp0_status & ST0_TS; | |
1090 | ||
1da177e4 | 1091 | show_regs(regs); |
cac4bcbc RB |
1092 | |
1093 | if (multi_match) { | |
1094 | printk("Index : %0x\n", read_c0_index()); | |
1095 | printk("Pagemask: %0x\n", read_c0_pagemask()); | |
1096 | printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); | |
1097 | printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); | |
1098 | printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); | |
1099 | printk("\n"); | |
1100 | dump_tlb_all(); | |
1101 | } | |
1102 | ||
e1bb8289 | 1103 | show_code((unsigned int __user *) regs->cp0_epc); |
cac4bcbc | 1104 | |
1da177e4 LT |
1105 | /* |
1106 | * Some chips may have other causes of machine check (e.g. SB1 | |
1107 | * graduation timer) | |
1108 | */ | |
1109 | panic("Caught Machine Check exception - %scaused by multiple " | |
1110 | "matching entries in the TLB.", | |
cac4bcbc | 1111 | (multi_match) ? "" : "not "); |
1da177e4 LT |
1112 | } |
1113 | ||
340ee4b9 RB |
1114 | asmlinkage void do_mt(struct pt_regs *regs) |
1115 | { | |
41c594ab RB |
1116 | int subcode; |
1117 | ||
41c594ab RB |
1118 | subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) |
1119 | >> VPECONTROL_EXCPT_SHIFT; | |
1120 | switch (subcode) { | |
1121 | case 0: | |
e35a5e35 | 1122 | printk(KERN_DEBUG "Thread Underflow\n"); |
41c594ab RB |
1123 | break; |
1124 | case 1: | |
e35a5e35 | 1125 | printk(KERN_DEBUG "Thread Overflow\n"); |
41c594ab RB |
1126 | break; |
1127 | case 2: | |
e35a5e35 | 1128 | printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); |
41c594ab RB |
1129 | break; |
1130 | case 3: | |
e35a5e35 | 1131 | printk(KERN_DEBUG "Gating Storage Exception\n"); |
41c594ab RB |
1132 | break; |
1133 | case 4: | |
e35a5e35 | 1134 | printk(KERN_DEBUG "YIELD Scheduler Exception\n"); |
41c594ab RB |
1135 | break; |
1136 | case 5: | |
e35a5e35 | 1137 | printk(KERN_DEBUG "Gating Storage Schedulier Exception\n"); |
41c594ab RB |
1138 | break; |
1139 | default: | |
e35a5e35 | 1140 | printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", |
41c594ab RB |
1141 | subcode); |
1142 | break; | |
1143 | } | |
340ee4b9 RB |
1144 | die_if_kernel("MIPS MT Thread exception in kernel", regs); |
1145 | ||
1146 | force_sig(SIGILL, current); | |
1147 | } | |
1148 | ||
1149 | ||
e50c0a8f RB |
1150 | asmlinkage void do_dsp(struct pt_regs *regs) |
1151 | { | |
1152 | if (cpu_has_dsp) | |
1153 | panic("Unexpected DSP exception\n"); | |
1154 | ||
1155 | force_sig(SIGILL, current); | |
1156 | } | |
1157 | ||
1da177e4 LT |
1158 | asmlinkage void do_reserved(struct pt_regs *regs) |
1159 | { | |
1160 | /* | |
1161 | * Game over - no way to handle this if it ever occurs. Most probably | |
1162 | * caused by a new unknown cpu type or after another deadly | |
1163 | * hard/software error. | |
1164 | */ | |
1165 | show_regs(regs); | |
1166 | panic("Caught reserved exception %ld - should not happen.", | |
1167 | (regs->cp0_cause & 0x7f) >> 2); | |
1168 | } | |
1169 | ||
39b8d525 RB |
1170 | static int __initdata l1parity = 1; |
1171 | static int __init nol1parity(char *s) | |
1172 | { | |
1173 | l1parity = 0; | |
1174 | return 1; | |
1175 | } | |
1176 | __setup("nol1par", nol1parity); | |
1177 | static int __initdata l2parity = 1; | |
1178 | static int __init nol2parity(char *s) | |
1179 | { | |
1180 | l2parity = 0; | |
1181 | return 1; | |
1182 | } | |
1183 | __setup("nol2par", nol2parity); | |
1184 | ||
1da177e4 LT |
1185 | /* |
1186 | * Some MIPS CPUs can enable/disable for cache parity detection, but do | |
1187 | * it different ways. | |
1188 | */ | |
1189 | static inline void parity_protection_init(void) | |
1190 | { | |
10cc3529 | 1191 | switch (current_cpu_type()) { |
1da177e4 | 1192 | case CPU_24K: |
98a41de9 | 1193 | case CPU_34K: |
39b8d525 RB |
1194 | case CPU_74K: |
1195 | case CPU_1004K: | |
1196 | { | |
1197 | #define ERRCTL_PE 0x80000000 | |
1198 | #define ERRCTL_L2P 0x00800000 | |
1199 | unsigned long errctl; | |
1200 | unsigned int l1parity_present, l2parity_present; | |
1201 | ||
1202 | errctl = read_c0_ecc(); | |
1203 | errctl &= ~(ERRCTL_PE|ERRCTL_L2P); | |
1204 | ||
1205 | /* probe L1 parity support */ | |
1206 | write_c0_ecc(errctl | ERRCTL_PE); | |
1207 | back_to_back_c0_hazard(); | |
1208 | l1parity_present = (read_c0_ecc() & ERRCTL_PE); | |
1209 | ||
1210 | /* probe L2 parity support */ | |
1211 | write_c0_ecc(errctl|ERRCTL_L2P); | |
1212 | back_to_back_c0_hazard(); | |
1213 | l2parity_present = (read_c0_ecc() & ERRCTL_L2P); | |
1214 | ||
1215 | if (l1parity_present && l2parity_present) { | |
1216 | if (l1parity) | |
1217 | errctl |= ERRCTL_PE; | |
1218 | if (l1parity ^ l2parity) | |
1219 | errctl |= ERRCTL_L2P; | |
1220 | } else if (l1parity_present) { | |
1221 | if (l1parity) | |
1222 | errctl |= ERRCTL_PE; | |
1223 | } else if (l2parity_present) { | |
1224 | if (l2parity) | |
1225 | errctl |= ERRCTL_L2P; | |
1226 | } else { | |
1227 | /* No parity available */ | |
1228 | } | |
1229 | ||
1230 | printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); | |
1231 | ||
1232 | write_c0_ecc(errctl); | |
1233 | back_to_back_c0_hazard(); | |
1234 | errctl = read_c0_ecc(); | |
1235 | printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); | |
1236 | ||
1237 | if (l1parity_present) | |
1238 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1239 | (errctl & ERRCTL_PE) ? "en" : "dis"); | |
1240 | ||
1241 | if (l2parity_present) { | |
1242 | if (l1parity_present && l1parity) | |
1243 | errctl ^= ERRCTL_L2P; | |
1244 | printk(KERN_INFO "L2 cache parity protection %sabled\n", | |
1245 | (errctl & ERRCTL_L2P) ? "en" : "dis"); | |
1246 | } | |
1247 | } | |
1248 | break; | |
1249 | ||
1da177e4 | 1250 | case CPU_5KC: |
14f18b7f RB |
1251 | write_c0_ecc(0x80000000); |
1252 | back_to_back_c0_hazard(); | |
1253 | /* Set the PE bit (bit 31) in the c0_errctl register. */ | |
1254 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1255 | (read_c0_ecc() & 0x80000000) ? "en" : "dis"); | |
1da177e4 LT |
1256 | break; |
1257 | case CPU_20KC: | |
1258 | case CPU_25KF: | |
1259 | /* Clear the DE bit (bit 16) in the c0_status register. */ | |
1260 | printk(KERN_INFO "Enable cache parity protection for " | |
1261 | "MIPS 20KC/25KF CPUs.\n"); | |
1262 | clear_c0_status(ST0_DE); | |
1263 | break; | |
1264 | default: | |
1265 | break; | |
1266 | } | |
1267 | } | |
1268 | ||
1269 | asmlinkage void cache_parity_error(void) | |
1270 | { | |
1271 | const int field = 2 * sizeof(unsigned long); | |
1272 | unsigned int reg_val; | |
1273 | ||
1274 | /* For the moment, report the problem and hang. */ | |
1275 | printk("Cache error exception:\n"); | |
1276 | printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); | |
1277 | reg_val = read_c0_cacheerr(); | |
1278 | printk("c0_cacheerr == %08x\n", reg_val); | |
1279 | ||
1280 | printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", | |
1281 | reg_val & (1<<30) ? "secondary" : "primary", | |
1282 | reg_val & (1<<31) ? "data" : "insn"); | |
1283 | printk("Error bits: %s%s%s%s%s%s%s\n", | |
1284 | reg_val & (1<<29) ? "ED " : "", | |
1285 | reg_val & (1<<28) ? "ET " : "", | |
1286 | reg_val & (1<<26) ? "EE " : "", | |
1287 | reg_val & (1<<25) ? "EB " : "", | |
1288 | reg_val & (1<<24) ? "EI " : "", | |
1289 | reg_val & (1<<23) ? "E1 " : "", | |
1290 | reg_val & (1<<22) ? "E0 " : ""); | |
1291 | printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); | |
1292 | ||
ec917c2c | 1293 | #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) |
1da177e4 LT |
1294 | if (reg_val & (1<<22)) |
1295 | printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); | |
1296 | ||
1297 | if (reg_val & (1<<23)) | |
1298 | printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); | |
1299 | #endif | |
1300 | ||
1301 | panic("Can't handle the cache error!"); | |
1302 | } | |
1303 | ||
1304 | /* | |
1305 | * SDBBP EJTAG debug exception handler. | |
1306 | * We skip the instruction and return to the next instruction. | |
1307 | */ | |
1308 | void ejtag_exception_handler(struct pt_regs *regs) | |
1309 | { | |
1310 | const int field = 2 * sizeof(unsigned long); | |
1311 | unsigned long depc, old_epc; | |
1312 | unsigned int debug; | |
1313 | ||
70ae6126 | 1314 | printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); |
1da177e4 LT |
1315 | depc = read_c0_depc(); |
1316 | debug = read_c0_debug(); | |
70ae6126 | 1317 | printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); |
1da177e4 LT |
1318 | if (debug & 0x80000000) { |
1319 | /* | |
1320 | * In branch delay slot. | |
1321 | * We cheat a little bit here and use EPC to calculate the | |
1322 | * debug return address (DEPC). EPC is restored after the | |
1323 | * calculation. | |
1324 | */ | |
1325 | old_epc = regs->cp0_epc; | |
1326 | regs->cp0_epc = depc; | |
1327 | __compute_return_epc(regs); | |
1328 | depc = regs->cp0_epc; | |
1329 | regs->cp0_epc = old_epc; | |
1330 | } else | |
1331 | depc += 4; | |
1332 | write_c0_depc(depc); | |
1333 | ||
1334 | #if 0 | |
70ae6126 | 1335 | printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); |
1da177e4 LT |
1336 | write_c0_debug(debug | 0x100); |
1337 | #endif | |
1338 | } | |
1339 | ||
1340 | /* | |
1341 | * NMI exception handler. | |
1342 | */ | |
9402c95f | 1343 | void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs) |
1da177e4 | 1344 | { |
41c594ab | 1345 | bust_spinlocks(1); |
1da177e4 LT |
1346 | printk("NMI taken!!!!\n"); |
1347 | die("NMI", regs); | |
1da177e4 LT |
1348 | } |
1349 | ||
e01402b1 RB |
1350 | #define VECTORSPACING 0x100 /* for EI/VI mode */ |
1351 | ||
1352 | unsigned long ebase; | |
1da177e4 | 1353 | unsigned long exception_handlers[32]; |
e01402b1 | 1354 | unsigned long vi_handlers[64]; |
1da177e4 | 1355 | |
2d1b6e95 | 1356 | void __init *set_except_vector(int n, void *addr) |
1da177e4 LT |
1357 | { |
1358 | unsigned long handler = (unsigned long) addr; | |
1359 | unsigned long old_handler = exception_handlers[n]; | |
1360 | ||
1361 | exception_handlers[n] = handler; | |
1362 | if (n == 0 && cpu_has_divec) { | |
92bbe1b9 FF |
1363 | unsigned long jump_mask = ~((1 << 28) - 1); |
1364 | u32 *buf = (u32 *)(ebase + 0x200); | |
1365 | unsigned int k0 = 26; | |
1366 | if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { | |
1367 | uasm_i_j(&buf, handler & ~jump_mask); | |
1368 | uasm_i_nop(&buf); | |
1369 | } else { | |
1370 | UASM_i_LA(&buf, k0, handler); | |
1371 | uasm_i_jr(&buf, k0); | |
1372 | uasm_i_nop(&buf); | |
1373 | } | |
1374 | local_flush_icache_range(ebase + 0x200, (unsigned long)buf); | |
e01402b1 RB |
1375 | } |
1376 | return (void *)old_handler; | |
1377 | } | |
1378 | ||
6ba07e59 AN |
1379 | static asmlinkage void do_default_vi(void) |
1380 | { | |
1381 | show_regs(get_irq_regs()); | |
1382 | panic("Caught unexpected vectored interrupt."); | |
1383 | } | |
1384 | ||
ef300e42 | 1385 | static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) |
e01402b1 RB |
1386 | { |
1387 | unsigned long handler; | |
1388 | unsigned long old_handler = vi_handlers[n]; | |
f6771dbb | 1389 | int srssets = current_cpu_data.srsets; |
e01402b1 RB |
1390 | u32 *w; |
1391 | unsigned char *b; | |
1392 | ||
b72b7092 | 1393 | BUG_ON(!cpu_has_veic && !cpu_has_vint); |
e01402b1 RB |
1394 | |
1395 | if (addr == NULL) { | |
1396 | handler = (unsigned long) do_default_vi; | |
1397 | srs = 0; | |
41c594ab | 1398 | } else |
e01402b1 RB |
1399 | handler = (unsigned long) addr; |
1400 | vi_handlers[n] = (unsigned long) addr; | |
1401 | ||
1402 | b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); | |
1403 | ||
f6771dbb | 1404 | if (srs >= srssets) |
e01402b1 RB |
1405 | panic("Shadow register set %d not supported", srs); |
1406 | ||
1407 | if (cpu_has_veic) { | |
1408 | if (board_bind_eic_interrupt) | |
49a89efb | 1409 | board_bind_eic_interrupt(n, srs); |
41c594ab | 1410 | } else if (cpu_has_vint) { |
e01402b1 | 1411 | /* SRSMap is only defined if shadow sets are implemented */ |
f6771dbb | 1412 | if (srssets > 1) |
49a89efb | 1413 | change_c0_srsmap(0xf << n*4, srs << n*4); |
e01402b1 RB |
1414 | } |
1415 | ||
1416 | if (srs == 0) { | |
1417 | /* | |
1418 | * If no shadow set is selected then use the default handler | |
1419 | * that does normal register saving and a standard interrupt exit | |
1420 | */ | |
1421 | ||
1422 | extern char except_vec_vi, except_vec_vi_lui; | |
1423 | extern char except_vec_vi_ori, except_vec_vi_end; | |
c65a5480 AN |
1424 | extern char rollback_except_vec_vi; |
1425 | char *vec_start = (cpu_wait == r4k_wait) ? | |
1426 | &rollback_except_vec_vi : &except_vec_vi; | |
41c594ab RB |
1427 | #ifdef CONFIG_MIPS_MT_SMTC |
1428 | /* | |
1429 | * We need to provide the SMTC vectored interrupt handler | |
1430 | * not only with the address of the handler, but with the | |
1431 | * Status.IM bit to be masked before going there. | |
1432 | */ | |
1433 | extern char except_vec_vi_mori; | |
c65a5480 | 1434 | const int mori_offset = &except_vec_vi_mori - vec_start; |
41c594ab | 1435 | #endif /* CONFIG_MIPS_MT_SMTC */ |
c65a5480 AN |
1436 | const int handler_len = &except_vec_vi_end - vec_start; |
1437 | const int lui_offset = &except_vec_vi_lui - vec_start; | |
1438 | const int ori_offset = &except_vec_vi_ori - vec_start; | |
e01402b1 RB |
1439 | |
1440 | if (handler_len > VECTORSPACING) { | |
1441 | /* | |
1442 | * Sigh... panicing won't help as the console | |
1443 | * is probably not configured :( | |
1444 | */ | |
49a89efb | 1445 | panic("VECTORSPACING too small"); |
e01402b1 RB |
1446 | } |
1447 | ||
c65a5480 | 1448 | memcpy(b, vec_start, handler_len); |
41c594ab | 1449 | #ifdef CONFIG_MIPS_MT_SMTC |
8e8a52ed RB |
1450 | BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ |
1451 | ||
41c594ab RB |
1452 | w = (u32 *)(b + mori_offset); |
1453 | *w = (*w & 0xffff0000) | (0x100 << n); | |
1454 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
e01402b1 RB |
1455 | w = (u32 *)(b + lui_offset); |
1456 | *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); | |
1457 | w = (u32 *)(b + ori_offset); | |
1458 | *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); | |
e0cee3ee TB |
1459 | local_flush_icache_range((unsigned long)b, |
1460 | (unsigned long)(b+handler_len)); | |
e01402b1 RB |
1461 | } |
1462 | else { | |
1463 | /* | |
1464 | * In other cases jump directly to the interrupt handler | |
1465 | * | |
1466 | * It is the handlers responsibility to save registers if required | |
1467 | * (eg hi/lo) and return from the exception using "eret" | |
1468 | */ | |
1469 | w = (u32 *)b; | |
1470 | *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ | |
1471 | *w = 0; | |
e0cee3ee TB |
1472 | local_flush_icache_range((unsigned long)b, |
1473 | (unsigned long)(b+8)); | |
1da177e4 | 1474 | } |
e01402b1 | 1475 | |
1da177e4 LT |
1476 | return (void *)old_handler; |
1477 | } | |
1478 | ||
ef300e42 | 1479 | void *set_vi_handler(int n, vi_handler_t addr) |
e01402b1 | 1480 | { |
ff3eab2a | 1481 | return set_vi_srs_handler(n, addr, 0); |
e01402b1 | 1482 | } |
f41ae0b2 | 1483 | |
1da177e4 LT |
1484 | extern void cpu_cache_init(void); |
1485 | extern void tlb_init(void); | |
1d40cfcd | 1486 | extern void flush_tlb_handlers(void); |
1da177e4 | 1487 | |
42f77542 RB |
1488 | /* |
1489 | * Timer interrupt | |
1490 | */ | |
1491 | int cp0_compare_irq; | |
010c108d | 1492 | int cp0_compare_irq_shift; |
42f77542 RB |
1493 | |
1494 | /* | |
1495 | * Performance counter IRQ or -1 if shared with timer | |
1496 | */ | |
1497 | int cp0_perfcount_irq; | |
1498 | EXPORT_SYMBOL_GPL(cp0_perfcount_irq); | |
1499 | ||
bdc94eb4 CD |
1500 | static int __cpuinitdata noulri; |
1501 | ||
1502 | static int __init ulri_disable(char *s) | |
1503 | { | |
1504 | pr_info("Disabling ulri\n"); | |
1505 | noulri = 1; | |
1506 | ||
1507 | return 1; | |
1508 | } | |
1509 | __setup("noulri", ulri_disable); | |
1510 | ||
234fcd14 | 1511 | void __cpuinit per_cpu_trap_init(void) |
1da177e4 LT |
1512 | { |
1513 | unsigned int cpu = smp_processor_id(); | |
1514 | unsigned int status_set = ST0_CU0; | |
18d693b3 | 1515 | unsigned int hwrena = cpu_hwrena_impl_bits; |
41c594ab RB |
1516 | #ifdef CONFIG_MIPS_MT_SMTC |
1517 | int secondaryTC = 0; | |
1518 | int bootTC = (cpu == 0); | |
1519 | ||
1520 | /* | |
1521 | * Only do per_cpu_trap_init() for first TC of Each VPE. | |
1522 | * Note that this hack assumes that the SMTC init code | |
1523 | * assigns TCs consecutively and in ascending order. | |
1524 | */ | |
1525 | ||
1526 | if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && | |
1527 | ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) | |
1528 | secondaryTC = 1; | |
1529 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
1530 | |
1531 | /* | |
1532 | * Disable coprocessors and select 32-bit or 64-bit addressing | |
1533 | * and the 16/32 or 32/32 FPR register model. Reset the BEV | |
1534 | * flag that some firmware may have left set and the TS bit (for | |
1535 | * IP27). Set XX for ISA IV code to work. | |
1536 | */ | |
875d43e7 | 1537 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1538 | status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; |
1539 | #endif | |
1540 | if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) | |
1541 | status_set |= ST0_XX; | |
bbaf238b CD |
1542 | if (cpu_has_dsp) |
1543 | status_set |= ST0_MX; | |
1544 | ||
b38c7399 | 1545 | change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, |
1da177e4 LT |
1546 | status_set); |
1547 | ||
18d693b3 KC |
1548 | if (cpu_has_mips_r2) |
1549 | hwrena |= 0x0000000f; | |
a3692020 | 1550 | |
18d693b3 KC |
1551 | if (!noulri && cpu_has_userlocal) |
1552 | hwrena |= (1 << 29); | |
a3692020 | 1553 | |
18d693b3 KC |
1554 | if (hwrena) |
1555 | write_c0_hwrena(hwrena); | |
e01402b1 | 1556 | |
41c594ab RB |
1557 | #ifdef CONFIG_MIPS_MT_SMTC |
1558 | if (!secondaryTC) { | |
1559 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1560 | ||
e01402b1 | 1561 | if (cpu_has_veic || cpu_has_vint) { |
9fb4c2b9 | 1562 | unsigned long sr = set_c0_status(ST0_BEV); |
49a89efb | 1563 | write_c0_ebase(ebase); |
9fb4c2b9 | 1564 | write_c0_status(sr); |
e01402b1 | 1565 | /* Setting vector spacing enables EI/VI mode */ |
49a89efb | 1566 | change_c0_intctl(0x3e0, VECTORSPACING); |
e01402b1 | 1567 | } |
d03d0a57 RB |
1568 | if (cpu_has_divec) { |
1569 | if (cpu_has_mipsmt) { | |
1570 | unsigned int vpflags = dvpe(); | |
1571 | set_c0_cause(CAUSEF_IV); | |
1572 | evpe(vpflags); | |
1573 | } else | |
1574 | set_c0_cause(CAUSEF_IV); | |
1575 | } | |
3b1d4ed5 RB |
1576 | |
1577 | /* | |
1578 | * Before R2 both interrupt numbers were fixed to 7, so on R2 only: | |
1579 | * | |
1580 | * o read IntCtl.IPTI to determine the timer interrupt | |
1581 | * o read IntCtl.IPPCI to determine the performance counter interrupt | |
1582 | */ | |
1583 | if (cpu_has_mips_r2) { | |
010c108d DV |
1584 | cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; |
1585 | cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; | |
1586 | cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; | |
c3e838a2 | 1587 | if (cp0_perfcount_irq == cp0_compare_irq) |
3b1d4ed5 | 1588 | cp0_perfcount_irq = -1; |
c3e838a2 CD |
1589 | } else { |
1590 | cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; | |
f4fc580b | 1591 | cp0_compare_irq_shift = cp0_compare_irq; |
c3e838a2 | 1592 | cp0_perfcount_irq = -1; |
3b1d4ed5 RB |
1593 | } |
1594 | ||
41c594ab RB |
1595 | #ifdef CONFIG_MIPS_MT_SMTC |
1596 | } | |
1597 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 | 1598 | |
5c200197 MR |
1599 | if (!cpu_data[cpu].asid_cache) |
1600 | cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; | |
1da177e4 LT |
1601 | |
1602 | atomic_inc(&init_mm.mm_count); | |
1603 | current->active_mm = &init_mm; | |
1604 | BUG_ON(current->mm); | |
1605 | enter_lazy_tlb(&init_mm, current); | |
1606 | ||
41c594ab RB |
1607 | #ifdef CONFIG_MIPS_MT_SMTC |
1608 | if (bootTC) { | |
1609 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1610 | cpu_cache_init(); | |
1611 | tlb_init(); | |
1612 | #ifdef CONFIG_MIPS_MT_SMTC | |
6a05888d RB |
1613 | } else if (!secondaryTC) { |
1614 | /* | |
1615 | * First TC in non-boot VPE must do subset of tlb_init() | |
1616 | * for MMU countrol registers. | |
1617 | */ | |
1618 | write_c0_pagemask(PM_DEFAULT_MASK); | |
1619 | write_c0_wired(0); | |
41c594ab RB |
1620 | } |
1621 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
3d8bfdd0 | 1622 | TLBMISS_HANDLER_SETUP(); |
1da177e4 LT |
1623 | } |
1624 | ||
e01402b1 | 1625 | /* Install CPU exception handler */ |
49a89efb | 1626 | void __init set_handler(unsigned long offset, void *addr, unsigned long size) |
e01402b1 RB |
1627 | { |
1628 | memcpy((void *)(ebase + offset), addr, size); | |
e0cee3ee | 1629 | local_flush_icache_range(ebase + offset, ebase + offset + size); |
e01402b1 RB |
1630 | } |
1631 | ||
234fcd14 | 1632 | static char panic_null_cerr[] __cpuinitdata = |
641e97f3 RB |
1633 | "Trying to set NULL cache error exception handler"; |
1634 | ||
42fe7ee3 RB |
1635 | /* |
1636 | * Install uncached CPU exception handler. | |
1637 | * This is suitable only for the cache error exception which is the only | |
1638 | * exception handler that is being run uncached. | |
1639 | */ | |
234fcd14 RB |
1640 | void __cpuinit set_uncached_handler(unsigned long offset, void *addr, |
1641 | unsigned long size) | |
e01402b1 | 1642 | { |
4f81b01a | 1643 | unsigned long uncached_ebase = CKSEG1ADDR(ebase); |
e01402b1 | 1644 | |
641e97f3 RB |
1645 | if (!addr) |
1646 | panic(panic_null_cerr); | |
1647 | ||
e01402b1 RB |
1648 | memcpy((void *)(uncached_ebase + offset), addr, size); |
1649 | } | |
1650 | ||
5b10496b AN |
1651 | static int __initdata rdhwr_noopt; |
1652 | static int __init set_rdhwr_noopt(char *str) | |
1653 | { | |
1654 | rdhwr_noopt = 1; | |
1655 | return 1; | |
1656 | } | |
1657 | ||
1658 | __setup("rdhwr_noopt", set_rdhwr_noopt); | |
1659 | ||
1da177e4 LT |
1660 | void __init trap_init(void) |
1661 | { | |
1662 | extern char except_vec3_generic, except_vec3_r4000; | |
1da177e4 LT |
1663 | extern char except_vec4; |
1664 | unsigned long i; | |
c65a5480 AN |
1665 | int rollback; |
1666 | ||
1667 | check_wait(); | |
1668 | rollback = (cpu_wait == r4k_wait); | |
1da177e4 | 1669 | |
88547001 JW |
1670 | #if defined(CONFIG_KGDB) |
1671 | if (kgdb_early_setup) | |
1672 | return; /* Already done */ | |
1673 | #endif | |
1674 | ||
9fb4c2b9 CD |
1675 | if (cpu_has_veic || cpu_has_vint) { |
1676 | unsigned long size = 0x200 + VECTORSPACING*64; | |
1677 | ebase = (unsigned long) | |
1678 | __alloc_bootmem(size, 1 << fls(size), 0); | |
1679 | } else { | |
f6be75d0 | 1680 | ebase = CKSEG0; |
566f74f6 DD |
1681 | if (cpu_has_mips_r2) |
1682 | ebase += (read_c0_ebase() & 0x3ffff000); | |
1683 | } | |
e01402b1 | 1684 | |
1da177e4 LT |
1685 | per_cpu_trap_init(); |
1686 | ||
1687 | /* | |
1688 | * Copy the generic exception handlers to their final destination. | |
1689 | * This will be overriden later as suitable for a particular | |
1690 | * configuration. | |
1691 | */ | |
e01402b1 | 1692 | set_handler(0x180, &except_vec3_generic, 0x80); |
1da177e4 LT |
1693 | |
1694 | /* | |
1695 | * Setup default vectors | |
1696 | */ | |
1697 | for (i = 0; i <= 31; i++) | |
1698 | set_except_vector(i, handle_reserved); | |
1699 | ||
1700 | /* | |
1701 | * Copy the EJTAG debug exception vector handler code to it's final | |
1702 | * destination. | |
1703 | */ | |
e01402b1 | 1704 | if (cpu_has_ejtag && board_ejtag_handler_setup) |
49a89efb | 1705 | board_ejtag_handler_setup(); |
1da177e4 LT |
1706 | |
1707 | /* | |
1708 | * Only some CPUs have the watch exceptions. | |
1709 | */ | |
1710 | if (cpu_has_watch) | |
1711 | set_except_vector(23, handle_watch); | |
1712 | ||
1713 | /* | |
e01402b1 | 1714 | * Initialise interrupt handlers |
1da177e4 | 1715 | */ |
e01402b1 RB |
1716 | if (cpu_has_veic || cpu_has_vint) { |
1717 | int nvec = cpu_has_veic ? 64 : 8; | |
1718 | for (i = 0; i < nvec; i++) | |
ff3eab2a | 1719 | set_vi_handler(i, NULL); |
e01402b1 RB |
1720 | } |
1721 | else if (cpu_has_divec) | |
1722 | set_handler(0x200, &except_vec4, 0x8); | |
1da177e4 LT |
1723 | |
1724 | /* | |
1725 | * Some CPUs can enable/disable for cache parity detection, but does | |
1726 | * it different ways. | |
1727 | */ | |
1728 | parity_protection_init(); | |
1729 | ||
1730 | /* | |
1731 | * The Data Bus Errors / Instruction Bus Errors are signaled | |
1732 | * by external hardware. Therefore these two exceptions | |
1733 | * may have board specific handlers. | |
1734 | */ | |
1735 | if (board_be_init) | |
1736 | board_be_init(); | |
1737 | ||
c65a5480 | 1738 | set_except_vector(0, rollback ? rollback_handle_int : handle_int); |
1da177e4 LT |
1739 | set_except_vector(1, handle_tlbm); |
1740 | set_except_vector(2, handle_tlbl); | |
1741 | set_except_vector(3, handle_tlbs); | |
1742 | ||
1743 | set_except_vector(4, handle_adel); | |
1744 | set_except_vector(5, handle_ades); | |
1745 | ||
1746 | set_except_vector(6, handle_ibe); | |
1747 | set_except_vector(7, handle_dbe); | |
1748 | ||
1749 | set_except_vector(8, handle_sys); | |
1750 | set_except_vector(9, handle_bp); | |
5b10496b AN |
1751 | set_except_vector(10, rdhwr_noopt ? handle_ri : |
1752 | (cpu_has_vtag_icache ? | |
1753 | handle_ri_rdhwr_vivt : handle_ri_rdhwr)); | |
1da177e4 LT |
1754 | set_except_vector(11, handle_cpu); |
1755 | set_except_vector(12, handle_ov); | |
1756 | set_except_vector(13, handle_tr); | |
1da177e4 | 1757 | |
10cc3529 RB |
1758 | if (current_cpu_type() == CPU_R6000 || |
1759 | current_cpu_type() == CPU_R6000A) { | |
1da177e4 LT |
1760 | /* |
1761 | * The R6000 is the only R-series CPU that features a machine | |
1762 | * check exception (similar to the R4000 cache error) and | |
1763 | * unaligned ldc1/sdc1 exception. The handlers have not been | |
1764 | * written yet. Well, anyway there is no R6000 machine on the | |
1765 | * current list of targets for Linux/MIPS. | |
1766 | * (Duh, crap, there is someone with a triple R6k machine) | |
1767 | */ | |
1768 | //set_except_vector(14, handle_mc); | |
1769 | //set_except_vector(15, handle_ndc); | |
1770 | } | |
1771 | ||
e01402b1 RB |
1772 | |
1773 | if (board_nmi_handler_setup) | |
1774 | board_nmi_handler_setup(); | |
1775 | ||
e50c0a8f RB |
1776 | if (cpu_has_fpu && !cpu_has_nofpuex) |
1777 | set_except_vector(15, handle_fpe); | |
1778 | ||
1779 | set_except_vector(22, handle_mdmx); | |
1780 | ||
1781 | if (cpu_has_mcheck) | |
1782 | set_except_vector(24, handle_mcheck); | |
1783 | ||
340ee4b9 RB |
1784 | if (cpu_has_mipsmt) |
1785 | set_except_vector(25, handle_mt); | |
1786 | ||
acaec427 | 1787 | set_except_vector(26, handle_dsp); |
e50c0a8f RB |
1788 | |
1789 | if (cpu_has_vce) | |
1790 | /* Special exception: R4[04]00 uses also the divec space. */ | |
566f74f6 | 1791 | memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100); |
e50c0a8f | 1792 | else if (cpu_has_4kex) |
566f74f6 | 1793 | memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80); |
e50c0a8f | 1794 | else |
566f74f6 | 1795 | memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80); |
e50c0a8f | 1796 | |
e0cee3ee | 1797 | local_flush_icache_range(ebase, ebase + 0x400); |
1d40cfcd | 1798 | flush_tlb_handlers(); |
0510617b TB |
1799 | |
1800 | sort_extable(__start___dbe_table, __stop___dbe_table); | |
69f3a7de | 1801 | |
4483b159 | 1802 | cu2_notifier(default_cu2_call, 0x80000000); /* Run last */ |
1da177e4 | 1803 | } |