Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
36ccf1c0 | 6 | * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle |
1da177e4 LT |
7 | * Copyright (C) 1995, 1996 Paul M. Antoine |
8 | * Copyright (C) 1998 Ulf Carlsson | |
9 | * Copyright (C) 1999 Silicon Graphics, Inc. | |
10 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
60b0d655 | 11 | * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki |
2a0b24f5 | 12 | * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved. |
1da177e4 | 13 | */ |
8e8a52ed | 14 | #include <linux/bug.h> |
60b0d655 | 15 | #include <linux/compiler.h> |
c3fc5cd5 | 16 | #include <linux/context_tracking.h> |
7aa1c8f4 | 17 | #include <linux/kexec.h> |
1da177e4 | 18 | #include <linux/init.h> |
8742cd23 | 19 | #include <linux/kernel.h> |
f9ded569 | 20 | #include <linux/module.h> |
1da177e4 | 21 | #include <linux/mm.h> |
1da177e4 LT |
22 | #include <linux/sched.h> |
23 | #include <linux/smp.h> | |
1da177e4 LT |
24 | #include <linux/spinlock.h> |
25 | #include <linux/kallsyms.h> | |
e01402b1 | 26 | #include <linux/bootmem.h> |
d4fd1989 | 27 | #include <linux/interrupt.h> |
39b8d525 | 28 | #include <linux/ptrace.h> |
88547001 JW |
29 | #include <linux/kgdb.h> |
30 | #include <linux/kdebug.h> | |
c1bf207d | 31 | #include <linux/kprobes.h> |
69f3a7de | 32 | #include <linux/notifier.h> |
5dd11d5d | 33 | #include <linux/kdb.h> |
ca4d3e67 | 34 | #include <linux/irq.h> |
7f788d2d | 35 | #include <linux/perf_event.h> |
1da177e4 LT |
36 | |
37 | #include <asm/bootinfo.h> | |
38 | #include <asm/branch.h> | |
39 | #include <asm/break.h> | |
69f3a7de | 40 | #include <asm/cop2.h> |
1da177e4 | 41 | #include <asm/cpu.h> |
e50c0a8f | 42 | #include <asm/dsp.h> |
1da177e4 | 43 | #include <asm/fpu.h> |
ba3049ed | 44 | #include <asm/fpu_emulator.h> |
bdc92d74 | 45 | #include <asm/idle.h> |
340ee4b9 RB |
46 | #include <asm/mipsregs.h> |
47 | #include <asm/mipsmtregs.h> | |
1da177e4 LT |
48 | #include <asm/module.h> |
49 | #include <asm/pgtable.h> | |
50 | #include <asm/ptrace.h> | |
51 | #include <asm/sections.h> | |
1da177e4 LT |
52 | #include <asm/tlbdebug.h> |
53 | #include <asm/traps.h> | |
54 | #include <asm/uaccess.h> | |
b67b2b70 | 55 | #include <asm/watch.h> |
1da177e4 | 56 | #include <asm/mmu_context.h> |
1da177e4 | 57 | #include <asm/types.h> |
1df0f0ff | 58 | #include <asm/stacktrace.h> |
92bbe1b9 | 59 | #include <asm/uasm.h> |
1da177e4 | 60 | |
c65a5480 | 61 | extern void check_wait(void); |
c65a5480 | 62 | extern asmlinkage void rollback_handle_int(void); |
e4ac58af | 63 | extern asmlinkage void handle_int(void); |
86a1708a RB |
64 | extern u32 handle_tlbl[]; |
65 | extern u32 handle_tlbs[]; | |
66 | extern u32 handle_tlbm[]; | |
1da177e4 LT |
67 | extern asmlinkage void handle_adel(void); |
68 | extern asmlinkage void handle_ades(void); | |
69 | extern asmlinkage void handle_ibe(void); | |
70 | extern asmlinkage void handle_dbe(void); | |
71 | extern asmlinkage void handle_sys(void); | |
72 | extern asmlinkage void handle_bp(void); | |
73 | extern asmlinkage void handle_ri(void); | |
5b10496b AN |
74 | extern asmlinkage void handle_ri_rdhwr_vivt(void); |
75 | extern asmlinkage void handle_ri_rdhwr(void); | |
1da177e4 LT |
76 | extern asmlinkage void handle_cpu(void); |
77 | extern asmlinkage void handle_ov(void); | |
78 | extern asmlinkage void handle_tr(void); | |
79 | extern asmlinkage void handle_fpe(void); | |
80 | extern asmlinkage void handle_mdmx(void); | |
81 | extern asmlinkage void handle_watch(void); | |
340ee4b9 | 82 | extern asmlinkage void handle_mt(void); |
e50c0a8f | 83 | extern asmlinkage void handle_dsp(void); |
1da177e4 LT |
84 | extern asmlinkage void handle_mcheck(void); |
85 | extern asmlinkage void handle_reserved(void); | |
86 | ||
1da177e4 LT |
87 | void (*board_be_init)(void); |
88 | int (*board_be_handler)(struct pt_regs *regs, int is_fixup); | |
e01402b1 RB |
89 | void (*board_nmi_handler_setup)(void); |
90 | void (*board_ejtag_handler_setup)(void); | |
91 | void (*board_bind_eic_interrupt)(int irq, int regset); | |
6fb97eff | 92 | void (*board_ebase_setup)(void); |
fcbf1dfd | 93 | void __cpuinitdata(*board_cache_error_setup)(void); |
1da177e4 | 94 | |
4d157d5e | 95 | static void show_raw_backtrace(unsigned long reg29) |
e889d78f | 96 | { |
39b8d525 | 97 | unsigned long *sp = (unsigned long *)(reg29 & ~3); |
e889d78f AN |
98 | unsigned long addr; |
99 | ||
100 | printk("Call Trace:"); | |
101 | #ifdef CONFIG_KALLSYMS | |
102 | printk("\n"); | |
103 | #endif | |
10220c88 TB |
104 | while (!kstack_end(sp)) { |
105 | unsigned long __user *p = | |
106 | (unsigned long __user *)(unsigned long)sp++; | |
107 | if (__get_user(addr, p)) { | |
108 | printk(" (Bad stack address)"); | |
109 | break; | |
39b8d525 | 110 | } |
10220c88 TB |
111 | if (__kernel_text_address(addr)) |
112 | print_ip_sym(addr); | |
e889d78f | 113 | } |
10220c88 | 114 | printk("\n"); |
e889d78f AN |
115 | } |
116 | ||
f66686f7 | 117 | #ifdef CONFIG_KALLSYMS |
1df0f0ff | 118 | int raw_show_trace; |
f66686f7 AN |
119 | static int __init set_raw_show_trace(char *str) |
120 | { | |
121 | raw_show_trace = 1; | |
122 | return 1; | |
123 | } | |
124 | __setup("raw_show_trace", set_raw_show_trace); | |
1df0f0ff | 125 | #endif |
4d157d5e | 126 | |
eae23f2c | 127 | static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) |
f66686f7 | 128 | { |
4d157d5e FBH |
129 | unsigned long sp = regs->regs[29]; |
130 | unsigned long ra = regs->regs[31]; | |
f66686f7 | 131 | unsigned long pc = regs->cp0_epc; |
f66686f7 | 132 | |
e909be82 VW |
133 | if (!task) |
134 | task = current; | |
135 | ||
f66686f7 | 136 | if (raw_show_trace || !__kernel_text_address(pc)) { |
87151ae3 | 137 | show_raw_backtrace(sp); |
f66686f7 AN |
138 | return; |
139 | } | |
140 | printk("Call Trace:\n"); | |
4d157d5e | 141 | do { |
87151ae3 | 142 | print_ip_sym(pc); |
1924600c | 143 | pc = unwind_stack(task, &sp, pc, &ra); |
4d157d5e | 144 | } while (pc); |
f66686f7 AN |
145 | printk("\n"); |
146 | } | |
f66686f7 | 147 | |
1da177e4 LT |
148 | /* |
149 | * This routine abuses get_user()/put_user() to reference pointers | |
150 | * with at least a bit of error checking ... | |
151 | */ | |
eae23f2c RB |
152 | static void show_stacktrace(struct task_struct *task, |
153 | const struct pt_regs *regs) | |
1da177e4 LT |
154 | { |
155 | const int field = 2 * sizeof(unsigned long); | |
156 | long stackdata; | |
157 | int i; | |
5e0373b8 | 158 | unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; |
1da177e4 LT |
159 | |
160 | printk("Stack :"); | |
161 | i = 0; | |
162 | while ((unsigned long) sp & (PAGE_SIZE - 1)) { | |
163 | if (i && ((i % (64 / field)) == 0)) | |
70342287 | 164 | printk("\n "); |
1da177e4 LT |
165 | if (i > 39) { |
166 | printk(" ..."); | |
167 | break; | |
168 | } | |
169 | ||
170 | if (__get_user(stackdata, sp++)) { | |
171 | printk(" (Bad stack address)"); | |
172 | break; | |
173 | } | |
174 | ||
175 | printk(" %0*lx", field, stackdata); | |
176 | i++; | |
177 | } | |
178 | printk("\n"); | |
87151ae3 | 179 | show_backtrace(task, regs); |
f66686f7 AN |
180 | } |
181 | ||
f66686f7 AN |
182 | void show_stack(struct task_struct *task, unsigned long *sp) |
183 | { | |
184 | struct pt_regs regs; | |
185 | if (sp) { | |
186 | regs.regs[29] = (unsigned long)sp; | |
187 | regs.regs[31] = 0; | |
188 | regs.cp0_epc = 0; | |
189 | } else { | |
190 | if (task && task != current) { | |
191 | regs.regs[29] = task->thread.reg29; | |
192 | regs.regs[31] = 0; | |
193 | regs.cp0_epc = task->thread.reg31; | |
5dd11d5d JW |
194 | #ifdef CONFIG_KGDB_KDB |
195 | } else if (atomic_read(&kgdb_active) != -1 && | |
196 | kdb_current_regs) { | |
197 | memcpy(®s, kdb_current_regs, sizeof(regs)); | |
198 | #endif /* CONFIG_KGDB_KDB */ | |
f66686f7 AN |
199 | } else { |
200 | prepare_frametrace(®s); | |
201 | } | |
202 | } | |
203 | show_stacktrace(task, ®s); | |
1da177e4 LT |
204 | } |
205 | ||
e1bb8289 | 206 | static void show_code(unsigned int __user *pc) |
1da177e4 LT |
207 | { |
208 | long i; | |
39b8d525 | 209 | unsigned short __user *pc16 = NULL; |
1da177e4 LT |
210 | |
211 | printk("\nCode:"); | |
212 | ||
39b8d525 RB |
213 | if ((unsigned long)pc & 1) |
214 | pc16 = (unsigned short __user *)((unsigned long)pc & ~1); | |
1da177e4 LT |
215 | for(i = -3 ; i < 6 ; i++) { |
216 | unsigned int insn; | |
39b8d525 | 217 | if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { |
1da177e4 LT |
218 | printk(" (Bad address in epc)\n"); |
219 | break; | |
220 | } | |
39b8d525 | 221 | printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); |
1da177e4 LT |
222 | } |
223 | } | |
224 | ||
eae23f2c | 225 | static void __show_regs(const struct pt_regs *regs) |
1da177e4 LT |
226 | { |
227 | const int field = 2 * sizeof(unsigned long); | |
228 | unsigned int cause = regs->cp0_cause; | |
229 | int i; | |
230 | ||
a43cb95d | 231 | show_regs_print_info(KERN_DEFAULT); |
1da177e4 LT |
232 | |
233 | /* | |
234 | * Saved main processor registers | |
235 | */ | |
236 | for (i = 0; i < 32; ) { | |
237 | if ((i % 4) == 0) | |
238 | printk("$%2d :", i); | |
239 | if (i == 0) | |
240 | printk(" %0*lx", field, 0UL); | |
241 | else if (i == 26 || i == 27) | |
242 | printk(" %*s", field, ""); | |
243 | else | |
244 | printk(" %0*lx", field, regs->regs[i]); | |
245 | ||
246 | i++; | |
247 | if ((i % 4) == 0) | |
248 | printk("\n"); | |
249 | } | |
250 | ||
9693a853 FBH |
251 | #ifdef CONFIG_CPU_HAS_SMARTMIPS |
252 | printk("Acx : %0*lx\n", field, regs->acx); | |
253 | #endif | |
1da177e4 LT |
254 | printk("Hi : %0*lx\n", field, regs->hi); |
255 | printk("Lo : %0*lx\n", field, regs->lo); | |
256 | ||
257 | /* | |
258 | * Saved cp0 registers | |
259 | */ | |
b012cffe RB |
260 | printk("epc : %0*lx %pS\n", field, regs->cp0_epc, |
261 | (void *) regs->cp0_epc); | |
1da177e4 | 262 | printk(" %s\n", print_tainted()); |
b012cffe RB |
263 | printk("ra : %0*lx %pS\n", field, regs->regs[31], |
264 | (void *) regs->regs[31]); | |
1da177e4 | 265 | |
70342287 | 266 | printk("Status: %08x ", (uint32_t) regs->cp0_status); |
1da177e4 | 267 | |
1990e542 | 268 | if (cpu_has_3kex) { |
3b2396d9 MR |
269 | if (regs->cp0_status & ST0_KUO) |
270 | printk("KUo "); | |
271 | if (regs->cp0_status & ST0_IEO) | |
272 | printk("IEo "); | |
273 | if (regs->cp0_status & ST0_KUP) | |
274 | printk("KUp "); | |
275 | if (regs->cp0_status & ST0_IEP) | |
276 | printk("IEp "); | |
277 | if (regs->cp0_status & ST0_KUC) | |
278 | printk("KUc "); | |
279 | if (regs->cp0_status & ST0_IEC) | |
280 | printk("IEc "); | |
1990e542 | 281 | } else if (cpu_has_4kex) { |
3b2396d9 MR |
282 | if (regs->cp0_status & ST0_KX) |
283 | printk("KX "); | |
284 | if (regs->cp0_status & ST0_SX) | |
285 | printk("SX "); | |
286 | if (regs->cp0_status & ST0_UX) | |
287 | printk("UX "); | |
288 | switch (regs->cp0_status & ST0_KSU) { | |
289 | case KSU_USER: | |
290 | printk("USER "); | |
291 | break; | |
292 | case KSU_SUPERVISOR: | |
293 | printk("SUPERVISOR "); | |
294 | break; | |
295 | case KSU_KERNEL: | |
296 | printk("KERNEL "); | |
297 | break; | |
298 | default: | |
299 | printk("BAD_MODE "); | |
300 | break; | |
301 | } | |
302 | if (regs->cp0_status & ST0_ERL) | |
303 | printk("ERL "); | |
304 | if (regs->cp0_status & ST0_EXL) | |
305 | printk("EXL "); | |
306 | if (regs->cp0_status & ST0_IE) | |
307 | printk("IE "); | |
1da177e4 | 308 | } |
1da177e4 LT |
309 | printk("\n"); |
310 | ||
311 | printk("Cause : %08x\n", cause); | |
312 | ||
313 | cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; | |
314 | if (1 <= cause && cause <= 5) | |
315 | printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); | |
316 | ||
9966db25 RB |
317 | printk("PrId : %08x (%s)\n", read_c0_prid(), |
318 | cpu_name_string()); | |
1da177e4 LT |
319 | } |
320 | ||
eae23f2c RB |
321 | /* |
322 | * FIXME: really the generic show_regs should take a const pointer argument. | |
323 | */ | |
324 | void show_regs(struct pt_regs *regs) | |
325 | { | |
326 | __show_regs((struct pt_regs *)regs); | |
327 | } | |
328 | ||
c1bf207d | 329 | void show_registers(struct pt_regs *regs) |
1da177e4 | 330 | { |
39b8d525 RB |
331 | const int field = 2 * sizeof(unsigned long); |
332 | ||
eae23f2c | 333 | __show_regs(regs); |
1da177e4 | 334 | print_modules(); |
39b8d525 RB |
335 | printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", |
336 | current->comm, current->pid, current_thread_info(), current, | |
337 | field, current_thread_info()->tp_value); | |
338 | if (cpu_has_userlocal) { | |
339 | unsigned long tls; | |
340 | ||
341 | tls = read_c0_userlocal(); | |
342 | if (tls != current_thread_info()->tp_value) | |
343 | printk("*HwTLS: %0*lx\n", field, tls); | |
344 | } | |
345 | ||
f66686f7 | 346 | show_stacktrace(current, regs); |
e1bb8289 | 347 | show_code((unsigned int __user *) regs->cp0_epc); |
1da177e4 LT |
348 | printk("\n"); |
349 | } | |
350 | ||
70dc6f04 DD |
351 | static int regs_to_trapnr(struct pt_regs *regs) |
352 | { | |
353 | return (regs->cp0_cause >> 2) & 0x1f; | |
354 | } | |
355 | ||
4d85f6af | 356 | static DEFINE_RAW_SPINLOCK(die_lock); |
1da177e4 | 357 | |
70dc6f04 | 358 | void __noreturn die(const char *str, struct pt_regs *regs) |
1da177e4 LT |
359 | { |
360 | static int die_counter; | |
ce384d83 | 361 | int sig = SIGSEGV; |
41c594ab | 362 | #ifdef CONFIG_MIPS_MT_SMTC |
8742cd23 | 363 | unsigned long dvpret; |
41c594ab | 364 | #endif /* CONFIG_MIPS_MT_SMTC */ |
1da177e4 | 365 | |
8742cd23 NL |
366 | oops_enter(); |
367 | ||
10423c91 RB |
368 | if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP) |
369 | sig = 0; | |
5dd11d5d | 370 | |
1da177e4 | 371 | console_verbose(); |
4d85f6af | 372 | raw_spin_lock_irq(&die_lock); |
8742cd23 NL |
373 | #ifdef CONFIG_MIPS_MT_SMTC |
374 | dvpret = dvpe(); | |
375 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
41c594ab RB |
376 | bust_spinlocks(1); |
377 | #ifdef CONFIG_MIPS_MT_SMTC | |
378 | mips_mt_regdump(dvpret); | |
379 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
ce384d83 | 380 | |
178086c8 | 381 | printk("%s[#%d]:\n", str, ++die_counter); |
1da177e4 | 382 | show_registers(regs); |
373d4d09 | 383 | add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); |
4d85f6af | 384 | raw_spin_unlock_irq(&die_lock); |
d4fd1989 | 385 | |
8742cd23 NL |
386 | oops_exit(); |
387 | ||
d4fd1989 MB |
388 | if (in_interrupt()) |
389 | panic("Fatal exception in interrupt"); | |
390 | ||
391 | if (panic_on_oops) { | |
ab75dc02 | 392 | printk(KERN_EMERG "Fatal exception: panic in 5 seconds"); |
d4fd1989 MB |
393 | ssleep(5); |
394 | panic("Fatal exception"); | |
395 | } | |
396 | ||
7aa1c8f4 RB |
397 | if (regs && kexec_should_crash(current)) |
398 | crash_kexec(regs); | |
399 | ||
ce384d83 | 400 | do_exit(sig); |
1da177e4 LT |
401 | } |
402 | ||
0510617b TB |
403 | extern struct exception_table_entry __start___dbe_table[]; |
404 | extern struct exception_table_entry __stop___dbe_table[]; | |
1da177e4 | 405 | |
b6dcec9b RB |
406 | __asm__( |
407 | " .section __dbe_table, \"a\"\n" | |
408 | " .previous \n"); | |
1da177e4 LT |
409 | |
410 | /* Given an address, look for it in the exception tables. */ | |
411 | static const struct exception_table_entry *search_dbe_tables(unsigned long addr) | |
412 | { | |
413 | const struct exception_table_entry *e; | |
414 | ||
415 | e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); | |
416 | if (!e) | |
417 | e = search_module_dbetables(addr); | |
418 | return e; | |
419 | } | |
420 | ||
421 | asmlinkage void do_be(struct pt_regs *regs) | |
422 | { | |
423 | const int field = 2 * sizeof(unsigned long); | |
424 | const struct exception_table_entry *fixup = NULL; | |
425 | int data = regs->cp0_cause & 4; | |
426 | int action = MIPS_BE_FATAL; | |
c3fc5cd5 | 427 | enum ctx_state prev_state; |
1da177e4 | 428 | |
c3fc5cd5 | 429 | prev_state = exception_enter(); |
70342287 | 430 | /* XXX For now. Fixme, this searches the wrong table ... */ |
1da177e4 LT |
431 | if (data && !user_mode(regs)) |
432 | fixup = search_dbe_tables(exception_epc(regs)); | |
433 | ||
434 | if (fixup) | |
435 | action = MIPS_BE_FIXUP; | |
436 | ||
437 | if (board_be_handler) | |
28fc582c | 438 | action = board_be_handler(regs, fixup != NULL); |
1da177e4 LT |
439 | |
440 | switch (action) { | |
441 | case MIPS_BE_DISCARD: | |
c3fc5cd5 | 442 | goto out; |
1da177e4 LT |
443 | case MIPS_BE_FIXUP: |
444 | if (fixup) { | |
445 | regs->cp0_epc = fixup->nextinsn; | |
c3fc5cd5 | 446 | goto out; |
1da177e4 LT |
447 | } |
448 | break; | |
449 | default: | |
450 | break; | |
451 | } | |
452 | ||
453 | /* | |
454 | * Assume it would be too dangerous to continue ... | |
455 | */ | |
456 | printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", | |
457 | data ? "Data" : "Instruction", | |
458 | field, regs->cp0_epc, field, regs->regs[31]); | |
70dc6f04 | 459 | if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS) |
88547001 | 460 | == NOTIFY_STOP) |
c3fc5cd5 | 461 | goto out; |
88547001 | 462 | |
1da177e4 LT |
463 | die_if_kernel("Oops", regs); |
464 | force_sig(SIGBUS, current); | |
c3fc5cd5 RB |
465 | |
466 | out: | |
467 | exception_exit(prev_state); | |
1da177e4 LT |
468 | } |
469 | ||
1da177e4 | 470 | /* |
60b0d655 | 471 | * ll/sc, rdhwr, sync emulation |
1da177e4 LT |
472 | */ |
473 | ||
474 | #define OPCODE 0xfc000000 | |
475 | #define BASE 0x03e00000 | |
476 | #define RT 0x001f0000 | |
477 | #define OFFSET 0x0000ffff | |
478 | #define LL 0xc0000000 | |
479 | #define SC 0xe0000000 | |
60b0d655 | 480 | #define SPEC0 0x00000000 |
3c37026d RB |
481 | #define SPEC3 0x7c000000 |
482 | #define RD 0x0000f800 | |
483 | #define FUNC 0x0000003f | |
60b0d655 | 484 | #define SYNC 0x0000000f |
3c37026d | 485 | #define RDHWR 0x0000003b |
1da177e4 | 486 | |
2a0b24f5 SH |
487 | /* microMIPS definitions */ |
488 | #define MM_POOL32A_FUNC 0xfc00ffff | |
489 | #define MM_RDHWR 0x00006b3c | |
490 | #define MM_RS 0x001f0000 | |
491 | #define MM_RT 0x03e00000 | |
492 | ||
1da177e4 LT |
493 | /* |
494 | * The ll_bit is cleared by r*_switch.S | |
495 | */ | |
496 | ||
f1e39a4a RB |
497 | unsigned int ll_bit; |
498 | struct task_struct *ll_task; | |
1da177e4 | 499 | |
60b0d655 | 500 | static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 501 | { |
fe00f943 | 502 | unsigned long value, __user *vaddr; |
1da177e4 | 503 | long offset; |
1da177e4 LT |
504 | |
505 | /* | |
506 | * analyse the ll instruction that just caused a ri exception | |
507 | * and put the referenced address to addr. | |
508 | */ | |
509 | ||
510 | /* sign extend offset */ | |
511 | offset = opcode & OFFSET; | |
512 | offset <<= 16; | |
513 | offset >>= 16; | |
514 | ||
fe00f943 | 515 | vaddr = (unsigned long __user *) |
b9688310 | 516 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); |
1da177e4 | 517 | |
60b0d655 MR |
518 | if ((unsigned long)vaddr & 3) |
519 | return SIGBUS; | |
520 | if (get_user(value, vaddr)) | |
521 | return SIGSEGV; | |
1da177e4 LT |
522 | |
523 | preempt_disable(); | |
524 | ||
525 | if (ll_task == NULL || ll_task == current) { | |
526 | ll_bit = 1; | |
527 | } else { | |
528 | ll_bit = 0; | |
529 | } | |
530 | ll_task = current; | |
531 | ||
532 | preempt_enable(); | |
533 | ||
534 | regs->regs[(opcode & RT) >> 16] = value; | |
535 | ||
60b0d655 | 536 | return 0; |
1da177e4 LT |
537 | } |
538 | ||
60b0d655 | 539 | static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 540 | { |
fe00f943 RB |
541 | unsigned long __user *vaddr; |
542 | unsigned long reg; | |
1da177e4 | 543 | long offset; |
1da177e4 LT |
544 | |
545 | /* | |
546 | * analyse the sc instruction that just caused a ri exception | |
547 | * and put the referenced address to addr. | |
548 | */ | |
549 | ||
550 | /* sign extend offset */ | |
551 | offset = opcode & OFFSET; | |
552 | offset <<= 16; | |
553 | offset >>= 16; | |
554 | ||
fe00f943 | 555 | vaddr = (unsigned long __user *) |
b9688310 | 556 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); |
1da177e4 LT |
557 | reg = (opcode & RT) >> 16; |
558 | ||
60b0d655 MR |
559 | if ((unsigned long)vaddr & 3) |
560 | return SIGBUS; | |
1da177e4 LT |
561 | |
562 | preempt_disable(); | |
563 | ||
564 | if (ll_bit == 0 || ll_task != current) { | |
565 | regs->regs[reg] = 0; | |
566 | preempt_enable(); | |
60b0d655 | 567 | return 0; |
1da177e4 LT |
568 | } |
569 | ||
570 | preempt_enable(); | |
571 | ||
60b0d655 MR |
572 | if (put_user(regs->regs[reg], vaddr)) |
573 | return SIGSEGV; | |
1da177e4 LT |
574 | |
575 | regs->regs[reg] = 1; | |
576 | ||
60b0d655 | 577 | return 0; |
1da177e4 LT |
578 | } |
579 | ||
580 | /* | |
581 | * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both | |
582 | * opcodes are supposed to result in coprocessor unusable exceptions if | |
583 | * executed on ll/sc-less processors. That's the theory. In practice a | |
584 | * few processors such as NEC's VR4100 throw reserved instruction exceptions | |
585 | * instead, so we're doing the emulation thing in both exception handlers. | |
586 | */ | |
60b0d655 | 587 | static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 588 | { |
7f788d2d DCZ |
589 | if ((opcode & OPCODE) == LL) { |
590 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 591 | 1, regs, 0); |
60b0d655 | 592 | return simulate_ll(regs, opcode); |
7f788d2d DCZ |
593 | } |
594 | if ((opcode & OPCODE) == SC) { | |
595 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 596 | 1, regs, 0); |
60b0d655 | 597 | return simulate_sc(regs, opcode); |
7f788d2d | 598 | } |
1da177e4 | 599 | |
60b0d655 | 600 | return -1; /* Must be something else ... */ |
1da177e4 LT |
601 | } |
602 | ||
3c37026d RB |
603 | /* |
604 | * Simulate trapping 'rdhwr' instructions to provide user accessible | |
1f5826bd | 605 | * registers not implemented in hardware. |
3c37026d | 606 | */ |
2a0b24f5 | 607 | static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt) |
3c37026d | 608 | { |
dc8f6029 | 609 | struct thread_info *ti = task_thread_info(current); |
3c37026d | 610 | |
2a0b24f5 SH |
611 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, |
612 | 1, regs, 0); | |
613 | switch (rd) { | |
614 | case 0: /* CPU number */ | |
615 | regs->regs[rt] = smp_processor_id(); | |
616 | return 0; | |
617 | case 1: /* SYNCI length */ | |
618 | regs->regs[rt] = min(current_cpu_data.dcache.linesz, | |
619 | current_cpu_data.icache.linesz); | |
620 | return 0; | |
621 | case 2: /* Read count register */ | |
622 | regs->regs[rt] = read_c0_count(); | |
623 | return 0; | |
624 | case 3: /* Count register resolution */ | |
625 | switch (current_cpu_data.cputype) { | |
626 | case CPU_20KC: | |
627 | case CPU_25KF: | |
628 | regs->regs[rt] = 1; | |
629 | break; | |
630 | default: | |
631 | regs->regs[rt] = 2; | |
632 | } | |
633 | return 0; | |
634 | case 29: | |
635 | regs->regs[rt] = ti->tp_value; | |
636 | return 0; | |
637 | default: | |
638 | return -1; | |
639 | } | |
640 | } | |
641 | ||
642 | static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode) | |
643 | { | |
3c37026d RB |
644 | if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { |
645 | int rd = (opcode & RD) >> 11; | |
646 | int rt = (opcode & RT) >> 16; | |
2a0b24f5 SH |
647 | |
648 | simulate_rdhwr(regs, rd, rt); | |
649 | return 0; | |
650 | } | |
651 | ||
652 | /* Not ours. */ | |
653 | return -1; | |
654 | } | |
655 | ||
656 | static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode) | |
657 | { | |
658 | if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) { | |
659 | int rd = (opcode & MM_RS) >> 16; | |
660 | int rt = (opcode & MM_RT) >> 21; | |
661 | simulate_rdhwr(regs, rd, rt); | |
662 | return 0; | |
3c37026d RB |
663 | } |
664 | ||
56ebd51b | 665 | /* Not ours. */ |
60b0d655 MR |
666 | return -1; |
667 | } | |
e5679882 | 668 | |
60b0d655 MR |
669 | static int simulate_sync(struct pt_regs *regs, unsigned int opcode) |
670 | { | |
7f788d2d DCZ |
671 | if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) { |
672 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 673 | 1, regs, 0); |
60b0d655 | 674 | return 0; |
7f788d2d | 675 | } |
60b0d655 MR |
676 | |
677 | return -1; /* Must be something else ... */ | |
3c37026d RB |
678 | } |
679 | ||
1da177e4 LT |
680 | asmlinkage void do_ov(struct pt_regs *regs) |
681 | { | |
c3fc5cd5 | 682 | enum ctx_state prev_state; |
1da177e4 LT |
683 | siginfo_t info; |
684 | ||
c3fc5cd5 | 685 | prev_state = exception_enter(); |
36ccf1c0 RB |
686 | die_if_kernel("Integer overflow", regs); |
687 | ||
1da177e4 LT |
688 | info.si_code = FPE_INTOVF; |
689 | info.si_signo = SIGFPE; | |
690 | info.si_errno = 0; | |
fe00f943 | 691 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 | 692 | force_sig_info(SIGFPE, &info, current); |
c3fc5cd5 | 693 | exception_exit(prev_state); |
1da177e4 LT |
694 | } |
695 | ||
102cedc3 | 696 | int process_fpemu_return(int sig, void __user *fault_addr) |
515b029d DD |
697 | { |
698 | if (sig == SIGSEGV || sig == SIGBUS) { | |
699 | struct siginfo si = {0}; | |
700 | si.si_addr = fault_addr; | |
701 | si.si_signo = sig; | |
702 | if (sig == SIGSEGV) { | |
703 | if (find_vma(current->mm, (unsigned long)fault_addr)) | |
704 | si.si_code = SEGV_ACCERR; | |
705 | else | |
706 | si.si_code = SEGV_MAPERR; | |
707 | } else { | |
708 | si.si_code = BUS_ADRERR; | |
709 | } | |
710 | force_sig_info(sig, &si, current); | |
711 | return 1; | |
712 | } else if (sig) { | |
713 | force_sig(sig, current); | |
714 | return 1; | |
715 | } else { | |
716 | return 0; | |
717 | } | |
718 | } | |
719 | ||
1da177e4 LT |
720 | /* |
721 | * XXX Delayed fp exceptions when doing a lazy ctx switch XXX | |
722 | */ | |
723 | asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) | |
724 | { | |
c3fc5cd5 | 725 | enum ctx_state prev_state; |
515b029d | 726 | siginfo_t info = {0}; |
948a34cf | 727 | |
c3fc5cd5 | 728 | prev_state = exception_enter(); |
70dc6f04 | 729 | if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE) |
88547001 | 730 | == NOTIFY_STOP) |
c3fc5cd5 | 731 | goto out; |
57725f9e CD |
732 | die_if_kernel("FP exception in kernel code", regs); |
733 | ||
1da177e4 LT |
734 | if (fcr31 & FPU_CSR_UNI_X) { |
735 | int sig; | |
515b029d | 736 | void __user *fault_addr = NULL; |
1da177e4 | 737 | |
1da177e4 | 738 | /* |
a3dddd56 | 739 | * Unimplemented operation exception. If we've got the full |
1da177e4 LT |
740 | * software emulator on-board, let's use it... |
741 | * | |
742 | * Force FPU to dump state into task/thread context. We're | |
743 | * moving a lot of data here for what is probably a single | |
744 | * instruction, but the alternative is to pre-decode the FP | |
745 | * register operands before invoking the emulator, which seems | |
746 | * a bit extreme for what should be an infrequent event. | |
747 | */ | |
cd21dfcf | 748 | /* Ensure 'resume' not overwrite saved fp context again. */ |
53dc8028 | 749 | lose_fpu(1); |
1da177e4 LT |
750 | |
751 | /* Run the emulator */ | |
515b029d DD |
752 | sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, |
753 | &fault_addr); | |
1da177e4 LT |
754 | |
755 | /* | |
756 | * We can't allow the emulated instruction to leave any of | |
757 | * the cause bit set in $fcr31. | |
758 | */ | |
eae89076 | 759 | current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; |
1da177e4 LT |
760 | |
761 | /* Restore the hardware register state */ | |
70342287 | 762 | own_fpu(1); /* Using the FPU again. */ |
1da177e4 LT |
763 | |
764 | /* If something went wrong, signal */ | |
515b029d | 765 | process_fpemu_return(sig, fault_addr); |
1da177e4 | 766 | |
c3fc5cd5 | 767 | goto out; |
948a34cf TS |
768 | } else if (fcr31 & FPU_CSR_INV_X) |
769 | info.si_code = FPE_FLTINV; | |
770 | else if (fcr31 & FPU_CSR_DIV_X) | |
771 | info.si_code = FPE_FLTDIV; | |
772 | else if (fcr31 & FPU_CSR_OVF_X) | |
773 | info.si_code = FPE_FLTOVF; | |
774 | else if (fcr31 & FPU_CSR_UDF_X) | |
775 | info.si_code = FPE_FLTUND; | |
776 | else if (fcr31 & FPU_CSR_INE_X) | |
777 | info.si_code = FPE_FLTRES; | |
778 | else | |
779 | info.si_code = __SI_FAULT; | |
780 | info.si_signo = SIGFPE; | |
781 | info.si_errno = 0; | |
782 | info.si_addr = (void __user *) regs->cp0_epc; | |
783 | force_sig_info(SIGFPE, &info, current); | |
c3fc5cd5 RB |
784 | |
785 | out: | |
786 | exception_exit(prev_state); | |
1da177e4 LT |
787 | } |
788 | ||
df270051 RB |
789 | static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, |
790 | const char *str) | |
1da177e4 | 791 | { |
1da177e4 | 792 | siginfo_t info; |
df270051 | 793 | char b[40]; |
1da177e4 | 794 | |
5dd11d5d | 795 | #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP |
70dc6f04 | 796 | if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) |
5dd11d5d JW |
797 | return; |
798 | #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ | |
799 | ||
70dc6f04 | 800 | if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) |
88547001 JW |
801 | return; |
802 | ||
1da177e4 | 803 | /* |
df270051 RB |
804 | * A short test says that IRIX 5.3 sends SIGTRAP for all trap |
805 | * insns, even for trap and break codes that indicate arithmetic | |
806 | * failures. Weird ... | |
1da177e4 LT |
807 | * But should we continue the brokenness??? --macro |
808 | */ | |
df270051 RB |
809 | switch (code) { |
810 | case BRK_OVERFLOW: | |
811 | case BRK_DIVZERO: | |
812 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); | |
813 | die_if_kernel(b, regs); | |
814 | if (code == BRK_DIVZERO) | |
1da177e4 LT |
815 | info.si_code = FPE_INTDIV; |
816 | else | |
817 | info.si_code = FPE_INTOVF; | |
818 | info.si_signo = SIGFPE; | |
819 | info.si_errno = 0; | |
fe00f943 | 820 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
821 | force_sig_info(SIGFPE, &info, current); |
822 | break; | |
63dc68a8 | 823 | case BRK_BUG: |
df270051 RB |
824 | die_if_kernel("Kernel bug detected", regs); |
825 | force_sig(SIGTRAP, current); | |
63dc68a8 | 826 | break; |
ba3049ed RB |
827 | case BRK_MEMU: |
828 | /* | |
829 | * Address errors may be deliberately induced by the FPU | |
830 | * emulator to retake control of the CPU after executing the | |
831 | * instruction in the delay slot of an emulated branch. | |
832 | * | |
833 | * Terminate if exception was recognized as a delay slot return | |
834 | * otherwise handle as normal. | |
835 | */ | |
836 | if (do_dsemulret(regs)) | |
837 | return; | |
838 | ||
839 | die_if_kernel("Math emu break/trap", regs); | |
840 | force_sig(SIGTRAP, current); | |
841 | break; | |
1da177e4 | 842 | default: |
df270051 RB |
843 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); |
844 | die_if_kernel(b, regs); | |
1da177e4 LT |
845 | force_sig(SIGTRAP, current); |
846 | } | |
df270051 RB |
847 | } |
848 | ||
849 | asmlinkage void do_bp(struct pt_regs *regs) | |
850 | { | |
851 | unsigned int opcode, bcode; | |
c3fc5cd5 | 852 | enum ctx_state prev_state; |
2a0b24f5 SH |
853 | unsigned long epc; |
854 | u16 instr[2]; | |
855 | ||
c3fc5cd5 | 856 | prev_state = exception_enter(); |
2a0b24f5 SH |
857 | if (get_isa16_mode(regs->cp0_epc)) { |
858 | /* Calculate EPC. */ | |
859 | epc = exception_epc(regs); | |
860 | if (cpu_has_mmips) { | |
861 | if ((__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc)) || | |
862 | (__get_user(instr[1], (u16 __user *)msk_isa16_mode(epc + 2))))) | |
863 | goto out_sigsegv; | |
864 | opcode = (instr[0] << 16) | instr[1]; | |
865 | } else { | |
866 | /* MIPS16e mode */ | |
867 | if (__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc))) | |
868 | goto out_sigsegv; | |
869 | bcode = (instr[0] >> 6) & 0x3f; | |
870 | do_trap_or_bp(regs, bcode, "Break"); | |
c3fc5cd5 | 871 | goto out; |
2a0b24f5 SH |
872 | } |
873 | } else { | |
874 | if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) | |
875 | goto out_sigsegv; | |
876 | } | |
df270051 RB |
877 | |
878 | /* | |
879 | * There is the ancient bug in the MIPS assemblers that the break | |
880 | * code starts left to bit 16 instead to bit 6 in the opcode. | |
881 | * Gas is bug-compatible, but not always, grrr... | |
882 | * We handle both cases with a simple heuristics. --macro | |
883 | */ | |
884 | bcode = ((opcode >> 6) & ((1 << 20) - 1)); | |
885 | if (bcode >= (1 << 10)) | |
886 | bcode >>= 10; | |
887 | ||
c1bf207d DD |
888 | /* |
889 | * notify the kprobe handlers, if instruction is likely to | |
890 | * pertain to them. | |
891 | */ | |
892 | switch (bcode) { | |
893 | case BRK_KPROBE_BP: | |
70dc6f04 | 894 | if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) |
c3fc5cd5 | 895 | goto out; |
c1bf207d DD |
896 | else |
897 | break; | |
898 | case BRK_KPROBE_SSTEPBP: | |
70dc6f04 | 899 | if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) |
c3fc5cd5 | 900 | goto out; |
c1bf207d DD |
901 | else |
902 | break; | |
903 | default: | |
904 | break; | |
905 | } | |
906 | ||
df270051 | 907 | do_trap_or_bp(regs, bcode, "Break"); |
c3fc5cd5 RB |
908 | |
909 | out: | |
910 | exception_exit(prev_state); | |
90fccb13 | 911 | return; |
e5679882 RB |
912 | |
913 | out_sigsegv: | |
914 | force_sig(SIGSEGV, current); | |
c3fc5cd5 | 915 | goto out; |
1da177e4 LT |
916 | } |
917 | ||
918 | asmlinkage void do_tr(struct pt_regs *regs) | |
919 | { | |
a9a6e7a0 | 920 | u32 opcode, tcode = 0; |
c3fc5cd5 | 921 | enum ctx_state prev_state; |
2a0b24f5 | 922 | u16 instr[2]; |
a9a6e7a0 | 923 | unsigned long epc = msk_isa16_mode(exception_epc(regs)); |
1da177e4 | 924 | |
c3fc5cd5 | 925 | prev_state = exception_enter(); |
a9a6e7a0 MR |
926 | if (get_isa16_mode(regs->cp0_epc)) { |
927 | if (__get_user(instr[0], (u16 __user *)(epc + 0)) || | |
928 | __get_user(instr[1], (u16 __user *)(epc + 2))) | |
2a0b24f5 | 929 | goto out_sigsegv; |
a9a6e7a0 MR |
930 | opcode = (instr[0] << 16) | instr[1]; |
931 | /* Immediate versions don't provide a code. */ | |
932 | if (!(opcode & OPCODE)) | |
933 | tcode = (opcode >> 12) & ((1 << 4) - 1); | |
934 | } else { | |
935 | if (__get_user(opcode, (u32 __user *)epc)) | |
936 | goto out_sigsegv; | |
937 | /* Immediate versions don't provide a code. */ | |
938 | if (!(opcode & OPCODE)) | |
939 | tcode = (opcode >> 6) & ((1 << 10) - 1); | |
2a0b24f5 | 940 | } |
1da177e4 | 941 | |
df270051 | 942 | do_trap_or_bp(regs, tcode, "Trap"); |
c3fc5cd5 RB |
943 | |
944 | out: | |
945 | exception_exit(prev_state); | |
90fccb13 | 946 | return; |
e5679882 RB |
947 | |
948 | out_sigsegv: | |
949 | force_sig(SIGSEGV, current); | |
c3fc5cd5 | 950 | goto out; |
1da177e4 LT |
951 | } |
952 | ||
953 | asmlinkage void do_ri(struct pt_regs *regs) | |
954 | { | |
60b0d655 MR |
955 | unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); |
956 | unsigned long old_epc = regs->cp0_epc; | |
2a0b24f5 | 957 | unsigned long old31 = regs->regs[31]; |
c3fc5cd5 | 958 | enum ctx_state prev_state; |
60b0d655 MR |
959 | unsigned int opcode = 0; |
960 | int status = -1; | |
1da177e4 | 961 | |
c3fc5cd5 | 962 | prev_state = exception_enter(); |
70dc6f04 | 963 | if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL) |
88547001 | 964 | == NOTIFY_STOP) |
c3fc5cd5 | 965 | goto out; |
88547001 | 966 | |
60b0d655 | 967 | die_if_kernel("Reserved instruction in kernel code", regs); |
1da177e4 | 968 | |
60b0d655 | 969 | if (unlikely(compute_return_epc(regs) < 0)) |
c3fc5cd5 | 970 | goto out; |
3c37026d | 971 | |
2a0b24f5 SH |
972 | if (get_isa16_mode(regs->cp0_epc)) { |
973 | unsigned short mmop[2] = { 0 }; | |
60b0d655 | 974 | |
2a0b24f5 SH |
975 | if (unlikely(get_user(mmop[0], epc) < 0)) |
976 | status = SIGSEGV; | |
977 | if (unlikely(get_user(mmop[1], epc) < 0)) | |
978 | status = SIGSEGV; | |
979 | opcode = (mmop[0] << 16) | mmop[1]; | |
60b0d655 | 980 | |
2a0b24f5 SH |
981 | if (status < 0) |
982 | status = simulate_rdhwr_mm(regs, opcode); | |
983 | } else { | |
984 | if (unlikely(get_user(opcode, epc) < 0)) | |
985 | status = SIGSEGV; | |
60b0d655 | 986 | |
2a0b24f5 SH |
987 | if (!cpu_has_llsc && status < 0) |
988 | status = simulate_llsc(regs, opcode); | |
989 | ||
990 | if (status < 0) | |
991 | status = simulate_rdhwr_normal(regs, opcode); | |
992 | ||
993 | if (status < 0) | |
994 | status = simulate_sync(regs, opcode); | |
995 | } | |
60b0d655 MR |
996 | |
997 | if (status < 0) | |
998 | status = SIGILL; | |
999 | ||
1000 | if (unlikely(status > 0)) { | |
1001 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
2a0b24f5 | 1002 | regs->regs[31] = old31; |
60b0d655 MR |
1003 | force_sig(status, current); |
1004 | } | |
c3fc5cd5 RB |
1005 | |
1006 | out: | |
1007 | exception_exit(prev_state); | |
1da177e4 LT |
1008 | } |
1009 | ||
d223a861 RB |
1010 | /* |
1011 | * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've | |
1012 | * emulated more than some threshold number of instructions, force migration to | |
1013 | * a "CPU" that has FP support. | |
1014 | */ | |
1015 | static void mt_ase_fp_affinity(void) | |
1016 | { | |
1017 | #ifdef CONFIG_MIPS_MT_FPAFF | |
1018 | if (mt_fpemul_threshold > 0 && | |
1019 | ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { | |
1020 | /* | |
1021 | * If there's no FPU present, or if the application has already | |
1022 | * restricted the allowed set to exclude any CPUs with FPUs, | |
1023 | * we'll skip the procedure. | |
1024 | */ | |
1025 | if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { | |
1026 | cpumask_t tmask; | |
1027 | ||
9cc12363 KK |
1028 | current->thread.user_cpus_allowed |
1029 | = current->cpus_allowed; | |
1030 | cpus_and(tmask, current->cpus_allowed, | |
1031 | mt_fpu_cpumask); | |
ed1bbdef | 1032 | set_cpus_allowed_ptr(current, &tmask); |
293c5bd1 | 1033 | set_thread_flag(TIF_FPUBOUND); |
d223a861 RB |
1034 | } |
1035 | } | |
1036 | #endif /* CONFIG_MIPS_MT_FPAFF */ | |
1037 | } | |
1038 | ||
69f3a7de RB |
1039 | /* |
1040 | * No lock; only written during early bootup by CPU 0. | |
1041 | */ | |
1042 | static RAW_NOTIFIER_HEAD(cu2_chain); | |
1043 | ||
1044 | int __ref register_cu2_notifier(struct notifier_block *nb) | |
1045 | { | |
1046 | return raw_notifier_chain_register(&cu2_chain, nb); | |
1047 | } | |
1048 | ||
1049 | int cu2_notifier_call_chain(unsigned long val, void *v) | |
1050 | { | |
1051 | return raw_notifier_call_chain(&cu2_chain, val, v); | |
1052 | } | |
1053 | ||
1054 | static int default_cu2_call(struct notifier_block *nfb, unsigned long action, | |
70342287 | 1055 | void *data) |
69f3a7de RB |
1056 | { |
1057 | struct pt_regs *regs = data; | |
1058 | ||
83bee792 | 1059 | die_if_kernel("COP2: Unhandled kernel unaligned access or invalid " |
69f3a7de | 1060 | "instruction", regs); |
83bee792 | 1061 | force_sig(SIGILL, current); |
69f3a7de RB |
1062 | |
1063 | return NOTIFY_OK; | |
1064 | } | |
1065 | ||
1da177e4 LT |
1066 | asmlinkage void do_cpu(struct pt_regs *regs) |
1067 | { | |
c3fc5cd5 | 1068 | enum ctx_state prev_state; |
60b0d655 | 1069 | unsigned int __user *epc; |
2a0b24f5 | 1070 | unsigned long old_epc, old31; |
60b0d655 | 1071 | unsigned int opcode; |
1da177e4 | 1072 | unsigned int cpid; |
60b0d655 | 1073 | int status; |
f9bb4cf3 | 1074 | unsigned long __maybe_unused flags; |
1da177e4 | 1075 | |
c3fc5cd5 | 1076 | prev_state = exception_enter(); |
1da177e4 LT |
1077 | cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; |
1078 | ||
83bee792 J |
1079 | if (cpid != 2) |
1080 | die_if_kernel("do_cpu invoked from kernel context!", regs); | |
1081 | ||
1da177e4 LT |
1082 | switch (cpid) { |
1083 | case 0: | |
60b0d655 MR |
1084 | epc = (unsigned int __user *)exception_epc(regs); |
1085 | old_epc = regs->cp0_epc; | |
2a0b24f5 | 1086 | old31 = regs->regs[31]; |
60b0d655 MR |
1087 | opcode = 0; |
1088 | status = -1; | |
1da177e4 | 1089 | |
60b0d655 | 1090 | if (unlikely(compute_return_epc(regs) < 0)) |
c3fc5cd5 | 1091 | goto out; |
3c37026d | 1092 | |
2a0b24f5 SH |
1093 | if (get_isa16_mode(regs->cp0_epc)) { |
1094 | unsigned short mmop[2] = { 0 }; | |
60b0d655 | 1095 | |
2a0b24f5 SH |
1096 | if (unlikely(get_user(mmop[0], epc) < 0)) |
1097 | status = SIGSEGV; | |
1098 | if (unlikely(get_user(mmop[1], epc) < 0)) | |
1099 | status = SIGSEGV; | |
1100 | opcode = (mmop[0] << 16) | mmop[1]; | |
60b0d655 | 1101 | |
2a0b24f5 SH |
1102 | if (status < 0) |
1103 | status = simulate_rdhwr_mm(regs, opcode); | |
1104 | } else { | |
1105 | if (unlikely(get_user(opcode, epc) < 0)) | |
1106 | status = SIGSEGV; | |
1107 | ||
1108 | if (!cpu_has_llsc && status < 0) | |
1109 | status = simulate_llsc(regs, opcode); | |
1110 | ||
1111 | if (status < 0) | |
1112 | status = simulate_rdhwr_normal(regs, opcode); | |
1113 | } | |
60b0d655 MR |
1114 | |
1115 | if (status < 0) | |
1116 | status = SIGILL; | |
1117 | ||
1118 | if (unlikely(status > 0)) { | |
1119 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
2a0b24f5 | 1120 | regs->regs[31] = old31; |
60b0d655 MR |
1121 | force_sig(status, current); |
1122 | } | |
1123 | ||
c3fc5cd5 | 1124 | goto out; |
1da177e4 | 1125 | |
051ff44a MR |
1126 | case 3: |
1127 | /* | |
1128 | * Old (MIPS I and MIPS II) processors will set this code | |
1129 | * for COP1X opcode instructions that replaced the original | |
70342287 | 1130 | * COP3 space. We don't limit COP1 space instructions in |
051ff44a MR |
1131 | * the emulator according to the CPU ISA, so we want to |
1132 | * treat COP1X instructions consistently regardless of which | |
70342287 | 1133 | * code the CPU chose. Therefore we redirect this trap to |
051ff44a MR |
1134 | * the FP emulator too. |
1135 | * | |
1136 | * Then some newer FPU-less processors use this code | |
1137 | * erroneously too, so they are covered by this choice | |
1138 | * as well. | |
1139 | */ | |
1140 | if (raw_cpu_has_fpu) | |
1141 | break; | |
1142 | /* Fall through. */ | |
1143 | ||
1da177e4 | 1144 | case 1: |
70342287 | 1145 | if (used_math()) /* Using the FPU again. */ |
53dc8028 | 1146 | own_fpu(1); |
70342287 | 1147 | else { /* First time FPU user. */ |
1da177e4 LT |
1148 | init_fpu(); |
1149 | set_used_math(); | |
1150 | } | |
1151 | ||
5323180d | 1152 | if (!raw_cpu_has_fpu) { |
e04582b7 | 1153 | int sig; |
515b029d | 1154 | void __user *fault_addr = NULL; |
e04582b7 | 1155 | sig = fpu_emulator_cop1Handler(regs, |
515b029d DD |
1156 | ¤t->thread.fpu, |
1157 | 0, &fault_addr); | |
1158 | if (!process_fpemu_return(sig, fault_addr)) | |
d223a861 | 1159 | mt_ase_fp_affinity(); |
1da177e4 LT |
1160 | } |
1161 | ||
c3fc5cd5 | 1162 | goto out; |
1da177e4 LT |
1163 | |
1164 | case 2: | |
69f3a7de | 1165 | raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); |
c3fc5cd5 | 1166 | goto out; |
1da177e4 LT |
1167 | } |
1168 | ||
1169 | force_sig(SIGILL, current); | |
c3fc5cd5 RB |
1170 | |
1171 | out: | |
1172 | exception_exit(prev_state); | |
1da177e4 LT |
1173 | } |
1174 | ||
1175 | asmlinkage void do_mdmx(struct pt_regs *regs) | |
1176 | { | |
c3fc5cd5 RB |
1177 | enum ctx_state prev_state; |
1178 | ||
1179 | prev_state = exception_enter(); | |
1da177e4 | 1180 | force_sig(SIGILL, current); |
c3fc5cd5 | 1181 | exception_exit(prev_state); |
1da177e4 LT |
1182 | } |
1183 | ||
8bc6d05b DD |
1184 | /* |
1185 | * Called with interrupts disabled. | |
1186 | */ | |
1da177e4 LT |
1187 | asmlinkage void do_watch(struct pt_regs *regs) |
1188 | { | |
c3fc5cd5 | 1189 | enum ctx_state prev_state; |
b67b2b70 DD |
1190 | u32 cause; |
1191 | ||
c3fc5cd5 | 1192 | prev_state = exception_enter(); |
1da177e4 | 1193 | /* |
b67b2b70 DD |
1194 | * Clear WP (bit 22) bit of cause register so we don't loop |
1195 | * forever. | |
1da177e4 | 1196 | */ |
b67b2b70 DD |
1197 | cause = read_c0_cause(); |
1198 | cause &= ~(1 << 22); | |
1199 | write_c0_cause(cause); | |
1200 | ||
1201 | /* | |
1202 | * If the current thread has the watch registers loaded, save | |
1203 | * their values and send SIGTRAP. Otherwise another thread | |
1204 | * left the registers set, clear them and continue. | |
1205 | */ | |
1206 | if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { | |
1207 | mips_read_watch_registers(); | |
8bc6d05b | 1208 | local_irq_enable(); |
b67b2b70 | 1209 | force_sig(SIGTRAP, current); |
8bc6d05b | 1210 | } else { |
b67b2b70 | 1211 | mips_clear_watch_registers(); |
8bc6d05b DD |
1212 | local_irq_enable(); |
1213 | } | |
c3fc5cd5 | 1214 | exception_exit(prev_state); |
1da177e4 LT |
1215 | } |
1216 | ||
1217 | asmlinkage void do_mcheck(struct pt_regs *regs) | |
1218 | { | |
cac4bcbc RB |
1219 | const int field = 2 * sizeof(unsigned long); |
1220 | int multi_match = regs->cp0_status & ST0_TS; | |
c3fc5cd5 | 1221 | enum ctx_state prev_state; |
cac4bcbc | 1222 | |
c3fc5cd5 | 1223 | prev_state = exception_enter(); |
1da177e4 | 1224 | show_regs(regs); |
cac4bcbc RB |
1225 | |
1226 | if (multi_match) { | |
70342287 | 1227 | printk("Index : %0x\n", read_c0_index()); |
cac4bcbc RB |
1228 | printk("Pagemask: %0x\n", read_c0_pagemask()); |
1229 | printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); | |
1230 | printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); | |
1231 | printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); | |
1232 | printk("\n"); | |
1233 | dump_tlb_all(); | |
1234 | } | |
1235 | ||
e1bb8289 | 1236 | show_code((unsigned int __user *) regs->cp0_epc); |
cac4bcbc | 1237 | |
1da177e4 LT |
1238 | /* |
1239 | * Some chips may have other causes of machine check (e.g. SB1 | |
1240 | * graduation timer) | |
1241 | */ | |
1242 | panic("Caught Machine Check exception - %scaused by multiple " | |
1243 | "matching entries in the TLB.", | |
cac4bcbc | 1244 | (multi_match) ? "" : "not "); |
c3fc5cd5 | 1245 | exception_exit(prev_state); |
1da177e4 LT |
1246 | } |
1247 | ||
340ee4b9 RB |
1248 | asmlinkage void do_mt(struct pt_regs *regs) |
1249 | { | |
41c594ab RB |
1250 | int subcode; |
1251 | ||
41c594ab RB |
1252 | subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) |
1253 | >> VPECONTROL_EXCPT_SHIFT; | |
1254 | switch (subcode) { | |
1255 | case 0: | |
e35a5e35 | 1256 | printk(KERN_DEBUG "Thread Underflow\n"); |
41c594ab RB |
1257 | break; |
1258 | case 1: | |
e35a5e35 | 1259 | printk(KERN_DEBUG "Thread Overflow\n"); |
41c594ab RB |
1260 | break; |
1261 | case 2: | |
e35a5e35 | 1262 | printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); |
41c594ab RB |
1263 | break; |
1264 | case 3: | |
e35a5e35 | 1265 | printk(KERN_DEBUG "Gating Storage Exception\n"); |
41c594ab RB |
1266 | break; |
1267 | case 4: | |
e35a5e35 | 1268 | printk(KERN_DEBUG "YIELD Scheduler Exception\n"); |
41c594ab RB |
1269 | break; |
1270 | case 5: | |
f232c7e8 | 1271 | printk(KERN_DEBUG "Gating Storage Scheduler Exception\n"); |
41c594ab RB |
1272 | break; |
1273 | default: | |
e35a5e35 | 1274 | printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", |
41c594ab RB |
1275 | subcode); |
1276 | break; | |
1277 | } | |
340ee4b9 RB |
1278 | die_if_kernel("MIPS MT Thread exception in kernel", regs); |
1279 | ||
1280 | force_sig(SIGILL, current); | |
1281 | } | |
1282 | ||
1283 | ||
e50c0a8f RB |
1284 | asmlinkage void do_dsp(struct pt_regs *regs) |
1285 | { | |
1286 | if (cpu_has_dsp) | |
ab75dc02 | 1287 | panic("Unexpected DSP exception"); |
e50c0a8f RB |
1288 | |
1289 | force_sig(SIGILL, current); | |
1290 | } | |
1291 | ||
1da177e4 LT |
1292 | asmlinkage void do_reserved(struct pt_regs *regs) |
1293 | { | |
1294 | /* | |
70342287 | 1295 | * Game over - no way to handle this if it ever occurs. Most probably |
1da177e4 LT |
1296 | * caused by a new unknown cpu type or after another deadly |
1297 | * hard/software error. | |
1298 | */ | |
1299 | show_regs(regs); | |
1300 | panic("Caught reserved exception %ld - should not happen.", | |
1301 | (regs->cp0_cause & 0x7f) >> 2); | |
1302 | } | |
1303 | ||
39b8d525 RB |
1304 | static int __initdata l1parity = 1; |
1305 | static int __init nol1parity(char *s) | |
1306 | { | |
1307 | l1parity = 0; | |
1308 | return 1; | |
1309 | } | |
1310 | __setup("nol1par", nol1parity); | |
1311 | static int __initdata l2parity = 1; | |
1312 | static int __init nol2parity(char *s) | |
1313 | { | |
1314 | l2parity = 0; | |
1315 | return 1; | |
1316 | } | |
1317 | __setup("nol2par", nol2parity); | |
1318 | ||
1da177e4 LT |
1319 | /* |
1320 | * Some MIPS CPUs can enable/disable for cache parity detection, but do | |
1321 | * it different ways. | |
1322 | */ | |
1323 | static inline void parity_protection_init(void) | |
1324 | { | |
10cc3529 | 1325 | switch (current_cpu_type()) { |
1da177e4 | 1326 | case CPU_24K: |
98a41de9 | 1327 | case CPU_34K: |
39b8d525 RB |
1328 | case CPU_74K: |
1329 | case CPU_1004K: | |
1330 | { | |
1331 | #define ERRCTL_PE 0x80000000 | |
1332 | #define ERRCTL_L2P 0x00800000 | |
1333 | unsigned long errctl; | |
1334 | unsigned int l1parity_present, l2parity_present; | |
1335 | ||
1336 | errctl = read_c0_ecc(); | |
1337 | errctl &= ~(ERRCTL_PE|ERRCTL_L2P); | |
1338 | ||
1339 | /* probe L1 parity support */ | |
1340 | write_c0_ecc(errctl | ERRCTL_PE); | |
1341 | back_to_back_c0_hazard(); | |
1342 | l1parity_present = (read_c0_ecc() & ERRCTL_PE); | |
1343 | ||
1344 | /* probe L2 parity support */ | |
1345 | write_c0_ecc(errctl|ERRCTL_L2P); | |
1346 | back_to_back_c0_hazard(); | |
1347 | l2parity_present = (read_c0_ecc() & ERRCTL_L2P); | |
1348 | ||
1349 | if (l1parity_present && l2parity_present) { | |
1350 | if (l1parity) | |
1351 | errctl |= ERRCTL_PE; | |
1352 | if (l1parity ^ l2parity) | |
1353 | errctl |= ERRCTL_L2P; | |
1354 | } else if (l1parity_present) { | |
1355 | if (l1parity) | |
1356 | errctl |= ERRCTL_PE; | |
1357 | } else if (l2parity_present) { | |
1358 | if (l2parity) | |
1359 | errctl |= ERRCTL_L2P; | |
1360 | } else { | |
1361 | /* No parity available */ | |
1362 | } | |
1363 | ||
1364 | printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); | |
1365 | ||
1366 | write_c0_ecc(errctl); | |
1367 | back_to_back_c0_hazard(); | |
1368 | errctl = read_c0_ecc(); | |
1369 | printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); | |
1370 | ||
1371 | if (l1parity_present) | |
1372 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1373 | (errctl & ERRCTL_PE) ? "en" : "dis"); | |
1374 | ||
1375 | if (l2parity_present) { | |
1376 | if (l1parity_present && l1parity) | |
1377 | errctl ^= ERRCTL_L2P; | |
1378 | printk(KERN_INFO "L2 cache parity protection %sabled\n", | |
1379 | (errctl & ERRCTL_L2P) ? "en" : "dis"); | |
1380 | } | |
1381 | } | |
1382 | break; | |
1383 | ||
1da177e4 | 1384 | case CPU_5KC: |
78d4803f | 1385 | case CPU_5KE: |
2fa36399 | 1386 | case CPU_LOONGSON1: |
14f18b7f RB |
1387 | write_c0_ecc(0x80000000); |
1388 | back_to_back_c0_hazard(); | |
1389 | /* Set the PE bit (bit 31) in the c0_errctl register. */ | |
1390 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1391 | (read_c0_ecc() & 0x80000000) ? "en" : "dis"); | |
1da177e4 LT |
1392 | break; |
1393 | case CPU_20KC: | |
1394 | case CPU_25KF: | |
1395 | /* Clear the DE bit (bit 16) in the c0_status register. */ | |
1396 | printk(KERN_INFO "Enable cache parity protection for " | |
1397 | "MIPS 20KC/25KF CPUs.\n"); | |
1398 | clear_c0_status(ST0_DE); | |
1399 | break; | |
1400 | default: | |
1401 | break; | |
1402 | } | |
1403 | } | |
1404 | ||
1405 | asmlinkage void cache_parity_error(void) | |
1406 | { | |
1407 | const int field = 2 * sizeof(unsigned long); | |
1408 | unsigned int reg_val; | |
1409 | ||
1410 | /* For the moment, report the problem and hang. */ | |
1411 | printk("Cache error exception:\n"); | |
1412 | printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); | |
1413 | reg_val = read_c0_cacheerr(); | |
1414 | printk("c0_cacheerr == %08x\n", reg_val); | |
1415 | ||
1416 | printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", | |
1417 | reg_val & (1<<30) ? "secondary" : "primary", | |
1418 | reg_val & (1<<31) ? "data" : "insn"); | |
1419 | printk("Error bits: %s%s%s%s%s%s%s\n", | |
1420 | reg_val & (1<<29) ? "ED " : "", | |
1421 | reg_val & (1<<28) ? "ET " : "", | |
1422 | reg_val & (1<<26) ? "EE " : "", | |
1423 | reg_val & (1<<25) ? "EB " : "", | |
1424 | reg_val & (1<<24) ? "EI " : "", | |
1425 | reg_val & (1<<23) ? "E1 " : "", | |
1426 | reg_val & (1<<22) ? "E0 " : ""); | |
1427 | printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); | |
1428 | ||
ec917c2c | 1429 | #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) |
1da177e4 LT |
1430 | if (reg_val & (1<<22)) |
1431 | printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); | |
1432 | ||
1433 | if (reg_val & (1<<23)) | |
1434 | printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); | |
1435 | #endif | |
1436 | ||
1437 | panic("Can't handle the cache error!"); | |
1438 | } | |
1439 | ||
1440 | /* | |
1441 | * SDBBP EJTAG debug exception handler. | |
1442 | * We skip the instruction and return to the next instruction. | |
1443 | */ | |
1444 | void ejtag_exception_handler(struct pt_regs *regs) | |
1445 | { | |
1446 | const int field = 2 * sizeof(unsigned long); | |
2a0b24f5 | 1447 | unsigned long depc, old_epc, old_ra; |
1da177e4 LT |
1448 | unsigned int debug; |
1449 | ||
70ae6126 | 1450 | printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); |
1da177e4 LT |
1451 | depc = read_c0_depc(); |
1452 | debug = read_c0_debug(); | |
70ae6126 | 1453 | printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); |
1da177e4 LT |
1454 | if (debug & 0x80000000) { |
1455 | /* | |
1456 | * In branch delay slot. | |
1457 | * We cheat a little bit here and use EPC to calculate the | |
1458 | * debug return address (DEPC). EPC is restored after the | |
1459 | * calculation. | |
1460 | */ | |
1461 | old_epc = regs->cp0_epc; | |
2a0b24f5 | 1462 | old_ra = regs->regs[31]; |
1da177e4 | 1463 | regs->cp0_epc = depc; |
2a0b24f5 | 1464 | compute_return_epc(regs); |
1da177e4 LT |
1465 | depc = regs->cp0_epc; |
1466 | regs->cp0_epc = old_epc; | |
2a0b24f5 | 1467 | regs->regs[31] = old_ra; |
1da177e4 LT |
1468 | } else |
1469 | depc += 4; | |
1470 | write_c0_depc(depc); | |
1471 | ||
1472 | #if 0 | |
70ae6126 | 1473 | printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); |
1da177e4 LT |
1474 | write_c0_debug(debug | 0x100); |
1475 | #endif | |
1476 | } | |
1477 | ||
1478 | /* | |
1479 | * NMI exception handler. | |
34bd92e2 | 1480 | * No lock; only written during early bootup by CPU 0. |
1da177e4 | 1481 | */ |
34bd92e2 KC |
1482 | static RAW_NOTIFIER_HEAD(nmi_chain); |
1483 | ||
1484 | int register_nmi_notifier(struct notifier_block *nb) | |
1485 | { | |
1486 | return raw_notifier_chain_register(&nmi_chain, nb); | |
1487 | } | |
1488 | ||
ff2d8b19 | 1489 | void __noreturn nmi_exception_handler(struct pt_regs *regs) |
1da177e4 | 1490 | { |
34bd92e2 | 1491 | raw_notifier_call_chain(&nmi_chain, 0, regs); |
41c594ab | 1492 | bust_spinlocks(1); |
1da177e4 LT |
1493 | printk("NMI taken!!!!\n"); |
1494 | die("NMI", regs); | |
1da177e4 LT |
1495 | } |
1496 | ||
e01402b1 RB |
1497 | #define VECTORSPACING 0x100 /* for EI/VI mode */ |
1498 | ||
1499 | unsigned long ebase; | |
1da177e4 | 1500 | unsigned long exception_handlers[32]; |
e01402b1 | 1501 | unsigned long vi_handlers[64]; |
1da177e4 | 1502 | |
2d1b6e95 | 1503 | void __init *set_except_vector(int n, void *addr) |
1da177e4 LT |
1504 | { |
1505 | unsigned long handler = (unsigned long) addr; | |
b22d1b6a | 1506 | unsigned long old_handler; |
1da177e4 | 1507 | |
2a0b24f5 SH |
1508 | #ifdef CONFIG_CPU_MICROMIPS |
1509 | /* | |
1510 | * Only the TLB handlers are cache aligned with an even | |
1511 | * address. All other handlers are on an odd address and | |
1512 | * require no modification. Otherwise, MIPS32 mode will | |
1513 | * be entered when handling any TLB exceptions. That | |
1514 | * would be bad...since we must stay in microMIPS mode. | |
1515 | */ | |
1516 | if (!(handler & 0x1)) | |
1517 | handler |= 1; | |
1518 | #endif | |
b22d1b6a | 1519 | old_handler = xchg(&exception_handlers[n], handler); |
1da177e4 | 1520 | |
1da177e4 | 1521 | if (n == 0 && cpu_has_divec) { |
2a0b24f5 SH |
1522 | #ifdef CONFIG_CPU_MICROMIPS |
1523 | unsigned long jump_mask = ~((1 << 27) - 1); | |
1524 | #else | |
92bbe1b9 | 1525 | unsigned long jump_mask = ~((1 << 28) - 1); |
2a0b24f5 | 1526 | #endif |
92bbe1b9 FF |
1527 | u32 *buf = (u32 *)(ebase + 0x200); |
1528 | unsigned int k0 = 26; | |
1529 | if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { | |
1530 | uasm_i_j(&buf, handler & ~jump_mask); | |
1531 | uasm_i_nop(&buf); | |
1532 | } else { | |
1533 | UASM_i_LA(&buf, k0, handler); | |
1534 | uasm_i_jr(&buf, k0); | |
1535 | uasm_i_nop(&buf); | |
1536 | } | |
1537 | local_flush_icache_range(ebase + 0x200, (unsigned long)buf); | |
e01402b1 RB |
1538 | } |
1539 | return (void *)old_handler; | |
1540 | } | |
1541 | ||
86a1708a | 1542 | static void do_default_vi(void) |
6ba07e59 AN |
1543 | { |
1544 | show_regs(get_irq_regs()); | |
1545 | panic("Caught unexpected vectored interrupt."); | |
1546 | } | |
1547 | ||
ef300e42 | 1548 | static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) |
e01402b1 RB |
1549 | { |
1550 | unsigned long handler; | |
1551 | unsigned long old_handler = vi_handlers[n]; | |
f6771dbb | 1552 | int srssets = current_cpu_data.srsets; |
2a0b24f5 | 1553 | u16 *h; |
e01402b1 RB |
1554 | unsigned char *b; |
1555 | ||
b72b7092 | 1556 | BUG_ON(!cpu_has_veic && !cpu_has_vint); |
2a0b24f5 | 1557 | BUG_ON((n < 0) && (n > 9)); |
e01402b1 RB |
1558 | |
1559 | if (addr == NULL) { | |
1560 | handler = (unsigned long) do_default_vi; | |
1561 | srs = 0; | |
41c594ab | 1562 | } else |
e01402b1 | 1563 | handler = (unsigned long) addr; |
2a0b24f5 | 1564 | vi_handlers[n] = handler; |
e01402b1 RB |
1565 | |
1566 | b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); | |
1567 | ||
f6771dbb | 1568 | if (srs >= srssets) |
e01402b1 RB |
1569 | panic("Shadow register set %d not supported", srs); |
1570 | ||
1571 | if (cpu_has_veic) { | |
1572 | if (board_bind_eic_interrupt) | |
49a89efb | 1573 | board_bind_eic_interrupt(n, srs); |
41c594ab | 1574 | } else if (cpu_has_vint) { |
e01402b1 | 1575 | /* SRSMap is only defined if shadow sets are implemented */ |
f6771dbb | 1576 | if (srssets > 1) |
49a89efb | 1577 | change_c0_srsmap(0xf << n*4, srs << n*4); |
e01402b1 RB |
1578 | } |
1579 | ||
1580 | if (srs == 0) { | |
1581 | /* | |
1582 | * If no shadow set is selected then use the default handler | |
2a0b24f5 | 1583 | * that does normal register saving and standard interrupt exit |
e01402b1 | 1584 | */ |
e01402b1 RB |
1585 | extern char except_vec_vi, except_vec_vi_lui; |
1586 | extern char except_vec_vi_ori, except_vec_vi_end; | |
c65a5480 | 1587 | extern char rollback_except_vec_vi; |
f94d9a8e | 1588 | char *vec_start = using_rollback_handler() ? |
c65a5480 | 1589 | &rollback_except_vec_vi : &except_vec_vi; |
41c594ab RB |
1590 | #ifdef CONFIG_MIPS_MT_SMTC |
1591 | /* | |
1592 | * We need to provide the SMTC vectored interrupt handler | |
1593 | * not only with the address of the handler, but with the | |
1594 | * Status.IM bit to be masked before going there. | |
1595 | */ | |
1596 | extern char except_vec_vi_mori; | |
2a0b24f5 SH |
1597 | #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) |
1598 | const int mori_offset = &except_vec_vi_mori - vec_start + 2; | |
1599 | #else | |
c65a5480 | 1600 | const int mori_offset = &except_vec_vi_mori - vec_start; |
2a0b24f5 | 1601 | #endif |
41c594ab | 1602 | #endif /* CONFIG_MIPS_MT_SMTC */ |
2a0b24f5 SH |
1603 | #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) |
1604 | const int lui_offset = &except_vec_vi_lui - vec_start + 2; | |
1605 | const int ori_offset = &except_vec_vi_ori - vec_start + 2; | |
1606 | #else | |
c65a5480 AN |
1607 | const int lui_offset = &except_vec_vi_lui - vec_start; |
1608 | const int ori_offset = &except_vec_vi_ori - vec_start; | |
2a0b24f5 SH |
1609 | #endif |
1610 | const int handler_len = &except_vec_vi_end - vec_start; | |
e01402b1 RB |
1611 | |
1612 | if (handler_len > VECTORSPACING) { | |
1613 | /* | |
1614 | * Sigh... panicing won't help as the console | |
1615 | * is probably not configured :( | |
1616 | */ | |
49a89efb | 1617 | panic("VECTORSPACING too small"); |
e01402b1 RB |
1618 | } |
1619 | ||
2a0b24f5 SH |
1620 | set_handler(((unsigned long)b - ebase), vec_start, |
1621 | #ifdef CONFIG_CPU_MICROMIPS | |
1622 | (handler_len - 1)); | |
1623 | #else | |
1624 | handler_len); | |
1625 | #endif | |
41c594ab | 1626 | #ifdef CONFIG_MIPS_MT_SMTC |
8e8a52ed RB |
1627 | BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ |
1628 | ||
2a0b24f5 SH |
1629 | h = (u16 *)(b + mori_offset); |
1630 | *h = (0x100 << n); | |
41c594ab | 1631 | #endif /* CONFIG_MIPS_MT_SMTC */ |
2a0b24f5 SH |
1632 | h = (u16 *)(b + lui_offset); |
1633 | *h = (handler >> 16) & 0xffff; | |
1634 | h = (u16 *)(b + ori_offset); | |
1635 | *h = (handler & 0xffff); | |
e0cee3ee TB |
1636 | local_flush_icache_range((unsigned long)b, |
1637 | (unsigned long)(b+handler_len)); | |
e01402b1 RB |
1638 | } |
1639 | else { | |
1640 | /* | |
2a0b24f5 SH |
1641 | * In other cases jump directly to the interrupt handler. It |
1642 | * is the handler's responsibility to save registers if required | |
1643 | * (eg hi/lo) and return from the exception using "eret". | |
e01402b1 | 1644 | */ |
2a0b24f5 SH |
1645 | u32 insn; |
1646 | ||
1647 | h = (u16 *)b; | |
1648 | /* j handler */ | |
1649 | #ifdef CONFIG_CPU_MICROMIPS | |
1650 | insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1); | |
1651 | #else | |
1652 | insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2); | |
1653 | #endif | |
1654 | h[0] = (insn >> 16) & 0xffff; | |
1655 | h[1] = insn & 0xffff; | |
1656 | h[2] = 0; | |
1657 | h[3] = 0; | |
e0cee3ee TB |
1658 | local_flush_icache_range((unsigned long)b, |
1659 | (unsigned long)(b+8)); | |
1da177e4 | 1660 | } |
e01402b1 | 1661 | |
1da177e4 LT |
1662 | return (void *)old_handler; |
1663 | } | |
1664 | ||
ef300e42 | 1665 | void *set_vi_handler(int n, vi_handler_t addr) |
e01402b1 | 1666 | { |
ff3eab2a | 1667 | return set_vi_srs_handler(n, addr, 0); |
e01402b1 | 1668 | } |
f41ae0b2 | 1669 | |
1da177e4 LT |
1670 | extern void tlb_init(void); |
1671 | ||
42f77542 RB |
1672 | /* |
1673 | * Timer interrupt | |
1674 | */ | |
1675 | int cp0_compare_irq; | |
68b6352c | 1676 | EXPORT_SYMBOL_GPL(cp0_compare_irq); |
010c108d | 1677 | int cp0_compare_irq_shift; |
42f77542 RB |
1678 | |
1679 | /* | |
1680 | * Performance counter IRQ or -1 if shared with timer | |
1681 | */ | |
1682 | int cp0_perfcount_irq; | |
1683 | EXPORT_SYMBOL_GPL(cp0_perfcount_irq); | |
1684 | ||
bdc94eb4 CD |
1685 | static int __cpuinitdata noulri; |
1686 | ||
1687 | static int __init ulri_disable(char *s) | |
1688 | { | |
1689 | pr_info("Disabling ulri\n"); | |
1690 | noulri = 1; | |
1691 | ||
1692 | return 1; | |
1693 | } | |
1694 | __setup("noulri", ulri_disable); | |
1695 | ||
6650df3c | 1696 | void __cpuinit per_cpu_trap_init(bool is_boot_cpu) |
1da177e4 LT |
1697 | { |
1698 | unsigned int cpu = smp_processor_id(); | |
1699 | unsigned int status_set = ST0_CU0; | |
18d693b3 | 1700 | unsigned int hwrena = cpu_hwrena_impl_bits; |
41c594ab RB |
1701 | #ifdef CONFIG_MIPS_MT_SMTC |
1702 | int secondaryTC = 0; | |
1703 | int bootTC = (cpu == 0); | |
1704 | ||
1705 | /* | |
1706 | * Only do per_cpu_trap_init() for first TC of Each VPE. | |
1707 | * Note that this hack assumes that the SMTC init code | |
1708 | * assigns TCs consecutively and in ascending order. | |
1709 | */ | |
1710 | ||
1711 | if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && | |
1712 | ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) | |
1713 | secondaryTC = 1; | |
1714 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
1715 | |
1716 | /* | |
1717 | * Disable coprocessors and select 32-bit or 64-bit addressing | |
1718 | * and the 16/32 or 32/32 FPR register model. Reset the BEV | |
1719 | * flag that some firmware may have left set and the TS bit (for | |
1720 | * IP27). Set XX for ISA IV code to work. | |
1721 | */ | |
875d43e7 | 1722 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1723 | status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; |
1724 | #endif | |
adb37892 | 1725 | if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV) |
1da177e4 | 1726 | status_set |= ST0_XX; |
bbaf238b CD |
1727 | if (cpu_has_dsp) |
1728 | status_set |= ST0_MX; | |
1729 | ||
b38c7399 | 1730 | change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, |
1da177e4 LT |
1731 | status_set); |
1732 | ||
18d693b3 KC |
1733 | if (cpu_has_mips_r2) |
1734 | hwrena |= 0x0000000f; | |
a3692020 | 1735 | |
18d693b3 KC |
1736 | if (!noulri && cpu_has_userlocal) |
1737 | hwrena |= (1 << 29); | |
a3692020 | 1738 | |
18d693b3 KC |
1739 | if (hwrena) |
1740 | write_c0_hwrena(hwrena); | |
e01402b1 | 1741 | |
41c594ab RB |
1742 | #ifdef CONFIG_MIPS_MT_SMTC |
1743 | if (!secondaryTC) { | |
1744 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1745 | ||
e01402b1 | 1746 | if (cpu_has_veic || cpu_has_vint) { |
9fb4c2b9 | 1747 | unsigned long sr = set_c0_status(ST0_BEV); |
49a89efb | 1748 | write_c0_ebase(ebase); |
9fb4c2b9 | 1749 | write_c0_status(sr); |
e01402b1 | 1750 | /* Setting vector spacing enables EI/VI mode */ |
49a89efb | 1751 | change_c0_intctl(0x3e0, VECTORSPACING); |
e01402b1 | 1752 | } |
d03d0a57 RB |
1753 | if (cpu_has_divec) { |
1754 | if (cpu_has_mipsmt) { | |
1755 | unsigned int vpflags = dvpe(); | |
1756 | set_c0_cause(CAUSEF_IV); | |
1757 | evpe(vpflags); | |
1758 | } else | |
1759 | set_c0_cause(CAUSEF_IV); | |
1760 | } | |
3b1d4ed5 RB |
1761 | |
1762 | /* | |
1763 | * Before R2 both interrupt numbers were fixed to 7, so on R2 only: | |
1764 | * | |
1765 | * o read IntCtl.IPTI to determine the timer interrupt | |
1766 | * o read IntCtl.IPPCI to determine the performance counter interrupt | |
1767 | */ | |
1768 | if (cpu_has_mips_r2) { | |
010c108d DV |
1769 | cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; |
1770 | cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; | |
1771 | cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; | |
c3e838a2 | 1772 | if (cp0_perfcount_irq == cp0_compare_irq) |
3b1d4ed5 | 1773 | cp0_perfcount_irq = -1; |
c3e838a2 CD |
1774 | } else { |
1775 | cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; | |
c6a4ebb9 | 1776 | cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ; |
c3e838a2 | 1777 | cp0_perfcount_irq = -1; |
3b1d4ed5 RB |
1778 | } |
1779 | ||
41c594ab RB |
1780 | #ifdef CONFIG_MIPS_MT_SMTC |
1781 | } | |
1782 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 | 1783 | |
48c4ac97 DD |
1784 | if (!cpu_data[cpu].asid_cache) |
1785 | cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; | |
1da177e4 LT |
1786 | |
1787 | atomic_inc(&init_mm.mm_count); | |
1788 | current->active_mm = &init_mm; | |
1789 | BUG_ON(current->mm); | |
1790 | enter_lazy_tlb(&init_mm, current); | |
1791 | ||
41c594ab RB |
1792 | #ifdef CONFIG_MIPS_MT_SMTC |
1793 | if (bootTC) { | |
1794 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
6650df3c DD |
1795 | /* Boot CPU's cache setup in setup_arch(). */ |
1796 | if (!is_boot_cpu) | |
1797 | cpu_cache_init(); | |
41c594ab RB |
1798 | tlb_init(); |
1799 | #ifdef CONFIG_MIPS_MT_SMTC | |
6a05888d RB |
1800 | } else if (!secondaryTC) { |
1801 | /* | |
1802 | * First TC in non-boot VPE must do subset of tlb_init() | |
1803 | * for MMU countrol registers. | |
1804 | */ | |
1805 | write_c0_pagemask(PM_DEFAULT_MASK); | |
1806 | write_c0_wired(0); | |
41c594ab RB |
1807 | } |
1808 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
3d8bfdd0 | 1809 | TLBMISS_HANDLER_SETUP(); |
1da177e4 LT |
1810 | } |
1811 | ||
e01402b1 | 1812 | /* Install CPU exception handler */ |
e3dc81f2 | 1813 | void __cpuinit set_handler(unsigned long offset, void *addr, unsigned long size) |
e01402b1 | 1814 | { |
2a0b24f5 SH |
1815 | #ifdef CONFIG_CPU_MICROMIPS |
1816 | memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size); | |
1817 | #else | |
e01402b1 | 1818 | memcpy((void *)(ebase + offset), addr, size); |
2a0b24f5 | 1819 | #endif |
e0cee3ee | 1820 | local_flush_icache_range(ebase + offset, ebase + offset + size); |
e01402b1 RB |
1821 | } |
1822 | ||
234fcd14 | 1823 | static char panic_null_cerr[] __cpuinitdata = |
641e97f3 RB |
1824 | "Trying to set NULL cache error exception handler"; |
1825 | ||
42fe7ee3 RB |
1826 | /* |
1827 | * Install uncached CPU exception handler. | |
1828 | * This is suitable only for the cache error exception which is the only | |
1829 | * exception handler that is being run uncached. | |
1830 | */ | |
234fcd14 RB |
1831 | void __cpuinit set_uncached_handler(unsigned long offset, void *addr, |
1832 | unsigned long size) | |
e01402b1 | 1833 | { |
4f81b01a | 1834 | unsigned long uncached_ebase = CKSEG1ADDR(ebase); |
e01402b1 | 1835 | |
641e97f3 RB |
1836 | if (!addr) |
1837 | panic(panic_null_cerr); | |
1838 | ||
e01402b1 RB |
1839 | memcpy((void *)(uncached_ebase + offset), addr, size); |
1840 | } | |
1841 | ||
5b10496b AN |
1842 | static int __initdata rdhwr_noopt; |
1843 | static int __init set_rdhwr_noopt(char *str) | |
1844 | { | |
1845 | rdhwr_noopt = 1; | |
1846 | return 1; | |
1847 | } | |
1848 | ||
1849 | __setup("rdhwr_noopt", set_rdhwr_noopt); | |
1850 | ||
1da177e4 LT |
1851 | void __init trap_init(void) |
1852 | { | |
2a0b24f5 | 1853 | extern char except_vec3_generic; |
1da177e4 | 1854 | extern char except_vec4; |
2a0b24f5 | 1855 | extern char except_vec3_r4000; |
1da177e4 | 1856 | unsigned long i; |
c65a5480 AN |
1857 | |
1858 | check_wait(); | |
1da177e4 | 1859 | |
88547001 JW |
1860 | #if defined(CONFIG_KGDB) |
1861 | if (kgdb_early_setup) | |
70342287 | 1862 | return; /* Already done */ |
88547001 JW |
1863 | #endif |
1864 | ||
9fb4c2b9 CD |
1865 | if (cpu_has_veic || cpu_has_vint) { |
1866 | unsigned long size = 0x200 + VECTORSPACING*64; | |
1867 | ebase = (unsigned long) | |
1868 | __alloc_bootmem(size, 1 << fls(size), 0); | |
1869 | } else { | |
9843b030 SL |
1870 | #ifdef CONFIG_KVM_GUEST |
1871 | #define KVM_GUEST_KSEG0 0x40000000 | |
1872 | ebase = KVM_GUEST_KSEG0; | |
1873 | #else | |
1874 | ebase = CKSEG0; | |
1875 | #endif | |
566f74f6 DD |
1876 | if (cpu_has_mips_r2) |
1877 | ebase += (read_c0_ebase() & 0x3ffff000); | |
1878 | } | |
e01402b1 | 1879 | |
c6213c6c SH |
1880 | if (cpu_has_mmips) { |
1881 | unsigned int config3 = read_c0_config3(); | |
1882 | ||
1883 | if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) | |
1884 | write_c0_config3(config3 | MIPS_CONF3_ISA_OE); | |
1885 | else | |
1886 | write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE); | |
1887 | } | |
1888 | ||
6fb97eff KC |
1889 | if (board_ebase_setup) |
1890 | board_ebase_setup(); | |
6650df3c | 1891 | per_cpu_trap_init(true); |
1da177e4 LT |
1892 | |
1893 | /* | |
1894 | * Copy the generic exception handlers to their final destination. | |
1895 | * This will be overriden later as suitable for a particular | |
1896 | * configuration. | |
1897 | */ | |
e01402b1 | 1898 | set_handler(0x180, &except_vec3_generic, 0x80); |
1da177e4 LT |
1899 | |
1900 | /* | |
1901 | * Setup default vectors | |
1902 | */ | |
1903 | for (i = 0; i <= 31; i++) | |
1904 | set_except_vector(i, handle_reserved); | |
1905 | ||
1906 | /* | |
1907 | * Copy the EJTAG debug exception vector handler code to it's final | |
1908 | * destination. | |
1909 | */ | |
e01402b1 | 1910 | if (cpu_has_ejtag && board_ejtag_handler_setup) |
49a89efb | 1911 | board_ejtag_handler_setup(); |
1da177e4 LT |
1912 | |
1913 | /* | |
1914 | * Only some CPUs have the watch exceptions. | |
1915 | */ | |
1916 | if (cpu_has_watch) | |
1917 | set_except_vector(23, handle_watch); | |
1918 | ||
1919 | /* | |
e01402b1 | 1920 | * Initialise interrupt handlers |
1da177e4 | 1921 | */ |
e01402b1 RB |
1922 | if (cpu_has_veic || cpu_has_vint) { |
1923 | int nvec = cpu_has_veic ? 64 : 8; | |
1924 | for (i = 0; i < nvec; i++) | |
ff3eab2a | 1925 | set_vi_handler(i, NULL); |
e01402b1 RB |
1926 | } |
1927 | else if (cpu_has_divec) | |
1928 | set_handler(0x200, &except_vec4, 0x8); | |
1da177e4 LT |
1929 | |
1930 | /* | |
1931 | * Some CPUs can enable/disable for cache parity detection, but does | |
1932 | * it different ways. | |
1933 | */ | |
1934 | parity_protection_init(); | |
1935 | ||
1936 | /* | |
1937 | * The Data Bus Errors / Instruction Bus Errors are signaled | |
1938 | * by external hardware. Therefore these two exceptions | |
1939 | * may have board specific handlers. | |
1940 | */ | |
1941 | if (board_be_init) | |
1942 | board_be_init(); | |
1943 | ||
f94d9a8e RB |
1944 | set_except_vector(0, using_rollback_handler() ? rollback_handle_int |
1945 | : handle_int); | |
1da177e4 LT |
1946 | set_except_vector(1, handle_tlbm); |
1947 | set_except_vector(2, handle_tlbl); | |
1948 | set_except_vector(3, handle_tlbs); | |
1949 | ||
1950 | set_except_vector(4, handle_adel); | |
1951 | set_except_vector(5, handle_ades); | |
1952 | ||
1953 | set_except_vector(6, handle_ibe); | |
1954 | set_except_vector(7, handle_dbe); | |
1955 | ||
1956 | set_except_vector(8, handle_sys); | |
1957 | set_except_vector(9, handle_bp); | |
5b10496b AN |
1958 | set_except_vector(10, rdhwr_noopt ? handle_ri : |
1959 | (cpu_has_vtag_icache ? | |
1960 | handle_ri_rdhwr_vivt : handle_ri_rdhwr)); | |
1da177e4 LT |
1961 | set_except_vector(11, handle_cpu); |
1962 | set_except_vector(12, handle_ov); | |
1963 | set_except_vector(13, handle_tr); | |
1da177e4 | 1964 | |
10cc3529 RB |
1965 | if (current_cpu_type() == CPU_R6000 || |
1966 | current_cpu_type() == CPU_R6000A) { | |
1da177e4 LT |
1967 | /* |
1968 | * The R6000 is the only R-series CPU that features a machine | |
1969 | * check exception (similar to the R4000 cache error) and | |
1970 | * unaligned ldc1/sdc1 exception. The handlers have not been | |
70342287 | 1971 | * written yet. Well, anyway there is no R6000 machine on the |
1da177e4 LT |
1972 | * current list of targets for Linux/MIPS. |
1973 | * (Duh, crap, there is someone with a triple R6k machine) | |
1974 | */ | |
1975 | //set_except_vector(14, handle_mc); | |
1976 | //set_except_vector(15, handle_ndc); | |
1977 | } | |
1978 | ||
e01402b1 RB |
1979 | |
1980 | if (board_nmi_handler_setup) | |
1981 | board_nmi_handler_setup(); | |
1982 | ||
e50c0a8f RB |
1983 | if (cpu_has_fpu && !cpu_has_nofpuex) |
1984 | set_except_vector(15, handle_fpe); | |
1985 | ||
1986 | set_except_vector(22, handle_mdmx); | |
1987 | ||
1988 | if (cpu_has_mcheck) | |
1989 | set_except_vector(24, handle_mcheck); | |
1990 | ||
340ee4b9 RB |
1991 | if (cpu_has_mipsmt) |
1992 | set_except_vector(25, handle_mt); | |
1993 | ||
acaec427 | 1994 | set_except_vector(26, handle_dsp); |
e50c0a8f | 1995 | |
fcbf1dfd DD |
1996 | if (board_cache_error_setup) |
1997 | board_cache_error_setup(); | |
1998 | ||
e50c0a8f RB |
1999 | if (cpu_has_vce) |
2000 | /* Special exception: R4[04]00 uses also the divec space. */ | |
2a0b24f5 | 2001 | set_handler(0x180, &except_vec3_r4000, 0x100); |
e50c0a8f | 2002 | else if (cpu_has_4kex) |
2a0b24f5 | 2003 | set_handler(0x180, &except_vec3_generic, 0x80); |
e50c0a8f | 2004 | else |
2a0b24f5 | 2005 | set_handler(0x080, &except_vec3_generic, 0x80); |
e50c0a8f | 2006 | |
e0cee3ee | 2007 | local_flush_icache_range(ebase, ebase + 0x400); |
0510617b TB |
2008 | |
2009 | sort_extable(__start___dbe_table, __stop___dbe_table); | |
69f3a7de | 2010 | |
4483b159 | 2011 | cu2_notifier(default_cu2_call, 0x80000000); /* Run last */ |
1da177e4 | 2012 | } |