Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
36ccf1c0 | 6 | * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle |
1da177e4 LT |
7 | * Copyright (C) 1995, 1996 Paul M. Antoine |
8 | * Copyright (C) 1998 Ulf Carlsson | |
9 | * Copyright (C) 1999 Silicon Graphics, Inc. | |
10 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
60b0d655 | 11 | * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki |
2a0b24f5 | 12 | * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved. |
b08a9c95 | 13 | * Copyright (C) 2014, Imagination Technologies Ltd. |
1da177e4 | 14 | */ |
8e8a52ed | 15 | #include <linux/bug.h> |
60b0d655 | 16 | #include <linux/compiler.h> |
c3fc5cd5 | 17 | #include <linux/context_tracking.h> |
7aa1c8f4 | 18 | #include <linux/kexec.h> |
1da177e4 | 19 | #include <linux/init.h> |
8742cd23 | 20 | #include <linux/kernel.h> |
f9ded569 | 21 | #include <linux/module.h> |
1da177e4 | 22 | #include <linux/mm.h> |
1da177e4 LT |
23 | #include <linux/sched.h> |
24 | #include <linux/smp.h> | |
1da177e4 LT |
25 | #include <linux/spinlock.h> |
26 | #include <linux/kallsyms.h> | |
e01402b1 | 27 | #include <linux/bootmem.h> |
d4fd1989 | 28 | #include <linux/interrupt.h> |
39b8d525 | 29 | #include <linux/ptrace.h> |
88547001 JW |
30 | #include <linux/kgdb.h> |
31 | #include <linux/kdebug.h> | |
c1bf207d | 32 | #include <linux/kprobes.h> |
69f3a7de | 33 | #include <linux/notifier.h> |
5dd11d5d | 34 | #include <linux/kdb.h> |
ca4d3e67 | 35 | #include <linux/irq.h> |
7f788d2d | 36 | #include <linux/perf_event.h> |
1da177e4 LT |
37 | |
38 | #include <asm/bootinfo.h> | |
39 | #include <asm/branch.h> | |
40 | #include <asm/break.h> | |
69f3a7de | 41 | #include <asm/cop2.h> |
1da177e4 | 42 | #include <asm/cpu.h> |
69f24d17 | 43 | #include <asm/cpu-type.h> |
e50c0a8f | 44 | #include <asm/dsp.h> |
1da177e4 | 45 | #include <asm/fpu.h> |
ba3049ed | 46 | #include <asm/fpu_emulator.h> |
bdc92d74 | 47 | #include <asm/idle.h> |
340ee4b9 RB |
48 | #include <asm/mipsregs.h> |
49 | #include <asm/mipsmtregs.h> | |
1da177e4 | 50 | #include <asm/module.h> |
1db1af84 | 51 | #include <asm/msa.h> |
1da177e4 LT |
52 | #include <asm/pgtable.h> |
53 | #include <asm/ptrace.h> | |
54 | #include <asm/sections.h> | |
1da177e4 LT |
55 | #include <asm/tlbdebug.h> |
56 | #include <asm/traps.h> | |
57 | #include <asm/uaccess.h> | |
b67b2b70 | 58 | #include <asm/watch.h> |
1da177e4 | 59 | #include <asm/mmu_context.h> |
1da177e4 | 60 | #include <asm/types.h> |
1df0f0ff | 61 | #include <asm/stacktrace.h> |
92bbe1b9 | 62 | #include <asm/uasm.h> |
1da177e4 | 63 | |
c65a5480 | 64 | extern void check_wait(void); |
c65a5480 | 65 | extern asmlinkage void rollback_handle_int(void); |
e4ac58af | 66 | extern asmlinkage void handle_int(void); |
86a1708a RB |
67 | extern u32 handle_tlbl[]; |
68 | extern u32 handle_tlbs[]; | |
69 | extern u32 handle_tlbm[]; | |
1da177e4 LT |
70 | extern asmlinkage void handle_adel(void); |
71 | extern asmlinkage void handle_ades(void); | |
72 | extern asmlinkage void handle_ibe(void); | |
73 | extern asmlinkage void handle_dbe(void); | |
74 | extern asmlinkage void handle_sys(void); | |
75 | extern asmlinkage void handle_bp(void); | |
76 | extern asmlinkage void handle_ri(void); | |
5b10496b AN |
77 | extern asmlinkage void handle_ri_rdhwr_vivt(void); |
78 | extern asmlinkage void handle_ri_rdhwr(void); | |
1da177e4 LT |
79 | extern asmlinkage void handle_cpu(void); |
80 | extern asmlinkage void handle_ov(void); | |
81 | extern asmlinkage void handle_tr(void); | |
2bcb3fbc | 82 | extern asmlinkage void handle_msa_fpe(void); |
1da177e4 | 83 | extern asmlinkage void handle_fpe(void); |
75b5b5e0 | 84 | extern asmlinkage void handle_ftlb(void); |
1db1af84 | 85 | extern asmlinkage void handle_msa(void); |
1da177e4 LT |
86 | extern asmlinkage void handle_mdmx(void); |
87 | extern asmlinkage void handle_watch(void); | |
340ee4b9 | 88 | extern asmlinkage void handle_mt(void); |
e50c0a8f | 89 | extern asmlinkage void handle_dsp(void); |
1da177e4 LT |
90 | extern asmlinkage void handle_mcheck(void); |
91 | extern asmlinkage void handle_reserved(void); | |
92 | ||
1da177e4 LT |
93 | void (*board_be_init)(void); |
94 | int (*board_be_handler)(struct pt_regs *regs, int is_fixup); | |
e01402b1 RB |
95 | void (*board_nmi_handler_setup)(void); |
96 | void (*board_ejtag_handler_setup)(void); | |
97 | void (*board_bind_eic_interrupt)(int irq, int regset); | |
6fb97eff | 98 | void (*board_ebase_setup)(void); |
078a55fc | 99 | void(*board_cache_error_setup)(void); |
1da177e4 | 100 | |
4d157d5e | 101 | static void show_raw_backtrace(unsigned long reg29) |
e889d78f | 102 | { |
39b8d525 | 103 | unsigned long *sp = (unsigned long *)(reg29 & ~3); |
e889d78f AN |
104 | unsigned long addr; |
105 | ||
106 | printk("Call Trace:"); | |
107 | #ifdef CONFIG_KALLSYMS | |
108 | printk("\n"); | |
109 | #endif | |
10220c88 TB |
110 | while (!kstack_end(sp)) { |
111 | unsigned long __user *p = | |
112 | (unsigned long __user *)(unsigned long)sp++; | |
113 | if (__get_user(addr, p)) { | |
114 | printk(" (Bad stack address)"); | |
115 | break; | |
39b8d525 | 116 | } |
10220c88 TB |
117 | if (__kernel_text_address(addr)) |
118 | print_ip_sym(addr); | |
e889d78f | 119 | } |
10220c88 | 120 | printk("\n"); |
e889d78f AN |
121 | } |
122 | ||
f66686f7 | 123 | #ifdef CONFIG_KALLSYMS |
1df0f0ff | 124 | int raw_show_trace; |
f66686f7 AN |
125 | static int __init set_raw_show_trace(char *str) |
126 | { | |
127 | raw_show_trace = 1; | |
128 | return 1; | |
129 | } | |
130 | __setup("raw_show_trace", set_raw_show_trace); | |
1df0f0ff | 131 | #endif |
4d157d5e | 132 | |
eae23f2c | 133 | static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) |
f66686f7 | 134 | { |
4d157d5e FBH |
135 | unsigned long sp = regs->regs[29]; |
136 | unsigned long ra = regs->regs[31]; | |
f66686f7 | 137 | unsigned long pc = regs->cp0_epc; |
f66686f7 | 138 | |
e909be82 VW |
139 | if (!task) |
140 | task = current; | |
141 | ||
f66686f7 | 142 | if (raw_show_trace || !__kernel_text_address(pc)) { |
87151ae3 | 143 | show_raw_backtrace(sp); |
f66686f7 AN |
144 | return; |
145 | } | |
146 | printk("Call Trace:\n"); | |
4d157d5e | 147 | do { |
87151ae3 | 148 | print_ip_sym(pc); |
1924600c | 149 | pc = unwind_stack(task, &sp, pc, &ra); |
4d157d5e | 150 | } while (pc); |
f66686f7 AN |
151 | printk("\n"); |
152 | } | |
f66686f7 | 153 | |
1da177e4 LT |
154 | /* |
155 | * This routine abuses get_user()/put_user() to reference pointers | |
156 | * with at least a bit of error checking ... | |
157 | */ | |
eae23f2c RB |
158 | static void show_stacktrace(struct task_struct *task, |
159 | const struct pt_regs *regs) | |
1da177e4 LT |
160 | { |
161 | const int field = 2 * sizeof(unsigned long); | |
162 | long stackdata; | |
163 | int i; | |
5e0373b8 | 164 | unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; |
1da177e4 LT |
165 | |
166 | printk("Stack :"); | |
167 | i = 0; | |
168 | while ((unsigned long) sp & (PAGE_SIZE - 1)) { | |
169 | if (i && ((i % (64 / field)) == 0)) | |
70342287 | 170 | printk("\n "); |
1da177e4 LT |
171 | if (i > 39) { |
172 | printk(" ..."); | |
173 | break; | |
174 | } | |
175 | ||
176 | if (__get_user(stackdata, sp++)) { | |
177 | printk(" (Bad stack address)"); | |
178 | break; | |
179 | } | |
180 | ||
181 | printk(" %0*lx", field, stackdata); | |
182 | i++; | |
183 | } | |
184 | printk("\n"); | |
87151ae3 | 185 | show_backtrace(task, regs); |
f66686f7 AN |
186 | } |
187 | ||
f66686f7 AN |
188 | void show_stack(struct task_struct *task, unsigned long *sp) |
189 | { | |
190 | struct pt_regs regs; | |
191 | if (sp) { | |
192 | regs.regs[29] = (unsigned long)sp; | |
193 | regs.regs[31] = 0; | |
194 | regs.cp0_epc = 0; | |
195 | } else { | |
196 | if (task && task != current) { | |
197 | regs.regs[29] = task->thread.reg29; | |
198 | regs.regs[31] = 0; | |
199 | regs.cp0_epc = task->thread.reg31; | |
5dd11d5d JW |
200 | #ifdef CONFIG_KGDB_KDB |
201 | } else if (atomic_read(&kgdb_active) != -1 && | |
202 | kdb_current_regs) { | |
203 | memcpy(®s, kdb_current_regs, sizeof(regs)); | |
204 | #endif /* CONFIG_KGDB_KDB */ | |
f66686f7 AN |
205 | } else { |
206 | prepare_frametrace(®s); | |
207 | } | |
208 | } | |
209 | show_stacktrace(task, ®s); | |
1da177e4 LT |
210 | } |
211 | ||
e1bb8289 | 212 | static void show_code(unsigned int __user *pc) |
1da177e4 LT |
213 | { |
214 | long i; | |
39b8d525 | 215 | unsigned short __user *pc16 = NULL; |
1da177e4 LT |
216 | |
217 | printk("\nCode:"); | |
218 | ||
39b8d525 RB |
219 | if ((unsigned long)pc & 1) |
220 | pc16 = (unsigned short __user *)((unsigned long)pc & ~1); | |
1da177e4 LT |
221 | for(i = -3 ; i < 6 ; i++) { |
222 | unsigned int insn; | |
39b8d525 | 223 | if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { |
1da177e4 LT |
224 | printk(" (Bad address in epc)\n"); |
225 | break; | |
226 | } | |
39b8d525 | 227 | printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); |
1da177e4 LT |
228 | } |
229 | } | |
230 | ||
eae23f2c | 231 | static void __show_regs(const struct pt_regs *regs) |
1da177e4 LT |
232 | { |
233 | const int field = 2 * sizeof(unsigned long); | |
234 | unsigned int cause = regs->cp0_cause; | |
235 | int i; | |
236 | ||
a43cb95d | 237 | show_regs_print_info(KERN_DEFAULT); |
1da177e4 LT |
238 | |
239 | /* | |
240 | * Saved main processor registers | |
241 | */ | |
242 | for (i = 0; i < 32; ) { | |
243 | if ((i % 4) == 0) | |
244 | printk("$%2d :", i); | |
245 | if (i == 0) | |
246 | printk(" %0*lx", field, 0UL); | |
247 | else if (i == 26 || i == 27) | |
248 | printk(" %*s", field, ""); | |
249 | else | |
250 | printk(" %0*lx", field, regs->regs[i]); | |
251 | ||
252 | i++; | |
253 | if ((i % 4) == 0) | |
254 | printk("\n"); | |
255 | } | |
256 | ||
9693a853 FBH |
257 | #ifdef CONFIG_CPU_HAS_SMARTMIPS |
258 | printk("Acx : %0*lx\n", field, regs->acx); | |
259 | #endif | |
1da177e4 LT |
260 | printk("Hi : %0*lx\n", field, regs->hi); |
261 | printk("Lo : %0*lx\n", field, regs->lo); | |
262 | ||
263 | /* | |
264 | * Saved cp0 registers | |
265 | */ | |
b012cffe RB |
266 | printk("epc : %0*lx %pS\n", field, regs->cp0_epc, |
267 | (void *) regs->cp0_epc); | |
1da177e4 | 268 | printk(" %s\n", print_tainted()); |
b012cffe RB |
269 | printk("ra : %0*lx %pS\n", field, regs->regs[31], |
270 | (void *) regs->regs[31]); | |
1da177e4 | 271 | |
70342287 | 272 | printk("Status: %08x ", (uint32_t) regs->cp0_status); |
1da177e4 | 273 | |
1990e542 | 274 | if (cpu_has_3kex) { |
3b2396d9 MR |
275 | if (regs->cp0_status & ST0_KUO) |
276 | printk("KUo "); | |
277 | if (regs->cp0_status & ST0_IEO) | |
278 | printk("IEo "); | |
279 | if (regs->cp0_status & ST0_KUP) | |
280 | printk("KUp "); | |
281 | if (regs->cp0_status & ST0_IEP) | |
282 | printk("IEp "); | |
283 | if (regs->cp0_status & ST0_KUC) | |
284 | printk("KUc "); | |
285 | if (regs->cp0_status & ST0_IEC) | |
286 | printk("IEc "); | |
1990e542 | 287 | } else if (cpu_has_4kex) { |
3b2396d9 MR |
288 | if (regs->cp0_status & ST0_KX) |
289 | printk("KX "); | |
290 | if (regs->cp0_status & ST0_SX) | |
291 | printk("SX "); | |
292 | if (regs->cp0_status & ST0_UX) | |
293 | printk("UX "); | |
294 | switch (regs->cp0_status & ST0_KSU) { | |
295 | case KSU_USER: | |
296 | printk("USER "); | |
297 | break; | |
298 | case KSU_SUPERVISOR: | |
299 | printk("SUPERVISOR "); | |
300 | break; | |
301 | case KSU_KERNEL: | |
302 | printk("KERNEL "); | |
303 | break; | |
304 | default: | |
305 | printk("BAD_MODE "); | |
306 | break; | |
307 | } | |
308 | if (regs->cp0_status & ST0_ERL) | |
309 | printk("ERL "); | |
310 | if (regs->cp0_status & ST0_EXL) | |
311 | printk("EXL "); | |
312 | if (regs->cp0_status & ST0_IE) | |
313 | printk("IE "); | |
1da177e4 | 314 | } |
1da177e4 LT |
315 | printk("\n"); |
316 | ||
317 | printk("Cause : %08x\n", cause); | |
318 | ||
319 | cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; | |
320 | if (1 <= cause && cause <= 5) | |
321 | printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); | |
322 | ||
9966db25 RB |
323 | printk("PrId : %08x (%s)\n", read_c0_prid(), |
324 | cpu_name_string()); | |
1da177e4 LT |
325 | } |
326 | ||
eae23f2c RB |
327 | /* |
328 | * FIXME: really the generic show_regs should take a const pointer argument. | |
329 | */ | |
330 | void show_regs(struct pt_regs *regs) | |
331 | { | |
332 | __show_regs((struct pt_regs *)regs); | |
333 | } | |
334 | ||
c1bf207d | 335 | void show_registers(struct pt_regs *regs) |
1da177e4 | 336 | { |
39b8d525 | 337 | const int field = 2 * sizeof(unsigned long); |
83e4da1e | 338 | mm_segment_t old_fs = get_fs(); |
39b8d525 | 339 | |
eae23f2c | 340 | __show_regs(regs); |
1da177e4 | 341 | print_modules(); |
39b8d525 RB |
342 | printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", |
343 | current->comm, current->pid, current_thread_info(), current, | |
344 | field, current_thread_info()->tp_value); | |
345 | if (cpu_has_userlocal) { | |
346 | unsigned long tls; | |
347 | ||
348 | tls = read_c0_userlocal(); | |
349 | if (tls != current_thread_info()->tp_value) | |
350 | printk("*HwTLS: %0*lx\n", field, tls); | |
351 | } | |
352 | ||
83e4da1e LY |
353 | if (!user_mode(regs)) |
354 | /* Necessary for getting the correct stack content */ | |
355 | set_fs(KERNEL_DS); | |
f66686f7 | 356 | show_stacktrace(current, regs); |
e1bb8289 | 357 | show_code((unsigned int __user *) regs->cp0_epc); |
1da177e4 | 358 | printk("\n"); |
83e4da1e | 359 | set_fs(old_fs); |
1da177e4 LT |
360 | } |
361 | ||
70dc6f04 DD |
362 | static int regs_to_trapnr(struct pt_regs *regs) |
363 | { | |
364 | return (regs->cp0_cause >> 2) & 0x1f; | |
365 | } | |
366 | ||
4d85f6af | 367 | static DEFINE_RAW_SPINLOCK(die_lock); |
1da177e4 | 368 | |
70dc6f04 | 369 | void __noreturn die(const char *str, struct pt_regs *regs) |
1da177e4 LT |
370 | { |
371 | static int die_counter; | |
ce384d83 | 372 | int sig = SIGSEGV; |
41c594ab | 373 | #ifdef CONFIG_MIPS_MT_SMTC |
8742cd23 | 374 | unsigned long dvpret; |
41c594ab | 375 | #endif /* CONFIG_MIPS_MT_SMTC */ |
1da177e4 | 376 | |
8742cd23 NL |
377 | oops_enter(); |
378 | ||
dc73e4c1 RB |
379 | if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), |
380 | SIGSEGV) == NOTIFY_STOP) | |
10423c91 | 381 | sig = 0; |
5dd11d5d | 382 | |
1da177e4 | 383 | console_verbose(); |
4d85f6af | 384 | raw_spin_lock_irq(&die_lock); |
8742cd23 NL |
385 | #ifdef CONFIG_MIPS_MT_SMTC |
386 | dvpret = dvpe(); | |
387 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
41c594ab RB |
388 | bust_spinlocks(1); |
389 | #ifdef CONFIG_MIPS_MT_SMTC | |
390 | mips_mt_regdump(dvpret); | |
391 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
ce384d83 | 392 | |
178086c8 | 393 | printk("%s[#%d]:\n", str, ++die_counter); |
1da177e4 | 394 | show_registers(regs); |
373d4d09 | 395 | add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); |
4d85f6af | 396 | raw_spin_unlock_irq(&die_lock); |
d4fd1989 | 397 | |
8742cd23 NL |
398 | oops_exit(); |
399 | ||
d4fd1989 MB |
400 | if (in_interrupt()) |
401 | panic("Fatal exception in interrupt"); | |
402 | ||
403 | if (panic_on_oops) { | |
ab75dc02 | 404 | printk(KERN_EMERG "Fatal exception: panic in 5 seconds"); |
d4fd1989 MB |
405 | ssleep(5); |
406 | panic("Fatal exception"); | |
407 | } | |
408 | ||
7aa1c8f4 RB |
409 | if (regs && kexec_should_crash(current)) |
410 | crash_kexec(regs); | |
411 | ||
ce384d83 | 412 | do_exit(sig); |
1da177e4 LT |
413 | } |
414 | ||
0510617b TB |
415 | extern struct exception_table_entry __start___dbe_table[]; |
416 | extern struct exception_table_entry __stop___dbe_table[]; | |
1da177e4 | 417 | |
b6dcec9b RB |
418 | __asm__( |
419 | " .section __dbe_table, \"a\"\n" | |
420 | " .previous \n"); | |
1da177e4 LT |
421 | |
422 | /* Given an address, look for it in the exception tables. */ | |
423 | static const struct exception_table_entry *search_dbe_tables(unsigned long addr) | |
424 | { | |
425 | const struct exception_table_entry *e; | |
426 | ||
427 | e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); | |
428 | if (!e) | |
429 | e = search_module_dbetables(addr); | |
430 | return e; | |
431 | } | |
432 | ||
433 | asmlinkage void do_be(struct pt_regs *regs) | |
434 | { | |
435 | const int field = 2 * sizeof(unsigned long); | |
436 | const struct exception_table_entry *fixup = NULL; | |
437 | int data = regs->cp0_cause & 4; | |
438 | int action = MIPS_BE_FATAL; | |
c3fc5cd5 | 439 | enum ctx_state prev_state; |
1da177e4 | 440 | |
c3fc5cd5 | 441 | prev_state = exception_enter(); |
70342287 | 442 | /* XXX For now. Fixme, this searches the wrong table ... */ |
1da177e4 LT |
443 | if (data && !user_mode(regs)) |
444 | fixup = search_dbe_tables(exception_epc(regs)); | |
445 | ||
446 | if (fixup) | |
447 | action = MIPS_BE_FIXUP; | |
448 | ||
449 | if (board_be_handler) | |
28fc582c | 450 | action = board_be_handler(regs, fixup != NULL); |
1da177e4 LT |
451 | |
452 | switch (action) { | |
453 | case MIPS_BE_DISCARD: | |
c3fc5cd5 | 454 | goto out; |
1da177e4 LT |
455 | case MIPS_BE_FIXUP: |
456 | if (fixup) { | |
457 | regs->cp0_epc = fixup->nextinsn; | |
c3fc5cd5 | 458 | goto out; |
1da177e4 LT |
459 | } |
460 | break; | |
461 | default: | |
462 | break; | |
463 | } | |
464 | ||
465 | /* | |
466 | * Assume it would be too dangerous to continue ... | |
467 | */ | |
468 | printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", | |
469 | data ? "Data" : "Instruction", | |
470 | field, regs->cp0_epc, field, regs->regs[31]); | |
dc73e4c1 RB |
471 | if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), |
472 | SIGBUS) == NOTIFY_STOP) | |
c3fc5cd5 | 473 | goto out; |
88547001 | 474 | |
1da177e4 LT |
475 | die_if_kernel("Oops", regs); |
476 | force_sig(SIGBUS, current); | |
c3fc5cd5 RB |
477 | |
478 | out: | |
479 | exception_exit(prev_state); | |
1da177e4 LT |
480 | } |
481 | ||
1da177e4 | 482 | /* |
60b0d655 | 483 | * ll/sc, rdhwr, sync emulation |
1da177e4 LT |
484 | */ |
485 | ||
486 | #define OPCODE 0xfc000000 | |
487 | #define BASE 0x03e00000 | |
488 | #define RT 0x001f0000 | |
489 | #define OFFSET 0x0000ffff | |
490 | #define LL 0xc0000000 | |
491 | #define SC 0xe0000000 | |
60b0d655 | 492 | #define SPEC0 0x00000000 |
3c37026d RB |
493 | #define SPEC3 0x7c000000 |
494 | #define RD 0x0000f800 | |
495 | #define FUNC 0x0000003f | |
60b0d655 | 496 | #define SYNC 0x0000000f |
3c37026d | 497 | #define RDHWR 0x0000003b |
1da177e4 | 498 | |
2a0b24f5 SH |
499 | /* microMIPS definitions */ |
500 | #define MM_POOL32A_FUNC 0xfc00ffff | |
501 | #define MM_RDHWR 0x00006b3c | |
502 | #define MM_RS 0x001f0000 | |
503 | #define MM_RT 0x03e00000 | |
504 | ||
1da177e4 LT |
505 | /* |
506 | * The ll_bit is cleared by r*_switch.S | |
507 | */ | |
508 | ||
f1e39a4a RB |
509 | unsigned int ll_bit; |
510 | struct task_struct *ll_task; | |
1da177e4 | 511 | |
60b0d655 | 512 | static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 513 | { |
fe00f943 | 514 | unsigned long value, __user *vaddr; |
1da177e4 | 515 | long offset; |
1da177e4 LT |
516 | |
517 | /* | |
518 | * analyse the ll instruction that just caused a ri exception | |
519 | * and put the referenced address to addr. | |
520 | */ | |
521 | ||
522 | /* sign extend offset */ | |
523 | offset = opcode & OFFSET; | |
524 | offset <<= 16; | |
525 | offset >>= 16; | |
526 | ||
fe00f943 | 527 | vaddr = (unsigned long __user *) |
b9688310 | 528 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); |
1da177e4 | 529 | |
60b0d655 MR |
530 | if ((unsigned long)vaddr & 3) |
531 | return SIGBUS; | |
532 | if (get_user(value, vaddr)) | |
533 | return SIGSEGV; | |
1da177e4 LT |
534 | |
535 | preempt_disable(); | |
536 | ||
537 | if (ll_task == NULL || ll_task == current) { | |
538 | ll_bit = 1; | |
539 | } else { | |
540 | ll_bit = 0; | |
541 | } | |
542 | ll_task = current; | |
543 | ||
544 | preempt_enable(); | |
545 | ||
546 | regs->regs[(opcode & RT) >> 16] = value; | |
547 | ||
60b0d655 | 548 | return 0; |
1da177e4 LT |
549 | } |
550 | ||
60b0d655 | 551 | static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 552 | { |
fe00f943 RB |
553 | unsigned long __user *vaddr; |
554 | unsigned long reg; | |
1da177e4 | 555 | long offset; |
1da177e4 LT |
556 | |
557 | /* | |
558 | * analyse the sc instruction that just caused a ri exception | |
559 | * and put the referenced address to addr. | |
560 | */ | |
561 | ||
562 | /* sign extend offset */ | |
563 | offset = opcode & OFFSET; | |
564 | offset <<= 16; | |
565 | offset >>= 16; | |
566 | ||
fe00f943 | 567 | vaddr = (unsigned long __user *) |
b9688310 | 568 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); |
1da177e4 LT |
569 | reg = (opcode & RT) >> 16; |
570 | ||
60b0d655 MR |
571 | if ((unsigned long)vaddr & 3) |
572 | return SIGBUS; | |
1da177e4 LT |
573 | |
574 | preempt_disable(); | |
575 | ||
576 | if (ll_bit == 0 || ll_task != current) { | |
577 | regs->regs[reg] = 0; | |
578 | preempt_enable(); | |
60b0d655 | 579 | return 0; |
1da177e4 LT |
580 | } |
581 | ||
582 | preempt_enable(); | |
583 | ||
60b0d655 MR |
584 | if (put_user(regs->regs[reg], vaddr)) |
585 | return SIGSEGV; | |
1da177e4 LT |
586 | |
587 | regs->regs[reg] = 1; | |
588 | ||
60b0d655 | 589 | return 0; |
1da177e4 LT |
590 | } |
591 | ||
592 | /* | |
593 | * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both | |
594 | * opcodes are supposed to result in coprocessor unusable exceptions if | |
595 | * executed on ll/sc-less processors. That's the theory. In practice a | |
596 | * few processors such as NEC's VR4100 throw reserved instruction exceptions | |
597 | * instead, so we're doing the emulation thing in both exception handlers. | |
598 | */ | |
60b0d655 | 599 | static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 600 | { |
7f788d2d DCZ |
601 | if ((opcode & OPCODE) == LL) { |
602 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 603 | 1, regs, 0); |
60b0d655 | 604 | return simulate_ll(regs, opcode); |
7f788d2d DCZ |
605 | } |
606 | if ((opcode & OPCODE) == SC) { | |
607 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 608 | 1, regs, 0); |
60b0d655 | 609 | return simulate_sc(regs, opcode); |
7f788d2d | 610 | } |
1da177e4 | 611 | |
60b0d655 | 612 | return -1; /* Must be something else ... */ |
1da177e4 LT |
613 | } |
614 | ||
3c37026d RB |
615 | /* |
616 | * Simulate trapping 'rdhwr' instructions to provide user accessible | |
1f5826bd | 617 | * registers not implemented in hardware. |
3c37026d | 618 | */ |
2a0b24f5 | 619 | static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt) |
3c37026d | 620 | { |
dc8f6029 | 621 | struct thread_info *ti = task_thread_info(current); |
3c37026d | 622 | |
2a0b24f5 SH |
623 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, |
624 | 1, regs, 0); | |
625 | switch (rd) { | |
626 | case 0: /* CPU number */ | |
627 | regs->regs[rt] = smp_processor_id(); | |
628 | return 0; | |
629 | case 1: /* SYNCI length */ | |
630 | regs->regs[rt] = min(current_cpu_data.dcache.linesz, | |
631 | current_cpu_data.icache.linesz); | |
632 | return 0; | |
633 | case 2: /* Read count register */ | |
634 | regs->regs[rt] = read_c0_count(); | |
635 | return 0; | |
636 | case 3: /* Count register resolution */ | |
69f24d17 | 637 | switch (current_cpu_type()) { |
2a0b24f5 SH |
638 | case CPU_20KC: |
639 | case CPU_25KF: | |
640 | regs->regs[rt] = 1; | |
641 | break; | |
642 | default: | |
643 | regs->regs[rt] = 2; | |
644 | } | |
645 | return 0; | |
646 | case 29: | |
647 | regs->regs[rt] = ti->tp_value; | |
648 | return 0; | |
649 | default: | |
650 | return -1; | |
651 | } | |
652 | } | |
653 | ||
654 | static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode) | |
655 | { | |
3c37026d RB |
656 | if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { |
657 | int rd = (opcode & RD) >> 11; | |
658 | int rt = (opcode & RT) >> 16; | |
2a0b24f5 SH |
659 | |
660 | simulate_rdhwr(regs, rd, rt); | |
661 | return 0; | |
662 | } | |
663 | ||
664 | /* Not ours. */ | |
665 | return -1; | |
666 | } | |
667 | ||
668 | static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode) | |
669 | { | |
670 | if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) { | |
671 | int rd = (opcode & MM_RS) >> 16; | |
672 | int rt = (opcode & MM_RT) >> 21; | |
673 | simulate_rdhwr(regs, rd, rt); | |
674 | return 0; | |
3c37026d RB |
675 | } |
676 | ||
56ebd51b | 677 | /* Not ours. */ |
60b0d655 MR |
678 | return -1; |
679 | } | |
e5679882 | 680 | |
60b0d655 MR |
681 | static int simulate_sync(struct pt_regs *regs, unsigned int opcode) |
682 | { | |
7f788d2d DCZ |
683 | if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) { |
684 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 685 | 1, regs, 0); |
60b0d655 | 686 | return 0; |
7f788d2d | 687 | } |
60b0d655 MR |
688 | |
689 | return -1; /* Must be something else ... */ | |
3c37026d RB |
690 | } |
691 | ||
1da177e4 LT |
692 | asmlinkage void do_ov(struct pt_regs *regs) |
693 | { | |
c3fc5cd5 | 694 | enum ctx_state prev_state; |
1da177e4 LT |
695 | siginfo_t info; |
696 | ||
c3fc5cd5 | 697 | prev_state = exception_enter(); |
36ccf1c0 RB |
698 | die_if_kernel("Integer overflow", regs); |
699 | ||
1da177e4 LT |
700 | info.si_code = FPE_INTOVF; |
701 | info.si_signo = SIGFPE; | |
702 | info.si_errno = 0; | |
fe00f943 | 703 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 | 704 | force_sig_info(SIGFPE, &info, current); |
c3fc5cd5 | 705 | exception_exit(prev_state); |
1da177e4 LT |
706 | } |
707 | ||
102cedc3 | 708 | int process_fpemu_return(int sig, void __user *fault_addr) |
515b029d DD |
709 | { |
710 | if (sig == SIGSEGV || sig == SIGBUS) { | |
711 | struct siginfo si = {0}; | |
712 | si.si_addr = fault_addr; | |
713 | si.si_signo = sig; | |
714 | if (sig == SIGSEGV) { | |
715 | if (find_vma(current->mm, (unsigned long)fault_addr)) | |
716 | si.si_code = SEGV_ACCERR; | |
717 | else | |
718 | si.si_code = SEGV_MAPERR; | |
719 | } else { | |
720 | si.si_code = BUS_ADRERR; | |
721 | } | |
722 | force_sig_info(sig, &si, current); | |
723 | return 1; | |
724 | } else if (sig) { | |
725 | force_sig(sig, current); | |
726 | return 1; | |
727 | } else { | |
728 | return 0; | |
729 | } | |
730 | } | |
731 | ||
1da177e4 LT |
732 | /* |
733 | * XXX Delayed fp exceptions when doing a lazy ctx switch XXX | |
734 | */ | |
735 | asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) | |
736 | { | |
c3fc5cd5 | 737 | enum ctx_state prev_state; |
515b029d | 738 | siginfo_t info = {0}; |
948a34cf | 739 | |
c3fc5cd5 | 740 | prev_state = exception_enter(); |
dc73e4c1 RB |
741 | if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), |
742 | SIGFPE) == NOTIFY_STOP) | |
c3fc5cd5 | 743 | goto out; |
57725f9e CD |
744 | die_if_kernel("FP exception in kernel code", regs); |
745 | ||
1da177e4 LT |
746 | if (fcr31 & FPU_CSR_UNI_X) { |
747 | int sig; | |
515b029d | 748 | void __user *fault_addr = NULL; |
1da177e4 | 749 | |
1da177e4 | 750 | /* |
a3dddd56 | 751 | * Unimplemented operation exception. If we've got the full |
1da177e4 LT |
752 | * software emulator on-board, let's use it... |
753 | * | |
754 | * Force FPU to dump state into task/thread context. We're | |
755 | * moving a lot of data here for what is probably a single | |
756 | * instruction, but the alternative is to pre-decode the FP | |
757 | * register operands before invoking the emulator, which seems | |
758 | * a bit extreme for what should be an infrequent event. | |
759 | */ | |
cd21dfcf | 760 | /* Ensure 'resume' not overwrite saved fp context again. */ |
53dc8028 | 761 | lose_fpu(1); |
1da177e4 LT |
762 | |
763 | /* Run the emulator */ | |
515b029d DD |
764 | sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, |
765 | &fault_addr); | |
1da177e4 LT |
766 | |
767 | /* | |
768 | * We can't allow the emulated instruction to leave any of | |
769 | * the cause bit set in $fcr31. | |
770 | */ | |
eae89076 | 771 | current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; |
1da177e4 LT |
772 | |
773 | /* Restore the hardware register state */ | |
70342287 | 774 | own_fpu(1); /* Using the FPU again. */ |
1da177e4 LT |
775 | |
776 | /* If something went wrong, signal */ | |
515b029d | 777 | process_fpemu_return(sig, fault_addr); |
1da177e4 | 778 | |
c3fc5cd5 | 779 | goto out; |
948a34cf TS |
780 | } else if (fcr31 & FPU_CSR_INV_X) |
781 | info.si_code = FPE_FLTINV; | |
782 | else if (fcr31 & FPU_CSR_DIV_X) | |
783 | info.si_code = FPE_FLTDIV; | |
784 | else if (fcr31 & FPU_CSR_OVF_X) | |
785 | info.si_code = FPE_FLTOVF; | |
786 | else if (fcr31 & FPU_CSR_UDF_X) | |
787 | info.si_code = FPE_FLTUND; | |
788 | else if (fcr31 & FPU_CSR_INE_X) | |
789 | info.si_code = FPE_FLTRES; | |
790 | else | |
791 | info.si_code = __SI_FAULT; | |
792 | info.si_signo = SIGFPE; | |
793 | info.si_errno = 0; | |
794 | info.si_addr = (void __user *) regs->cp0_epc; | |
795 | force_sig_info(SIGFPE, &info, current); | |
c3fc5cd5 RB |
796 | |
797 | out: | |
798 | exception_exit(prev_state); | |
1da177e4 LT |
799 | } |
800 | ||
df270051 RB |
801 | static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, |
802 | const char *str) | |
1da177e4 | 803 | { |
1da177e4 | 804 | siginfo_t info; |
df270051 | 805 | char b[40]; |
1da177e4 | 806 | |
5dd11d5d | 807 | #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP |
70dc6f04 | 808 | if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) |
5dd11d5d JW |
809 | return; |
810 | #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ | |
811 | ||
dc73e4c1 RB |
812 | if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), |
813 | SIGTRAP) == NOTIFY_STOP) | |
88547001 JW |
814 | return; |
815 | ||
1da177e4 | 816 | /* |
df270051 RB |
817 | * A short test says that IRIX 5.3 sends SIGTRAP for all trap |
818 | * insns, even for trap and break codes that indicate arithmetic | |
819 | * failures. Weird ... | |
1da177e4 LT |
820 | * But should we continue the brokenness??? --macro |
821 | */ | |
df270051 RB |
822 | switch (code) { |
823 | case BRK_OVERFLOW: | |
824 | case BRK_DIVZERO: | |
825 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); | |
826 | die_if_kernel(b, regs); | |
827 | if (code == BRK_DIVZERO) | |
1da177e4 LT |
828 | info.si_code = FPE_INTDIV; |
829 | else | |
830 | info.si_code = FPE_INTOVF; | |
831 | info.si_signo = SIGFPE; | |
832 | info.si_errno = 0; | |
fe00f943 | 833 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
834 | force_sig_info(SIGFPE, &info, current); |
835 | break; | |
63dc68a8 | 836 | case BRK_BUG: |
df270051 RB |
837 | die_if_kernel("Kernel bug detected", regs); |
838 | force_sig(SIGTRAP, current); | |
63dc68a8 | 839 | break; |
ba3049ed RB |
840 | case BRK_MEMU: |
841 | /* | |
842 | * Address errors may be deliberately induced by the FPU | |
843 | * emulator to retake control of the CPU after executing the | |
844 | * instruction in the delay slot of an emulated branch. | |
845 | * | |
846 | * Terminate if exception was recognized as a delay slot return | |
847 | * otherwise handle as normal. | |
848 | */ | |
849 | if (do_dsemulret(regs)) | |
850 | return; | |
851 | ||
852 | die_if_kernel("Math emu break/trap", regs); | |
853 | force_sig(SIGTRAP, current); | |
854 | break; | |
1da177e4 | 855 | default: |
df270051 RB |
856 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); |
857 | die_if_kernel(b, regs); | |
1da177e4 LT |
858 | force_sig(SIGTRAP, current); |
859 | } | |
df270051 RB |
860 | } |
861 | ||
862 | asmlinkage void do_bp(struct pt_regs *regs) | |
863 | { | |
864 | unsigned int opcode, bcode; | |
c3fc5cd5 | 865 | enum ctx_state prev_state; |
2a0b24f5 SH |
866 | unsigned long epc; |
867 | u16 instr[2]; | |
868 | ||
c3fc5cd5 | 869 | prev_state = exception_enter(); |
2a0b24f5 SH |
870 | if (get_isa16_mode(regs->cp0_epc)) { |
871 | /* Calculate EPC. */ | |
872 | epc = exception_epc(regs); | |
873 | if (cpu_has_mmips) { | |
874 | if ((__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc)) || | |
875 | (__get_user(instr[1], (u16 __user *)msk_isa16_mode(epc + 2))))) | |
876 | goto out_sigsegv; | |
b08a9c95 | 877 | opcode = (instr[0] << 16) | instr[1]; |
2a0b24f5 | 878 | } else { |
b08a9c95 MC |
879 | /* MIPS16e mode */ |
880 | if (__get_user(instr[0], | |
881 | (u16 __user *)msk_isa16_mode(epc))) | |
2a0b24f5 | 882 | goto out_sigsegv; |
b08a9c95 MC |
883 | bcode = (instr[0] >> 6) & 0x3f; |
884 | do_trap_or_bp(regs, bcode, "Break"); | |
885 | goto out; | |
2a0b24f5 SH |
886 | } |
887 | } else { | |
b08a9c95 MC |
888 | if (__get_user(opcode, |
889 | (unsigned int __user *) exception_epc(regs))) | |
2a0b24f5 SH |
890 | goto out_sigsegv; |
891 | } | |
df270051 RB |
892 | |
893 | /* | |
894 | * There is the ancient bug in the MIPS assemblers that the break | |
895 | * code starts left to bit 16 instead to bit 6 in the opcode. | |
896 | * Gas is bug-compatible, but not always, grrr... | |
897 | * We handle both cases with a simple heuristics. --macro | |
898 | */ | |
899 | bcode = ((opcode >> 6) & ((1 << 20) - 1)); | |
900 | if (bcode >= (1 << 10)) | |
901 | bcode >>= 10; | |
902 | ||
c1bf207d DD |
903 | /* |
904 | * notify the kprobe handlers, if instruction is likely to | |
905 | * pertain to them. | |
906 | */ | |
907 | switch (bcode) { | |
908 | case BRK_KPROBE_BP: | |
dc73e4c1 RB |
909 | if (notify_die(DIE_BREAK, "debug", regs, bcode, |
910 | regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) | |
c3fc5cd5 | 911 | goto out; |
c1bf207d DD |
912 | else |
913 | break; | |
914 | case BRK_KPROBE_SSTEPBP: | |
dc73e4c1 RB |
915 | if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, |
916 | regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) | |
c3fc5cd5 | 917 | goto out; |
c1bf207d DD |
918 | else |
919 | break; | |
920 | default: | |
921 | break; | |
922 | } | |
923 | ||
df270051 | 924 | do_trap_or_bp(regs, bcode, "Break"); |
c3fc5cd5 RB |
925 | |
926 | out: | |
927 | exception_exit(prev_state); | |
90fccb13 | 928 | return; |
e5679882 RB |
929 | |
930 | out_sigsegv: | |
931 | force_sig(SIGSEGV, current); | |
c3fc5cd5 | 932 | goto out; |
1da177e4 LT |
933 | } |
934 | ||
935 | asmlinkage void do_tr(struct pt_regs *regs) | |
936 | { | |
a9a6e7a0 | 937 | u32 opcode, tcode = 0; |
c3fc5cd5 | 938 | enum ctx_state prev_state; |
2a0b24f5 | 939 | u16 instr[2]; |
a9a6e7a0 | 940 | unsigned long epc = msk_isa16_mode(exception_epc(regs)); |
1da177e4 | 941 | |
c3fc5cd5 | 942 | prev_state = exception_enter(); |
a9a6e7a0 MR |
943 | if (get_isa16_mode(regs->cp0_epc)) { |
944 | if (__get_user(instr[0], (u16 __user *)(epc + 0)) || | |
945 | __get_user(instr[1], (u16 __user *)(epc + 2))) | |
2a0b24f5 | 946 | goto out_sigsegv; |
a9a6e7a0 MR |
947 | opcode = (instr[0] << 16) | instr[1]; |
948 | /* Immediate versions don't provide a code. */ | |
949 | if (!(opcode & OPCODE)) | |
950 | tcode = (opcode >> 12) & ((1 << 4) - 1); | |
951 | } else { | |
952 | if (__get_user(opcode, (u32 __user *)epc)) | |
953 | goto out_sigsegv; | |
954 | /* Immediate versions don't provide a code. */ | |
955 | if (!(opcode & OPCODE)) | |
956 | tcode = (opcode >> 6) & ((1 << 10) - 1); | |
2a0b24f5 | 957 | } |
1da177e4 | 958 | |
df270051 | 959 | do_trap_or_bp(regs, tcode, "Trap"); |
c3fc5cd5 RB |
960 | |
961 | out: | |
962 | exception_exit(prev_state); | |
90fccb13 | 963 | return; |
e5679882 RB |
964 | |
965 | out_sigsegv: | |
966 | force_sig(SIGSEGV, current); | |
c3fc5cd5 | 967 | goto out; |
1da177e4 LT |
968 | } |
969 | ||
970 | asmlinkage void do_ri(struct pt_regs *regs) | |
971 | { | |
60b0d655 MR |
972 | unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); |
973 | unsigned long old_epc = regs->cp0_epc; | |
2a0b24f5 | 974 | unsigned long old31 = regs->regs[31]; |
c3fc5cd5 | 975 | enum ctx_state prev_state; |
60b0d655 MR |
976 | unsigned int opcode = 0; |
977 | int status = -1; | |
1da177e4 | 978 | |
c3fc5cd5 | 979 | prev_state = exception_enter(); |
dc73e4c1 RB |
980 | if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), |
981 | SIGILL) == NOTIFY_STOP) | |
c3fc5cd5 | 982 | goto out; |
88547001 | 983 | |
60b0d655 | 984 | die_if_kernel("Reserved instruction in kernel code", regs); |
1da177e4 | 985 | |
60b0d655 | 986 | if (unlikely(compute_return_epc(regs) < 0)) |
c3fc5cd5 | 987 | goto out; |
3c37026d | 988 | |
2a0b24f5 SH |
989 | if (get_isa16_mode(regs->cp0_epc)) { |
990 | unsigned short mmop[2] = { 0 }; | |
60b0d655 | 991 | |
2a0b24f5 SH |
992 | if (unlikely(get_user(mmop[0], epc) < 0)) |
993 | status = SIGSEGV; | |
994 | if (unlikely(get_user(mmop[1], epc) < 0)) | |
995 | status = SIGSEGV; | |
996 | opcode = (mmop[0] << 16) | mmop[1]; | |
60b0d655 | 997 | |
2a0b24f5 SH |
998 | if (status < 0) |
999 | status = simulate_rdhwr_mm(regs, opcode); | |
1000 | } else { | |
1001 | if (unlikely(get_user(opcode, epc) < 0)) | |
1002 | status = SIGSEGV; | |
60b0d655 | 1003 | |
2a0b24f5 SH |
1004 | if (!cpu_has_llsc && status < 0) |
1005 | status = simulate_llsc(regs, opcode); | |
1006 | ||
1007 | if (status < 0) | |
1008 | status = simulate_rdhwr_normal(regs, opcode); | |
1009 | ||
1010 | if (status < 0) | |
1011 | status = simulate_sync(regs, opcode); | |
1012 | } | |
60b0d655 MR |
1013 | |
1014 | if (status < 0) | |
1015 | status = SIGILL; | |
1016 | ||
1017 | if (unlikely(status > 0)) { | |
1018 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
2a0b24f5 | 1019 | regs->regs[31] = old31; |
60b0d655 MR |
1020 | force_sig(status, current); |
1021 | } | |
c3fc5cd5 RB |
1022 | |
1023 | out: | |
1024 | exception_exit(prev_state); | |
1da177e4 LT |
1025 | } |
1026 | ||
d223a861 RB |
1027 | /* |
1028 | * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've | |
1029 | * emulated more than some threshold number of instructions, force migration to | |
1030 | * a "CPU" that has FP support. | |
1031 | */ | |
1032 | static void mt_ase_fp_affinity(void) | |
1033 | { | |
1034 | #ifdef CONFIG_MIPS_MT_FPAFF | |
1035 | if (mt_fpemul_threshold > 0 && | |
1036 | ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { | |
1037 | /* | |
1038 | * If there's no FPU present, or if the application has already | |
1039 | * restricted the allowed set to exclude any CPUs with FPUs, | |
1040 | * we'll skip the procedure. | |
1041 | */ | |
1042 | if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { | |
1043 | cpumask_t tmask; | |
1044 | ||
9cc12363 KK |
1045 | current->thread.user_cpus_allowed |
1046 | = current->cpus_allowed; | |
1047 | cpus_and(tmask, current->cpus_allowed, | |
1048 | mt_fpu_cpumask); | |
ed1bbdef | 1049 | set_cpus_allowed_ptr(current, &tmask); |
293c5bd1 | 1050 | set_thread_flag(TIF_FPUBOUND); |
d223a861 RB |
1051 | } |
1052 | } | |
1053 | #endif /* CONFIG_MIPS_MT_FPAFF */ | |
1054 | } | |
1055 | ||
69f3a7de RB |
1056 | /* |
1057 | * No lock; only written during early bootup by CPU 0. | |
1058 | */ | |
1059 | static RAW_NOTIFIER_HEAD(cu2_chain); | |
1060 | ||
1061 | int __ref register_cu2_notifier(struct notifier_block *nb) | |
1062 | { | |
1063 | return raw_notifier_chain_register(&cu2_chain, nb); | |
1064 | } | |
1065 | ||
1066 | int cu2_notifier_call_chain(unsigned long val, void *v) | |
1067 | { | |
1068 | return raw_notifier_call_chain(&cu2_chain, val, v); | |
1069 | } | |
1070 | ||
1071 | static int default_cu2_call(struct notifier_block *nfb, unsigned long action, | |
70342287 | 1072 | void *data) |
69f3a7de RB |
1073 | { |
1074 | struct pt_regs *regs = data; | |
1075 | ||
83bee792 | 1076 | die_if_kernel("COP2: Unhandled kernel unaligned access or invalid " |
69f3a7de | 1077 | "instruction", regs); |
83bee792 | 1078 | force_sig(SIGILL, current); |
69f3a7de RB |
1079 | |
1080 | return NOTIFY_OK; | |
1081 | } | |
1082 | ||
1db1af84 PB |
1083 | static int enable_restore_fp_context(int msa) |
1084 | { | |
1085 | int err, was_fpu_owner; | |
1086 | ||
1087 | if (!used_math()) { | |
1088 | /* First time FP context user. */ | |
1089 | err = init_fpu(); | |
1090 | if (msa && !err) | |
1091 | enable_msa(); | |
1092 | if (!err) | |
1093 | set_used_math(); | |
1094 | return err; | |
1095 | } | |
1096 | ||
1097 | /* | |
1098 | * This task has formerly used the FP context. | |
1099 | * | |
1100 | * If this thread has no live MSA vector context then we can simply | |
1101 | * restore the scalar FP context. If it has live MSA vector context | |
1102 | * (that is, it has or may have used MSA since last performing a | |
1103 | * function call) then we'll need to restore the vector context. This | |
1104 | * applies even if we're currently only executing a scalar FP | |
1105 | * instruction. This is because if we were to later execute an MSA | |
1106 | * instruction then we'd either have to: | |
1107 | * | |
1108 | * - Restore the vector context & clobber any registers modified by | |
1109 | * scalar FP instructions between now & then. | |
1110 | * | |
1111 | * or | |
1112 | * | |
1113 | * - Not restore the vector context & lose the most significant bits | |
1114 | * of all vector registers. | |
1115 | * | |
1116 | * Neither of those options is acceptable. We cannot restore the least | |
1117 | * significant bits of the registers now & only restore the most | |
1118 | * significant bits later because the most significant bits of any | |
1119 | * vector registers whose aliased FP register is modified now will have | |
1120 | * been zeroed. We'd have no way to know that when restoring the vector | |
1121 | * context & thus may load an outdated value for the most significant | |
1122 | * bits of a vector register. | |
1123 | */ | |
1124 | if (!msa && !thread_msa_context_live()) | |
1125 | return own_fpu(1); | |
1126 | ||
1127 | /* | |
1128 | * This task is using or has previously used MSA. Thus we require | |
1129 | * that Status.FR == 1. | |
1130 | */ | |
1131 | was_fpu_owner = is_fpu_owner(); | |
1132 | err = own_fpu(0); | |
1133 | if (err) | |
1134 | return err; | |
1135 | ||
1136 | enable_msa(); | |
1137 | write_msa_csr(current->thread.fpu.msacsr); | |
1138 | set_thread_flag(TIF_USEDMSA); | |
1139 | ||
1140 | /* | |
1141 | * If this is the first time that the task is using MSA and it has | |
1142 | * previously used scalar FP in this time slice then we already nave | |
1143 | * FP context which we shouldn't clobber. | |
1144 | */ | |
1145 | if (!test_and_set_thread_flag(TIF_MSA_CTX_LIVE) && was_fpu_owner) | |
1146 | return 0; | |
1147 | ||
1148 | /* We need to restore the vector context. */ | |
1149 | restore_msa(current); | |
1150 | return 0; | |
1151 | } | |
1152 | ||
1da177e4 LT |
1153 | asmlinkage void do_cpu(struct pt_regs *regs) |
1154 | { | |
c3fc5cd5 | 1155 | enum ctx_state prev_state; |
60b0d655 | 1156 | unsigned int __user *epc; |
2a0b24f5 | 1157 | unsigned long old_epc, old31; |
60b0d655 | 1158 | unsigned int opcode; |
1da177e4 | 1159 | unsigned int cpid; |
597ce172 | 1160 | int status, err; |
f9bb4cf3 | 1161 | unsigned long __maybe_unused flags; |
1da177e4 | 1162 | |
c3fc5cd5 | 1163 | prev_state = exception_enter(); |
1da177e4 LT |
1164 | cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; |
1165 | ||
83bee792 J |
1166 | if (cpid != 2) |
1167 | die_if_kernel("do_cpu invoked from kernel context!", regs); | |
1168 | ||
1da177e4 LT |
1169 | switch (cpid) { |
1170 | case 0: | |
60b0d655 MR |
1171 | epc = (unsigned int __user *)exception_epc(regs); |
1172 | old_epc = regs->cp0_epc; | |
2a0b24f5 | 1173 | old31 = regs->regs[31]; |
60b0d655 MR |
1174 | opcode = 0; |
1175 | status = -1; | |
1da177e4 | 1176 | |
60b0d655 | 1177 | if (unlikely(compute_return_epc(regs) < 0)) |
c3fc5cd5 | 1178 | goto out; |
3c37026d | 1179 | |
2a0b24f5 SH |
1180 | if (get_isa16_mode(regs->cp0_epc)) { |
1181 | unsigned short mmop[2] = { 0 }; | |
60b0d655 | 1182 | |
2a0b24f5 SH |
1183 | if (unlikely(get_user(mmop[0], epc) < 0)) |
1184 | status = SIGSEGV; | |
1185 | if (unlikely(get_user(mmop[1], epc) < 0)) | |
1186 | status = SIGSEGV; | |
1187 | opcode = (mmop[0] << 16) | mmop[1]; | |
60b0d655 | 1188 | |
2a0b24f5 SH |
1189 | if (status < 0) |
1190 | status = simulate_rdhwr_mm(regs, opcode); | |
1191 | } else { | |
1192 | if (unlikely(get_user(opcode, epc) < 0)) | |
1193 | status = SIGSEGV; | |
1194 | ||
1195 | if (!cpu_has_llsc && status < 0) | |
1196 | status = simulate_llsc(regs, opcode); | |
1197 | ||
1198 | if (status < 0) | |
1199 | status = simulate_rdhwr_normal(regs, opcode); | |
1200 | } | |
60b0d655 MR |
1201 | |
1202 | if (status < 0) | |
1203 | status = SIGILL; | |
1204 | ||
1205 | if (unlikely(status > 0)) { | |
1206 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
2a0b24f5 | 1207 | regs->regs[31] = old31; |
60b0d655 MR |
1208 | force_sig(status, current); |
1209 | } | |
1210 | ||
c3fc5cd5 | 1211 | goto out; |
1da177e4 | 1212 | |
051ff44a MR |
1213 | case 3: |
1214 | /* | |
1215 | * Old (MIPS I and MIPS II) processors will set this code | |
1216 | * for COP1X opcode instructions that replaced the original | |
70342287 | 1217 | * COP3 space. We don't limit COP1 space instructions in |
051ff44a MR |
1218 | * the emulator according to the CPU ISA, so we want to |
1219 | * treat COP1X instructions consistently regardless of which | |
70342287 | 1220 | * code the CPU chose. Therefore we redirect this trap to |
051ff44a MR |
1221 | * the FP emulator too. |
1222 | * | |
1223 | * Then some newer FPU-less processors use this code | |
1224 | * erroneously too, so they are covered by this choice | |
1225 | * as well. | |
1226 | */ | |
1227 | if (raw_cpu_has_fpu) | |
1228 | break; | |
1229 | /* Fall through. */ | |
1230 | ||
1da177e4 | 1231 | case 1: |
1db1af84 | 1232 | err = enable_restore_fp_context(0); |
1da177e4 | 1233 | |
597ce172 | 1234 | if (!raw_cpu_has_fpu || err) { |
e04582b7 | 1235 | int sig; |
515b029d | 1236 | void __user *fault_addr = NULL; |
e04582b7 | 1237 | sig = fpu_emulator_cop1Handler(regs, |
515b029d DD |
1238 | ¤t->thread.fpu, |
1239 | 0, &fault_addr); | |
597ce172 | 1240 | if (!process_fpemu_return(sig, fault_addr) && !err) |
d223a861 | 1241 | mt_ase_fp_affinity(); |
1da177e4 LT |
1242 | } |
1243 | ||
c3fc5cd5 | 1244 | goto out; |
1da177e4 LT |
1245 | |
1246 | case 2: | |
69f3a7de | 1247 | raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); |
c3fc5cd5 | 1248 | goto out; |
1da177e4 LT |
1249 | } |
1250 | ||
1251 | force_sig(SIGILL, current); | |
c3fc5cd5 RB |
1252 | |
1253 | out: | |
1254 | exception_exit(prev_state); | |
1da177e4 LT |
1255 | } |
1256 | ||
2bcb3fbc PB |
1257 | asmlinkage void do_msa_fpe(struct pt_regs *regs) |
1258 | { | |
1259 | enum ctx_state prev_state; | |
1260 | ||
1261 | prev_state = exception_enter(); | |
1262 | die_if_kernel("do_msa_fpe invoked from kernel context!", regs); | |
1263 | force_sig(SIGFPE, current); | |
1264 | exception_exit(prev_state); | |
1265 | } | |
1266 | ||
1db1af84 PB |
1267 | asmlinkage void do_msa(struct pt_regs *regs) |
1268 | { | |
1269 | enum ctx_state prev_state; | |
1270 | int err; | |
1271 | ||
1272 | prev_state = exception_enter(); | |
1273 | ||
1274 | if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) { | |
1275 | force_sig(SIGILL, current); | |
1276 | goto out; | |
1277 | } | |
1278 | ||
1279 | die_if_kernel("do_msa invoked from kernel context!", regs); | |
1280 | ||
1281 | err = enable_restore_fp_context(1); | |
1282 | if (err) | |
1283 | force_sig(SIGILL, current); | |
1284 | out: | |
1285 | exception_exit(prev_state); | |
1286 | } | |
1287 | ||
1da177e4 LT |
1288 | asmlinkage void do_mdmx(struct pt_regs *regs) |
1289 | { | |
c3fc5cd5 RB |
1290 | enum ctx_state prev_state; |
1291 | ||
1292 | prev_state = exception_enter(); | |
1da177e4 | 1293 | force_sig(SIGILL, current); |
c3fc5cd5 | 1294 | exception_exit(prev_state); |
1da177e4 LT |
1295 | } |
1296 | ||
8bc6d05b DD |
1297 | /* |
1298 | * Called with interrupts disabled. | |
1299 | */ | |
1da177e4 LT |
1300 | asmlinkage void do_watch(struct pt_regs *regs) |
1301 | { | |
c3fc5cd5 | 1302 | enum ctx_state prev_state; |
b67b2b70 DD |
1303 | u32 cause; |
1304 | ||
c3fc5cd5 | 1305 | prev_state = exception_enter(); |
1da177e4 | 1306 | /* |
b67b2b70 DD |
1307 | * Clear WP (bit 22) bit of cause register so we don't loop |
1308 | * forever. | |
1da177e4 | 1309 | */ |
b67b2b70 DD |
1310 | cause = read_c0_cause(); |
1311 | cause &= ~(1 << 22); | |
1312 | write_c0_cause(cause); | |
1313 | ||
1314 | /* | |
1315 | * If the current thread has the watch registers loaded, save | |
1316 | * their values and send SIGTRAP. Otherwise another thread | |
1317 | * left the registers set, clear them and continue. | |
1318 | */ | |
1319 | if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { | |
1320 | mips_read_watch_registers(); | |
8bc6d05b | 1321 | local_irq_enable(); |
b67b2b70 | 1322 | force_sig(SIGTRAP, current); |
8bc6d05b | 1323 | } else { |
b67b2b70 | 1324 | mips_clear_watch_registers(); |
8bc6d05b DD |
1325 | local_irq_enable(); |
1326 | } | |
c3fc5cd5 | 1327 | exception_exit(prev_state); |
1da177e4 LT |
1328 | } |
1329 | ||
1330 | asmlinkage void do_mcheck(struct pt_regs *regs) | |
1331 | { | |
cac4bcbc RB |
1332 | const int field = 2 * sizeof(unsigned long); |
1333 | int multi_match = regs->cp0_status & ST0_TS; | |
c3fc5cd5 | 1334 | enum ctx_state prev_state; |
cac4bcbc | 1335 | |
c3fc5cd5 | 1336 | prev_state = exception_enter(); |
1da177e4 | 1337 | show_regs(regs); |
cac4bcbc RB |
1338 | |
1339 | if (multi_match) { | |
70342287 | 1340 | printk("Index : %0x\n", read_c0_index()); |
cac4bcbc RB |
1341 | printk("Pagemask: %0x\n", read_c0_pagemask()); |
1342 | printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); | |
1343 | printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); | |
1344 | printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); | |
1345 | printk("\n"); | |
1346 | dump_tlb_all(); | |
1347 | } | |
1348 | ||
e1bb8289 | 1349 | show_code((unsigned int __user *) regs->cp0_epc); |
cac4bcbc | 1350 | |
1da177e4 LT |
1351 | /* |
1352 | * Some chips may have other causes of machine check (e.g. SB1 | |
1353 | * graduation timer) | |
1354 | */ | |
1355 | panic("Caught Machine Check exception - %scaused by multiple " | |
1356 | "matching entries in the TLB.", | |
cac4bcbc | 1357 | (multi_match) ? "" : "not "); |
1da177e4 LT |
1358 | } |
1359 | ||
340ee4b9 RB |
1360 | asmlinkage void do_mt(struct pt_regs *regs) |
1361 | { | |
41c594ab RB |
1362 | int subcode; |
1363 | ||
41c594ab RB |
1364 | subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) |
1365 | >> VPECONTROL_EXCPT_SHIFT; | |
1366 | switch (subcode) { | |
1367 | case 0: | |
e35a5e35 | 1368 | printk(KERN_DEBUG "Thread Underflow\n"); |
41c594ab RB |
1369 | break; |
1370 | case 1: | |
e35a5e35 | 1371 | printk(KERN_DEBUG "Thread Overflow\n"); |
41c594ab RB |
1372 | break; |
1373 | case 2: | |
e35a5e35 | 1374 | printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); |
41c594ab RB |
1375 | break; |
1376 | case 3: | |
e35a5e35 | 1377 | printk(KERN_DEBUG "Gating Storage Exception\n"); |
41c594ab RB |
1378 | break; |
1379 | case 4: | |
e35a5e35 | 1380 | printk(KERN_DEBUG "YIELD Scheduler Exception\n"); |
41c594ab RB |
1381 | break; |
1382 | case 5: | |
f232c7e8 | 1383 | printk(KERN_DEBUG "Gating Storage Scheduler Exception\n"); |
41c594ab RB |
1384 | break; |
1385 | default: | |
e35a5e35 | 1386 | printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", |
41c594ab RB |
1387 | subcode); |
1388 | break; | |
1389 | } | |
340ee4b9 RB |
1390 | die_if_kernel("MIPS MT Thread exception in kernel", regs); |
1391 | ||
1392 | force_sig(SIGILL, current); | |
1393 | } | |
1394 | ||
1395 | ||
e50c0a8f RB |
1396 | asmlinkage void do_dsp(struct pt_regs *regs) |
1397 | { | |
1398 | if (cpu_has_dsp) | |
ab75dc02 | 1399 | panic("Unexpected DSP exception"); |
e50c0a8f RB |
1400 | |
1401 | force_sig(SIGILL, current); | |
1402 | } | |
1403 | ||
1da177e4 LT |
1404 | asmlinkage void do_reserved(struct pt_regs *regs) |
1405 | { | |
1406 | /* | |
70342287 | 1407 | * Game over - no way to handle this if it ever occurs. Most probably |
1da177e4 LT |
1408 | * caused by a new unknown cpu type or after another deadly |
1409 | * hard/software error. | |
1410 | */ | |
1411 | show_regs(regs); | |
1412 | panic("Caught reserved exception %ld - should not happen.", | |
1413 | (regs->cp0_cause & 0x7f) >> 2); | |
1414 | } | |
1415 | ||
39b8d525 RB |
1416 | static int __initdata l1parity = 1; |
1417 | static int __init nol1parity(char *s) | |
1418 | { | |
1419 | l1parity = 0; | |
1420 | return 1; | |
1421 | } | |
1422 | __setup("nol1par", nol1parity); | |
1423 | static int __initdata l2parity = 1; | |
1424 | static int __init nol2parity(char *s) | |
1425 | { | |
1426 | l2parity = 0; | |
1427 | return 1; | |
1428 | } | |
1429 | __setup("nol2par", nol2parity); | |
1430 | ||
1da177e4 LT |
1431 | /* |
1432 | * Some MIPS CPUs can enable/disable for cache parity detection, but do | |
1433 | * it different ways. | |
1434 | */ | |
1435 | static inline void parity_protection_init(void) | |
1436 | { | |
10cc3529 | 1437 | switch (current_cpu_type()) { |
1da177e4 | 1438 | case CPU_24K: |
98a41de9 | 1439 | case CPU_34K: |
39b8d525 RB |
1440 | case CPU_74K: |
1441 | case CPU_1004K: | |
442e14a2 | 1442 | case CPU_1074K: |
26ab96df | 1443 | case CPU_INTERAPTIV: |
708ac4b8 | 1444 | case CPU_PROAPTIV: |
aced4cbd | 1445 | case CPU_P5600: |
39b8d525 RB |
1446 | { |
1447 | #define ERRCTL_PE 0x80000000 | |
1448 | #define ERRCTL_L2P 0x00800000 | |
1449 | unsigned long errctl; | |
1450 | unsigned int l1parity_present, l2parity_present; | |
1451 | ||
1452 | errctl = read_c0_ecc(); | |
1453 | errctl &= ~(ERRCTL_PE|ERRCTL_L2P); | |
1454 | ||
1455 | /* probe L1 parity support */ | |
1456 | write_c0_ecc(errctl | ERRCTL_PE); | |
1457 | back_to_back_c0_hazard(); | |
1458 | l1parity_present = (read_c0_ecc() & ERRCTL_PE); | |
1459 | ||
1460 | /* probe L2 parity support */ | |
1461 | write_c0_ecc(errctl|ERRCTL_L2P); | |
1462 | back_to_back_c0_hazard(); | |
1463 | l2parity_present = (read_c0_ecc() & ERRCTL_L2P); | |
1464 | ||
1465 | if (l1parity_present && l2parity_present) { | |
1466 | if (l1parity) | |
1467 | errctl |= ERRCTL_PE; | |
1468 | if (l1parity ^ l2parity) | |
1469 | errctl |= ERRCTL_L2P; | |
1470 | } else if (l1parity_present) { | |
1471 | if (l1parity) | |
1472 | errctl |= ERRCTL_PE; | |
1473 | } else if (l2parity_present) { | |
1474 | if (l2parity) | |
1475 | errctl |= ERRCTL_L2P; | |
1476 | } else { | |
1477 | /* No parity available */ | |
1478 | } | |
1479 | ||
1480 | printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); | |
1481 | ||
1482 | write_c0_ecc(errctl); | |
1483 | back_to_back_c0_hazard(); | |
1484 | errctl = read_c0_ecc(); | |
1485 | printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); | |
1486 | ||
1487 | if (l1parity_present) | |
1488 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1489 | (errctl & ERRCTL_PE) ? "en" : "dis"); | |
1490 | ||
1491 | if (l2parity_present) { | |
1492 | if (l1parity_present && l1parity) | |
1493 | errctl ^= ERRCTL_L2P; | |
1494 | printk(KERN_INFO "L2 cache parity protection %sabled\n", | |
1495 | (errctl & ERRCTL_L2P) ? "en" : "dis"); | |
1496 | } | |
1497 | } | |
1498 | break; | |
1499 | ||
1da177e4 | 1500 | case CPU_5KC: |
78d4803f | 1501 | case CPU_5KE: |
2fa36399 | 1502 | case CPU_LOONGSON1: |
14f18b7f RB |
1503 | write_c0_ecc(0x80000000); |
1504 | back_to_back_c0_hazard(); | |
1505 | /* Set the PE bit (bit 31) in the c0_errctl register. */ | |
1506 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1507 | (read_c0_ecc() & 0x80000000) ? "en" : "dis"); | |
1da177e4 LT |
1508 | break; |
1509 | case CPU_20KC: | |
1510 | case CPU_25KF: | |
1511 | /* Clear the DE bit (bit 16) in the c0_status register. */ | |
1512 | printk(KERN_INFO "Enable cache parity protection for " | |
1513 | "MIPS 20KC/25KF CPUs.\n"); | |
1514 | clear_c0_status(ST0_DE); | |
1515 | break; | |
1516 | default: | |
1517 | break; | |
1518 | } | |
1519 | } | |
1520 | ||
1521 | asmlinkage void cache_parity_error(void) | |
1522 | { | |
1523 | const int field = 2 * sizeof(unsigned long); | |
1524 | unsigned int reg_val; | |
1525 | ||
1526 | /* For the moment, report the problem and hang. */ | |
1527 | printk("Cache error exception:\n"); | |
1528 | printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); | |
1529 | reg_val = read_c0_cacheerr(); | |
1530 | printk("c0_cacheerr == %08x\n", reg_val); | |
1531 | ||
1532 | printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", | |
1533 | reg_val & (1<<30) ? "secondary" : "primary", | |
1534 | reg_val & (1<<31) ? "data" : "insn"); | |
6de20451 LY |
1535 | if (cpu_has_mips_r2 && |
1536 | ((current_cpu_data.processor_id && 0xff0000) == PRID_COMP_MIPS)) { | |
1537 | pr_err("Error bits: %s%s%s%s%s%s%s%s\n", | |
1538 | reg_val & (1<<29) ? "ED " : "", | |
1539 | reg_val & (1<<28) ? "ET " : "", | |
1540 | reg_val & (1<<27) ? "ES " : "", | |
1541 | reg_val & (1<<26) ? "EE " : "", | |
1542 | reg_val & (1<<25) ? "EB " : "", | |
1543 | reg_val & (1<<24) ? "EI " : "", | |
1544 | reg_val & (1<<23) ? "E1 " : "", | |
1545 | reg_val & (1<<22) ? "E0 " : ""); | |
1546 | } else { | |
1547 | pr_err("Error bits: %s%s%s%s%s%s%s\n", | |
1548 | reg_val & (1<<29) ? "ED " : "", | |
1549 | reg_val & (1<<28) ? "ET " : "", | |
1550 | reg_val & (1<<26) ? "EE " : "", | |
1551 | reg_val & (1<<25) ? "EB " : "", | |
1552 | reg_val & (1<<24) ? "EI " : "", | |
1553 | reg_val & (1<<23) ? "E1 " : "", | |
1554 | reg_val & (1<<22) ? "E0 " : ""); | |
1555 | } | |
1da177e4 LT |
1556 | printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); |
1557 | ||
ec917c2c | 1558 | #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) |
1da177e4 LT |
1559 | if (reg_val & (1<<22)) |
1560 | printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); | |
1561 | ||
1562 | if (reg_val & (1<<23)) | |
1563 | printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); | |
1564 | #endif | |
1565 | ||
1566 | panic("Can't handle the cache error!"); | |
1567 | } | |
1568 | ||
75b5b5e0 LY |
1569 | asmlinkage void do_ftlb(void) |
1570 | { | |
1571 | const int field = 2 * sizeof(unsigned long); | |
1572 | unsigned int reg_val; | |
1573 | ||
1574 | /* For the moment, report the problem and hang. */ | |
1575 | if (cpu_has_mips_r2 && | |
1576 | ((current_cpu_data.processor_id && 0xff0000) == PRID_COMP_MIPS)) { | |
1577 | pr_err("FTLB error exception, cp0_ecc=0x%08x:\n", | |
1578 | read_c0_ecc()); | |
1579 | pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); | |
1580 | reg_val = read_c0_cacheerr(); | |
1581 | pr_err("c0_cacheerr == %08x\n", reg_val); | |
1582 | ||
1583 | if ((reg_val & 0xc0000000) == 0xc0000000) { | |
1584 | pr_err("Decoded c0_cacheerr: FTLB parity error\n"); | |
1585 | } else { | |
1586 | pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n", | |
1587 | reg_val & (1<<30) ? "secondary" : "primary", | |
1588 | reg_val & (1<<31) ? "data" : "insn"); | |
1589 | } | |
1590 | } else { | |
1591 | pr_err("FTLB error exception\n"); | |
1592 | } | |
1593 | /* Just print the cacheerr bits for now */ | |
1594 | cache_parity_error(); | |
1595 | } | |
1596 | ||
1da177e4 LT |
1597 | /* |
1598 | * SDBBP EJTAG debug exception handler. | |
1599 | * We skip the instruction and return to the next instruction. | |
1600 | */ | |
1601 | void ejtag_exception_handler(struct pt_regs *regs) | |
1602 | { | |
1603 | const int field = 2 * sizeof(unsigned long); | |
2a0b24f5 | 1604 | unsigned long depc, old_epc, old_ra; |
1da177e4 LT |
1605 | unsigned int debug; |
1606 | ||
70ae6126 | 1607 | printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); |
1da177e4 LT |
1608 | depc = read_c0_depc(); |
1609 | debug = read_c0_debug(); | |
70ae6126 | 1610 | printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); |
1da177e4 LT |
1611 | if (debug & 0x80000000) { |
1612 | /* | |
1613 | * In branch delay slot. | |
1614 | * We cheat a little bit here and use EPC to calculate the | |
1615 | * debug return address (DEPC). EPC is restored after the | |
1616 | * calculation. | |
1617 | */ | |
1618 | old_epc = regs->cp0_epc; | |
2a0b24f5 | 1619 | old_ra = regs->regs[31]; |
1da177e4 | 1620 | regs->cp0_epc = depc; |
2a0b24f5 | 1621 | compute_return_epc(regs); |
1da177e4 LT |
1622 | depc = regs->cp0_epc; |
1623 | regs->cp0_epc = old_epc; | |
2a0b24f5 | 1624 | regs->regs[31] = old_ra; |
1da177e4 LT |
1625 | } else |
1626 | depc += 4; | |
1627 | write_c0_depc(depc); | |
1628 | ||
1629 | #if 0 | |
70ae6126 | 1630 | printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); |
1da177e4 LT |
1631 | write_c0_debug(debug | 0x100); |
1632 | #endif | |
1633 | } | |
1634 | ||
1635 | /* | |
1636 | * NMI exception handler. | |
34bd92e2 | 1637 | * No lock; only written during early bootup by CPU 0. |
1da177e4 | 1638 | */ |
34bd92e2 KC |
1639 | static RAW_NOTIFIER_HEAD(nmi_chain); |
1640 | ||
1641 | int register_nmi_notifier(struct notifier_block *nb) | |
1642 | { | |
1643 | return raw_notifier_chain_register(&nmi_chain, nb); | |
1644 | } | |
1645 | ||
ff2d8b19 | 1646 | void __noreturn nmi_exception_handler(struct pt_regs *regs) |
1da177e4 | 1647 | { |
83e4da1e LY |
1648 | char str[100]; |
1649 | ||
34bd92e2 | 1650 | raw_notifier_call_chain(&nmi_chain, 0, regs); |
41c594ab | 1651 | bust_spinlocks(1); |
83e4da1e LY |
1652 | snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n", |
1653 | smp_processor_id(), regs->cp0_epc); | |
1654 | regs->cp0_epc = read_c0_errorepc(); | |
1655 | die(str, regs); | |
1da177e4 LT |
1656 | } |
1657 | ||
e01402b1 RB |
1658 | #define VECTORSPACING 0x100 /* for EI/VI mode */ |
1659 | ||
1660 | unsigned long ebase; | |
1da177e4 | 1661 | unsigned long exception_handlers[32]; |
e01402b1 | 1662 | unsigned long vi_handlers[64]; |
1da177e4 | 1663 | |
2d1b6e95 | 1664 | void __init *set_except_vector(int n, void *addr) |
1da177e4 LT |
1665 | { |
1666 | unsigned long handler = (unsigned long) addr; | |
b22d1b6a | 1667 | unsigned long old_handler; |
1da177e4 | 1668 | |
2a0b24f5 SH |
1669 | #ifdef CONFIG_CPU_MICROMIPS |
1670 | /* | |
1671 | * Only the TLB handlers are cache aligned with an even | |
1672 | * address. All other handlers are on an odd address and | |
1673 | * require no modification. Otherwise, MIPS32 mode will | |
1674 | * be entered when handling any TLB exceptions. That | |
1675 | * would be bad...since we must stay in microMIPS mode. | |
1676 | */ | |
1677 | if (!(handler & 0x1)) | |
1678 | handler |= 1; | |
1679 | #endif | |
b22d1b6a | 1680 | old_handler = xchg(&exception_handlers[n], handler); |
1da177e4 | 1681 | |
1da177e4 | 1682 | if (n == 0 && cpu_has_divec) { |
2a0b24f5 SH |
1683 | #ifdef CONFIG_CPU_MICROMIPS |
1684 | unsigned long jump_mask = ~((1 << 27) - 1); | |
1685 | #else | |
92bbe1b9 | 1686 | unsigned long jump_mask = ~((1 << 28) - 1); |
2a0b24f5 | 1687 | #endif |
92bbe1b9 FF |
1688 | u32 *buf = (u32 *)(ebase + 0x200); |
1689 | unsigned int k0 = 26; | |
1690 | if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { | |
1691 | uasm_i_j(&buf, handler & ~jump_mask); | |
1692 | uasm_i_nop(&buf); | |
1693 | } else { | |
1694 | UASM_i_LA(&buf, k0, handler); | |
1695 | uasm_i_jr(&buf, k0); | |
1696 | uasm_i_nop(&buf); | |
1697 | } | |
1698 | local_flush_icache_range(ebase + 0x200, (unsigned long)buf); | |
e01402b1 RB |
1699 | } |
1700 | return (void *)old_handler; | |
1701 | } | |
1702 | ||
86a1708a | 1703 | static void do_default_vi(void) |
6ba07e59 AN |
1704 | { |
1705 | show_regs(get_irq_regs()); | |
1706 | panic("Caught unexpected vectored interrupt."); | |
1707 | } | |
1708 | ||
ef300e42 | 1709 | static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) |
e01402b1 RB |
1710 | { |
1711 | unsigned long handler; | |
1712 | unsigned long old_handler = vi_handlers[n]; | |
f6771dbb | 1713 | int srssets = current_cpu_data.srsets; |
2a0b24f5 | 1714 | u16 *h; |
e01402b1 RB |
1715 | unsigned char *b; |
1716 | ||
b72b7092 | 1717 | BUG_ON(!cpu_has_veic && !cpu_has_vint); |
e01402b1 RB |
1718 | |
1719 | if (addr == NULL) { | |
1720 | handler = (unsigned long) do_default_vi; | |
1721 | srs = 0; | |
41c594ab | 1722 | } else |
e01402b1 | 1723 | handler = (unsigned long) addr; |
2a0b24f5 | 1724 | vi_handlers[n] = handler; |
e01402b1 RB |
1725 | |
1726 | b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); | |
1727 | ||
f6771dbb | 1728 | if (srs >= srssets) |
e01402b1 RB |
1729 | panic("Shadow register set %d not supported", srs); |
1730 | ||
1731 | if (cpu_has_veic) { | |
1732 | if (board_bind_eic_interrupt) | |
49a89efb | 1733 | board_bind_eic_interrupt(n, srs); |
41c594ab | 1734 | } else if (cpu_has_vint) { |
e01402b1 | 1735 | /* SRSMap is only defined if shadow sets are implemented */ |
f6771dbb | 1736 | if (srssets > 1) |
49a89efb | 1737 | change_c0_srsmap(0xf << n*4, srs << n*4); |
e01402b1 RB |
1738 | } |
1739 | ||
1740 | if (srs == 0) { | |
1741 | /* | |
1742 | * If no shadow set is selected then use the default handler | |
2a0b24f5 | 1743 | * that does normal register saving and standard interrupt exit |
e01402b1 | 1744 | */ |
e01402b1 RB |
1745 | extern char except_vec_vi, except_vec_vi_lui; |
1746 | extern char except_vec_vi_ori, except_vec_vi_end; | |
c65a5480 | 1747 | extern char rollback_except_vec_vi; |
f94d9a8e | 1748 | char *vec_start = using_rollback_handler() ? |
c65a5480 | 1749 | &rollback_except_vec_vi : &except_vec_vi; |
41c594ab RB |
1750 | #ifdef CONFIG_MIPS_MT_SMTC |
1751 | /* | |
1752 | * We need to provide the SMTC vectored interrupt handler | |
1753 | * not only with the address of the handler, but with the | |
1754 | * Status.IM bit to be masked before going there. | |
1755 | */ | |
1756 | extern char except_vec_vi_mori; | |
2a0b24f5 SH |
1757 | #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) |
1758 | const int mori_offset = &except_vec_vi_mori - vec_start + 2; | |
1759 | #else | |
c65a5480 | 1760 | const int mori_offset = &except_vec_vi_mori - vec_start; |
2a0b24f5 | 1761 | #endif |
41c594ab | 1762 | #endif /* CONFIG_MIPS_MT_SMTC */ |
2a0b24f5 SH |
1763 | #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) |
1764 | const int lui_offset = &except_vec_vi_lui - vec_start + 2; | |
1765 | const int ori_offset = &except_vec_vi_ori - vec_start + 2; | |
1766 | #else | |
c65a5480 AN |
1767 | const int lui_offset = &except_vec_vi_lui - vec_start; |
1768 | const int ori_offset = &except_vec_vi_ori - vec_start; | |
2a0b24f5 SH |
1769 | #endif |
1770 | const int handler_len = &except_vec_vi_end - vec_start; | |
e01402b1 RB |
1771 | |
1772 | if (handler_len > VECTORSPACING) { | |
1773 | /* | |
1774 | * Sigh... panicing won't help as the console | |
1775 | * is probably not configured :( | |
1776 | */ | |
49a89efb | 1777 | panic("VECTORSPACING too small"); |
e01402b1 RB |
1778 | } |
1779 | ||
2a0b24f5 SH |
1780 | set_handler(((unsigned long)b - ebase), vec_start, |
1781 | #ifdef CONFIG_CPU_MICROMIPS | |
1782 | (handler_len - 1)); | |
1783 | #else | |
1784 | handler_len); | |
1785 | #endif | |
41c594ab | 1786 | #ifdef CONFIG_MIPS_MT_SMTC |
8e8a52ed RB |
1787 | BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ |
1788 | ||
2a0b24f5 SH |
1789 | h = (u16 *)(b + mori_offset); |
1790 | *h = (0x100 << n); | |
41c594ab | 1791 | #endif /* CONFIG_MIPS_MT_SMTC */ |
2a0b24f5 SH |
1792 | h = (u16 *)(b + lui_offset); |
1793 | *h = (handler >> 16) & 0xffff; | |
1794 | h = (u16 *)(b + ori_offset); | |
1795 | *h = (handler & 0xffff); | |
e0cee3ee TB |
1796 | local_flush_icache_range((unsigned long)b, |
1797 | (unsigned long)(b+handler_len)); | |
e01402b1 RB |
1798 | } |
1799 | else { | |
1800 | /* | |
2a0b24f5 SH |
1801 | * In other cases jump directly to the interrupt handler. It |
1802 | * is the handler's responsibility to save registers if required | |
1803 | * (eg hi/lo) and return from the exception using "eret". | |
e01402b1 | 1804 | */ |
2a0b24f5 SH |
1805 | u32 insn; |
1806 | ||
1807 | h = (u16 *)b; | |
1808 | /* j handler */ | |
1809 | #ifdef CONFIG_CPU_MICROMIPS | |
1810 | insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1); | |
1811 | #else | |
1812 | insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2); | |
1813 | #endif | |
1814 | h[0] = (insn >> 16) & 0xffff; | |
1815 | h[1] = insn & 0xffff; | |
1816 | h[2] = 0; | |
1817 | h[3] = 0; | |
e0cee3ee TB |
1818 | local_flush_icache_range((unsigned long)b, |
1819 | (unsigned long)(b+8)); | |
1da177e4 | 1820 | } |
e01402b1 | 1821 | |
1da177e4 LT |
1822 | return (void *)old_handler; |
1823 | } | |
1824 | ||
ef300e42 | 1825 | void *set_vi_handler(int n, vi_handler_t addr) |
e01402b1 | 1826 | { |
ff3eab2a | 1827 | return set_vi_srs_handler(n, addr, 0); |
e01402b1 | 1828 | } |
f41ae0b2 | 1829 | |
1da177e4 LT |
1830 | extern void tlb_init(void); |
1831 | ||
42f77542 RB |
1832 | /* |
1833 | * Timer interrupt | |
1834 | */ | |
1835 | int cp0_compare_irq; | |
68b6352c | 1836 | EXPORT_SYMBOL_GPL(cp0_compare_irq); |
010c108d | 1837 | int cp0_compare_irq_shift; |
42f77542 RB |
1838 | |
1839 | /* | |
1840 | * Performance counter IRQ or -1 if shared with timer | |
1841 | */ | |
1842 | int cp0_perfcount_irq; | |
1843 | EXPORT_SYMBOL_GPL(cp0_perfcount_irq); | |
1844 | ||
078a55fc | 1845 | static int noulri; |
bdc94eb4 CD |
1846 | |
1847 | static int __init ulri_disable(char *s) | |
1848 | { | |
1849 | pr_info("Disabling ulri\n"); | |
1850 | noulri = 1; | |
1851 | ||
1852 | return 1; | |
1853 | } | |
1854 | __setup("noulri", ulri_disable); | |
1855 | ||
078a55fc | 1856 | void per_cpu_trap_init(bool is_boot_cpu) |
1da177e4 LT |
1857 | { |
1858 | unsigned int cpu = smp_processor_id(); | |
1859 | unsigned int status_set = ST0_CU0; | |
18d693b3 | 1860 | unsigned int hwrena = cpu_hwrena_impl_bits; |
41c594ab RB |
1861 | #ifdef CONFIG_MIPS_MT_SMTC |
1862 | int secondaryTC = 0; | |
1863 | int bootTC = (cpu == 0); | |
1864 | ||
1865 | /* | |
1866 | * Only do per_cpu_trap_init() for first TC of Each VPE. | |
1867 | * Note that this hack assumes that the SMTC init code | |
1868 | * assigns TCs consecutively and in ascending order. | |
1869 | */ | |
1870 | ||
1871 | if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && | |
1872 | ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) | |
1873 | secondaryTC = 1; | |
1874 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
1875 | |
1876 | /* | |
1877 | * Disable coprocessors and select 32-bit or 64-bit addressing | |
1878 | * and the 16/32 or 32/32 FPR register model. Reset the BEV | |
1879 | * flag that some firmware may have left set and the TS bit (for | |
1880 | * IP27). Set XX for ISA IV code to work. | |
1881 | */ | |
875d43e7 | 1882 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1883 | status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; |
1884 | #endif | |
adb37892 | 1885 | if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV) |
1da177e4 | 1886 | status_set |= ST0_XX; |
bbaf238b CD |
1887 | if (cpu_has_dsp) |
1888 | status_set |= ST0_MX; | |
1889 | ||
b38c7399 | 1890 | change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, |
1da177e4 LT |
1891 | status_set); |
1892 | ||
18d693b3 KC |
1893 | if (cpu_has_mips_r2) |
1894 | hwrena |= 0x0000000f; | |
a3692020 | 1895 | |
18d693b3 KC |
1896 | if (!noulri && cpu_has_userlocal) |
1897 | hwrena |= (1 << 29); | |
a3692020 | 1898 | |
18d693b3 KC |
1899 | if (hwrena) |
1900 | write_c0_hwrena(hwrena); | |
e01402b1 | 1901 | |
41c594ab RB |
1902 | #ifdef CONFIG_MIPS_MT_SMTC |
1903 | if (!secondaryTC) { | |
1904 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1905 | ||
e01402b1 | 1906 | if (cpu_has_veic || cpu_has_vint) { |
9fb4c2b9 | 1907 | unsigned long sr = set_c0_status(ST0_BEV); |
49a89efb | 1908 | write_c0_ebase(ebase); |
9fb4c2b9 | 1909 | write_c0_status(sr); |
e01402b1 | 1910 | /* Setting vector spacing enables EI/VI mode */ |
49a89efb | 1911 | change_c0_intctl(0x3e0, VECTORSPACING); |
e01402b1 | 1912 | } |
d03d0a57 RB |
1913 | if (cpu_has_divec) { |
1914 | if (cpu_has_mipsmt) { | |
1915 | unsigned int vpflags = dvpe(); | |
1916 | set_c0_cause(CAUSEF_IV); | |
1917 | evpe(vpflags); | |
1918 | } else | |
1919 | set_c0_cause(CAUSEF_IV); | |
1920 | } | |
3b1d4ed5 RB |
1921 | |
1922 | /* | |
1923 | * Before R2 both interrupt numbers were fixed to 7, so on R2 only: | |
1924 | * | |
1925 | * o read IntCtl.IPTI to determine the timer interrupt | |
1926 | * o read IntCtl.IPPCI to determine the performance counter interrupt | |
1927 | */ | |
1928 | if (cpu_has_mips_r2) { | |
010c108d DV |
1929 | cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; |
1930 | cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; | |
1931 | cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; | |
c3e838a2 | 1932 | if (cp0_perfcount_irq == cp0_compare_irq) |
3b1d4ed5 | 1933 | cp0_perfcount_irq = -1; |
c3e838a2 CD |
1934 | } else { |
1935 | cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; | |
c6a4ebb9 | 1936 | cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ; |
c3e838a2 | 1937 | cp0_perfcount_irq = -1; |
3b1d4ed5 RB |
1938 | } |
1939 | ||
41c594ab RB |
1940 | #ifdef CONFIG_MIPS_MT_SMTC |
1941 | } | |
1942 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 | 1943 | |
48c4ac97 DD |
1944 | if (!cpu_data[cpu].asid_cache) |
1945 | cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; | |
1da177e4 LT |
1946 | |
1947 | atomic_inc(&init_mm.mm_count); | |
1948 | current->active_mm = &init_mm; | |
1949 | BUG_ON(current->mm); | |
1950 | enter_lazy_tlb(&init_mm, current); | |
1951 | ||
41c594ab RB |
1952 | #ifdef CONFIG_MIPS_MT_SMTC |
1953 | if (bootTC) { | |
1954 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
6650df3c DD |
1955 | /* Boot CPU's cache setup in setup_arch(). */ |
1956 | if (!is_boot_cpu) | |
1957 | cpu_cache_init(); | |
41c594ab RB |
1958 | tlb_init(); |
1959 | #ifdef CONFIG_MIPS_MT_SMTC | |
6a05888d RB |
1960 | } else if (!secondaryTC) { |
1961 | /* | |
1962 | * First TC in non-boot VPE must do subset of tlb_init() | |
1963 | * for MMU countrol registers. | |
1964 | */ | |
1965 | write_c0_pagemask(PM_DEFAULT_MASK); | |
1966 | write_c0_wired(0); | |
41c594ab RB |
1967 | } |
1968 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
3d8bfdd0 | 1969 | TLBMISS_HANDLER_SETUP(); |
1da177e4 LT |
1970 | } |
1971 | ||
e01402b1 | 1972 | /* Install CPU exception handler */ |
078a55fc | 1973 | void set_handler(unsigned long offset, void *addr, unsigned long size) |
e01402b1 | 1974 | { |
2a0b24f5 SH |
1975 | #ifdef CONFIG_CPU_MICROMIPS |
1976 | memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size); | |
1977 | #else | |
e01402b1 | 1978 | memcpy((void *)(ebase + offset), addr, size); |
2a0b24f5 | 1979 | #endif |
e0cee3ee | 1980 | local_flush_icache_range(ebase + offset, ebase + offset + size); |
e01402b1 RB |
1981 | } |
1982 | ||
078a55fc | 1983 | static char panic_null_cerr[] = |
641e97f3 RB |
1984 | "Trying to set NULL cache error exception handler"; |
1985 | ||
42fe7ee3 RB |
1986 | /* |
1987 | * Install uncached CPU exception handler. | |
1988 | * This is suitable only for the cache error exception which is the only | |
1989 | * exception handler that is being run uncached. | |
1990 | */ | |
078a55fc | 1991 | void set_uncached_handler(unsigned long offset, void *addr, |
234fcd14 | 1992 | unsigned long size) |
e01402b1 | 1993 | { |
4f81b01a | 1994 | unsigned long uncached_ebase = CKSEG1ADDR(ebase); |
e01402b1 | 1995 | |
641e97f3 RB |
1996 | if (!addr) |
1997 | panic(panic_null_cerr); | |
1998 | ||
e01402b1 RB |
1999 | memcpy((void *)(uncached_ebase + offset), addr, size); |
2000 | } | |
2001 | ||
5b10496b AN |
2002 | static int __initdata rdhwr_noopt; |
2003 | static int __init set_rdhwr_noopt(char *str) | |
2004 | { | |
2005 | rdhwr_noopt = 1; | |
2006 | return 1; | |
2007 | } | |
2008 | ||
2009 | __setup("rdhwr_noopt", set_rdhwr_noopt); | |
2010 | ||
1da177e4 LT |
2011 | void __init trap_init(void) |
2012 | { | |
2a0b24f5 | 2013 | extern char except_vec3_generic; |
1da177e4 | 2014 | extern char except_vec4; |
2a0b24f5 | 2015 | extern char except_vec3_r4000; |
1da177e4 | 2016 | unsigned long i; |
c65a5480 AN |
2017 | |
2018 | check_wait(); | |
1da177e4 | 2019 | |
88547001 JW |
2020 | #if defined(CONFIG_KGDB) |
2021 | if (kgdb_early_setup) | |
70342287 | 2022 | return; /* Already done */ |
88547001 JW |
2023 | #endif |
2024 | ||
9fb4c2b9 CD |
2025 | if (cpu_has_veic || cpu_has_vint) { |
2026 | unsigned long size = 0x200 + VECTORSPACING*64; | |
2027 | ebase = (unsigned long) | |
2028 | __alloc_bootmem(size, 1 << fls(size), 0); | |
2029 | } else { | |
9843b030 SL |
2030 | #ifdef CONFIG_KVM_GUEST |
2031 | #define KVM_GUEST_KSEG0 0x40000000 | |
2032 | ebase = KVM_GUEST_KSEG0; | |
2033 | #else | |
2034 | ebase = CKSEG0; | |
2035 | #endif | |
566f74f6 DD |
2036 | if (cpu_has_mips_r2) |
2037 | ebase += (read_c0_ebase() & 0x3ffff000); | |
2038 | } | |
e01402b1 | 2039 | |
c6213c6c SH |
2040 | if (cpu_has_mmips) { |
2041 | unsigned int config3 = read_c0_config3(); | |
2042 | ||
2043 | if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) | |
2044 | write_c0_config3(config3 | MIPS_CONF3_ISA_OE); | |
2045 | else | |
2046 | write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE); | |
2047 | } | |
2048 | ||
6fb97eff KC |
2049 | if (board_ebase_setup) |
2050 | board_ebase_setup(); | |
6650df3c | 2051 | per_cpu_trap_init(true); |
1da177e4 LT |
2052 | |
2053 | /* | |
2054 | * Copy the generic exception handlers to their final destination. | |
2055 | * This will be overriden later as suitable for a particular | |
2056 | * configuration. | |
2057 | */ | |
e01402b1 | 2058 | set_handler(0x180, &except_vec3_generic, 0x80); |
1da177e4 LT |
2059 | |
2060 | /* | |
2061 | * Setup default vectors | |
2062 | */ | |
2063 | for (i = 0; i <= 31; i++) | |
2064 | set_except_vector(i, handle_reserved); | |
2065 | ||
2066 | /* | |
2067 | * Copy the EJTAG debug exception vector handler code to it's final | |
2068 | * destination. | |
2069 | */ | |
e01402b1 | 2070 | if (cpu_has_ejtag && board_ejtag_handler_setup) |
49a89efb | 2071 | board_ejtag_handler_setup(); |
1da177e4 LT |
2072 | |
2073 | /* | |
2074 | * Only some CPUs have the watch exceptions. | |
2075 | */ | |
2076 | if (cpu_has_watch) | |
2077 | set_except_vector(23, handle_watch); | |
2078 | ||
2079 | /* | |
e01402b1 | 2080 | * Initialise interrupt handlers |
1da177e4 | 2081 | */ |
e01402b1 RB |
2082 | if (cpu_has_veic || cpu_has_vint) { |
2083 | int nvec = cpu_has_veic ? 64 : 8; | |
2084 | for (i = 0; i < nvec; i++) | |
ff3eab2a | 2085 | set_vi_handler(i, NULL); |
e01402b1 RB |
2086 | } |
2087 | else if (cpu_has_divec) | |
2088 | set_handler(0x200, &except_vec4, 0x8); | |
1da177e4 LT |
2089 | |
2090 | /* | |
2091 | * Some CPUs can enable/disable for cache parity detection, but does | |
2092 | * it different ways. | |
2093 | */ | |
2094 | parity_protection_init(); | |
2095 | ||
2096 | /* | |
2097 | * The Data Bus Errors / Instruction Bus Errors are signaled | |
2098 | * by external hardware. Therefore these two exceptions | |
2099 | * may have board specific handlers. | |
2100 | */ | |
2101 | if (board_be_init) | |
2102 | board_be_init(); | |
2103 | ||
f94d9a8e RB |
2104 | set_except_vector(0, using_rollback_handler() ? rollback_handle_int |
2105 | : handle_int); | |
1da177e4 LT |
2106 | set_except_vector(1, handle_tlbm); |
2107 | set_except_vector(2, handle_tlbl); | |
2108 | set_except_vector(3, handle_tlbs); | |
2109 | ||
2110 | set_except_vector(4, handle_adel); | |
2111 | set_except_vector(5, handle_ades); | |
2112 | ||
2113 | set_except_vector(6, handle_ibe); | |
2114 | set_except_vector(7, handle_dbe); | |
2115 | ||
2116 | set_except_vector(8, handle_sys); | |
2117 | set_except_vector(9, handle_bp); | |
5b10496b AN |
2118 | set_except_vector(10, rdhwr_noopt ? handle_ri : |
2119 | (cpu_has_vtag_icache ? | |
2120 | handle_ri_rdhwr_vivt : handle_ri_rdhwr)); | |
1da177e4 LT |
2121 | set_except_vector(11, handle_cpu); |
2122 | set_except_vector(12, handle_ov); | |
2123 | set_except_vector(13, handle_tr); | |
2bcb3fbc | 2124 | set_except_vector(14, handle_msa_fpe); |
1da177e4 | 2125 | |
10cc3529 RB |
2126 | if (current_cpu_type() == CPU_R6000 || |
2127 | current_cpu_type() == CPU_R6000A) { | |
1da177e4 LT |
2128 | /* |
2129 | * The R6000 is the only R-series CPU that features a machine | |
2130 | * check exception (similar to the R4000 cache error) and | |
2131 | * unaligned ldc1/sdc1 exception. The handlers have not been | |
70342287 | 2132 | * written yet. Well, anyway there is no R6000 machine on the |
1da177e4 LT |
2133 | * current list of targets for Linux/MIPS. |
2134 | * (Duh, crap, there is someone with a triple R6k machine) | |
2135 | */ | |
2136 | //set_except_vector(14, handle_mc); | |
2137 | //set_except_vector(15, handle_ndc); | |
2138 | } | |
2139 | ||
e01402b1 RB |
2140 | |
2141 | if (board_nmi_handler_setup) | |
2142 | board_nmi_handler_setup(); | |
2143 | ||
e50c0a8f RB |
2144 | if (cpu_has_fpu && !cpu_has_nofpuex) |
2145 | set_except_vector(15, handle_fpe); | |
2146 | ||
75b5b5e0 | 2147 | set_except_vector(16, handle_ftlb); |
1db1af84 | 2148 | set_except_vector(21, handle_msa); |
e50c0a8f RB |
2149 | set_except_vector(22, handle_mdmx); |
2150 | ||
2151 | if (cpu_has_mcheck) | |
2152 | set_except_vector(24, handle_mcheck); | |
2153 | ||
340ee4b9 RB |
2154 | if (cpu_has_mipsmt) |
2155 | set_except_vector(25, handle_mt); | |
2156 | ||
acaec427 | 2157 | set_except_vector(26, handle_dsp); |
e50c0a8f | 2158 | |
fcbf1dfd DD |
2159 | if (board_cache_error_setup) |
2160 | board_cache_error_setup(); | |
2161 | ||
e50c0a8f RB |
2162 | if (cpu_has_vce) |
2163 | /* Special exception: R4[04]00 uses also the divec space. */ | |
2a0b24f5 | 2164 | set_handler(0x180, &except_vec3_r4000, 0x100); |
e50c0a8f | 2165 | else if (cpu_has_4kex) |
2a0b24f5 | 2166 | set_handler(0x180, &except_vec3_generic, 0x80); |
e50c0a8f | 2167 | else |
2a0b24f5 | 2168 | set_handler(0x080, &except_vec3_generic, 0x80); |
e50c0a8f | 2169 | |
e0cee3ee | 2170 | local_flush_icache_range(ebase, ebase + 0x400); |
0510617b TB |
2171 | |
2172 | sort_extable(__start___dbe_table, __stop___dbe_table); | |
69f3a7de | 2173 | |
4483b159 | 2174 | cu2_notifier(default_cu2_call, 0x80000000); /* Run last */ |
1da177e4 | 2175 | } |