Commit | Line | Data |
---|---|---|
6aa3524c DD |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2008 David Daney | |
7 | */ | |
8 | ||
9 | #include <linux/sched.h> | |
10 | ||
11 | #include <asm/processor.h> | |
12 | #include <asm/watch.h> | |
13 | ||
14 | /* | |
70342287 | 15 | * Install the watch registers for the current thread. A maximum of |
6aa3524c DD |
16 | * four registers are installed although the machine may have more. |
17 | */ | |
a7e89326 | 18 | void mips_install_watch_registers(struct task_struct *t) |
6aa3524c | 19 | { |
a7e89326 | 20 | struct mips3264_watch_reg_state *watches = &t->thread.watch.mips3264; |
6aa3524c DD |
21 | switch (current_cpu_data.watch_reg_use_cnt) { |
22 | default: | |
23 | BUG(); | |
24 | case 4: | |
25 | write_c0_watchlo3(watches->watchlo[3]); | |
26 | /* Write 1 to the I, R, and W bits to clear them, and | |
27 | 1 to G so all ASIDs are trapped. */ | |
50af501c JH |
28 | write_c0_watchhi3(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW | |
29 | watches->watchhi[3]); | |
6aa3524c DD |
30 | case 3: |
31 | write_c0_watchlo2(watches->watchlo[2]); | |
50af501c JH |
32 | write_c0_watchhi2(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW | |
33 | watches->watchhi[2]); | |
6aa3524c DD |
34 | case 2: |
35 | write_c0_watchlo1(watches->watchlo[1]); | |
50af501c JH |
36 | write_c0_watchhi1(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW | |
37 | watches->watchhi[1]); | |
6aa3524c DD |
38 | case 1: |
39 | write_c0_watchlo0(watches->watchlo[0]); | |
50af501c JH |
40 | write_c0_watchhi0(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW | |
41 | watches->watchhi[0]); | |
6aa3524c DD |
42 | } |
43 | } | |
44 | ||
45 | /* | |
46 | * Read back the watchhi registers so the user space debugger has | |
47 | * access to the I, R, and W bits. A maximum of four registers are | |
48 | * read although the machine may have more. | |
49 | */ | |
50 | void mips_read_watch_registers(void) | |
51 | { | |
52 | struct mips3264_watch_reg_state *watches = | |
53 | ¤t->thread.watch.mips3264; | |
54 | switch (current_cpu_data.watch_reg_use_cnt) { | |
55 | default: | |
56 | BUG(); | |
57 | case 4: | |
50af501c JH |
58 | watches->watchhi[3] = (read_c0_watchhi3() & |
59 | (MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW)); | |
6aa3524c | 60 | case 3: |
50af501c JH |
61 | watches->watchhi[2] = (read_c0_watchhi2() & |
62 | (MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW)); | |
6aa3524c | 63 | case 2: |
50af501c JH |
64 | watches->watchhi[1] = (read_c0_watchhi1() & |
65 | (MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW)); | |
6aa3524c | 66 | case 1: |
50af501c JH |
67 | watches->watchhi[0] = (read_c0_watchhi0() & |
68 | (MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW)); | |
6aa3524c DD |
69 | } |
70 | if (current_cpu_data.watch_reg_use_cnt == 1 && | |
50af501c | 71 | (watches->watchhi[0] & MIPS_WATCHHI_IRW) == 0) { |
6aa3524c DD |
72 | /* Pathological case of release 1 architecture that |
73 | * doesn't set the condition bits. We assume that | |
74 | * since we got here, the watch condition was met and | |
75 | * signal that the conditions requested in watchlo | |
76 | * were met. */ | |
50af501c | 77 | watches->watchhi[0] |= (watches->watchlo[0] & MIPS_WATCHHI_IRW); |
6aa3524c DD |
78 | } |
79 | } | |
80 | ||
81 | /* | |
70342287 | 82 | * Disable all watch registers. Although only four registers are |
6aa3524c DD |
83 | * installed, all are cleared to eliminate the possibility of endless |
84 | * looping in the watch handler. | |
85 | */ | |
86 | void mips_clear_watch_registers(void) | |
87 | { | |
88 | switch (current_cpu_data.watch_reg_count) { | |
89 | default: | |
90 | BUG(); | |
91 | case 8: | |
92 | write_c0_watchlo7(0); | |
93 | case 7: | |
94 | write_c0_watchlo6(0); | |
95 | case 6: | |
96 | write_c0_watchlo5(0); | |
97 | case 5: | |
98 | write_c0_watchlo4(0); | |
99 | case 4: | |
100 | write_c0_watchlo3(0); | |
101 | case 3: | |
102 | write_c0_watchlo2(0); | |
103 | case 2: | |
104 | write_c0_watchlo1(0); | |
105 | case 1: | |
106 | write_c0_watchlo0(0); | |
107 | } | |
108 | } | |
109 | ||
078a55fc | 110 | void mips_probe_watch_registers(struct cpuinfo_mips *c) |
6aa3524c DD |
111 | { |
112 | unsigned int t; | |
113 | ||
114 | if ((c->options & MIPS_CPU_WATCH) == 0) | |
115 | return; | |
116 | /* | |
117 | * Check which of the I,R and W bits are supported, then | |
118 | * disable the register. | |
119 | */ | |
50af501c | 120 | write_c0_watchlo0(MIPS_WATCHLO_IRW); |
c5e1503f | 121 | back_to_back_c0_hazard(); |
6aa3524c DD |
122 | t = read_c0_watchlo0(); |
123 | write_c0_watchlo0(0); | |
50af501c | 124 | c->watch_reg_masks[0] = t & MIPS_WATCHLO_IRW; |
6aa3524c DD |
125 | |
126 | /* Write the mask bits and read them back to determine which | |
127 | * can be used. */ | |
128 | c->watch_reg_count = 1; | |
129 | c->watch_reg_use_cnt = 1; | |
130 | t = read_c0_watchhi0(); | |
50af501c | 131 | write_c0_watchhi0(t | MIPS_WATCHHI_MASK); |
c5e1503f | 132 | back_to_back_c0_hazard(); |
6aa3524c | 133 | t = read_c0_watchhi0(); |
50af501c JH |
134 | c->watch_reg_masks[0] |= (t & MIPS_WATCHHI_MASK); |
135 | if ((t & MIPS_WATCHHI_M) == 0) | |
6aa3524c DD |
136 | return; |
137 | ||
50af501c | 138 | write_c0_watchlo1(MIPS_WATCHLO_IRW); |
c5e1503f | 139 | back_to_back_c0_hazard(); |
6aa3524c DD |
140 | t = read_c0_watchlo1(); |
141 | write_c0_watchlo1(0); | |
50af501c | 142 | c->watch_reg_masks[1] = t & MIPS_WATCHLO_IRW; |
6aa3524c DD |
143 | |
144 | c->watch_reg_count = 2; | |
145 | c->watch_reg_use_cnt = 2; | |
146 | t = read_c0_watchhi1(); | |
50af501c | 147 | write_c0_watchhi1(t | MIPS_WATCHHI_MASK); |
c5e1503f | 148 | back_to_back_c0_hazard(); |
6aa3524c | 149 | t = read_c0_watchhi1(); |
50af501c JH |
150 | c->watch_reg_masks[1] |= (t & MIPS_WATCHHI_MASK); |
151 | if ((t & MIPS_WATCHHI_M) == 0) | |
6aa3524c DD |
152 | return; |
153 | ||
50af501c | 154 | write_c0_watchlo2(MIPS_WATCHLO_IRW); |
c5e1503f | 155 | back_to_back_c0_hazard(); |
6aa3524c DD |
156 | t = read_c0_watchlo2(); |
157 | write_c0_watchlo2(0); | |
50af501c | 158 | c->watch_reg_masks[2] = t & MIPS_WATCHLO_IRW; |
6aa3524c DD |
159 | |
160 | c->watch_reg_count = 3; | |
161 | c->watch_reg_use_cnt = 3; | |
162 | t = read_c0_watchhi2(); | |
50af501c | 163 | write_c0_watchhi2(t | MIPS_WATCHHI_MASK); |
c5e1503f | 164 | back_to_back_c0_hazard(); |
6aa3524c | 165 | t = read_c0_watchhi2(); |
50af501c JH |
166 | c->watch_reg_masks[2] |= (t & MIPS_WATCHHI_MASK); |
167 | if ((t & MIPS_WATCHHI_M) == 0) | |
6aa3524c DD |
168 | return; |
169 | ||
50af501c | 170 | write_c0_watchlo3(MIPS_WATCHLO_IRW); |
c5e1503f | 171 | back_to_back_c0_hazard(); |
6aa3524c DD |
172 | t = read_c0_watchlo3(); |
173 | write_c0_watchlo3(0); | |
50af501c | 174 | c->watch_reg_masks[3] = t & MIPS_WATCHLO_IRW; |
6aa3524c DD |
175 | |
176 | c->watch_reg_count = 4; | |
177 | c->watch_reg_use_cnt = 4; | |
178 | t = read_c0_watchhi3(); | |
50af501c | 179 | write_c0_watchhi3(t | MIPS_WATCHHI_MASK); |
c5e1503f | 180 | back_to_back_c0_hazard(); |
6aa3524c | 181 | t = read_c0_watchhi3(); |
50af501c JH |
182 | c->watch_reg_masks[3] |= (t & MIPS_WATCHHI_MASK); |
183 | if ((t & MIPS_WATCHHI_M) == 0) | |
6aa3524c DD |
184 | return; |
185 | ||
186 | /* We use at most 4, but probe and report up to 8. */ | |
187 | c->watch_reg_count = 5; | |
188 | t = read_c0_watchhi4(); | |
50af501c | 189 | if ((t & MIPS_WATCHHI_M) == 0) |
6aa3524c DD |
190 | return; |
191 | ||
192 | c->watch_reg_count = 6; | |
193 | t = read_c0_watchhi5(); | |
50af501c | 194 | if ((t & MIPS_WATCHHI_M) == 0) |
6aa3524c DD |
195 | return; |
196 | ||
197 | c->watch_reg_count = 7; | |
198 | t = read_c0_watchhi6(); | |
50af501c | 199 | if ((t & MIPS_WATCHHI_M) == 0) |
6aa3524c DD |
200 | return; |
201 | ||
202 | c->watch_reg_count = 8; | |
203 | } |