Commit | Line | Data |
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e685c689 | 1 | /* |
d116e812 DCZ |
2 | * This file is subject to the terms and conditions of the GNU General Public |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * KVM/MIPS: Instruction/Exception emulation | |
7 | * | |
8 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. | |
9 | * Authors: Sanjay Lal <sanjayl@kymasys.com> | |
10 | */ | |
e685c689 SL |
11 | |
12 | #include <linux/errno.h> | |
13 | #include <linux/err.h> | |
e30492bb | 14 | #include <linux/ktime.h> |
e685c689 SL |
15 | #include <linux/kvm_host.h> |
16 | #include <linux/module.h> | |
17 | #include <linux/vmalloc.h> | |
18 | #include <linux/fs.h> | |
19 | #include <linux/bootmem.h> | |
20 | #include <linux/random.h> | |
21 | #include <asm/page.h> | |
22 | #include <asm/cacheflush.h> | |
f4956f62 | 23 | #include <asm/cacheops.h> |
e685c689 SL |
24 | #include <asm/cpu-info.h> |
25 | #include <asm/mmu_context.h> | |
26 | #include <asm/tlbflush.h> | |
27 | #include <asm/inst.h> | |
28 | ||
29 | #undef CONFIG_MIPS_MT | |
30 | #include <asm/r4kcache.h> | |
31 | #define CONFIG_MIPS_MT | |
32 | ||
d7d5b05f DCZ |
33 | #include "interrupt.h" |
34 | #include "commpage.h" | |
e685c689 SL |
35 | |
36 | #include "trace.h" | |
37 | ||
38 | /* | |
39 | * Compute the return address and do emulate branch simulation, if required. | |
40 | * This function should be called only in branch delay slot active. | |
41 | */ | |
42 | unsigned long kvm_compute_return_epc(struct kvm_vcpu *vcpu, | |
43 | unsigned long instpc) | |
44 | { | |
45 | unsigned int dspcontrol; | |
46 | union mips_instruction insn; | |
47 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
48 | long epc = instpc; | |
49 | long nextpc = KVM_INVALID_INST; | |
50 | ||
51 | if (epc & 3) | |
52 | goto unaligned; | |
53 | ||
d116e812 | 54 | /* Read the instruction */ |
8cffd197 | 55 | insn.word = kvm_get_inst((u32 *) epc, vcpu); |
e685c689 SL |
56 | |
57 | if (insn.word == KVM_INVALID_INST) | |
58 | return KVM_INVALID_INST; | |
59 | ||
60 | switch (insn.i_format.opcode) { | |
d116e812 | 61 | /* jr and jalr are in r_format format. */ |
e685c689 SL |
62 | case spec_op: |
63 | switch (insn.r_format.func) { | |
64 | case jalr_op: | |
65 | arch->gprs[insn.r_format.rd] = epc + 8; | |
66 | /* Fall through */ | |
67 | case jr_op: | |
68 | nextpc = arch->gprs[insn.r_format.rs]; | |
69 | break; | |
70 | } | |
71 | break; | |
72 | ||
73 | /* | |
74 | * This group contains: | |
75 | * bltz_op, bgez_op, bltzl_op, bgezl_op, | |
76 | * bltzal_op, bgezal_op, bltzall_op, bgezall_op. | |
77 | */ | |
78 | case bcond_op: | |
79 | switch (insn.i_format.rt) { | |
80 | case bltz_op: | |
81 | case bltzl_op: | |
82 | if ((long)arch->gprs[insn.i_format.rs] < 0) | |
83 | epc = epc + 4 + (insn.i_format.simmediate << 2); | |
84 | else | |
85 | epc += 8; | |
86 | nextpc = epc; | |
87 | break; | |
88 | ||
89 | case bgez_op: | |
90 | case bgezl_op: | |
91 | if ((long)arch->gprs[insn.i_format.rs] >= 0) | |
92 | epc = epc + 4 + (insn.i_format.simmediate << 2); | |
93 | else | |
94 | epc += 8; | |
95 | nextpc = epc; | |
96 | break; | |
97 | ||
98 | case bltzal_op: | |
99 | case bltzall_op: | |
100 | arch->gprs[31] = epc + 8; | |
101 | if ((long)arch->gprs[insn.i_format.rs] < 0) | |
102 | epc = epc + 4 + (insn.i_format.simmediate << 2); | |
103 | else | |
104 | epc += 8; | |
105 | nextpc = epc; | |
106 | break; | |
107 | ||
108 | case bgezal_op: | |
109 | case bgezall_op: | |
110 | arch->gprs[31] = epc + 8; | |
111 | if ((long)arch->gprs[insn.i_format.rs] >= 0) | |
112 | epc = epc + 4 + (insn.i_format.simmediate << 2); | |
113 | else | |
114 | epc += 8; | |
115 | nextpc = epc; | |
116 | break; | |
117 | case bposge32_op: | |
118 | if (!cpu_has_dsp) | |
119 | goto sigill; | |
120 | ||
121 | dspcontrol = rddsp(0x01); | |
122 | ||
d116e812 | 123 | if (dspcontrol >= 32) |
e685c689 | 124 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
d116e812 | 125 | else |
e685c689 SL |
126 | epc += 8; |
127 | nextpc = epc; | |
128 | break; | |
129 | } | |
130 | break; | |
131 | ||
d116e812 | 132 | /* These are unconditional and in j_format. */ |
e685c689 SL |
133 | case jal_op: |
134 | arch->gprs[31] = instpc + 8; | |
135 | case j_op: | |
136 | epc += 4; | |
137 | epc >>= 28; | |
138 | epc <<= 28; | |
139 | epc |= (insn.j_format.target << 2); | |
140 | nextpc = epc; | |
141 | break; | |
142 | ||
d116e812 | 143 | /* These are conditional and in i_format. */ |
e685c689 SL |
144 | case beq_op: |
145 | case beql_op: | |
146 | if (arch->gprs[insn.i_format.rs] == | |
147 | arch->gprs[insn.i_format.rt]) | |
148 | epc = epc + 4 + (insn.i_format.simmediate << 2); | |
149 | else | |
150 | epc += 8; | |
151 | nextpc = epc; | |
152 | break; | |
153 | ||
154 | case bne_op: | |
155 | case bnel_op: | |
156 | if (arch->gprs[insn.i_format.rs] != | |
157 | arch->gprs[insn.i_format.rt]) | |
158 | epc = epc + 4 + (insn.i_format.simmediate << 2); | |
159 | else | |
160 | epc += 8; | |
161 | nextpc = epc; | |
162 | break; | |
163 | ||
164 | case blez_op: /* not really i_format */ | |
165 | case blezl_op: | |
166 | /* rt field assumed to be zero */ | |
167 | if ((long)arch->gprs[insn.i_format.rs] <= 0) | |
168 | epc = epc + 4 + (insn.i_format.simmediate << 2); | |
169 | else | |
170 | epc += 8; | |
171 | nextpc = epc; | |
172 | break; | |
173 | ||
174 | case bgtz_op: | |
175 | case bgtzl_op: | |
176 | /* rt field assumed to be zero */ | |
177 | if ((long)arch->gprs[insn.i_format.rs] > 0) | |
178 | epc = epc + 4 + (insn.i_format.simmediate << 2); | |
179 | else | |
180 | epc += 8; | |
181 | nextpc = epc; | |
182 | break; | |
183 | ||
d116e812 | 184 | /* And now the FPA/cp1 branch instructions. */ |
e685c689 | 185 | case cop1_op: |
6ad78a5c | 186 | kvm_err("%s: unsupported cop1_op\n", __func__); |
e685c689 SL |
187 | break; |
188 | } | |
189 | ||
190 | return nextpc; | |
191 | ||
192 | unaligned: | |
6ad78a5c | 193 | kvm_err("%s: unaligned epc\n", __func__); |
e685c689 SL |
194 | return nextpc; |
195 | ||
196 | sigill: | |
6ad78a5c | 197 | kvm_err("%s: DSP branch but not DSP ASE\n", __func__); |
e685c689 SL |
198 | return nextpc; |
199 | } | |
200 | ||
bdb7ed86 | 201 | enum emulation_result update_pc(struct kvm_vcpu *vcpu, u32 cause) |
e685c689 SL |
202 | { |
203 | unsigned long branch_pc; | |
204 | enum emulation_result er = EMULATE_DONE; | |
205 | ||
206 | if (cause & CAUSEF_BD) { | |
207 | branch_pc = kvm_compute_return_epc(vcpu, vcpu->arch.pc); | |
208 | if (branch_pc == KVM_INVALID_INST) { | |
209 | er = EMULATE_FAIL; | |
210 | } else { | |
211 | vcpu->arch.pc = branch_pc; | |
d116e812 DCZ |
212 | kvm_debug("BD update_pc(): New PC: %#lx\n", |
213 | vcpu->arch.pc); | |
e685c689 SL |
214 | } |
215 | } else | |
216 | vcpu->arch.pc += 4; | |
217 | ||
218 | kvm_debug("update_pc(): New PC: %#lx\n", vcpu->arch.pc); | |
219 | ||
220 | return er; | |
221 | } | |
222 | ||
e30492bb JH |
223 | /** |
224 | * kvm_mips_count_disabled() - Find whether the CP0_Count timer is disabled. | |
225 | * @vcpu: Virtual CPU. | |
e685c689 | 226 | * |
f8239342 JH |
227 | * Returns: 1 if the CP0_Count timer is disabled by either the guest |
228 | * CP0_Cause.DC bit or the count_ctl.DC bit. | |
e30492bb | 229 | * 0 otherwise (in which case CP0_Count timer is running). |
e685c689 | 230 | */ |
e30492bb | 231 | static inline int kvm_mips_count_disabled(struct kvm_vcpu *vcpu) |
e685c689 SL |
232 | { |
233 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
d116e812 | 234 | |
f8239342 JH |
235 | return (vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) || |
236 | (kvm_read_c0_guest_cause(cop0) & CAUSEF_DC); | |
e30492bb | 237 | } |
e685c689 | 238 | |
e30492bb JH |
239 | /** |
240 | * kvm_mips_ktime_to_count() - Scale ktime_t to a 32-bit count. | |
241 | * | |
242 | * Caches the dynamic nanosecond bias in vcpu->arch.count_dyn_bias. | |
243 | * | |
244 | * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running). | |
245 | */ | |
bdb7ed86 | 246 | static u32 kvm_mips_ktime_to_count(struct kvm_vcpu *vcpu, ktime_t now) |
e30492bb JH |
247 | { |
248 | s64 now_ns, periods; | |
249 | u64 delta; | |
250 | ||
251 | now_ns = ktime_to_ns(now); | |
252 | delta = now_ns + vcpu->arch.count_dyn_bias; | |
253 | ||
254 | if (delta >= vcpu->arch.count_period) { | |
255 | /* If delta is out of safe range the bias needs adjusting */ | |
256 | periods = div64_s64(now_ns, vcpu->arch.count_period); | |
257 | vcpu->arch.count_dyn_bias = -periods * vcpu->arch.count_period; | |
258 | /* Recalculate delta with new bias */ | |
259 | delta = now_ns + vcpu->arch.count_dyn_bias; | |
e685c689 SL |
260 | } |
261 | ||
e30492bb JH |
262 | /* |
263 | * We've ensured that: | |
264 | * delta < count_period | |
265 | * | |
266 | * Therefore the intermediate delta*count_hz will never overflow since | |
267 | * at the boundary condition: | |
268 | * delta = count_period | |
269 | * delta = NSEC_PER_SEC * 2^32 / count_hz | |
270 | * delta * count_hz = NSEC_PER_SEC * 2^32 | |
271 | */ | |
272 | return div_u64(delta * vcpu->arch.count_hz, NSEC_PER_SEC); | |
273 | } | |
274 | ||
f8239342 JH |
275 | /** |
276 | * kvm_mips_count_time() - Get effective current time. | |
277 | * @vcpu: Virtual CPU. | |
278 | * | |
279 | * Get effective monotonic ktime. This is usually a straightforward ktime_get(), | |
280 | * except when the master disable bit is set in count_ctl, in which case it is | |
281 | * count_resume, i.e. the time that the count was disabled. | |
282 | * | |
283 | * Returns: Effective monotonic ktime for CP0_Count. | |
284 | */ | |
285 | static inline ktime_t kvm_mips_count_time(struct kvm_vcpu *vcpu) | |
286 | { | |
287 | if (unlikely(vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) | |
288 | return vcpu->arch.count_resume; | |
289 | ||
290 | return ktime_get(); | |
291 | } | |
292 | ||
e30492bb JH |
293 | /** |
294 | * kvm_mips_read_count_running() - Read the current count value as if running. | |
295 | * @vcpu: Virtual CPU. | |
296 | * @now: Kernel time to read CP0_Count at. | |
297 | * | |
298 | * Returns the current guest CP0_Count register at time @now and handles if the | |
299 | * timer interrupt is pending and hasn't been handled yet. | |
300 | * | |
301 | * Returns: The current value of the guest CP0_Count register. | |
302 | */ | |
bdb7ed86 | 303 | static u32 kvm_mips_read_count_running(struct kvm_vcpu *vcpu, ktime_t now) |
e30492bb | 304 | { |
4355c44f JH |
305 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
306 | ktime_t expires, threshold; | |
8cffd197 | 307 | u32 count, compare; |
e30492bb JH |
308 | int running; |
309 | ||
4355c44f JH |
310 | /* Calculate the biased and scaled guest CP0_Count */ |
311 | count = vcpu->arch.count_bias + kvm_mips_ktime_to_count(vcpu, now); | |
312 | compare = kvm_read_c0_guest_compare(cop0); | |
313 | ||
314 | /* | |
315 | * Find whether CP0_Count has reached the closest timer interrupt. If | |
316 | * not, we shouldn't inject it. | |
317 | */ | |
8cffd197 | 318 | if ((s32)(count - compare) < 0) |
4355c44f JH |
319 | return count; |
320 | ||
321 | /* | |
322 | * The CP0_Count we're going to return has already reached the closest | |
323 | * timer interrupt. Quickly check if it really is a new interrupt by | |
324 | * looking at whether the interval until the hrtimer expiry time is | |
325 | * less than 1/4 of the timer period. | |
326 | */ | |
e30492bb | 327 | expires = hrtimer_get_expires(&vcpu->arch.comparecount_timer); |
4355c44f JH |
328 | threshold = ktime_add_ns(now, vcpu->arch.count_period / 4); |
329 | if (ktime_before(expires, threshold)) { | |
e30492bb JH |
330 | /* |
331 | * Cancel it while we handle it so there's no chance of | |
332 | * interference with the timeout handler. | |
333 | */ | |
334 | running = hrtimer_cancel(&vcpu->arch.comparecount_timer); | |
335 | ||
336 | /* Nothing should be waiting on the timeout */ | |
337 | kvm_mips_callbacks->queue_timer_int(vcpu); | |
338 | ||
339 | /* | |
340 | * Restart the timer if it was running based on the expiry time | |
341 | * we read, so that we don't push it back 2 periods. | |
342 | */ | |
343 | if (running) { | |
344 | expires = ktime_add_ns(expires, | |
345 | vcpu->arch.count_period); | |
346 | hrtimer_start(&vcpu->arch.comparecount_timer, expires, | |
347 | HRTIMER_MODE_ABS); | |
348 | } | |
349 | } | |
350 | ||
4355c44f | 351 | return count; |
e30492bb JH |
352 | } |
353 | ||
354 | /** | |
355 | * kvm_mips_read_count() - Read the current count value. | |
356 | * @vcpu: Virtual CPU. | |
357 | * | |
358 | * Read the current guest CP0_Count value, taking into account whether the timer | |
359 | * is stopped. | |
360 | * | |
361 | * Returns: The current guest CP0_Count value. | |
362 | */ | |
bdb7ed86 | 363 | u32 kvm_mips_read_count(struct kvm_vcpu *vcpu) |
e30492bb JH |
364 | { |
365 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
366 | ||
367 | /* If count disabled just read static copy of count */ | |
368 | if (kvm_mips_count_disabled(vcpu)) | |
369 | return kvm_read_c0_guest_count(cop0); | |
370 | ||
371 | return kvm_mips_read_count_running(vcpu, ktime_get()); | |
372 | } | |
373 | ||
374 | /** | |
375 | * kvm_mips_freeze_hrtimer() - Safely stop the hrtimer. | |
376 | * @vcpu: Virtual CPU. | |
377 | * @count: Output pointer for CP0_Count value at point of freeze. | |
378 | * | |
379 | * Freeze the hrtimer safely and return both the ktime and the CP0_Count value | |
380 | * at the point it was frozen. It is guaranteed that any pending interrupts at | |
381 | * the point it was frozen are handled, and none after that point. | |
382 | * | |
383 | * This is useful where the time/CP0_Count is needed in the calculation of the | |
384 | * new parameters. | |
385 | * | |
386 | * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running). | |
387 | * | |
388 | * Returns: The ktime at the point of freeze. | |
389 | */ | |
bdb7ed86 | 390 | static ktime_t kvm_mips_freeze_hrtimer(struct kvm_vcpu *vcpu, u32 *count) |
e30492bb JH |
391 | { |
392 | ktime_t now; | |
393 | ||
394 | /* stop hrtimer before finding time */ | |
395 | hrtimer_cancel(&vcpu->arch.comparecount_timer); | |
396 | now = ktime_get(); | |
397 | ||
398 | /* find count at this point and handle pending hrtimer */ | |
399 | *count = kvm_mips_read_count_running(vcpu, now); | |
400 | ||
401 | return now; | |
402 | } | |
403 | ||
e30492bb JH |
404 | /** |
405 | * kvm_mips_resume_hrtimer() - Resume hrtimer, updating expiry. | |
406 | * @vcpu: Virtual CPU. | |
407 | * @now: ktime at point of resume. | |
408 | * @count: CP0_Count at point of resume. | |
409 | * | |
410 | * Resumes the timer and updates the timer expiry based on @now and @count. | |
411 | * This can be used in conjunction with kvm_mips_freeze_timer() when timer | |
412 | * parameters need to be changed. | |
413 | * | |
414 | * It is guaranteed that a timer interrupt immediately after resume will be | |
415 | * handled, but not if CP_Compare is exactly at @count. That case is already | |
416 | * handled by kvm_mips_freeze_timer(). | |
417 | * | |
418 | * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running). | |
419 | */ | |
420 | static void kvm_mips_resume_hrtimer(struct kvm_vcpu *vcpu, | |
bdb7ed86 | 421 | ktime_t now, u32 count) |
e30492bb JH |
422 | { |
423 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
8cffd197 | 424 | u32 compare; |
e30492bb JH |
425 | u64 delta; |
426 | ktime_t expire; | |
427 | ||
428 | /* Calculate timeout (wrap 0 to 2^32) */ | |
429 | compare = kvm_read_c0_guest_compare(cop0); | |
8cffd197 | 430 | delta = (u64)(u32)(compare - count - 1) + 1; |
e30492bb JH |
431 | delta = div_u64(delta * NSEC_PER_SEC, vcpu->arch.count_hz); |
432 | expire = ktime_add_ns(now, delta); | |
433 | ||
434 | /* Update hrtimer to use new timeout */ | |
435 | hrtimer_cancel(&vcpu->arch.comparecount_timer); | |
436 | hrtimer_start(&vcpu->arch.comparecount_timer, expire, HRTIMER_MODE_ABS); | |
437 | } | |
438 | ||
e30492bb JH |
439 | /** |
440 | * kvm_mips_write_count() - Modify the count and update timer. | |
441 | * @vcpu: Virtual CPU. | |
442 | * @count: Guest CP0_Count value to set. | |
443 | * | |
444 | * Sets the CP0_Count value and updates the timer accordingly. | |
445 | */ | |
bdb7ed86 | 446 | void kvm_mips_write_count(struct kvm_vcpu *vcpu, u32 count) |
e30492bb JH |
447 | { |
448 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
449 | ktime_t now; | |
450 | ||
451 | /* Calculate bias */ | |
f8239342 | 452 | now = kvm_mips_count_time(vcpu); |
e30492bb JH |
453 | vcpu->arch.count_bias = count - kvm_mips_ktime_to_count(vcpu, now); |
454 | ||
455 | if (kvm_mips_count_disabled(vcpu)) | |
456 | /* The timer's disabled, adjust the static count */ | |
457 | kvm_write_c0_guest_count(cop0, count); | |
458 | else | |
459 | /* Update timeout */ | |
460 | kvm_mips_resume_hrtimer(vcpu, now, count); | |
461 | } | |
462 | ||
463 | /** | |
464 | * kvm_mips_init_count() - Initialise timer. | |
465 | * @vcpu: Virtual CPU. | |
466 | * | |
467 | * Initialise the timer to a sensible frequency, namely 100MHz, zero it, and set | |
468 | * it going if it's enabled. | |
469 | */ | |
470 | void kvm_mips_init_count(struct kvm_vcpu *vcpu) | |
471 | { | |
472 | /* 100 MHz */ | |
473 | vcpu->arch.count_hz = 100*1000*1000; | |
474 | vcpu->arch.count_period = div_u64((u64)NSEC_PER_SEC << 32, | |
475 | vcpu->arch.count_hz); | |
476 | vcpu->arch.count_dyn_bias = 0; | |
477 | ||
478 | /* Starting at 0 */ | |
479 | kvm_mips_write_count(vcpu, 0); | |
480 | } | |
481 | ||
f74a8e22 JH |
482 | /** |
483 | * kvm_mips_set_count_hz() - Update the frequency of the timer. | |
484 | * @vcpu: Virtual CPU. | |
485 | * @count_hz: Frequency of CP0_Count timer in Hz. | |
486 | * | |
487 | * Change the frequency of the CP0_Count timer. This is done atomically so that | |
488 | * CP0_Count is continuous and no timer interrupt is lost. | |
489 | * | |
490 | * Returns: -EINVAL if @count_hz is out of range. | |
491 | * 0 on success. | |
492 | */ | |
493 | int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz) | |
494 | { | |
495 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
496 | int dc; | |
497 | ktime_t now; | |
498 | u32 count; | |
499 | ||
500 | /* ensure the frequency is in a sensible range... */ | |
501 | if (count_hz <= 0 || count_hz > NSEC_PER_SEC) | |
502 | return -EINVAL; | |
503 | /* ... and has actually changed */ | |
504 | if (vcpu->arch.count_hz == count_hz) | |
505 | return 0; | |
506 | ||
507 | /* Safely freeze timer so we can keep it continuous */ | |
508 | dc = kvm_mips_count_disabled(vcpu); | |
509 | if (dc) { | |
510 | now = kvm_mips_count_time(vcpu); | |
511 | count = kvm_read_c0_guest_count(cop0); | |
512 | } else { | |
513 | now = kvm_mips_freeze_hrtimer(vcpu, &count); | |
514 | } | |
515 | ||
516 | /* Update the frequency */ | |
517 | vcpu->arch.count_hz = count_hz; | |
518 | vcpu->arch.count_period = div_u64((u64)NSEC_PER_SEC << 32, count_hz); | |
519 | vcpu->arch.count_dyn_bias = 0; | |
520 | ||
521 | /* Calculate adjusted bias so dynamic count is unchanged */ | |
522 | vcpu->arch.count_bias = count - kvm_mips_ktime_to_count(vcpu, now); | |
523 | ||
524 | /* Update and resume hrtimer */ | |
525 | if (!dc) | |
526 | kvm_mips_resume_hrtimer(vcpu, now, count); | |
527 | return 0; | |
528 | } | |
529 | ||
e30492bb JH |
530 | /** |
531 | * kvm_mips_write_compare() - Modify compare and update timer. | |
532 | * @vcpu: Virtual CPU. | |
533 | * @compare: New CP0_Compare value. | |
b45bacd2 | 534 | * @ack: Whether to acknowledge timer interrupt. |
e30492bb JH |
535 | * |
536 | * Update CP0_Compare to a new value and update the timeout. | |
b45bacd2 JH |
537 | * If @ack, atomically acknowledge any pending timer interrupt, otherwise ensure |
538 | * any pending timer interrupt is preserved. | |
e30492bb | 539 | */ |
bdb7ed86 | 540 | void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack) |
e30492bb JH |
541 | { |
542 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
b45bacd2 JH |
543 | int dc; |
544 | u32 old_compare = kvm_read_c0_guest_compare(cop0); | |
545 | ktime_t now; | |
8cffd197 | 546 | u32 count; |
e30492bb JH |
547 | |
548 | /* if unchanged, must just be an ack */ | |
b45bacd2 JH |
549 | if (old_compare == compare) { |
550 | if (!ack) | |
551 | return; | |
552 | kvm_mips_callbacks->dequeue_timer_int(vcpu); | |
553 | kvm_write_c0_guest_compare(cop0, compare); | |
e30492bb | 554 | return; |
b45bacd2 JH |
555 | } |
556 | ||
557 | /* freeze_hrtimer() takes care of timer interrupts <= count */ | |
558 | dc = kvm_mips_count_disabled(vcpu); | |
559 | if (!dc) | |
560 | now = kvm_mips_freeze_hrtimer(vcpu, &count); | |
561 | ||
562 | if (ack) | |
563 | kvm_mips_callbacks->dequeue_timer_int(vcpu); | |
e30492bb | 564 | |
e30492bb JH |
565 | kvm_write_c0_guest_compare(cop0, compare); |
566 | ||
b45bacd2 JH |
567 | /* resume_hrtimer() takes care of timer interrupts > count */ |
568 | if (!dc) | |
569 | kvm_mips_resume_hrtimer(vcpu, now, count); | |
e30492bb JH |
570 | } |
571 | ||
572 | /** | |
573 | * kvm_mips_count_disable() - Disable count. | |
574 | * @vcpu: Virtual CPU. | |
575 | * | |
576 | * Disable the CP0_Count timer. A timer interrupt on or before the final stop | |
577 | * time will be handled but not after. | |
578 | * | |
f8239342 JH |
579 | * Assumes CP0_Count was previously enabled but now Guest.CP0_Cause.DC or |
580 | * count_ctl.DC has been set (count disabled). | |
e30492bb JH |
581 | * |
582 | * Returns: The time that the timer was stopped. | |
583 | */ | |
584 | static ktime_t kvm_mips_count_disable(struct kvm_vcpu *vcpu) | |
585 | { | |
586 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
8cffd197 | 587 | u32 count; |
e30492bb JH |
588 | ktime_t now; |
589 | ||
590 | /* Stop hrtimer */ | |
591 | hrtimer_cancel(&vcpu->arch.comparecount_timer); | |
592 | ||
593 | /* Set the static count from the dynamic count, handling pending TI */ | |
594 | now = ktime_get(); | |
595 | count = kvm_mips_read_count_running(vcpu, now); | |
596 | kvm_write_c0_guest_count(cop0, count); | |
597 | ||
598 | return now; | |
599 | } | |
600 | ||
601 | /** | |
602 | * kvm_mips_count_disable_cause() - Disable count using CP0_Cause.DC. | |
603 | * @vcpu: Virtual CPU. | |
604 | * | |
605 | * Disable the CP0_Count timer and set CP0_Cause.DC. A timer interrupt on or | |
f8239342 JH |
606 | * before the final stop time will be handled if the timer isn't disabled by |
607 | * count_ctl.DC, but not after. | |
e30492bb JH |
608 | * |
609 | * Assumes CP0_Cause.DC is clear (count enabled). | |
610 | */ | |
611 | void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu) | |
612 | { | |
613 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
614 | ||
615 | kvm_set_c0_guest_cause(cop0, CAUSEF_DC); | |
f8239342 JH |
616 | if (!(vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) |
617 | kvm_mips_count_disable(vcpu); | |
e30492bb JH |
618 | } |
619 | ||
620 | /** | |
621 | * kvm_mips_count_enable_cause() - Enable count using CP0_Cause.DC. | |
622 | * @vcpu: Virtual CPU. | |
623 | * | |
624 | * Enable the CP0_Count timer and clear CP0_Cause.DC. A timer interrupt after | |
f8239342 JH |
625 | * the start time will be handled if the timer isn't disabled by count_ctl.DC, |
626 | * potentially before even returning, so the caller should be careful with | |
627 | * ordering of CP0_Cause modifications so as not to lose it. | |
e30492bb JH |
628 | * |
629 | * Assumes CP0_Cause.DC is set (count disabled). | |
630 | */ | |
631 | void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu) | |
632 | { | |
633 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
8cffd197 | 634 | u32 count; |
e30492bb JH |
635 | |
636 | kvm_clear_c0_guest_cause(cop0, CAUSEF_DC); | |
637 | ||
638 | /* | |
639 | * Set the dynamic count to match the static count. | |
f8239342 JH |
640 | * This starts the hrtimer if count_ctl.DC allows it. |
641 | * Otherwise it conveniently updates the biases. | |
e30492bb JH |
642 | */ |
643 | count = kvm_read_c0_guest_count(cop0); | |
644 | kvm_mips_write_count(vcpu, count); | |
645 | } | |
646 | ||
f8239342 JH |
647 | /** |
648 | * kvm_mips_set_count_ctl() - Update the count control KVM register. | |
649 | * @vcpu: Virtual CPU. | |
650 | * @count_ctl: Count control register new value. | |
651 | * | |
652 | * Set the count control KVM register. The timer is updated accordingly. | |
653 | * | |
654 | * Returns: -EINVAL if reserved bits are set. | |
655 | * 0 on success. | |
656 | */ | |
657 | int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl) | |
658 | { | |
659 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
660 | s64 changed = count_ctl ^ vcpu->arch.count_ctl; | |
661 | s64 delta; | |
662 | ktime_t expire, now; | |
8cffd197 | 663 | u32 count, compare; |
f8239342 JH |
664 | |
665 | /* Only allow defined bits to be changed */ | |
666 | if (changed & ~(s64)(KVM_REG_MIPS_COUNT_CTL_DC)) | |
667 | return -EINVAL; | |
668 | ||
669 | /* Apply new value */ | |
670 | vcpu->arch.count_ctl = count_ctl; | |
671 | ||
672 | /* Master CP0_Count disable */ | |
673 | if (changed & KVM_REG_MIPS_COUNT_CTL_DC) { | |
674 | /* Is CP0_Cause.DC already disabling CP0_Count? */ | |
675 | if (kvm_read_c0_guest_cause(cop0) & CAUSEF_DC) { | |
676 | if (count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) | |
677 | /* Just record the current time */ | |
678 | vcpu->arch.count_resume = ktime_get(); | |
679 | } else if (count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) { | |
680 | /* disable timer and record current time */ | |
681 | vcpu->arch.count_resume = kvm_mips_count_disable(vcpu); | |
682 | } else { | |
683 | /* | |
684 | * Calculate timeout relative to static count at resume | |
685 | * time (wrap 0 to 2^32). | |
686 | */ | |
687 | count = kvm_read_c0_guest_count(cop0); | |
688 | compare = kvm_read_c0_guest_compare(cop0); | |
8cffd197 | 689 | delta = (u64)(u32)(compare - count - 1) + 1; |
f8239342 JH |
690 | delta = div_u64(delta * NSEC_PER_SEC, |
691 | vcpu->arch.count_hz); | |
692 | expire = ktime_add_ns(vcpu->arch.count_resume, delta); | |
693 | ||
694 | /* Handle pending interrupt */ | |
695 | now = ktime_get(); | |
696 | if (ktime_compare(now, expire) >= 0) | |
697 | /* Nothing should be waiting on the timeout */ | |
698 | kvm_mips_callbacks->queue_timer_int(vcpu); | |
699 | ||
700 | /* Resume hrtimer without changing bias */ | |
701 | count = kvm_mips_read_count_running(vcpu, now); | |
702 | kvm_mips_resume_hrtimer(vcpu, now, count); | |
703 | } | |
704 | } | |
705 | ||
706 | return 0; | |
707 | } | |
708 | ||
709 | /** | |
710 | * kvm_mips_set_count_resume() - Update the count resume KVM register. | |
711 | * @vcpu: Virtual CPU. | |
712 | * @count_resume: Count resume register new value. | |
713 | * | |
714 | * Set the count resume KVM register. | |
715 | * | |
716 | * Returns: -EINVAL if out of valid range (0..now). | |
717 | * 0 on success. | |
718 | */ | |
719 | int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume) | |
720 | { | |
721 | /* | |
722 | * It doesn't make sense for the resume time to be in the future, as it | |
723 | * would be possible for the next interrupt to be more than a full | |
724 | * period in the future. | |
725 | */ | |
726 | if (count_resume < 0 || count_resume > ktime_to_ns(ktime_get())) | |
727 | return -EINVAL; | |
728 | ||
729 | vcpu->arch.count_resume = ns_to_ktime(count_resume); | |
730 | return 0; | |
731 | } | |
732 | ||
e30492bb JH |
733 | /** |
734 | * kvm_mips_count_timeout() - Push timer forward on timeout. | |
735 | * @vcpu: Virtual CPU. | |
736 | * | |
737 | * Handle an hrtimer event by push the hrtimer forward a period. | |
738 | * | |
739 | * Returns: The hrtimer_restart value to return to the hrtimer subsystem. | |
740 | */ | |
741 | enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu) | |
742 | { | |
743 | /* Add the Count period to the current expiry time */ | |
744 | hrtimer_add_expires_ns(&vcpu->arch.comparecount_timer, | |
745 | vcpu->arch.count_period); | |
746 | return HRTIMER_RESTART; | |
e685c689 SL |
747 | } |
748 | ||
749 | enum emulation_result kvm_mips_emul_eret(struct kvm_vcpu *vcpu) | |
750 | { | |
751 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
752 | enum emulation_result er = EMULATE_DONE; | |
753 | ||
754 | if (kvm_read_c0_guest_status(cop0) & ST0_EXL) { | |
755 | kvm_debug("[%#lx] ERET to %#lx\n", vcpu->arch.pc, | |
756 | kvm_read_c0_guest_epc(cop0)); | |
757 | kvm_clear_c0_guest_status(cop0, ST0_EXL); | |
758 | vcpu->arch.pc = kvm_read_c0_guest_epc(cop0); | |
759 | ||
760 | } else if (kvm_read_c0_guest_status(cop0) & ST0_ERL) { | |
761 | kvm_clear_c0_guest_status(cop0, ST0_ERL); | |
762 | vcpu->arch.pc = kvm_read_c0_guest_errorepc(cop0); | |
763 | } else { | |
6ad78a5c DCZ |
764 | kvm_err("[%#lx] ERET when MIPS_SR_EXL|MIPS_SR_ERL == 0\n", |
765 | vcpu->arch.pc); | |
e685c689 SL |
766 | er = EMULATE_FAIL; |
767 | } | |
768 | ||
769 | return er; | |
770 | } | |
771 | ||
772 | enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu *vcpu) | |
773 | { | |
e685c689 SL |
774 | kvm_debug("[%#lx] !!!WAIT!!! (%#lx)\n", vcpu->arch.pc, |
775 | vcpu->arch.pending_exceptions); | |
776 | ||
777 | ++vcpu->stat.wait_exits; | |
778 | trace_kvm_exit(vcpu, WAIT_EXITS); | |
779 | if (!vcpu->arch.pending_exceptions) { | |
780 | vcpu->arch.wait = 1; | |
781 | kvm_vcpu_block(vcpu); | |
782 | ||
d116e812 DCZ |
783 | /* |
784 | * We we are runnable, then definitely go off to user space to | |
785 | * check if any I/O interrupts are pending. | |
e685c689 SL |
786 | */ |
787 | if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) { | |
788 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); | |
789 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; | |
790 | } | |
791 | } | |
792 | ||
d98403a5 | 793 | return EMULATE_DONE; |
e685c689 SL |
794 | } |
795 | ||
d116e812 DCZ |
796 | /* |
797 | * XXXKYMA: Linux doesn't seem to use TLBR, return EMULATE_FAIL for now so that | |
798 | * we can catch this, if things ever change | |
e685c689 SL |
799 | */ |
800 | enum emulation_result kvm_mips_emul_tlbr(struct kvm_vcpu *vcpu) | |
801 | { | |
802 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
8cffd197 | 803 | unsigned long pc = vcpu->arch.pc; |
e685c689 | 804 | |
8cffd197 | 805 | kvm_err("[%#lx] COP0_TLBR [%ld]\n", pc, kvm_read_c0_guest_index(cop0)); |
d98403a5 | 806 | return EMULATE_FAIL; |
e685c689 SL |
807 | } |
808 | ||
809 | /* Write Guest TLB Entry @ Index */ | |
810 | enum emulation_result kvm_mips_emul_tlbwi(struct kvm_vcpu *vcpu) | |
811 | { | |
812 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
813 | int index = kvm_read_c0_guest_index(cop0); | |
e685c689 | 814 | struct kvm_mips_tlb *tlb = NULL; |
8cffd197 | 815 | unsigned long pc = vcpu->arch.pc; |
e685c689 SL |
816 | |
817 | if (index < 0 || index >= KVM_MIPS_GUEST_TLB_SIZE) { | |
6ad78a5c | 818 | kvm_debug("%s: illegal index: %d\n", __func__, index); |
8cffd197 | 819 | kvm_debug("[%#lx] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n", |
6ad78a5c DCZ |
820 | pc, index, kvm_read_c0_guest_entryhi(cop0), |
821 | kvm_read_c0_guest_entrylo0(cop0), | |
822 | kvm_read_c0_guest_entrylo1(cop0), | |
823 | kvm_read_c0_guest_pagemask(cop0)); | |
e685c689 SL |
824 | index = (index & ~0x80000000) % KVM_MIPS_GUEST_TLB_SIZE; |
825 | } | |
826 | ||
827 | tlb = &vcpu->arch.guest_tlb[index]; | |
d116e812 DCZ |
828 | /* |
829 | * Probe the shadow host TLB for the entry being overwritten, if one | |
830 | * matches, invalidate it | |
831 | */ | |
e685c689 | 832 | kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi); |
e685c689 SL |
833 | |
834 | tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0); | |
835 | tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0); | |
9fbfb06a JH |
836 | tlb->tlb_lo[0] = kvm_read_c0_guest_entrylo0(cop0); |
837 | tlb->tlb_lo[1] = kvm_read_c0_guest_entrylo1(cop0); | |
e685c689 | 838 | |
8cffd197 | 839 | kvm_debug("[%#lx] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n", |
d116e812 DCZ |
840 | pc, index, kvm_read_c0_guest_entryhi(cop0), |
841 | kvm_read_c0_guest_entrylo0(cop0), | |
842 | kvm_read_c0_guest_entrylo1(cop0), | |
843 | kvm_read_c0_guest_pagemask(cop0)); | |
e685c689 | 844 | |
d98403a5 | 845 | return EMULATE_DONE; |
e685c689 SL |
846 | } |
847 | ||
848 | /* Write Guest TLB Entry @ Random Index */ | |
849 | enum emulation_result kvm_mips_emul_tlbwr(struct kvm_vcpu *vcpu) | |
850 | { | |
851 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
e685c689 | 852 | struct kvm_mips_tlb *tlb = NULL; |
8cffd197 | 853 | unsigned long pc = vcpu->arch.pc; |
e685c689 SL |
854 | int index; |
855 | ||
e685c689 SL |
856 | get_random_bytes(&index, sizeof(index)); |
857 | index &= (KVM_MIPS_GUEST_TLB_SIZE - 1); | |
e685c689 | 858 | |
e685c689 SL |
859 | tlb = &vcpu->arch.guest_tlb[index]; |
860 | ||
d116e812 DCZ |
861 | /* |
862 | * Probe the shadow host TLB for the entry being overwritten, if one | |
863 | * matches, invalidate it | |
864 | */ | |
e685c689 | 865 | kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi); |
e685c689 SL |
866 | |
867 | tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0); | |
868 | tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0); | |
9fbfb06a JH |
869 | tlb->tlb_lo[0] = kvm_read_c0_guest_entrylo0(cop0); |
870 | tlb->tlb_lo[1] = kvm_read_c0_guest_entrylo1(cop0); | |
e685c689 | 871 | |
8cffd197 | 872 | kvm_debug("[%#lx] COP0_TLBWR[%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx)\n", |
d116e812 DCZ |
873 | pc, index, kvm_read_c0_guest_entryhi(cop0), |
874 | kvm_read_c0_guest_entrylo0(cop0), | |
875 | kvm_read_c0_guest_entrylo1(cop0)); | |
e685c689 | 876 | |
d98403a5 | 877 | return EMULATE_DONE; |
e685c689 SL |
878 | } |
879 | ||
880 | enum emulation_result kvm_mips_emul_tlbp(struct kvm_vcpu *vcpu) | |
881 | { | |
882 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
883 | long entryhi = kvm_read_c0_guest_entryhi(cop0); | |
8cffd197 | 884 | unsigned long pc = vcpu->arch.pc; |
e685c689 SL |
885 | int index = -1; |
886 | ||
887 | index = kvm_mips_guest_tlb_lookup(vcpu, entryhi); | |
888 | ||
889 | kvm_write_c0_guest_index(cop0, index); | |
890 | ||
8cffd197 | 891 | kvm_debug("[%#lx] COP0_TLBP (entryhi: %#lx), index: %d\n", pc, entryhi, |
e685c689 SL |
892 | index); |
893 | ||
d98403a5 | 894 | return EMULATE_DONE; |
e685c689 SL |
895 | } |
896 | ||
c771607a JH |
897 | /** |
898 | * kvm_mips_config1_wrmask() - Find mask of writable bits in guest Config1 | |
899 | * @vcpu: Virtual CPU. | |
900 | * | |
901 | * Finds the mask of bits which are writable in the guest's Config1 CP0 | |
902 | * register, by userland (currently read-only to the guest). | |
903 | */ | |
904 | unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu) | |
905 | { | |
6cdc65e3 JH |
906 | unsigned int mask = 0; |
907 | ||
908 | /* Permit FPU to be present if FPU is supported */ | |
909 | if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) | |
910 | mask |= MIPS_CONF1_FP; | |
911 | ||
912 | return mask; | |
c771607a JH |
913 | } |
914 | ||
915 | /** | |
916 | * kvm_mips_config3_wrmask() - Find mask of writable bits in guest Config3 | |
917 | * @vcpu: Virtual CPU. | |
918 | * | |
919 | * Finds the mask of bits which are writable in the guest's Config3 CP0 | |
920 | * register, by userland (currently read-only to the guest). | |
921 | */ | |
922 | unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu) | |
923 | { | |
924 | /* Config4 is optional */ | |
2b6009d6 JH |
925 | unsigned int mask = MIPS_CONF_M; |
926 | ||
927 | /* Permit MSA to be present if MSA is supported */ | |
928 | if (kvm_mips_guest_can_have_msa(&vcpu->arch)) | |
929 | mask |= MIPS_CONF3_MSA; | |
930 | ||
931 | return mask; | |
c771607a JH |
932 | } |
933 | ||
934 | /** | |
935 | * kvm_mips_config4_wrmask() - Find mask of writable bits in guest Config4 | |
936 | * @vcpu: Virtual CPU. | |
937 | * | |
938 | * Finds the mask of bits which are writable in the guest's Config4 CP0 | |
939 | * register, by userland (currently read-only to the guest). | |
940 | */ | |
941 | unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu) | |
942 | { | |
943 | /* Config5 is optional */ | |
944 | return MIPS_CONF_M; | |
945 | } | |
946 | ||
947 | /** | |
948 | * kvm_mips_config5_wrmask() - Find mask of writable bits in guest Config5 | |
949 | * @vcpu: Virtual CPU. | |
950 | * | |
951 | * Finds the mask of bits which are writable in the guest's Config5 CP0 | |
952 | * register, by the guest itself. | |
953 | */ | |
954 | unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu) | |
955 | { | |
6cdc65e3 JH |
956 | unsigned int mask = 0; |
957 | ||
2b6009d6 JH |
958 | /* Permit MSAEn changes if MSA supported and enabled */ |
959 | if (kvm_mips_guest_has_msa(&vcpu->arch)) | |
960 | mask |= MIPS_CONF5_MSAEN; | |
961 | ||
6cdc65e3 JH |
962 | /* |
963 | * Permit guest FPU mode changes if FPU is enabled and the relevant | |
964 | * feature exists according to FIR register. | |
965 | */ | |
966 | if (kvm_mips_guest_has_fpu(&vcpu->arch)) { | |
967 | if (cpu_has_fre) | |
968 | mask |= MIPS_CONF5_FRE; | |
969 | /* We don't support UFR or UFE */ | |
970 | } | |
971 | ||
972 | return mask; | |
c771607a JH |
973 | } |
974 | ||
bdb7ed86 JH |
975 | enum emulation_result kvm_mips_emulate_CP0(u32 inst, u32 *opc, u32 cause, |
976 | struct kvm_run *run, | |
d116e812 | 977 | struct kvm_vcpu *vcpu) |
e685c689 SL |
978 | { |
979 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
980 | enum emulation_result er = EMULATE_DONE; | |
8cffd197 JH |
981 | u32 rt, rd, copz, sel, co_bit, op; |
982 | unsigned long pc = vcpu->arch.pc; | |
e685c689 SL |
983 | unsigned long curr_pc; |
984 | ||
985 | /* | |
986 | * Update PC and hold onto current PC in case there is | |
987 | * an error and we want to rollback the PC | |
988 | */ | |
989 | curr_pc = vcpu->arch.pc; | |
990 | er = update_pc(vcpu, cause); | |
d116e812 | 991 | if (er == EMULATE_FAIL) |
e685c689 | 992 | return er; |
e685c689 SL |
993 | |
994 | copz = (inst >> 21) & 0x1f; | |
995 | rt = (inst >> 16) & 0x1f; | |
996 | rd = (inst >> 11) & 0x1f; | |
997 | sel = inst & 0x7; | |
998 | co_bit = (inst >> 25) & 1; | |
999 | ||
e685c689 SL |
1000 | if (co_bit) { |
1001 | op = (inst) & 0xff; | |
1002 | ||
1003 | switch (op) { | |
1004 | case tlbr_op: /* Read indexed TLB entry */ | |
1005 | er = kvm_mips_emul_tlbr(vcpu); | |
1006 | break; | |
1007 | case tlbwi_op: /* Write indexed */ | |
1008 | er = kvm_mips_emul_tlbwi(vcpu); | |
1009 | break; | |
1010 | case tlbwr_op: /* Write random */ | |
1011 | er = kvm_mips_emul_tlbwr(vcpu); | |
1012 | break; | |
1013 | case tlbp_op: /* TLB Probe */ | |
1014 | er = kvm_mips_emul_tlbp(vcpu); | |
1015 | break; | |
1016 | case rfe_op: | |
6ad78a5c | 1017 | kvm_err("!!!COP0_RFE!!!\n"); |
e685c689 SL |
1018 | break; |
1019 | case eret_op: | |
1020 | er = kvm_mips_emul_eret(vcpu); | |
1021 | goto dont_update_pc; | |
1022 | break; | |
1023 | case wait_op: | |
1024 | er = kvm_mips_emul_wait(vcpu); | |
1025 | break; | |
1026 | } | |
1027 | } else { | |
1028 | switch (copz) { | |
1029 | case mfc_op: | |
1030 | #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS | |
1031 | cop0->stat[rd][sel]++; | |
1032 | #endif | |
1033 | /* Get reg */ | |
1034 | if ((rd == MIPS_CP0_COUNT) && (sel == 0)) { | |
e30492bb | 1035 | vcpu->arch.gprs[rt] = kvm_mips_read_count(vcpu); |
e685c689 SL |
1036 | } else if ((rd == MIPS_CP0_ERRCTL) && (sel == 0)) { |
1037 | vcpu->arch.gprs[rt] = 0x0; | |
1038 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS | |
1039 | kvm_mips_trans_mfc0(inst, opc, vcpu); | |
1040 | #endif | |
d116e812 | 1041 | } else { |
e685c689 SL |
1042 | vcpu->arch.gprs[rt] = cop0->reg[rd][sel]; |
1043 | ||
1044 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS | |
1045 | kvm_mips_trans_mfc0(inst, opc, vcpu); | |
1046 | #endif | |
1047 | } | |
1048 | ||
1049 | kvm_debug | |
8cffd197 | 1050 | ("[%#lx] MFCz[%d][%d], vcpu->arch.gprs[%d]: %#lx\n", |
e685c689 SL |
1051 | pc, rd, sel, rt, vcpu->arch.gprs[rt]); |
1052 | ||
1053 | break; | |
1054 | ||
1055 | case dmfc_op: | |
1056 | vcpu->arch.gprs[rt] = cop0->reg[rd][sel]; | |
1057 | break; | |
1058 | ||
1059 | case mtc_op: | |
1060 | #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS | |
1061 | cop0->stat[rd][sel]++; | |
1062 | #endif | |
1063 | if ((rd == MIPS_CP0_TLB_INDEX) | |
1064 | && (vcpu->arch.gprs[rt] >= | |
1065 | KVM_MIPS_GUEST_TLB_SIZE)) { | |
6ad78a5c DCZ |
1066 | kvm_err("Invalid TLB Index: %ld", |
1067 | vcpu->arch.gprs[rt]); | |
e685c689 SL |
1068 | er = EMULATE_FAIL; |
1069 | break; | |
1070 | } | |
1071 | #define C0_EBASE_CORE_MASK 0xff | |
1072 | if ((rd == MIPS_CP0_PRID) && (sel == 1)) { | |
1073 | /* Preserve CORE number */ | |
1074 | kvm_change_c0_guest_ebase(cop0, | |
1075 | ~(C0_EBASE_CORE_MASK), | |
1076 | vcpu->arch.gprs[rt]); | |
6ad78a5c DCZ |
1077 | kvm_err("MTCz, cop0->reg[EBASE]: %#lx\n", |
1078 | kvm_read_c0_guest_ebase(cop0)); | |
e685c689 | 1079 | } else if (rd == MIPS_CP0_TLB_HI && sel == 0) { |
8cffd197 | 1080 | u32 nasid = |
ca64c2be | 1081 | vcpu->arch.gprs[rt] & KVM_ENTRYHI_ASID; |
d116e812 | 1082 | if ((KSEGX(vcpu->arch.gprs[rt]) != CKSEG0) && |
48c4ac97 | 1083 | ((kvm_read_c0_guest_entryhi(cop0) & |
ca64c2be | 1084 | KVM_ENTRYHI_ASID) != nasid)) { |
d116e812 DCZ |
1085 | kvm_debug("MTCz, change ASID from %#lx to %#lx\n", |
1086 | kvm_read_c0_guest_entryhi(cop0) | |
ca64c2be | 1087 | & KVM_ENTRYHI_ASID, |
d116e812 | 1088 | vcpu->arch.gprs[rt] |
ca64c2be | 1089 | & KVM_ENTRYHI_ASID); |
e685c689 SL |
1090 | |
1091 | /* Blow away the shadow host TLBs */ | |
1092 | kvm_mips_flush_host_tlb(1); | |
1093 | } | |
1094 | kvm_write_c0_guest_entryhi(cop0, | |
1095 | vcpu->arch.gprs[rt]); | |
1096 | } | |
1097 | /* Are we writing to COUNT */ | |
1098 | else if ((rd == MIPS_CP0_COUNT) && (sel == 0)) { | |
e30492bb | 1099 | kvm_mips_write_count(vcpu, vcpu->arch.gprs[rt]); |
e685c689 SL |
1100 | goto done; |
1101 | } else if ((rd == MIPS_CP0_COMPARE) && (sel == 0)) { | |
8cffd197 | 1102 | kvm_debug("[%#lx] MTCz, COMPARE %#lx <- %#lx\n", |
e685c689 SL |
1103 | pc, kvm_read_c0_guest_compare(cop0), |
1104 | vcpu->arch.gprs[rt]); | |
1105 | ||
1106 | /* If we are writing to COMPARE */ | |
1107 | /* Clear pending timer interrupt, if any */ | |
e30492bb | 1108 | kvm_mips_write_compare(vcpu, |
b45bacd2 JH |
1109 | vcpu->arch.gprs[rt], |
1110 | true); | |
e685c689 | 1111 | } else if ((rd == MIPS_CP0_STATUS) && (sel == 0)) { |
6cdc65e3 JH |
1112 | unsigned int old_val, val, change; |
1113 | ||
1114 | old_val = kvm_read_c0_guest_status(cop0); | |
1115 | val = vcpu->arch.gprs[rt]; | |
1116 | change = val ^ old_val; | |
1117 | ||
1118 | /* Make sure that the NMI bit is never set */ | |
1119 | val &= ~ST0_NMI; | |
1120 | ||
1121 | /* | |
1122 | * Don't allow CU1 or FR to be set unless FPU | |
1123 | * capability enabled and exists in guest | |
1124 | * configuration. | |
1125 | */ | |
1126 | if (!kvm_mips_guest_has_fpu(&vcpu->arch)) | |
1127 | val &= ~(ST0_CU1 | ST0_FR); | |
1128 | ||
1129 | /* | |
1130 | * Also don't allow FR to be set if host doesn't | |
1131 | * support it. | |
1132 | */ | |
1133 | if (!(current_cpu_data.fpu_id & MIPS_FPIR_F64)) | |
1134 | val &= ~ST0_FR; | |
1135 | ||
1136 | ||
1137 | /* Handle changes in FPU mode */ | |
1138 | preempt_disable(); | |
1139 | ||
1140 | /* | |
1141 | * FPU and Vector register state is made | |
1142 | * UNPREDICTABLE by a change of FR, so don't | |
1143 | * even bother saving it. | |
1144 | */ | |
1145 | if (change & ST0_FR) | |
1146 | kvm_drop_fpu(vcpu); | |
1147 | ||
2b6009d6 JH |
1148 | /* |
1149 | * If MSA state is already live, it is undefined | |
1150 | * how it interacts with FR=0 FPU state, and we | |
1151 | * don't want to hit reserved instruction | |
1152 | * exceptions trying to save the MSA state later | |
1153 | * when CU=1 && FR=1, so play it safe and save | |
1154 | * it first. | |
1155 | */ | |
1156 | if (change & ST0_CU1 && !(val & ST0_FR) && | |
f943176a | 1157 | vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) |
2b6009d6 JH |
1158 | kvm_lose_fpu(vcpu); |
1159 | ||
d116e812 | 1160 | /* |
6cdc65e3 JH |
1161 | * Propagate CU1 (FPU enable) changes |
1162 | * immediately if the FPU context is already | |
1163 | * loaded. When disabling we leave the context | |
1164 | * loaded so it can be quickly enabled again in | |
1165 | * the near future. | |
d116e812 | 1166 | */ |
6cdc65e3 | 1167 | if (change & ST0_CU1 && |
f943176a | 1168 | vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) |
6cdc65e3 JH |
1169 | change_c0_status(ST0_CU1, val); |
1170 | ||
1171 | preempt_enable(); | |
1172 | ||
1173 | kvm_write_c0_guest_status(cop0, val); | |
e685c689 SL |
1174 | |
1175 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS | |
6cdc65e3 JH |
1176 | /* |
1177 | * If FPU present, we need CU1/FR bits to take | |
1178 | * effect fairly soon. | |
1179 | */ | |
1180 | if (!kvm_mips_guest_has_fpu(&vcpu->arch)) | |
1181 | kvm_mips_trans_mtc0(inst, opc, vcpu); | |
e685c689 | 1182 | #endif |
6cdc65e3 JH |
1183 | } else if ((rd == MIPS_CP0_CONFIG) && (sel == 5)) { |
1184 | unsigned int old_val, val, change, wrmask; | |
1185 | ||
1186 | old_val = kvm_read_c0_guest_config5(cop0); | |
1187 | val = vcpu->arch.gprs[rt]; | |
1188 | ||
1189 | /* Only a few bits are writable in Config5 */ | |
1190 | wrmask = kvm_mips_config5_wrmask(vcpu); | |
1191 | change = (val ^ old_val) & wrmask; | |
1192 | val = old_val ^ change; | |
1193 | ||
1194 | ||
2b6009d6 | 1195 | /* Handle changes in FPU/MSA modes */ |
6cdc65e3 JH |
1196 | preempt_disable(); |
1197 | ||
1198 | /* | |
1199 | * Propagate FRE changes immediately if the FPU | |
1200 | * context is already loaded. | |
1201 | */ | |
1202 | if (change & MIPS_CONF5_FRE && | |
f943176a | 1203 | vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) |
6cdc65e3 JH |
1204 | change_c0_config5(MIPS_CONF5_FRE, val); |
1205 | ||
2b6009d6 JH |
1206 | /* |
1207 | * Propagate MSAEn changes immediately if the | |
1208 | * MSA context is already loaded. When disabling | |
1209 | * we leave the context loaded so it can be | |
1210 | * quickly enabled again in the near future. | |
1211 | */ | |
1212 | if (change & MIPS_CONF5_MSAEN && | |
f943176a | 1213 | vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) |
2b6009d6 JH |
1214 | change_c0_config5(MIPS_CONF5_MSAEN, |
1215 | val); | |
1216 | ||
6cdc65e3 JH |
1217 | preempt_enable(); |
1218 | ||
1219 | kvm_write_c0_guest_config5(cop0, val); | |
e30492bb | 1220 | } else if ((rd == MIPS_CP0_CAUSE) && (sel == 0)) { |
8cffd197 | 1221 | u32 old_cause, new_cause; |
d116e812 | 1222 | |
e30492bb JH |
1223 | old_cause = kvm_read_c0_guest_cause(cop0); |
1224 | new_cause = vcpu->arch.gprs[rt]; | |
1225 | /* Update R/W bits */ | |
1226 | kvm_change_c0_guest_cause(cop0, 0x08800300, | |
1227 | new_cause); | |
1228 | /* DC bit enabling/disabling timer? */ | |
1229 | if ((old_cause ^ new_cause) & CAUSEF_DC) { | |
1230 | if (new_cause & CAUSEF_DC) | |
1231 | kvm_mips_count_disable_cause(vcpu); | |
1232 | else | |
1233 | kvm_mips_count_enable_cause(vcpu); | |
1234 | } | |
e685c689 SL |
1235 | } else { |
1236 | cop0->reg[rd][sel] = vcpu->arch.gprs[rt]; | |
1237 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS | |
1238 | kvm_mips_trans_mtc0(inst, opc, vcpu); | |
1239 | #endif | |
1240 | } | |
1241 | ||
8cffd197 | 1242 | kvm_debug("[%#lx] MTCz, cop0->reg[%d][%d]: %#lx\n", pc, |
e685c689 SL |
1243 | rd, sel, cop0->reg[rd][sel]); |
1244 | break; | |
1245 | ||
1246 | case dmtc_op: | |
6ad78a5c DCZ |
1247 | kvm_err("!!!!!!![%#lx]dmtc_op: rt: %d, rd: %d, sel: %d!!!!!!\n", |
1248 | vcpu->arch.pc, rt, rd, sel); | |
e685c689 SL |
1249 | er = EMULATE_FAIL; |
1250 | break; | |
1251 | ||
b2c59635 | 1252 | case mfmc0_op: |
e685c689 SL |
1253 | #ifdef KVM_MIPS_DEBUG_COP0_COUNTERS |
1254 | cop0->stat[MIPS_CP0_STATUS][0]++; | |
1255 | #endif | |
caa1faa7 | 1256 | if (rt != 0) |
e685c689 SL |
1257 | vcpu->arch.gprs[rt] = |
1258 | kvm_read_c0_guest_status(cop0); | |
e685c689 SL |
1259 | /* EI */ |
1260 | if (inst & 0x20) { | |
b2c59635 | 1261 | kvm_debug("[%#lx] mfmc0_op: EI\n", |
e685c689 SL |
1262 | vcpu->arch.pc); |
1263 | kvm_set_c0_guest_status(cop0, ST0_IE); | |
1264 | } else { | |
b2c59635 | 1265 | kvm_debug("[%#lx] mfmc0_op: DI\n", |
e685c689 SL |
1266 | vcpu->arch.pc); |
1267 | kvm_clear_c0_guest_status(cop0, ST0_IE); | |
1268 | } | |
1269 | ||
1270 | break; | |
1271 | ||
1272 | case wrpgpr_op: | |
1273 | { | |
8cffd197 JH |
1274 | u32 css = cop0->reg[MIPS_CP0_STATUS][2] & 0xf; |
1275 | u32 pss = | |
e685c689 | 1276 | (cop0->reg[MIPS_CP0_STATUS][2] >> 6) & 0xf; |
d116e812 DCZ |
1277 | /* |
1278 | * We don't support any shadow register sets, so | |
1279 | * SRSCtl[PSS] == SRSCtl[CSS] = 0 | |
1280 | */ | |
e685c689 SL |
1281 | if (css || pss) { |
1282 | er = EMULATE_FAIL; | |
1283 | break; | |
1284 | } | |
1285 | kvm_debug("WRPGPR[%d][%d] = %#lx\n", pss, rd, | |
1286 | vcpu->arch.gprs[rt]); | |
1287 | vcpu->arch.gprs[rd] = vcpu->arch.gprs[rt]; | |
1288 | } | |
1289 | break; | |
1290 | default: | |
6ad78a5c DCZ |
1291 | kvm_err("[%#lx]MachEmulateCP0: unsupported COP0, copz: 0x%x\n", |
1292 | vcpu->arch.pc, copz); | |
e685c689 SL |
1293 | er = EMULATE_FAIL; |
1294 | break; | |
1295 | } | |
1296 | } | |
1297 | ||
1298 | done: | |
d116e812 DCZ |
1299 | /* Rollback PC only if emulation was unsuccessful */ |
1300 | if (er == EMULATE_FAIL) | |
e685c689 | 1301 | vcpu->arch.pc = curr_pc; |
e685c689 SL |
1302 | |
1303 | dont_update_pc: | |
1304 | /* | |
1305 | * This is for special instructions whose emulation | |
1306 | * updates the PC, so do not overwrite the PC under | |
1307 | * any circumstances | |
1308 | */ | |
1309 | ||
1310 | return er; | |
1311 | } | |
1312 | ||
bdb7ed86 | 1313 | enum emulation_result kvm_mips_emulate_store(u32 inst, u32 cause, |
d116e812 DCZ |
1314 | struct kvm_run *run, |
1315 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
1316 | { |
1317 | enum emulation_result er = EMULATE_DO_MMIO; | |
8cffd197 JH |
1318 | u32 op, base, rt; |
1319 | s16 offset; | |
1320 | u32 bytes; | |
e685c689 SL |
1321 | void *data = run->mmio.data; |
1322 | unsigned long curr_pc; | |
1323 | ||
1324 | /* | |
1325 | * Update PC and hold onto current PC in case there is | |
1326 | * an error and we want to rollback the PC | |
1327 | */ | |
1328 | curr_pc = vcpu->arch.pc; | |
1329 | er = update_pc(vcpu, cause); | |
1330 | if (er == EMULATE_FAIL) | |
1331 | return er; | |
1332 | ||
1333 | rt = (inst >> 16) & 0x1f; | |
1334 | base = (inst >> 21) & 0x1f; | |
8cffd197 | 1335 | offset = (s16)inst; |
e685c689 SL |
1336 | op = (inst >> 26) & 0x3f; |
1337 | ||
1338 | switch (op) { | |
1339 | case sb_op: | |
1340 | bytes = 1; | |
1341 | if (bytes > sizeof(run->mmio.data)) { | |
1342 | kvm_err("%s: bad MMIO length: %d\n", __func__, | |
1343 | run->mmio.len); | |
1344 | } | |
1345 | run->mmio.phys_addr = | |
1346 | kvm_mips_callbacks->gva_to_gpa(vcpu->arch. | |
1347 | host_cp0_badvaddr); | |
1348 | if (run->mmio.phys_addr == KVM_INVALID_ADDR) { | |
1349 | er = EMULATE_FAIL; | |
1350 | break; | |
1351 | } | |
1352 | run->mmio.len = bytes; | |
1353 | run->mmio.is_write = 1; | |
1354 | vcpu->mmio_needed = 1; | |
1355 | vcpu->mmio_is_write = 1; | |
1356 | *(u8 *) data = vcpu->arch.gprs[rt]; | |
1357 | kvm_debug("OP_SB: eaddr: %#lx, gpr: %#lx, data: %#x\n", | |
1358 | vcpu->arch.host_cp0_badvaddr, vcpu->arch.gprs[rt], | |
8cffd197 | 1359 | *(u8 *) data); |
e685c689 SL |
1360 | |
1361 | break; | |
1362 | ||
1363 | case sw_op: | |
1364 | bytes = 4; | |
1365 | if (bytes > sizeof(run->mmio.data)) { | |
1366 | kvm_err("%s: bad MMIO length: %d\n", __func__, | |
1367 | run->mmio.len); | |
1368 | } | |
1369 | run->mmio.phys_addr = | |
1370 | kvm_mips_callbacks->gva_to_gpa(vcpu->arch. | |
1371 | host_cp0_badvaddr); | |
1372 | if (run->mmio.phys_addr == KVM_INVALID_ADDR) { | |
1373 | er = EMULATE_FAIL; | |
1374 | break; | |
1375 | } | |
1376 | ||
1377 | run->mmio.len = bytes; | |
1378 | run->mmio.is_write = 1; | |
1379 | vcpu->mmio_needed = 1; | |
1380 | vcpu->mmio_is_write = 1; | |
8cffd197 | 1381 | *(u32 *) data = vcpu->arch.gprs[rt]; |
e685c689 SL |
1382 | |
1383 | kvm_debug("[%#lx] OP_SW: eaddr: %#lx, gpr: %#lx, data: %#x\n", | |
1384 | vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr, | |
8cffd197 | 1385 | vcpu->arch.gprs[rt], *(u32 *) data); |
e685c689 SL |
1386 | break; |
1387 | ||
1388 | case sh_op: | |
1389 | bytes = 2; | |
1390 | if (bytes > sizeof(run->mmio.data)) { | |
1391 | kvm_err("%s: bad MMIO length: %d\n", __func__, | |
1392 | run->mmio.len); | |
1393 | } | |
1394 | run->mmio.phys_addr = | |
1395 | kvm_mips_callbacks->gva_to_gpa(vcpu->arch. | |
1396 | host_cp0_badvaddr); | |
1397 | if (run->mmio.phys_addr == KVM_INVALID_ADDR) { | |
1398 | er = EMULATE_FAIL; | |
1399 | break; | |
1400 | } | |
1401 | ||
1402 | run->mmio.len = bytes; | |
1403 | run->mmio.is_write = 1; | |
1404 | vcpu->mmio_needed = 1; | |
1405 | vcpu->mmio_is_write = 1; | |
8cffd197 | 1406 | *(u16 *) data = vcpu->arch.gprs[rt]; |
e685c689 SL |
1407 | |
1408 | kvm_debug("[%#lx] OP_SH: eaddr: %#lx, gpr: %#lx, data: %#x\n", | |
1409 | vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr, | |
8cffd197 | 1410 | vcpu->arch.gprs[rt], *(u32 *) data); |
e685c689 SL |
1411 | break; |
1412 | ||
1413 | default: | |
6ad78a5c | 1414 | kvm_err("Store not yet supported"); |
e685c689 SL |
1415 | er = EMULATE_FAIL; |
1416 | break; | |
1417 | } | |
1418 | ||
d116e812 DCZ |
1419 | /* Rollback PC if emulation was unsuccessful */ |
1420 | if (er == EMULATE_FAIL) | |
e685c689 | 1421 | vcpu->arch.pc = curr_pc; |
e685c689 SL |
1422 | |
1423 | return er; | |
1424 | } | |
1425 | ||
bdb7ed86 | 1426 | enum emulation_result kvm_mips_emulate_load(u32 inst, u32 cause, |
d116e812 DCZ |
1427 | struct kvm_run *run, |
1428 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
1429 | { |
1430 | enum emulation_result er = EMULATE_DO_MMIO; | |
8cffd197 JH |
1431 | u32 op, base, rt; |
1432 | s16 offset; | |
1433 | u32 bytes; | |
e685c689 SL |
1434 | |
1435 | rt = (inst >> 16) & 0x1f; | |
1436 | base = (inst >> 21) & 0x1f; | |
8cffd197 | 1437 | offset = (s16)inst; |
e685c689 SL |
1438 | op = (inst >> 26) & 0x3f; |
1439 | ||
1440 | vcpu->arch.pending_load_cause = cause; | |
1441 | vcpu->arch.io_gpr = rt; | |
1442 | ||
1443 | switch (op) { | |
1444 | case lw_op: | |
1445 | bytes = 4; | |
1446 | if (bytes > sizeof(run->mmio.data)) { | |
1447 | kvm_err("%s: bad MMIO length: %d\n", __func__, | |
1448 | run->mmio.len); | |
1449 | er = EMULATE_FAIL; | |
1450 | break; | |
1451 | } | |
1452 | run->mmio.phys_addr = | |
1453 | kvm_mips_callbacks->gva_to_gpa(vcpu->arch. | |
1454 | host_cp0_badvaddr); | |
1455 | if (run->mmio.phys_addr == KVM_INVALID_ADDR) { | |
1456 | er = EMULATE_FAIL; | |
1457 | break; | |
1458 | } | |
1459 | ||
1460 | run->mmio.len = bytes; | |
1461 | run->mmio.is_write = 0; | |
1462 | vcpu->mmio_needed = 1; | |
1463 | vcpu->mmio_is_write = 0; | |
1464 | break; | |
1465 | ||
1466 | case lh_op: | |
1467 | case lhu_op: | |
1468 | bytes = 2; | |
1469 | if (bytes > sizeof(run->mmio.data)) { | |
1470 | kvm_err("%s: bad MMIO length: %d\n", __func__, | |
1471 | run->mmio.len); | |
1472 | er = EMULATE_FAIL; | |
1473 | break; | |
1474 | } | |
1475 | run->mmio.phys_addr = | |
1476 | kvm_mips_callbacks->gva_to_gpa(vcpu->arch. | |
1477 | host_cp0_badvaddr); | |
1478 | if (run->mmio.phys_addr == KVM_INVALID_ADDR) { | |
1479 | er = EMULATE_FAIL; | |
1480 | break; | |
1481 | } | |
1482 | ||
1483 | run->mmio.len = bytes; | |
1484 | run->mmio.is_write = 0; | |
1485 | vcpu->mmio_needed = 1; | |
1486 | vcpu->mmio_is_write = 0; | |
1487 | ||
1488 | if (op == lh_op) | |
1489 | vcpu->mmio_needed = 2; | |
1490 | else | |
1491 | vcpu->mmio_needed = 1; | |
1492 | ||
1493 | break; | |
1494 | ||
1495 | case lbu_op: | |
1496 | case lb_op: | |
1497 | bytes = 1; | |
1498 | if (bytes > sizeof(run->mmio.data)) { | |
1499 | kvm_err("%s: bad MMIO length: %d\n", __func__, | |
1500 | run->mmio.len); | |
1501 | er = EMULATE_FAIL; | |
1502 | break; | |
1503 | } | |
1504 | run->mmio.phys_addr = | |
1505 | kvm_mips_callbacks->gva_to_gpa(vcpu->arch. | |
1506 | host_cp0_badvaddr); | |
1507 | if (run->mmio.phys_addr == KVM_INVALID_ADDR) { | |
1508 | er = EMULATE_FAIL; | |
1509 | break; | |
1510 | } | |
1511 | ||
1512 | run->mmio.len = bytes; | |
1513 | run->mmio.is_write = 0; | |
1514 | vcpu->mmio_is_write = 0; | |
1515 | ||
1516 | if (op == lb_op) | |
1517 | vcpu->mmio_needed = 2; | |
1518 | else | |
1519 | vcpu->mmio_needed = 1; | |
1520 | ||
1521 | break; | |
1522 | ||
1523 | default: | |
6ad78a5c | 1524 | kvm_err("Load not yet supported"); |
e685c689 SL |
1525 | er = EMULATE_FAIL; |
1526 | break; | |
1527 | } | |
1528 | ||
1529 | return er; | |
1530 | } | |
1531 | ||
bdb7ed86 JH |
1532 | enum emulation_result kvm_mips_emulate_cache(u32 inst, u32 *opc, |
1533 | u32 cause, | |
d116e812 DCZ |
1534 | struct kvm_run *run, |
1535 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
1536 | { |
1537 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
e685c689 | 1538 | enum emulation_result er = EMULATE_DONE; |
8cffd197 JH |
1539 | u32 cache, op_inst, op, base; |
1540 | s16 offset; | |
e685c689 SL |
1541 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
1542 | unsigned long va; | |
1543 | unsigned long curr_pc; | |
1544 | ||
1545 | /* | |
1546 | * Update PC and hold onto current PC in case there is | |
1547 | * an error and we want to rollback the PC | |
1548 | */ | |
1549 | curr_pc = vcpu->arch.pc; | |
1550 | er = update_pc(vcpu, cause); | |
1551 | if (er == EMULATE_FAIL) | |
1552 | return er; | |
1553 | ||
1554 | base = (inst >> 21) & 0x1f; | |
1555 | op_inst = (inst >> 16) & 0x1f; | |
8cffd197 | 1556 | offset = (s16)inst; |
f4956f62 JH |
1557 | cache = op_inst & CacheOp_Cache; |
1558 | op = op_inst & CacheOp_Op; | |
e685c689 SL |
1559 | |
1560 | va = arch->gprs[base] + offset; | |
1561 | ||
1562 | kvm_debug("CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n", | |
1563 | cache, op, base, arch->gprs[base], offset); | |
1564 | ||
d116e812 DCZ |
1565 | /* |
1566 | * Treat INDEX_INV as a nop, basically issued by Linux on startup to | |
1567 | * invalidate the caches entirely by stepping through all the | |
1568 | * ways/indexes | |
e685c689 | 1569 | */ |
f4956f62 | 1570 | if (op == Index_Writeback_Inv) { |
d116e812 DCZ |
1571 | kvm_debug("@ %#lx/%#lx CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n", |
1572 | vcpu->arch.pc, vcpu->arch.gprs[31], cache, op, base, | |
1573 | arch->gprs[base], offset); | |
e685c689 | 1574 | |
f4956f62 | 1575 | if (cache == Cache_D) |
e685c689 | 1576 | r4k_blast_dcache(); |
f4956f62 | 1577 | else if (cache == Cache_I) |
e685c689 SL |
1578 | r4k_blast_icache(); |
1579 | else { | |
6ad78a5c DCZ |
1580 | kvm_err("%s: unsupported CACHE INDEX operation\n", |
1581 | __func__); | |
e685c689 SL |
1582 | return EMULATE_FAIL; |
1583 | } | |
1584 | ||
1585 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS | |
1586 | kvm_mips_trans_cache_index(inst, opc, vcpu); | |
1587 | #endif | |
1588 | goto done; | |
1589 | } | |
1590 | ||
1591 | preempt_disable(); | |
1592 | if (KVM_GUEST_KSEGX(va) == KVM_GUEST_KSEG0) { | |
d116e812 | 1593 | if (kvm_mips_host_tlb_lookup(vcpu, va) < 0) |
e685c689 | 1594 | kvm_mips_handle_kseg0_tlb_fault(va, vcpu); |
e685c689 SL |
1595 | } else if ((KVM_GUEST_KSEGX(va) < KVM_GUEST_KSEG0) || |
1596 | KVM_GUEST_KSEGX(va) == KVM_GUEST_KSEG23) { | |
1597 | int index; | |
1598 | ||
1599 | /* If an entry already exists then skip */ | |
d116e812 | 1600 | if (kvm_mips_host_tlb_lookup(vcpu, va) >= 0) |
e685c689 | 1601 | goto skip_fault; |
e685c689 | 1602 | |
d116e812 DCZ |
1603 | /* |
1604 | * If address not in the guest TLB, then give the guest a fault, | |
1605 | * the resulting handler will do the right thing | |
e685c689 SL |
1606 | */ |
1607 | index = kvm_mips_guest_tlb_lookup(vcpu, (va & VPN2_MASK) | | |
48c4ac97 | 1608 | (kvm_read_c0_guest_entryhi |
ca64c2be | 1609 | (cop0) & KVM_ENTRYHI_ASID)); |
e685c689 SL |
1610 | |
1611 | if (index < 0) { | |
e685c689 | 1612 | vcpu->arch.host_cp0_badvaddr = va; |
6df82a7b | 1613 | vcpu->arch.pc = curr_pc; |
e685c689 SL |
1614 | er = kvm_mips_emulate_tlbmiss_ld(cause, NULL, run, |
1615 | vcpu); | |
1616 | preempt_enable(); | |
1617 | goto dont_update_pc; | |
1618 | } else { | |
1619 | struct kvm_mips_tlb *tlb = &vcpu->arch.guest_tlb[index]; | |
d116e812 DCZ |
1620 | /* |
1621 | * Check if the entry is valid, if not then setup a TLB | |
1622 | * invalid exception to the guest | |
1623 | */ | |
e685c689 | 1624 | if (!TLB_IS_VALID(*tlb, va)) { |
6df82a7b JH |
1625 | vcpu->arch.host_cp0_badvaddr = va; |
1626 | vcpu->arch.pc = curr_pc; | |
e685c689 SL |
1627 | er = kvm_mips_emulate_tlbinv_ld(cause, NULL, |
1628 | run, vcpu); | |
1629 | preempt_enable(); | |
1630 | goto dont_update_pc; | |
1631 | } else { | |
d116e812 DCZ |
1632 | /* |
1633 | * We fault an entry from the guest tlb to the | |
1634 | * shadow host TLB | |
1635 | */ | |
26ee17ff | 1636 | kvm_mips_handle_mapped_seg_tlb_fault(vcpu, tlb); |
e685c689 SL |
1637 | } |
1638 | } | |
1639 | } else { | |
6ad78a5c DCZ |
1640 | kvm_err("INVALID CACHE INDEX/ADDRESS (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n", |
1641 | cache, op, base, arch->gprs[base], offset); | |
e685c689 SL |
1642 | er = EMULATE_FAIL; |
1643 | preempt_enable(); | |
cc81e948 | 1644 | goto done; |
e685c689 SL |
1645 | |
1646 | } | |
1647 | ||
1648 | skip_fault: | |
1649 | /* XXXKYMA: Only a subset of cache ops are supported, used by Linux */ | |
f4956f62 | 1650 | if (op_inst == Hit_Writeback_Inv_D || op_inst == Hit_Invalidate_D) { |
e685c689 SL |
1651 | flush_dcache_line(va); |
1652 | ||
1653 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS | |
d116e812 DCZ |
1654 | /* |
1655 | * Replace the CACHE instruction, with a SYNCI, not the same, | |
1656 | * but avoids a trap | |
1657 | */ | |
e685c689 SL |
1658 | kvm_mips_trans_cache_va(inst, opc, vcpu); |
1659 | #endif | |
f4956f62 | 1660 | } else if (op_inst == Hit_Invalidate_I) { |
e685c689 SL |
1661 | flush_dcache_line(va); |
1662 | flush_icache_line(va); | |
1663 | ||
1664 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS | |
1665 | /* Replace the CACHE instruction, with a SYNCI */ | |
1666 | kvm_mips_trans_cache_va(inst, opc, vcpu); | |
1667 | #endif | |
1668 | } else { | |
6ad78a5c DCZ |
1669 | kvm_err("NO-OP CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n", |
1670 | cache, op, base, arch->gprs[base], offset); | |
e685c689 | 1671 | er = EMULATE_FAIL; |
e685c689 SL |
1672 | } |
1673 | ||
1674 | preempt_enable(); | |
cc81e948 JH |
1675 | done: |
1676 | /* Rollback PC only if emulation was unsuccessful */ | |
1677 | if (er == EMULATE_FAIL) | |
1678 | vcpu->arch.pc = curr_pc; | |
e685c689 | 1679 | |
d116e812 | 1680 | dont_update_pc: |
cc81e948 JH |
1681 | /* |
1682 | * This is for exceptions whose emulation updates the PC, so do not | |
1683 | * overwrite the PC under any circumstances | |
1684 | */ | |
1685 | ||
e685c689 SL |
1686 | return er; |
1687 | } | |
1688 | ||
31cf7498 | 1689 | enum emulation_result kvm_mips_emulate_inst(u32 cause, u32 *opc, |
d116e812 DCZ |
1690 | struct kvm_run *run, |
1691 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
1692 | { |
1693 | enum emulation_result er = EMULATE_DONE; | |
8cffd197 | 1694 | u32 inst; |
e685c689 | 1695 | |
d116e812 DCZ |
1696 | /* Fetch the instruction. */ |
1697 | if (cause & CAUSEF_BD) | |
e685c689 | 1698 | opc += 1; |
e685c689 SL |
1699 | |
1700 | inst = kvm_get_inst(opc, vcpu); | |
1701 | ||
1702 | switch (((union mips_instruction)inst).r_format.opcode) { | |
1703 | case cop0_op: | |
1704 | er = kvm_mips_emulate_CP0(inst, opc, cause, run, vcpu); | |
1705 | break; | |
1706 | case sb_op: | |
1707 | case sh_op: | |
1708 | case sw_op: | |
1709 | er = kvm_mips_emulate_store(inst, cause, run, vcpu); | |
1710 | break; | |
1711 | case lb_op: | |
1712 | case lbu_op: | |
1713 | case lhu_op: | |
1714 | case lh_op: | |
1715 | case lw_op: | |
1716 | er = kvm_mips_emulate_load(inst, cause, run, vcpu); | |
1717 | break; | |
1718 | ||
1719 | case cache_op: | |
1720 | ++vcpu->stat.cache_exits; | |
1721 | trace_kvm_exit(vcpu, CACHE_EXITS); | |
1722 | er = kvm_mips_emulate_cache(inst, opc, cause, run, vcpu); | |
1723 | break; | |
1724 | ||
1725 | default: | |
6ad78a5c DCZ |
1726 | kvm_err("Instruction emulation not supported (%p/%#x)\n", opc, |
1727 | inst); | |
e685c689 SL |
1728 | kvm_arch_vcpu_dump_regs(vcpu); |
1729 | er = EMULATE_FAIL; | |
1730 | break; | |
1731 | } | |
1732 | ||
1733 | return er; | |
1734 | } | |
1735 | ||
31cf7498 | 1736 | enum emulation_result kvm_mips_emulate_syscall(u32 cause, |
bdb7ed86 | 1737 | u32 *opc, |
d116e812 DCZ |
1738 | struct kvm_run *run, |
1739 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
1740 | { |
1741 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
1742 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
1743 | enum emulation_result er = EMULATE_DONE; | |
1744 | ||
1745 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
1746 | /* save old pc */ | |
1747 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
1748 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
1749 | ||
1750 | if (cause & CAUSEF_BD) | |
1751 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
1752 | else | |
1753 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
1754 | ||
1755 | kvm_debug("Delivering SYSCALL @ pc %#lx\n", arch->pc); | |
1756 | ||
1757 | kvm_change_c0_guest_cause(cop0, (0xff), | |
16d100db | 1758 | (EXCCODE_SYS << CAUSEB_EXCCODE)); |
e685c689 SL |
1759 | |
1760 | /* Set PC to the exception entry point */ | |
1761 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
1762 | ||
1763 | } else { | |
6ad78a5c | 1764 | kvm_err("Trying to deliver SYSCALL when EXL is already set\n"); |
e685c689 SL |
1765 | er = EMULATE_FAIL; |
1766 | } | |
1767 | ||
1768 | return er; | |
1769 | } | |
1770 | ||
31cf7498 | 1771 | enum emulation_result kvm_mips_emulate_tlbmiss_ld(u32 cause, |
bdb7ed86 | 1772 | u32 *opc, |
d116e812 DCZ |
1773 | struct kvm_run *run, |
1774 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
1775 | { |
1776 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
1777 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
e685c689 | 1778 | unsigned long entryhi = (vcpu->arch. host_cp0_badvaddr & VPN2_MASK) | |
ca64c2be | 1779 | (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); |
e685c689 SL |
1780 | |
1781 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
1782 | /* save old pc */ | |
1783 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
1784 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
1785 | ||
1786 | if (cause & CAUSEF_BD) | |
1787 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
1788 | else | |
1789 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
1790 | ||
1791 | kvm_debug("[EXL == 0] delivering TLB MISS @ pc %#lx\n", | |
1792 | arch->pc); | |
1793 | ||
1794 | /* set pc to the exception entry point */ | |
1795 | arch->pc = KVM_GUEST_KSEG0 + 0x0; | |
1796 | ||
1797 | } else { | |
1798 | kvm_debug("[EXL == 1] delivering TLB MISS @ pc %#lx\n", | |
1799 | arch->pc); | |
1800 | ||
1801 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
1802 | } | |
1803 | ||
1804 | kvm_change_c0_guest_cause(cop0, (0xff), | |
16d100db | 1805 | (EXCCODE_TLBL << CAUSEB_EXCCODE)); |
e685c689 SL |
1806 | |
1807 | /* setup badvaddr, context and entryhi registers for the guest */ | |
1808 | kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); | |
1809 | /* XXXKYMA: is the context register used by linux??? */ | |
1810 | kvm_write_c0_guest_entryhi(cop0, entryhi); | |
1811 | /* Blow away the shadow host TLBs */ | |
1812 | kvm_mips_flush_host_tlb(1); | |
1813 | ||
d98403a5 | 1814 | return EMULATE_DONE; |
e685c689 SL |
1815 | } |
1816 | ||
31cf7498 | 1817 | enum emulation_result kvm_mips_emulate_tlbinv_ld(u32 cause, |
bdb7ed86 | 1818 | u32 *opc, |
d116e812 DCZ |
1819 | struct kvm_run *run, |
1820 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
1821 | { |
1822 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
1823 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
e685c689 SL |
1824 | unsigned long entryhi = |
1825 | (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) | | |
ca64c2be | 1826 | (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); |
e685c689 SL |
1827 | |
1828 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
1829 | /* save old pc */ | |
1830 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
1831 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
1832 | ||
1833 | if (cause & CAUSEF_BD) | |
1834 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
1835 | else | |
1836 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
1837 | ||
1838 | kvm_debug("[EXL == 0] delivering TLB INV @ pc %#lx\n", | |
1839 | arch->pc); | |
1840 | ||
1841 | /* set pc to the exception entry point */ | |
1842 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
1843 | ||
1844 | } else { | |
1845 | kvm_debug("[EXL == 1] delivering TLB MISS @ pc %#lx\n", | |
1846 | arch->pc); | |
1847 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
1848 | } | |
1849 | ||
1850 | kvm_change_c0_guest_cause(cop0, (0xff), | |
16d100db | 1851 | (EXCCODE_TLBL << CAUSEB_EXCCODE)); |
e685c689 SL |
1852 | |
1853 | /* setup badvaddr, context and entryhi registers for the guest */ | |
1854 | kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); | |
1855 | /* XXXKYMA: is the context register used by linux??? */ | |
1856 | kvm_write_c0_guest_entryhi(cop0, entryhi); | |
1857 | /* Blow away the shadow host TLBs */ | |
1858 | kvm_mips_flush_host_tlb(1); | |
1859 | ||
d98403a5 | 1860 | return EMULATE_DONE; |
e685c689 SL |
1861 | } |
1862 | ||
31cf7498 | 1863 | enum emulation_result kvm_mips_emulate_tlbmiss_st(u32 cause, |
bdb7ed86 | 1864 | u32 *opc, |
d116e812 DCZ |
1865 | struct kvm_run *run, |
1866 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
1867 | { |
1868 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
1869 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
e685c689 | 1870 | unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) | |
ca64c2be | 1871 | (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); |
e685c689 SL |
1872 | |
1873 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
1874 | /* save old pc */ | |
1875 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
1876 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
1877 | ||
1878 | if (cause & CAUSEF_BD) | |
1879 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
1880 | else | |
1881 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
1882 | ||
1883 | kvm_debug("[EXL == 0] Delivering TLB MISS @ pc %#lx\n", | |
1884 | arch->pc); | |
1885 | ||
1886 | /* Set PC to the exception entry point */ | |
1887 | arch->pc = KVM_GUEST_KSEG0 + 0x0; | |
1888 | } else { | |
1889 | kvm_debug("[EXL == 1] Delivering TLB MISS @ pc %#lx\n", | |
1890 | arch->pc); | |
1891 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
1892 | } | |
1893 | ||
1894 | kvm_change_c0_guest_cause(cop0, (0xff), | |
16d100db | 1895 | (EXCCODE_TLBS << CAUSEB_EXCCODE)); |
e685c689 SL |
1896 | |
1897 | /* setup badvaddr, context and entryhi registers for the guest */ | |
1898 | kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); | |
1899 | /* XXXKYMA: is the context register used by linux??? */ | |
1900 | kvm_write_c0_guest_entryhi(cop0, entryhi); | |
1901 | /* Blow away the shadow host TLBs */ | |
1902 | kvm_mips_flush_host_tlb(1); | |
1903 | ||
d98403a5 | 1904 | return EMULATE_DONE; |
e685c689 SL |
1905 | } |
1906 | ||
31cf7498 | 1907 | enum emulation_result kvm_mips_emulate_tlbinv_st(u32 cause, |
bdb7ed86 | 1908 | u32 *opc, |
d116e812 DCZ |
1909 | struct kvm_run *run, |
1910 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
1911 | { |
1912 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
1913 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
e685c689 | 1914 | unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) | |
ca64c2be | 1915 | (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); |
e685c689 SL |
1916 | |
1917 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
1918 | /* save old pc */ | |
1919 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
1920 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
1921 | ||
1922 | if (cause & CAUSEF_BD) | |
1923 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
1924 | else | |
1925 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
1926 | ||
1927 | kvm_debug("[EXL == 0] Delivering TLB MISS @ pc %#lx\n", | |
1928 | arch->pc); | |
1929 | ||
1930 | /* Set PC to the exception entry point */ | |
1931 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
1932 | } else { | |
1933 | kvm_debug("[EXL == 1] Delivering TLB MISS @ pc %#lx\n", | |
1934 | arch->pc); | |
1935 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
1936 | } | |
1937 | ||
1938 | kvm_change_c0_guest_cause(cop0, (0xff), | |
16d100db | 1939 | (EXCCODE_TLBS << CAUSEB_EXCCODE)); |
e685c689 SL |
1940 | |
1941 | /* setup badvaddr, context and entryhi registers for the guest */ | |
1942 | kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); | |
1943 | /* XXXKYMA: is the context register used by linux??? */ | |
1944 | kvm_write_c0_guest_entryhi(cop0, entryhi); | |
1945 | /* Blow away the shadow host TLBs */ | |
1946 | kvm_mips_flush_host_tlb(1); | |
1947 | ||
d98403a5 | 1948 | return EMULATE_DONE; |
e685c689 SL |
1949 | } |
1950 | ||
1951 | /* TLBMOD: store into address matching TLB with Dirty bit off */ | |
31cf7498 | 1952 | enum emulation_result kvm_mips_handle_tlbmod(u32 cause, u32 *opc, |
d116e812 DCZ |
1953 | struct kvm_run *run, |
1954 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
1955 | { |
1956 | enum emulation_result er = EMULATE_DONE; | |
e685c689 | 1957 | #ifdef DEBUG |
3d654833 JH |
1958 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
1959 | unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) | | |
ca64c2be | 1960 | (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); |
3d654833 JH |
1961 | int index; |
1962 | ||
d116e812 | 1963 | /* If address not in the guest TLB, then we are in trouble */ |
e685c689 SL |
1964 | index = kvm_mips_guest_tlb_lookup(vcpu, entryhi); |
1965 | if (index < 0) { | |
1966 | /* XXXKYMA Invalidate and retry */ | |
1967 | kvm_mips_host_tlb_inv(vcpu, vcpu->arch.host_cp0_badvaddr); | |
1968 | kvm_err("%s: host got TLBMOD for %#lx but entry not present in Guest TLB\n", | |
1969 | __func__, entryhi); | |
1970 | kvm_mips_dump_guest_tlbs(vcpu); | |
1971 | kvm_mips_dump_host_tlbs(); | |
1972 | return EMULATE_FAIL; | |
1973 | } | |
1974 | #endif | |
1975 | ||
1976 | er = kvm_mips_emulate_tlbmod(cause, opc, run, vcpu); | |
1977 | return er; | |
1978 | } | |
1979 | ||
31cf7498 | 1980 | enum emulation_result kvm_mips_emulate_tlbmod(u32 cause, |
bdb7ed86 | 1981 | u32 *opc, |
d116e812 DCZ |
1982 | struct kvm_run *run, |
1983 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
1984 | { |
1985 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
1986 | unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) | | |
ca64c2be | 1987 | (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); |
e685c689 | 1988 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
e685c689 SL |
1989 | |
1990 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
1991 | /* save old pc */ | |
1992 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
1993 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
1994 | ||
1995 | if (cause & CAUSEF_BD) | |
1996 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
1997 | else | |
1998 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
1999 | ||
2000 | kvm_debug("[EXL == 0] Delivering TLB MOD @ pc %#lx\n", | |
2001 | arch->pc); | |
2002 | ||
2003 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
2004 | } else { | |
2005 | kvm_debug("[EXL == 1] Delivering TLB MOD @ pc %#lx\n", | |
2006 | arch->pc); | |
2007 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
2008 | } | |
2009 | ||
16d100db JH |
2010 | kvm_change_c0_guest_cause(cop0, (0xff), |
2011 | (EXCCODE_MOD << CAUSEB_EXCCODE)); | |
e685c689 SL |
2012 | |
2013 | /* setup badvaddr, context and entryhi registers for the guest */ | |
2014 | kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); | |
2015 | /* XXXKYMA: is the context register used by linux??? */ | |
2016 | kvm_write_c0_guest_entryhi(cop0, entryhi); | |
2017 | /* Blow away the shadow host TLBs */ | |
2018 | kvm_mips_flush_host_tlb(1); | |
2019 | ||
d98403a5 | 2020 | return EMULATE_DONE; |
e685c689 SL |
2021 | } |
2022 | ||
31cf7498 | 2023 | enum emulation_result kvm_mips_emulate_fpu_exc(u32 cause, |
bdb7ed86 | 2024 | u32 *opc, |
d116e812 DCZ |
2025 | struct kvm_run *run, |
2026 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
2027 | { |
2028 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
2029 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
e685c689 SL |
2030 | |
2031 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
2032 | /* save old pc */ | |
2033 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
2034 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
2035 | ||
2036 | if (cause & CAUSEF_BD) | |
2037 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
2038 | else | |
2039 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
2040 | ||
2041 | } | |
2042 | ||
2043 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
2044 | ||
2045 | kvm_change_c0_guest_cause(cop0, (0xff), | |
16d100db | 2046 | (EXCCODE_CPU << CAUSEB_EXCCODE)); |
e685c689 SL |
2047 | kvm_change_c0_guest_cause(cop0, (CAUSEF_CE), (0x1 << CAUSEB_CE)); |
2048 | ||
d98403a5 | 2049 | return EMULATE_DONE; |
e685c689 SL |
2050 | } |
2051 | ||
31cf7498 | 2052 | enum emulation_result kvm_mips_emulate_ri_exc(u32 cause, |
bdb7ed86 | 2053 | u32 *opc, |
d116e812 DCZ |
2054 | struct kvm_run *run, |
2055 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
2056 | { |
2057 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
2058 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
2059 | enum emulation_result er = EMULATE_DONE; | |
2060 | ||
2061 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
2062 | /* save old pc */ | |
2063 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
2064 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
2065 | ||
2066 | if (cause & CAUSEF_BD) | |
2067 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
2068 | else | |
2069 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
2070 | ||
2071 | kvm_debug("Delivering RI @ pc %#lx\n", arch->pc); | |
2072 | ||
2073 | kvm_change_c0_guest_cause(cop0, (0xff), | |
16d100db | 2074 | (EXCCODE_RI << CAUSEB_EXCCODE)); |
e685c689 SL |
2075 | |
2076 | /* Set PC to the exception entry point */ | |
2077 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
2078 | ||
2079 | } else { | |
2080 | kvm_err("Trying to deliver RI when EXL is already set\n"); | |
2081 | er = EMULATE_FAIL; | |
2082 | } | |
2083 | ||
2084 | return er; | |
2085 | } | |
2086 | ||
31cf7498 | 2087 | enum emulation_result kvm_mips_emulate_bp_exc(u32 cause, |
bdb7ed86 | 2088 | u32 *opc, |
d116e812 DCZ |
2089 | struct kvm_run *run, |
2090 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
2091 | { |
2092 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
2093 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
2094 | enum emulation_result er = EMULATE_DONE; | |
2095 | ||
2096 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
2097 | /* save old pc */ | |
2098 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
2099 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
2100 | ||
2101 | if (cause & CAUSEF_BD) | |
2102 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
2103 | else | |
2104 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
2105 | ||
2106 | kvm_debug("Delivering BP @ pc %#lx\n", arch->pc); | |
2107 | ||
2108 | kvm_change_c0_guest_cause(cop0, (0xff), | |
16d100db | 2109 | (EXCCODE_BP << CAUSEB_EXCCODE)); |
e685c689 SL |
2110 | |
2111 | /* Set PC to the exception entry point */ | |
2112 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
2113 | ||
2114 | } else { | |
6ad78a5c | 2115 | kvm_err("Trying to deliver BP when EXL is already set\n"); |
e685c689 SL |
2116 | er = EMULATE_FAIL; |
2117 | } | |
2118 | ||
2119 | return er; | |
2120 | } | |
2121 | ||
31cf7498 | 2122 | enum emulation_result kvm_mips_emulate_trap_exc(u32 cause, |
bdb7ed86 | 2123 | u32 *opc, |
0a560427 JH |
2124 | struct kvm_run *run, |
2125 | struct kvm_vcpu *vcpu) | |
2126 | { | |
2127 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
2128 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
2129 | enum emulation_result er = EMULATE_DONE; | |
2130 | ||
2131 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
2132 | /* save old pc */ | |
2133 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
2134 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
2135 | ||
2136 | if (cause & CAUSEF_BD) | |
2137 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
2138 | else | |
2139 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
2140 | ||
2141 | kvm_debug("Delivering TRAP @ pc %#lx\n", arch->pc); | |
2142 | ||
2143 | kvm_change_c0_guest_cause(cop0, (0xff), | |
16d100db | 2144 | (EXCCODE_TR << CAUSEB_EXCCODE)); |
0a560427 JH |
2145 | |
2146 | /* Set PC to the exception entry point */ | |
2147 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
2148 | ||
2149 | } else { | |
2150 | kvm_err("Trying to deliver TRAP when EXL is already set\n"); | |
2151 | er = EMULATE_FAIL; | |
2152 | } | |
2153 | ||
2154 | return er; | |
2155 | } | |
2156 | ||
31cf7498 | 2157 | enum emulation_result kvm_mips_emulate_msafpe_exc(u32 cause, |
bdb7ed86 | 2158 | u32 *opc, |
c2537ed9 JH |
2159 | struct kvm_run *run, |
2160 | struct kvm_vcpu *vcpu) | |
2161 | { | |
2162 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
2163 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
2164 | enum emulation_result er = EMULATE_DONE; | |
2165 | ||
2166 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
2167 | /* save old pc */ | |
2168 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
2169 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
2170 | ||
2171 | if (cause & CAUSEF_BD) | |
2172 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
2173 | else | |
2174 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
2175 | ||
2176 | kvm_debug("Delivering MSAFPE @ pc %#lx\n", arch->pc); | |
2177 | ||
2178 | kvm_change_c0_guest_cause(cop0, (0xff), | |
16d100db | 2179 | (EXCCODE_MSAFPE << CAUSEB_EXCCODE)); |
c2537ed9 JH |
2180 | |
2181 | /* Set PC to the exception entry point */ | |
2182 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
2183 | ||
2184 | } else { | |
2185 | kvm_err("Trying to deliver MSAFPE when EXL is already set\n"); | |
2186 | er = EMULATE_FAIL; | |
2187 | } | |
2188 | ||
2189 | return er; | |
2190 | } | |
2191 | ||
31cf7498 | 2192 | enum emulation_result kvm_mips_emulate_fpe_exc(u32 cause, |
bdb7ed86 | 2193 | u32 *opc, |
1c0cd66a JH |
2194 | struct kvm_run *run, |
2195 | struct kvm_vcpu *vcpu) | |
2196 | { | |
2197 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
2198 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
2199 | enum emulation_result er = EMULATE_DONE; | |
2200 | ||
2201 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
2202 | /* save old pc */ | |
2203 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
2204 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
2205 | ||
2206 | if (cause & CAUSEF_BD) | |
2207 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
2208 | else | |
2209 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
2210 | ||
2211 | kvm_debug("Delivering FPE @ pc %#lx\n", arch->pc); | |
2212 | ||
2213 | kvm_change_c0_guest_cause(cop0, (0xff), | |
16d100db | 2214 | (EXCCODE_FPE << CAUSEB_EXCCODE)); |
1c0cd66a JH |
2215 | |
2216 | /* Set PC to the exception entry point */ | |
2217 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
2218 | ||
2219 | } else { | |
2220 | kvm_err("Trying to deliver FPE when EXL is already set\n"); | |
2221 | er = EMULATE_FAIL; | |
2222 | } | |
2223 | ||
2224 | return er; | |
2225 | } | |
2226 | ||
31cf7498 | 2227 | enum emulation_result kvm_mips_emulate_msadis_exc(u32 cause, |
bdb7ed86 | 2228 | u32 *opc, |
c2537ed9 JH |
2229 | struct kvm_run *run, |
2230 | struct kvm_vcpu *vcpu) | |
2231 | { | |
2232 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
2233 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
2234 | enum emulation_result er = EMULATE_DONE; | |
2235 | ||
2236 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
2237 | /* save old pc */ | |
2238 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
2239 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
2240 | ||
2241 | if (cause & CAUSEF_BD) | |
2242 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
2243 | else | |
2244 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
2245 | ||
2246 | kvm_debug("Delivering MSADIS @ pc %#lx\n", arch->pc); | |
2247 | ||
2248 | kvm_change_c0_guest_cause(cop0, (0xff), | |
16d100db | 2249 | (EXCCODE_MSADIS << CAUSEB_EXCCODE)); |
c2537ed9 JH |
2250 | |
2251 | /* Set PC to the exception entry point */ | |
2252 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
2253 | ||
2254 | } else { | |
2255 | kvm_err("Trying to deliver MSADIS when EXL is already set\n"); | |
2256 | er = EMULATE_FAIL; | |
2257 | } | |
2258 | ||
2259 | return er; | |
2260 | } | |
2261 | ||
d116e812 | 2262 | /* ll/sc, rdhwr, sync emulation */ |
e685c689 SL |
2263 | |
2264 | #define OPCODE 0xfc000000 | |
2265 | #define BASE 0x03e00000 | |
2266 | #define RT 0x001f0000 | |
2267 | #define OFFSET 0x0000ffff | |
2268 | #define LL 0xc0000000 | |
2269 | #define SC 0xe0000000 | |
2270 | #define SPEC0 0x00000000 | |
2271 | #define SPEC3 0x7c000000 | |
2272 | #define RD 0x0000f800 | |
2273 | #define FUNC 0x0000003f | |
2274 | #define SYNC 0x0000000f | |
2275 | #define RDHWR 0x0000003b | |
2276 | ||
31cf7498 | 2277 | enum emulation_result kvm_mips_handle_ri(u32 cause, u32 *opc, |
d116e812 DCZ |
2278 | struct kvm_run *run, |
2279 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
2280 | { |
2281 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
2282 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
2283 | enum emulation_result er = EMULATE_DONE; | |
2284 | unsigned long curr_pc; | |
8cffd197 | 2285 | u32 inst; |
e685c689 SL |
2286 | |
2287 | /* | |
2288 | * Update PC and hold onto current PC in case there is | |
2289 | * an error and we want to rollback the PC | |
2290 | */ | |
2291 | curr_pc = vcpu->arch.pc; | |
2292 | er = update_pc(vcpu, cause); | |
2293 | if (er == EMULATE_FAIL) | |
2294 | return er; | |
2295 | ||
d116e812 | 2296 | /* Fetch the instruction. */ |
e685c689 SL |
2297 | if (cause & CAUSEF_BD) |
2298 | opc += 1; | |
2299 | ||
2300 | inst = kvm_get_inst(opc, vcpu); | |
2301 | ||
2302 | if (inst == KVM_INVALID_INST) { | |
6ad78a5c | 2303 | kvm_err("%s: Cannot get inst @ %p\n", __func__, opc); |
e685c689 SL |
2304 | return EMULATE_FAIL; |
2305 | } | |
2306 | ||
2307 | if ((inst & OPCODE) == SPEC3 && (inst & FUNC) == RDHWR) { | |
26f4f3b5 | 2308 | int usermode = !KVM_GUEST_KERNEL_MODE(vcpu); |
e685c689 SL |
2309 | int rd = (inst & RD) >> 11; |
2310 | int rt = (inst & RT) >> 16; | |
26f4f3b5 JH |
2311 | /* If usermode, check RDHWR rd is allowed by guest HWREna */ |
2312 | if (usermode && !(kvm_read_c0_guest_hwrena(cop0) & BIT(rd))) { | |
2313 | kvm_debug("RDHWR %#x disallowed by HWREna @ %p\n", | |
2314 | rd, opc); | |
2315 | goto emulate_ri; | |
2316 | } | |
e685c689 SL |
2317 | switch (rd) { |
2318 | case 0: /* CPU number */ | |
2319 | arch->gprs[rt] = 0; | |
2320 | break; | |
2321 | case 1: /* SYNCI length */ | |
2322 | arch->gprs[rt] = min(current_cpu_data.dcache.linesz, | |
2323 | current_cpu_data.icache.linesz); | |
2324 | break; | |
2325 | case 2: /* Read count register */ | |
e30492bb | 2326 | arch->gprs[rt] = kvm_mips_read_count(vcpu); |
e685c689 SL |
2327 | break; |
2328 | case 3: /* Count register resolution */ | |
2329 | switch (current_cpu_data.cputype) { | |
2330 | case CPU_20KC: | |
2331 | case CPU_25KF: | |
2332 | arch->gprs[rt] = 1; | |
2333 | break; | |
2334 | default: | |
2335 | arch->gprs[rt] = 2; | |
2336 | } | |
2337 | break; | |
2338 | case 29: | |
e685c689 | 2339 | arch->gprs[rt] = kvm_read_c0_guest_userlocal(cop0); |
e685c689 SL |
2340 | break; |
2341 | ||
2342 | default: | |
15505679 | 2343 | kvm_debug("RDHWR %#x not supported @ %p\n", rd, opc); |
26f4f3b5 | 2344 | goto emulate_ri; |
e685c689 SL |
2345 | } |
2346 | } else { | |
15505679 | 2347 | kvm_debug("Emulate RI not supported @ %p: %#x\n", opc, inst); |
26f4f3b5 | 2348 | goto emulate_ri; |
e685c689 SL |
2349 | } |
2350 | ||
26f4f3b5 JH |
2351 | return EMULATE_DONE; |
2352 | ||
2353 | emulate_ri: | |
e685c689 | 2354 | /* |
26f4f3b5 JH |
2355 | * Rollback PC (if in branch delay slot then the PC already points to |
2356 | * branch target), and pass the RI exception to the guest OS. | |
e685c689 | 2357 | */ |
26f4f3b5 JH |
2358 | vcpu->arch.pc = curr_pc; |
2359 | return kvm_mips_emulate_ri_exc(cause, opc, run, vcpu); | |
e685c689 SL |
2360 | } |
2361 | ||
d116e812 DCZ |
2362 | enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu, |
2363 | struct kvm_run *run) | |
e685c689 SL |
2364 | { |
2365 | unsigned long *gpr = &vcpu->arch.gprs[vcpu->arch.io_gpr]; | |
2366 | enum emulation_result er = EMULATE_DONE; | |
e685c689 SL |
2367 | |
2368 | if (run->mmio.len > sizeof(*gpr)) { | |
6ad78a5c | 2369 | kvm_err("Bad MMIO length: %d", run->mmio.len); |
e685c689 SL |
2370 | er = EMULATE_FAIL; |
2371 | goto done; | |
2372 | } | |
2373 | ||
e685c689 SL |
2374 | er = update_pc(vcpu, vcpu->arch.pending_load_cause); |
2375 | if (er == EMULATE_FAIL) | |
2376 | return er; | |
2377 | ||
2378 | switch (run->mmio.len) { | |
2379 | case 4: | |
8cffd197 | 2380 | *gpr = *(s32 *) run->mmio.data; |
e685c689 SL |
2381 | break; |
2382 | ||
2383 | case 2: | |
2384 | if (vcpu->mmio_needed == 2) | |
8cffd197 | 2385 | *gpr = *(s16 *) run->mmio.data; |
e685c689 | 2386 | else |
8cffd197 | 2387 | *gpr = *(u16 *)run->mmio.data; |
e685c689 SL |
2388 | |
2389 | break; | |
2390 | case 1: | |
2391 | if (vcpu->mmio_needed == 2) | |
8cffd197 | 2392 | *gpr = *(s8 *) run->mmio.data; |
e685c689 SL |
2393 | else |
2394 | *gpr = *(u8 *) run->mmio.data; | |
2395 | break; | |
2396 | } | |
2397 | ||
2398 | if (vcpu->arch.pending_load_cause & CAUSEF_BD) | |
d116e812 DCZ |
2399 | kvm_debug("[%#lx] Completing %d byte BD Load to gpr %d (0x%08lx) type %d\n", |
2400 | vcpu->arch.pc, run->mmio.len, vcpu->arch.io_gpr, *gpr, | |
2401 | vcpu->mmio_needed); | |
e685c689 SL |
2402 | |
2403 | done: | |
2404 | return er; | |
2405 | } | |
2406 | ||
31cf7498 | 2407 | static enum emulation_result kvm_mips_emulate_exc(u32 cause, |
bdb7ed86 | 2408 | u32 *opc, |
d116e812 DCZ |
2409 | struct kvm_run *run, |
2410 | struct kvm_vcpu *vcpu) | |
e685c689 | 2411 | { |
8cffd197 | 2412 | u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f; |
e685c689 SL |
2413 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
2414 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
2415 | enum emulation_result er = EMULATE_DONE; | |
2416 | ||
2417 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
2418 | /* save old pc */ | |
2419 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
2420 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
2421 | ||
2422 | if (cause & CAUSEF_BD) | |
2423 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
2424 | else | |
2425 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
2426 | ||
2427 | kvm_change_c0_guest_cause(cop0, (0xff), | |
2428 | (exccode << CAUSEB_EXCCODE)); | |
2429 | ||
2430 | /* Set PC to the exception entry point */ | |
2431 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
2432 | kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); | |
2433 | ||
2434 | kvm_debug("Delivering EXC %d @ pc %#lx, badVaddr: %#lx\n", | |
2435 | exccode, kvm_read_c0_guest_epc(cop0), | |
2436 | kvm_read_c0_guest_badvaddr(cop0)); | |
2437 | } else { | |
6ad78a5c | 2438 | kvm_err("Trying to deliver EXC when EXL is already set\n"); |
e685c689 SL |
2439 | er = EMULATE_FAIL; |
2440 | } | |
2441 | ||
2442 | return er; | |
2443 | } | |
2444 | ||
31cf7498 | 2445 | enum emulation_result kvm_mips_check_privilege(u32 cause, |
bdb7ed86 | 2446 | u32 *opc, |
d116e812 DCZ |
2447 | struct kvm_run *run, |
2448 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
2449 | { |
2450 | enum emulation_result er = EMULATE_DONE; | |
8cffd197 | 2451 | u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f; |
e685c689 SL |
2452 | unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr; |
2453 | ||
2454 | int usermode = !KVM_GUEST_KERNEL_MODE(vcpu); | |
2455 | ||
2456 | if (usermode) { | |
2457 | switch (exccode) { | |
16d100db JH |
2458 | case EXCCODE_INT: |
2459 | case EXCCODE_SYS: | |
2460 | case EXCCODE_BP: | |
2461 | case EXCCODE_RI: | |
2462 | case EXCCODE_TR: | |
2463 | case EXCCODE_MSAFPE: | |
2464 | case EXCCODE_FPE: | |
2465 | case EXCCODE_MSADIS: | |
e685c689 SL |
2466 | break; |
2467 | ||
16d100db | 2468 | case EXCCODE_CPU: |
e685c689 SL |
2469 | if (((cause & CAUSEF_CE) >> CAUSEB_CE) == 0) |
2470 | er = EMULATE_PRIV_FAIL; | |
2471 | break; | |
2472 | ||
16d100db | 2473 | case EXCCODE_MOD: |
e685c689 SL |
2474 | break; |
2475 | ||
16d100db | 2476 | case EXCCODE_TLBL: |
d116e812 DCZ |
2477 | /* |
2478 | * We we are accessing Guest kernel space, then send an | |
2479 | * address error exception to the guest | |
2480 | */ | |
e685c689 | 2481 | if (badvaddr >= (unsigned long) KVM_GUEST_KSEG0) { |
6ad78a5c DCZ |
2482 | kvm_debug("%s: LD MISS @ %#lx\n", __func__, |
2483 | badvaddr); | |
e685c689 | 2484 | cause &= ~0xff; |
16d100db | 2485 | cause |= (EXCCODE_ADEL << CAUSEB_EXCCODE); |
e685c689 SL |
2486 | er = EMULATE_PRIV_FAIL; |
2487 | } | |
2488 | break; | |
2489 | ||
16d100db | 2490 | case EXCCODE_TLBS: |
d116e812 DCZ |
2491 | /* |
2492 | * We we are accessing Guest kernel space, then send an | |
2493 | * address error exception to the guest | |
2494 | */ | |
e685c689 | 2495 | if (badvaddr >= (unsigned long) KVM_GUEST_KSEG0) { |
6ad78a5c DCZ |
2496 | kvm_debug("%s: ST MISS @ %#lx\n", __func__, |
2497 | badvaddr); | |
e685c689 | 2498 | cause &= ~0xff; |
16d100db | 2499 | cause |= (EXCCODE_ADES << CAUSEB_EXCCODE); |
e685c689 SL |
2500 | er = EMULATE_PRIV_FAIL; |
2501 | } | |
2502 | break; | |
2503 | ||
16d100db | 2504 | case EXCCODE_ADES: |
6ad78a5c DCZ |
2505 | kvm_debug("%s: address error ST @ %#lx\n", __func__, |
2506 | badvaddr); | |
e685c689 SL |
2507 | if ((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR) { |
2508 | cause &= ~0xff; | |
16d100db | 2509 | cause |= (EXCCODE_TLBS << CAUSEB_EXCCODE); |
e685c689 SL |
2510 | } |
2511 | er = EMULATE_PRIV_FAIL; | |
2512 | break; | |
16d100db | 2513 | case EXCCODE_ADEL: |
6ad78a5c DCZ |
2514 | kvm_debug("%s: address error LD @ %#lx\n", __func__, |
2515 | badvaddr); | |
e685c689 SL |
2516 | if ((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR) { |
2517 | cause &= ~0xff; | |
16d100db | 2518 | cause |= (EXCCODE_TLBL << CAUSEB_EXCCODE); |
e685c689 SL |
2519 | } |
2520 | er = EMULATE_PRIV_FAIL; | |
2521 | break; | |
2522 | default: | |
2523 | er = EMULATE_PRIV_FAIL; | |
2524 | break; | |
2525 | } | |
2526 | } | |
2527 | ||
d116e812 | 2528 | if (er == EMULATE_PRIV_FAIL) |
e685c689 | 2529 | kvm_mips_emulate_exc(cause, opc, run, vcpu); |
d116e812 | 2530 | |
e685c689 SL |
2531 | return er; |
2532 | } | |
2533 | ||
d116e812 DCZ |
2534 | /* |
2535 | * User Address (UA) fault, this could happen if | |
e685c689 SL |
2536 | * (1) TLB entry not present/valid in both Guest and shadow host TLBs, in this |
2537 | * case we pass on the fault to the guest kernel and let it handle it. | |
2538 | * (2) TLB entry is present in the Guest TLB but not in the shadow, in this | |
2539 | * case we inject the TLB from the Guest TLB into the shadow host TLB | |
2540 | */ | |
31cf7498 | 2541 | enum emulation_result kvm_mips_handle_tlbmiss(u32 cause, |
bdb7ed86 | 2542 | u32 *opc, |
d116e812 DCZ |
2543 | struct kvm_run *run, |
2544 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
2545 | { |
2546 | enum emulation_result er = EMULATE_DONE; | |
8cffd197 | 2547 | u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f; |
e685c689 SL |
2548 | unsigned long va = vcpu->arch.host_cp0_badvaddr; |
2549 | int index; | |
2550 | ||
e4e94c0f JH |
2551 | kvm_debug("kvm_mips_handle_tlbmiss: badvaddr: %#lx\n", |
2552 | vcpu->arch.host_cp0_badvaddr); | |
e685c689 | 2553 | |
d116e812 DCZ |
2554 | /* |
2555 | * KVM would not have got the exception if this entry was valid in the | |
2556 | * shadow host TLB. Check the Guest TLB, if the entry is not there then | |
2557 | * send the guest an exception. The guest exc handler should then inject | |
2558 | * an entry into the guest TLB. | |
e685c689 SL |
2559 | */ |
2560 | index = kvm_mips_guest_tlb_lookup(vcpu, | |
caa1faa7 | 2561 | (va & VPN2_MASK) | |
ca64c2be PB |
2562 | (kvm_read_c0_guest_entryhi(vcpu->arch.cop0) & |
2563 | KVM_ENTRYHI_ASID)); | |
e685c689 | 2564 | if (index < 0) { |
16d100db | 2565 | if (exccode == EXCCODE_TLBL) { |
e685c689 | 2566 | er = kvm_mips_emulate_tlbmiss_ld(cause, opc, run, vcpu); |
16d100db | 2567 | } else if (exccode == EXCCODE_TLBS) { |
e685c689 SL |
2568 | er = kvm_mips_emulate_tlbmiss_st(cause, opc, run, vcpu); |
2569 | } else { | |
6ad78a5c DCZ |
2570 | kvm_err("%s: invalid exc code: %d\n", __func__, |
2571 | exccode); | |
e685c689 SL |
2572 | er = EMULATE_FAIL; |
2573 | } | |
2574 | } else { | |
2575 | struct kvm_mips_tlb *tlb = &vcpu->arch.guest_tlb[index]; | |
2576 | ||
d116e812 DCZ |
2577 | /* |
2578 | * Check if the entry is valid, if not then setup a TLB invalid | |
2579 | * exception to the guest | |
2580 | */ | |
e685c689 | 2581 | if (!TLB_IS_VALID(*tlb, va)) { |
16d100db | 2582 | if (exccode == EXCCODE_TLBL) { |
e685c689 SL |
2583 | er = kvm_mips_emulate_tlbinv_ld(cause, opc, run, |
2584 | vcpu); | |
16d100db | 2585 | } else if (exccode == EXCCODE_TLBS) { |
e685c689 SL |
2586 | er = kvm_mips_emulate_tlbinv_st(cause, opc, run, |
2587 | vcpu); | |
2588 | } else { | |
6ad78a5c DCZ |
2589 | kvm_err("%s: invalid exc code: %d\n", __func__, |
2590 | exccode); | |
e685c689 SL |
2591 | er = EMULATE_FAIL; |
2592 | } | |
2593 | } else { | |
d116e812 | 2594 | kvm_debug("Injecting hi: %#lx, lo0: %#lx, lo1: %#lx into shadow host TLB\n", |
9fbfb06a | 2595 | tlb->tlb_hi, tlb->tlb_lo[0], tlb->tlb_lo[1]); |
d116e812 DCZ |
2596 | /* |
2597 | * OK we have a Guest TLB entry, now inject it into the | |
2598 | * shadow host TLB | |
2599 | */ | |
26ee17ff | 2600 | kvm_mips_handle_mapped_seg_tlb_fault(vcpu, tlb); |
e685c689 SL |
2601 | } |
2602 | } | |
2603 | ||
2604 | return er; | |
2605 | } |