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MIPS: KVM: Emulate FPU bits in COP0 interface
[deliverable/linux.git] / arch / mips / kvm / mips.c
CommitLineData
669e846e
SL		 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * KVM/MIPS: MIPS specific KVM APIs
7 *
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
d116e812 10 */
669e846e
SL		 11
12#include <linux/errno.h>
13#include <linux/err.h>
98e91b84 14#include <linux/kdebug.h>
669e846e
SL		 15#include <linux/module.h>
16#include <linux/vmalloc.h>
17#include <linux/fs.h>
18#include <linux/bootmem.h>
f798217d 19#include <asm/fpu.h>
669e846e
SL		 20#include <asm/page.h>
21#include <asm/cacheflush.h>
22#include <asm/mmu_context.h>
c4c6f2ca 23#include <asm/pgtable.h>
669e846e
SL		 24
25#include <linux/kvm_host.h>
26
d7d5b05f
DCZ		 27#include "interrupt.h"
28#include "commpage.h"
669e846e
SL		 29
30#define CREATE_TRACE_POINTS
31#include "trace.h"
32
33#ifndef VECTORSPACING
34#define VECTORSPACING 0x100 /* for EI/VI mode */
35#endif
36
d116e812 37#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
669e846e 38struct kvm_stats_debugfs_item debugfs_entries[] = {
d116e812
DCZ		 39 { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU },
40 { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU },
41 { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU },
42 { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU },
43 { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
44 { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU },
45 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU },
46 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU },
47 { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU },
48 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU },
49 { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU },
50 { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU },
51 { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU },
0a560427 52 { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU },
d116e812 53 { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
f7819512 54 { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
d116e812 55 { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU },
669e846e
SL		 56 {NULL}
57};
58
59static int kvm_mips_reset_vcpu(struct kvm_vcpu *vcpu)
60{
61 int i;
d116e812 62
669e846e
SL		 63 for_each_possible_cpu(i) {
64 vcpu->arch.guest_kernel_asid[i] = 0;
65 vcpu->arch.guest_user_asid[i] = 0;
66 }
d116e812 67
669e846e
SL		 68 return 0;
69}
70
d116e812
DCZ		 71/*
72 * XXXKYMA: We are simulatoring a processor that has the WII bit set in
73 * Config7, so we are "runnable" if interrupts are pending
669e846e
SL		 74 */
75int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
76{
77 return !!(vcpu->arch.pending_exceptions);
78}
79
80int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
81{
82 return 1;
83}
84
13a34e06 85int kvm_arch_hardware_enable(void)
669e846e
SL		 86{
87 return 0;
88}
89
669e846e
SL		 90int kvm_arch_hardware_setup(void)
91{
92 return 0;
93}
94
669e846e
SL		 95void kvm_arch_check_processor_compat(void *rtn)
96{
d98403a5 97 *(int *)rtn = 0;
669e846e
SL		 98}
99
100static void kvm_mips_init_tlbs(struct kvm *kvm)
101{
102 unsigned long wired;
103
d116e812
DCZ		 104 /*
105 * Add a wired entry to the TLB, it is used to map the commpage to
106 * the Guest kernel
107 */
669e846e
SL		 108 wired = read_c0_wired();
109 write_c0_wired(wired + 1);
110 mtc0_tlbw_hazard();
111 kvm->arch.commpage_tlb = wired;
112
113 kvm_debug("[%d] commpage TLB: %d\n", smp_processor_id(),
114 kvm->arch.commpage_tlb);
115}
116
117static void kvm_mips_init_vm_percpu(void *arg)
118{
119 struct kvm *kvm = (struct kvm *)arg;
120
121 kvm_mips_init_tlbs(kvm);
122 kvm_mips_callbacks->vm_init(kvm);
123
124}
125
126int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
127{
128 if (atomic_inc_return(&kvm_mips_instance) == 1) {
6e95bfd2
JH		 129 kvm_debug("%s: 1st KVM instance, setup host TLB parameters\n",
130 __func__);
669e846e
SL		 131 on_each_cpu(kvm_mips_init_vm_percpu, kvm, 1);
132 }
133
669e846e
SL		 134 return 0;
135}
136
137void kvm_mips_free_vcpus(struct kvm *kvm)
138{
139 unsigned int i;
140 struct kvm_vcpu *vcpu;
141
142 /* Put the pages we reserved for the guest pmap */
143 for (i = 0; i < kvm->arch.guest_pmap_npages; i++) {
144 if (kvm->arch.guest_pmap[i] != KVM_INVALID_PAGE)
145 kvm_mips_release_pfn_clean(kvm->arch.guest_pmap[i]);
146 }
c6c0a663 147 kfree(kvm->arch.guest_pmap);
669e846e
SL		 148
149 kvm_for_each_vcpu(i, vcpu, kvm) {
150 kvm_arch_vcpu_free(vcpu);
151 }
152
153 mutex_lock(&kvm->lock);
154
155 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
156 kvm->vcpus[i] = NULL;
157
158 atomic_set(&kvm->online_vcpus, 0);
159
160 mutex_unlock(&kvm->lock);
161}
162
669e846e
SL		 163static void kvm_mips_uninit_tlbs(void *arg)
164{
165 /* Restore wired count */
166 write_c0_wired(0);
167 mtc0_tlbw_hazard();
168 /* Clear out all the TLBs */
169 kvm_local_flush_tlb_all();
170}
171
172void kvm_arch_destroy_vm(struct kvm *kvm)
173{
174 kvm_mips_free_vcpus(kvm);
175
176 /* If this is the last instance, restore wired count */
177 if (atomic_dec_return(&kvm_mips_instance) == 0) {
6e95bfd2
JH		 178 kvm_debug("%s: last KVM instance, restoring TLB parameters\n",
179 __func__);
669e846e
SL		 180 on_each_cpu(kvm_mips_uninit_tlbs, NULL, 1);
181 }
182}
183
d116e812
DCZ		 184long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
185 unsigned long arg)
669e846e 186{
ed829857 187 return -ENOIOCTLCMD;
669e846e
SL		 188}
189
5587027c
AK		 190int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
191 unsigned long npages)
669e846e
SL		 192{
193 return 0;
194}
195
196int kvm_arch_prepare_memory_region(struct kvm *kvm,
d116e812
DCZ		 197 struct kvm_memory_slot *memslot,
198 struct kvm_userspace_memory_region *mem,
199 enum kvm_mr_change change)
669e846e
SL		 200{
201 return 0;
202}
203
204void kvm_arch_commit_memory_region(struct kvm *kvm,
d116e812
DCZ		 205 struct kvm_userspace_memory_region *mem,
206 const struct kvm_memory_slot *old,
207 enum kvm_mr_change change)
669e846e
SL		 208{
209 unsigned long npages = 0;
d98403a5 210 int i;
669e846e
SL		 211
212 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
213 __func__, kvm, mem->slot, mem->guest_phys_addr,
214 mem->memory_size, mem->userspace_addr);
215
216 /* Setup Guest PMAP table */
217 if (!kvm->arch.guest_pmap) {
218 if (mem->slot == 0)
219 npages = mem->memory_size >> PAGE_SHIFT;
220
221 if (npages) {
222 kvm->arch.guest_pmap_npages = npages;
223 kvm->arch.guest_pmap =
224 kzalloc(npages * sizeof(unsigned long), GFP_KERNEL);
225
226 if (!kvm->arch.guest_pmap) {
227 kvm_err("Failed to allocate guest PMAP");
d98403a5 228 return;
669e846e
SL		 229 }
230
6e95bfd2
JH		 231 kvm_debug("Allocated space for Guest PMAP Table (%ld pages) @ %p\n",
232 npages, kvm->arch.guest_pmap);
669e846e
SL		 233
234 /* Now setup the page table */
d116e812 235 for (i = 0; i < npages; i++)
669e846e 236 kvm->arch.guest_pmap[i] = KVM_INVALID_PAGE;
669e846e
SL		 237 }
238 }
669e846e
SL		 239}
240
669e846e
SL		 241struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
242{
669e846e
SL		 243 int err, size, offset;
244 void *gebase;
245 int i;
246
247 struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
248
249 if (!vcpu) {
250 err = -ENOMEM;
251 goto out;
252 }
253
254 err = kvm_vcpu_init(vcpu, kvm, id);
255
256 if (err)
257 goto out_free_cpu;
258
6e95bfd2 259 kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
669e846e 260
d116e812
DCZ		 261 /*
262 * Allocate space for host mode exception handlers that handle
669e846e
SL		 263 * guest mode exits
264 */
d116e812 265 if (cpu_has_veic || cpu_has_vint)
669e846e 266 size = 0x200 + VECTORSPACING * 64;
d116e812 267 else
7006e2df 268 size = 0x4000;
669e846e
SL		 269
270 /* Save Linux EBASE */
271 vcpu->arch.host_ebase = (void *)read_c0_ebase();
272
273 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
274
275 if (!gebase) {
276 err = -ENOMEM;
277 goto out_free_cpu;
278 }
6e95bfd2
JH		 279 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
280 ALIGN(size, PAGE_SIZE), gebase);
669e846e
SL		 281
282 /* Save new ebase */
283 vcpu->arch.guest_ebase = gebase;
284
285 /* Copy L1 Guest Exception handler to correct offset */
286
287 /* TLB Refill, EXL = 0 */
288 memcpy(gebase, mips32_exception,
289 mips32_exceptionEnd - mips32_exception);
290
291 /* General Exception Entry point */
292 memcpy(gebase + 0x180, mips32_exception,
293 mips32_exceptionEnd - mips32_exception);
294
295 /* For vectored interrupts poke the exception code @ all offsets 0-7 */
296 for (i = 0; i < 8; i++) {
297 kvm_debug("L1 Vectored handler @ %p\n",
298 gebase + 0x200 + (i * VECTORSPACING));
299 memcpy(gebase + 0x200 + (i * VECTORSPACING), mips32_exception,
300 mips32_exceptionEnd - mips32_exception);
301 }
302
303 /* General handler, relocate to unmapped space for sanity's sake */
304 offset = 0x2000;
6e95bfd2
JH		 305 kvm_debug("Installing KVM Exception handlers @ %p, %#x bytes\n",
306 gebase + offset,
307 mips32_GuestExceptionEnd - mips32_GuestException);
669e846e
SL		 308
309 memcpy(gebase + offset, mips32_GuestException,
310 mips32_GuestExceptionEnd - mips32_GuestException);
311
312 /* Invalidate the icache for these ranges */
facaaec1
JH		 313 local_flush_icache_range((unsigned long)gebase,
314 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
669e846e 315
d116e812
DCZ		 316 /*
317 * Allocate comm page for guest kernel, a TLB will be reserved for
318 * mapping GVA @ 0xFFFF8000 to this page
319 */
669e846e
SL		 320 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
321
322 if (!vcpu->arch.kseg0_commpage) {
323 err = -ENOMEM;
324 goto out_free_gebase;
325 }
326
6e95bfd2 327 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
669e846e
SL		 328 kvm_mips_commpage_init(vcpu);
329
330 /* Init */
331 vcpu->arch.last_sched_cpu = -1;
332
333 /* Start off the timer */
e30492bb 334 kvm_mips_init_count(vcpu);
669e846e
SL		 335
336 return vcpu;
337
338out_free_gebase:
339 kfree(gebase);
340
341out_free_cpu:
342 kfree(vcpu);
343
344out:
345 return ERR_PTR(err);
346}
347
348void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
349{
350 hrtimer_cancel(&vcpu->arch.comparecount_timer);
351
352 kvm_vcpu_uninit(vcpu);
353
354 kvm_mips_dump_stats(vcpu);
355
c6c0a663
JH		 356 kfree(vcpu->arch.guest_ebase);
357 kfree(vcpu->arch.kseg0_commpage);
8c9eb041 358 kfree(vcpu);
669e846e
SL		 359}
360
361void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
362{
363 kvm_arch_vcpu_free(vcpu);
364}
365
d116e812
DCZ		 366int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
367 struct kvm_guest_debug *dbg)
669e846e 368{
ed829857 369 return -ENOIOCTLCMD;
669e846e
SL		 370}
371
372int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
373{
374 int r = 0;
375 sigset_t sigsaved;
376
377 if (vcpu->sigset_active)
378 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
379
380 if (vcpu->mmio_needed) {
381 if (!vcpu->mmio_is_write)
382 kvm_mips_complete_mmio_load(vcpu, run);
383 vcpu->mmio_needed = 0;
384 }
385
f798217d
JH		 386 lose_fpu(1);
387
044f0f03 388 local_irq_disable();
669e846e
SL		 389 /* Check if we have any exceptions/interrupts pending */
390 kvm_mips_deliver_interrupts(vcpu,
391 kvm_read_c0_guest_cause(vcpu->arch.cop0));
392
669e846e
SL		 393 kvm_guest_enter();
394
c4c6f2ca
JH		 395 /* Disable hardware page table walking while in guest */
396 htw_stop();
397
669e846e
SL		 398 r = __kvm_mips_vcpu_run(run, vcpu);
399
c4c6f2ca
JH		 400 /* Re-enable HTW before enabling interrupts */
401 htw_start();
402
669e846e
SL		 403 kvm_guest_exit();
404 local_irq_enable();
405
406 if (vcpu->sigset_active)
407 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
408
409 return r;
410}
411
d116e812
DCZ		 412int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
413 struct kvm_mips_interrupt *irq)
669e846e
SL		 414{
415 int intr = (int)irq->irq;
416 struct kvm_vcpu *dvcpu = NULL;
417
418 if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
419 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
420 (int)intr);
421
422 if (irq->cpu == -1)
423 dvcpu = vcpu;
424 else
425 dvcpu = vcpu->kvm->vcpus[irq->cpu];
426
427 if (intr == 2 || intr == 3 || intr == 4) {
428 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
429
430 } else if (intr == -2 || intr == -3 || intr == -4) {
431 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
432 } else {
433 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
434 irq->cpu, irq->irq);
435 return -EINVAL;
436 }
437
438 dvcpu->arch.wait = 0;
439
d116e812 440 if (waitqueue_active(&dvcpu->wq))
669e846e 441 wake_up_interruptible(&dvcpu->wq);
669e846e
SL		 442
443 return 0;
444}
445
d116e812
DCZ		 446int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
447 struct kvm_mp_state *mp_state)
669e846e 448{
ed829857 449 return -ENOIOCTLCMD;
669e846e
SL		 450}
451
d116e812
DCZ		 452int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
453 struct kvm_mp_state *mp_state)
669e846e 454{
ed829857 455 return -ENOIOCTLCMD;
669e846e
SL		 456}
457
4c73fb2b
DD		 458static u64 kvm_mips_get_one_regs[] = {
459 KVM_REG_MIPS_R0,
460 KVM_REG_MIPS_R1,
461 KVM_REG_MIPS_R2,
462 KVM_REG_MIPS_R3,
463 KVM_REG_MIPS_R4,
464 KVM_REG_MIPS_R5,
465 KVM_REG_MIPS_R6,
466 KVM_REG_MIPS_R7,
467 KVM_REG_MIPS_R8,
468 KVM_REG_MIPS_R9,
469 KVM_REG_MIPS_R10,
470 KVM_REG_MIPS_R11,
471 KVM_REG_MIPS_R12,
472 KVM_REG_MIPS_R13,
473 KVM_REG_MIPS_R14,
474 KVM_REG_MIPS_R15,
475 KVM_REG_MIPS_R16,
476 KVM_REG_MIPS_R17,
477 KVM_REG_MIPS_R18,
478 KVM_REG_MIPS_R19,
479 KVM_REG_MIPS_R20,
480 KVM_REG_MIPS_R21,
481 KVM_REG_MIPS_R22,
482 KVM_REG_MIPS_R23,
483 KVM_REG_MIPS_R24,
484 KVM_REG_MIPS_R25,
485 KVM_REG_MIPS_R26,
486 KVM_REG_MIPS_R27,
487 KVM_REG_MIPS_R28,
488 KVM_REG_MIPS_R29,
489 KVM_REG_MIPS_R30,
490 KVM_REG_MIPS_R31,
491
492 KVM_REG_MIPS_HI,
493 KVM_REG_MIPS_LO,
494 KVM_REG_MIPS_PC,
495
496 KVM_REG_MIPS_CP0_INDEX,
497 KVM_REG_MIPS_CP0_CONTEXT,
7767b7d2 498 KVM_REG_MIPS_CP0_USERLOCAL,
4c73fb2b
DD		 499 KVM_REG_MIPS_CP0_PAGEMASK,
500 KVM_REG_MIPS_CP0_WIRED,
16fd5c1d 501 KVM_REG_MIPS_CP0_HWRENA,
4c73fb2b 502 KVM_REG_MIPS_CP0_BADVADDR,
f8be02da 503 KVM_REG_MIPS_CP0_COUNT,
4c73fb2b 504 KVM_REG_MIPS_CP0_ENTRYHI,
f8be02da 505 KVM_REG_MIPS_CP0_COMPARE,
4c73fb2b
DD		 506 KVM_REG_MIPS_CP0_STATUS,
507 KVM_REG_MIPS_CP0_CAUSE,
fb6df0cd 508 KVM_REG_MIPS_CP0_EPC,
1068eaaf 509 KVM_REG_MIPS_CP0_PRID,
4c73fb2b
DD		 510 KVM_REG_MIPS_CP0_CONFIG,
511 KVM_REG_MIPS_CP0_CONFIG1,
512 KVM_REG_MIPS_CP0_CONFIG2,
513 KVM_REG_MIPS_CP0_CONFIG3,
c771607a
JH		 514 KVM_REG_MIPS_CP0_CONFIG4,
515 KVM_REG_MIPS_CP0_CONFIG5,
4c73fb2b 516 KVM_REG_MIPS_CP0_CONFIG7,
f8239342
JH		 517 KVM_REG_MIPS_CP0_ERROREPC,
518
519 KVM_REG_MIPS_COUNT_CTL,
520 KVM_REG_MIPS_COUNT_RESUME,
f74a8e22 521 KVM_REG_MIPS_COUNT_HZ,
4c73fb2b
DD		 522};
523
524static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
525 const struct kvm_one_reg *reg)
526{
4c73fb2b 527 struct mips_coproc *cop0 = vcpu->arch.cop0;
f8be02da 528 int ret;
4c73fb2b
DD		 529 s64 v;
530
531 switch (reg->id) {
532 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
533 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
534 break;
535 case KVM_REG_MIPS_HI:
536 v = (long)vcpu->arch.hi;
537 break;
538 case KVM_REG_MIPS_LO:
539 v = (long)vcpu->arch.lo;
540 break;
541 case KVM_REG_MIPS_PC:
542 v = (long)vcpu->arch.pc;
543 break;
544
545 case KVM_REG_MIPS_CP0_INDEX:
546 v = (long)kvm_read_c0_guest_index(cop0);
547 break;
548 case KVM_REG_MIPS_CP0_CONTEXT:
549 v = (long)kvm_read_c0_guest_context(cop0);
550 break;
7767b7d2
JH		 551 case KVM_REG_MIPS_CP0_USERLOCAL:
552 v = (long)kvm_read_c0_guest_userlocal(cop0);
553 break;
4c73fb2b
DD		 554 case KVM_REG_MIPS_CP0_PAGEMASK:
555 v = (long)kvm_read_c0_guest_pagemask(cop0);
556 break;
557 case KVM_REG_MIPS_CP0_WIRED:
558 v = (long)kvm_read_c0_guest_wired(cop0);
559 break;
16fd5c1d
JH		 560 case KVM_REG_MIPS_CP0_HWRENA:
561 v = (long)kvm_read_c0_guest_hwrena(cop0);
562 break;
4c73fb2b
DD		 563 case KVM_REG_MIPS_CP0_BADVADDR:
564 v = (long)kvm_read_c0_guest_badvaddr(cop0);
565 break;
566 case KVM_REG_MIPS_CP0_ENTRYHI:
567 v = (long)kvm_read_c0_guest_entryhi(cop0);
568 break;
f8be02da
JH		 569 case KVM_REG_MIPS_CP0_COMPARE:
570 v = (long)kvm_read_c0_guest_compare(cop0);
571 break;
4c73fb2b
DD		 572 case KVM_REG_MIPS_CP0_STATUS:
573 v = (long)kvm_read_c0_guest_status(cop0);
574 break;
575 case KVM_REG_MIPS_CP0_CAUSE:
576 v = (long)kvm_read_c0_guest_cause(cop0);
577 break;
fb6df0cd
JH		 578 case KVM_REG_MIPS_CP0_EPC:
579 v = (long)kvm_read_c0_guest_epc(cop0);
580 break;
1068eaaf
JH		 581 case KVM_REG_MIPS_CP0_PRID:
582 v = (long)kvm_read_c0_guest_prid(cop0);
583 break;
4c73fb2b
DD		 584 case KVM_REG_MIPS_CP0_CONFIG:
585 v = (long)kvm_read_c0_guest_config(cop0);
586 break;
587 case KVM_REG_MIPS_CP0_CONFIG1:
588 v = (long)kvm_read_c0_guest_config1(cop0);
589 break;
590 case KVM_REG_MIPS_CP0_CONFIG2:
591 v = (long)kvm_read_c0_guest_config2(cop0);
592 break;
593 case KVM_REG_MIPS_CP0_CONFIG3:
594 v = (long)kvm_read_c0_guest_config3(cop0);
595 break;
c771607a
JH		 596 case KVM_REG_MIPS_CP0_CONFIG4:
597 v = (long)kvm_read_c0_guest_config4(cop0);
598 break;
599 case KVM_REG_MIPS_CP0_CONFIG5:
600 v = (long)kvm_read_c0_guest_config5(cop0);
601 break;
4c73fb2b
DD		 602 case KVM_REG_MIPS_CP0_CONFIG7:
603 v = (long)kvm_read_c0_guest_config7(cop0);
604 break;
e93d4c15
JH		 605 case KVM_REG_MIPS_CP0_ERROREPC:
606 v = (long)kvm_read_c0_guest_errorepc(cop0);
607 break;
f8be02da
JH		 608 /* registers to be handled specially */
609 case KVM_REG_MIPS_CP0_COUNT:
f8239342
JH		 610 case KVM_REG_MIPS_COUNT_CTL:
611 case KVM_REG_MIPS_COUNT_RESUME:
f74a8e22 612 case KVM_REG_MIPS_COUNT_HZ:
f8be02da
JH		 613 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
614 if (ret)
615 return ret;
616 break;
4c73fb2b
DD		 617 default:
618 return -EINVAL;
619 }
681865d4
DD		 620 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
621 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
d116e812 622
681865d4
DD		 623 return put_user(v, uaddr64);
624 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
625 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
626 u32 v32 = (u32)v;
d116e812 627
681865d4
DD		 628 return put_user(v32, uaddr32);
629 } else {
630 return -EINVAL;
631 }
4c73fb2b
DD		 632}
633
634static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
635 const struct kvm_one_reg *reg)
636{
4c73fb2b
DD		 637 struct mips_coproc *cop0 = vcpu->arch.cop0;
638 u64 v;
639
681865d4
DD		 640 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
641 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
642
643 if (get_user(v, uaddr64) != 0)
644 return -EFAULT;
645 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
646 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
647 s32 v32;
648
649 if (get_user(v32, uaddr32) != 0)
650 return -EFAULT;
651 v = (s64)v32;
652 } else {
653 return -EINVAL;
654 }
4c73fb2b
DD		 655
656 switch (reg->id) {
657 case KVM_REG_MIPS_R0:
658 /* Silently ignore requests to set $0 */
659 break;
660 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
661 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
662 break;
663 case KVM_REG_MIPS_HI:
664 vcpu->arch.hi = v;
665 break;
666 case KVM_REG_MIPS_LO:
667 vcpu->arch.lo = v;
668 break;
669 case KVM_REG_MIPS_PC:
670 vcpu->arch.pc = v;
671 break;
672
673 case KVM_REG_MIPS_CP0_INDEX:
674 kvm_write_c0_guest_index(cop0, v);
675 break;
676 case KVM_REG_MIPS_CP0_CONTEXT:
677 kvm_write_c0_guest_context(cop0, v);
678 break;
7767b7d2
JH		 679 case KVM_REG_MIPS_CP0_USERLOCAL:
680 kvm_write_c0_guest_userlocal(cop0, v);
681 break;
4c73fb2b
DD		 682 case KVM_REG_MIPS_CP0_PAGEMASK:
683 kvm_write_c0_guest_pagemask(cop0, v);
684 break;
685 case KVM_REG_MIPS_CP0_WIRED:
686 kvm_write_c0_guest_wired(cop0, v);
687 break;
16fd5c1d
JH		 688 case KVM_REG_MIPS_CP0_HWRENA:
689 kvm_write_c0_guest_hwrena(cop0, v);
690 break;
4c73fb2b
DD		 691 case KVM_REG_MIPS_CP0_BADVADDR:
692 kvm_write_c0_guest_badvaddr(cop0, v);
693 break;
694 case KVM_REG_MIPS_CP0_ENTRYHI:
695 kvm_write_c0_guest_entryhi(cop0, v);
696 break;
697 case KVM_REG_MIPS_CP0_STATUS:
698 kvm_write_c0_guest_status(cop0, v);
699 break;
fb6df0cd
JH		 700 case KVM_REG_MIPS_CP0_EPC:
701 kvm_write_c0_guest_epc(cop0, v);
702 break;
1068eaaf
JH		 703 case KVM_REG_MIPS_CP0_PRID:
704 kvm_write_c0_guest_prid(cop0, v);
705 break;
4c73fb2b
DD		 706 case KVM_REG_MIPS_CP0_ERROREPC:
707 kvm_write_c0_guest_errorepc(cop0, v);
708 break;
f8be02da
JH		 709 /* registers to be handled specially */
710 case KVM_REG_MIPS_CP0_COUNT:
711 case KVM_REG_MIPS_CP0_COMPARE:
e30492bb 712 case KVM_REG_MIPS_CP0_CAUSE:
c771607a
JH		 713 case KVM_REG_MIPS_CP0_CONFIG:
714 case KVM_REG_MIPS_CP0_CONFIG1:
715 case KVM_REG_MIPS_CP0_CONFIG2:
716 case KVM_REG_MIPS_CP0_CONFIG3:
717 case KVM_REG_MIPS_CP0_CONFIG4:
718 case KVM_REG_MIPS_CP0_CONFIG5:
f8239342
JH		 719 case KVM_REG_MIPS_COUNT_CTL:
720 case KVM_REG_MIPS_COUNT_RESUME:
f74a8e22 721 case KVM_REG_MIPS_COUNT_HZ:
f8be02da 722 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
4c73fb2b
DD		 723 default:
724 return -EINVAL;
725 }
726 return 0;
727}
728
d116e812
DCZ		 729long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
730 unsigned long arg)
669e846e
SL		 731{
732 struct kvm_vcpu *vcpu = filp->private_data;
733 void __user *argp = (void __user *)arg;
734 long r;
669e846e
SL		 735
736 switch (ioctl) {
4c73fb2b
DD		 737 case KVM_SET_ONE_REG:
738 case KVM_GET_ONE_REG: {
739 struct kvm_one_reg reg;
d116e812 740
4c73fb2b
DD		 741 if (copy_from_user(&reg, argp, sizeof(reg)))
742 return -EFAULT;
743 if (ioctl == KVM_SET_ONE_REG)
744 return kvm_mips_set_reg(vcpu, &reg);
745 else
746 return kvm_mips_get_reg(vcpu, &reg);
747 }
748 case KVM_GET_REG_LIST: {
749 struct kvm_reg_list __user *user_list = argp;
750 u64 __user *reg_dest;
751 struct kvm_reg_list reg_list;
752 unsigned n;
753
754 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
755 return -EFAULT;
756 n = reg_list.n;
757 reg_list.n = ARRAY_SIZE(kvm_mips_get_one_regs);
758 if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
759 return -EFAULT;
760 if (n < reg_list.n)
761 return -E2BIG;
762 reg_dest = user_list->reg;
763 if (copy_to_user(reg_dest, kvm_mips_get_one_regs,
764 sizeof(kvm_mips_get_one_regs)))
765 return -EFAULT;
766 return 0;
767 }
669e846e
SL		 768 case KVM_NMI:
769 /* Treat the NMI as a CPU reset */
770 r = kvm_mips_reset_vcpu(vcpu);
771 break;
772 case KVM_INTERRUPT:
773 {
774 struct kvm_mips_interrupt irq;
d116e812 775
669e846e
SL		 776 r = -EFAULT;
777 if (copy_from_user(&irq, argp, sizeof(irq)))
778 goto out;
779
669e846e
SL		 780 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
781 irq.irq);
782
783 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
784 break;
785 }
786 default:
4c73fb2b 787 r = -ENOIOCTLCMD;
669e846e
SL		 788 }
789
790out:
791 return r;
792}
793
d116e812 794/* Get (and clear) the dirty memory log for a memory slot. */
669e846e
SL		 795int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
796{
797 struct kvm_memory_slot *memslot;
798 unsigned long ga, ga_end;
799 int is_dirty = 0;
800 int r;
801 unsigned long n;
802
803 mutex_lock(&kvm->slots_lock);
804
805 r = kvm_get_dirty_log(kvm, log, &is_dirty);
806 if (r)
807 goto out;
808
809 /* If nothing is dirty, don't bother messing with page tables. */
810 if (is_dirty) {
811 memslot = &kvm->memslots->memslots[log->slot];
812
813 ga = memslot->base_gfn << PAGE_SHIFT;
814 ga_end = ga + (memslot->npages << PAGE_SHIFT);
815
6ad78a5c
DCZ		 816 kvm_info("%s: dirty, ga: %#lx, ga_end %#lx\n", __func__, ga,
817 ga_end);
669e846e
SL		 818
819 n = kvm_dirty_bitmap_bytes(memslot);
820 memset(memslot->dirty_bitmap, 0, n);
821 }
822
823 r = 0;
824out:
825 mutex_unlock(&kvm->slots_lock);
826 return r;
827
828}
829
830long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
831{
832 long r;
833
834 switch (ioctl) {
835 default:
ed829857 836 r = -ENOIOCTLCMD;
669e846e
SL		 837 }
838
839 return r;
840}
841
842int kvm_arch_init(void *opaque)
843{
669e846e
SL		 844 if (kvm_mips_callbacks) {
845 kvm_err("kvm: module already exists\n");
846 return -EEXIST;
847 }
848
d98403a5 849 return kvm_mips_emulation_init(&kvm_mips_callbacks);
669e846e
SL		 850}
851
852void kvm_arch_exit(void)
853{
854 kvm_mips_callbacks = NULL;
855}
856
d116e812
DCZ		 857int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
858 struct kvm_sregs *sregs)
669e846e 859{
ed829857 860 return -ENOIOCTLCMD;
669e846e
SL		 861}
862
d116e812
DCZ		 863int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
864 struct kvm_sregs *sregs)
669e846e 865{
ed829857 866 return -ENOIOCTLCMD;
669e846e
SL		 867}
868
31928aa5 869void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
669e846e 870{
669e846e
SL		 871}
872
873int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
874{
ed829857 875 return -ENOIOCTLCMD;
669e846e
SL		 876}
877
878int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
879{
ed829857 880 return -ENOIOCTLCMD;
669e846e
SL		 881}
882
883int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
884{
885 return VM_FAULT_SIGBUS;
886}
887
784aa3d7 888int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
669e846e
SL		 889{
890 int r;
891
892 switch (ext) {
4c73fb2b
DD		 893 case KVM_CAP_ONE_REG:
894 r = 1;
895 break;
669e846e
SL		 896 case KVM_CAP_COALESCED_MMIO:
897 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
898 break;
899 default:
900 r = 0;
901 break;
902 }
903 return r;
669e846e
SL		 904}
905
906int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
907{
908 return kvm_mips_pending_timer(vcpu);
909}
910
911int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
912{
913 int i;
914 struct mips_coproc *cop0;
915
916 if (!vcpu)
917 return -1;
918
6ad78a5c
DCZ		 919 kvm_debug("VCPU Register Dump:\n");
920 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
921 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
669e846e
SL		 922
923 for (i = 0; i < 32; i += 4) {
6ad78a5c 924 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
669e846e
SL		 925 vcpu->arch.gprs[i],
926 vcpu->arch.gprs[i + 1],
927 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
928 }
6ad78a5c
DCZ		 929 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
930 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
669e846e
SL		 931
932 cop0 = vcpu->arch.cop0;
6ad78a5c
DCZ		 933 kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n",
934 kvm_read_c0_guest_status(cop0),
935 kvm_read_c0_guest_cause(cop0));
669e846e 936
6ad78a5c 937 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
669e846e
SL		 938
939 return 0;
940}
941
942int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
943{
944 int i;
945
8d17dd04 946 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
bf32ebf6 947 vcpu->arch.gprs[i] = regs->gpr[i];
8d17dd04 948 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
669e846e
SL		 949 vcpu->arch.hi = regs->hi;
950 vcpu->arch.lo = regs->lo;
951 vcpu->arch.pc = regs->pc;
952
4c73fb2b 953 return 0;
669e846e
SL		 954}
955
956int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
957{
958 int i;
959
8d17dd04 960 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
bf32ebf6 961 regs->gpr[i] = vcpu->arch.gprs[i];
669e846e
SL		 962
963 regs->hi = vcpu->arch.hi;
964 regs->lo = vcpu->arch.lo;
965 regs->pc = vcpu->arch.pc;
966
4c73fb2b 967 return 0;
669e846e
SL		 968}
969
0fae34f4 970static void kvm_mips_comparecount_func(unsigned long data)
669e846e
SL		 971{
972 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
973
974 kvm_mips_callbacks->queue_timer_int(vcpu);
975
976 vcpu->arch.wait = 0;
d116e812 977 if (waitqueue_active(&vcpu->wq))
669e846e 978 wake_up_interruptible(&vcpu->wq);
669e846e
SL		 979}
980
d116e812 981/* low level hrtimer wake routine */
0fae34f4 982static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
669e846e
SL		 983{
984 struct kvm_vcpu *vcpu;
985
986 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
987 kvm_mips_comparecount_func((unsigned long) vcpu);
e30492bb 988 return kvm_mips_count_timeout(vcpu);
669e846e
SL		 989}
990
991int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
992{
993 kvm_mips_callbacks->vcpu_init(vcpu);
994 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
995 HRTIMER_MODE_REL);
996 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
669e846e
SL		 997 return 0;
998}
999
d116e812
DCZ		 1000int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1001 struct kvm_translation *tr)
669e846e
SL		 1002{
1003 return 0;
1004}
1005
1006/* Initial guest state */
1007int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1008{
1009 return kvm_mips_callbacks->vcpu_setup(vcpu);
1010}
1011
d116e812 1012static void kvm_mips_set_c0_status(void)
669e846e
SL		 1013{
1014 uint32_t status = read_c0_status();
1015
669e846e
SL		 1016 if (cpu_has_dsp)
1017 status |= (ST0_MX);
1018
1019 write_c0_status(status);
1020 ehb();
1021}
1022
1023/*
1024 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1025 */
1026int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1027{
1028 uint32_t cause = vcpu->arch.host_cp0_cause;
1029 uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1030 uint32_t __user *opc = (uint32_t __user *) vcpu->arch.pc;
1031 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1032 enum emulation_result er = EMULATE_DONE;
1033 int ret = RESUME_GUEST;
1034
c4c6f2ca
JH		 1035 /* re-enable HTW before enabling interrupts */
1036 htw_start();
1037
669e846e
SL		 1038 /* Set a default exit reason */
1039 run->exit_reason = KVM_EXIT_UNKNOWN;
1040 run->ready_for_interrupt_injection = 1;
1041
d116e812
DCZ		 1042 /*
1043 * Set the appropriate status bits based on host CPU features,
1044 * before we hit the scheduler
1045 */
669e846e
SL		 1046 kvm_mips_set_c0_status();
1047
1048 local_irq_enable();
1049
1050 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1051 cause, opc, run, vcpu);
1052
d116e812
DCZ		 1053 /*
1054 * Do a privilege check, if in UM most of these exit conditions end up
669e846e
SL		 1055 * causing an exception to be delivered to the Guest Kernel
1056 */
1057 er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1058 if (er == EMULATE_PRIV_FAIL) {
1059 goto skip_emul;
1060 } else if (er == EMULATE_FAIL) {
1061 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1062 ret = RESUME_HOST;
1063 goto skip_emul;
1064 }
1065
1066 switch (exccode) {
1067 case T_INT:
1068 kvm_debug("[%d]T_INT @ %p\n", vcpu->vcpu_id, opc);
1069
1070 ++vcpu->stat.int_exits;
1071 trace_kvm_exit(vcpu, INT_EXITS);
1072
d116e812 1073 if (need_resched())
669e846e 1074 cond_resched();
669e846e
SL		 1075
1076 ret = RESUME_GUEST;
1077 break;
1078
1079 case T_COP_UNUSABLE:
1080 kvm_debug("T_COP_UNUSABLE: @ PC: %p\n", opc);
1081
1082 ++vcpu->stat.cop_unusable_exits;
1083 trace_kvm_exit(vcpu, COP_UNUSABLE_EXITS);
1084 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1085 /* XXXKYMA: Might need to return to user space */
d116e812 1086 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
669e846e 1087 ret = RESUME_HOST;
669e846e
SL		 1088 break;
1089
1090 case T_TLB_MOD:
1091 ++vcpu->stat.tlbmod_exits;
1092 trace_kvm_exit(vcpu, TLBMOD_EXITS);
1093 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1094 break;
1095
1096 case T_TLB_ST_MISS:
d116e812
DCZ		 1097 kvm_debug("TLB ST fault: cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n",
1098 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1099 badvaddr);
669e846e
SL		 1100
1101 ++vcpu->stat.tlbmiss_st_exits;
1102 trace_kvm_exit(vcpu, TLBMISS_ST_EXITS);
1103 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1104 break;
1105
1106 case T_TLB_LD_MISS:
1107 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1108 cause, opc, badvaddr);
1109
1110 ++vcpu->stat.tlbmiss_ld_exits;
1111 trace_kvm_exit(vcpu, TLBMISS_LD_EXITS);
1112 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1113 break;
1114
1115 case T_ADDR_ERR_ST:
1116 ++vcpu->stat.addrerr_st_exits;
1117 trace_kvm_exit(vcpu, ADDRERR_ST_EXITS);
1118 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1119 break;
1120
1121 case T_ADDR_ERR_LD:
1122 ++vcpu->stat.addrerr_ld_exits;
1123 trace_kvm_exit(vcpu, ADDRERR_LD_EXITS);
1124 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1125 break;
1126
1127 case T_SYSCALL:
1128 ++vcpu->stat.syscall_exits;
1129 trace_kvm_exit(vcpu, SYSCALL_EXITS);
1130 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1131 break;
1132
1133 case T_RES_INST:
1134 ++vcpu->stat.resvd_inst_exits;
1135 trace_kvm_exit(vcpu, RESVD_INST_EXITS);
1136 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1137 break;
1138
1139 case T_BREAK:
1140 ++vcpu->stat.break_inst_exits;
1141 trace_kvm_exit(vcpu, BREAK_INST_EXITS);
1142 ret = kvm_mips_callbacks->handle_break(vcpu);
1143 break;
1144
0a560427
JH		 1145 case T_TRAP:
1146 ++vcpu->stat.trap_inst_exits;
1147 trace_kvm_exit(vcpu, TRAP_INST_EXITS);
1148 ret = kvm_mips_callbacks->handle_trap(vcpu);
1149 break;
1150
98119ad5
JH		 1151 case T_MSADIS:
1152 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1153 break;
1154
669e846e 1155 default:
d116e812
DCZ		 1156 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#lx\n",
1157 exccode, opc, kvm_get_inst(opc, vcpu), badvaddr,
1158 kvm_read_c0_guest_status(vcpu->arch.cop0));
669e846e
SL		 1159 kvm_arch_vcpu_dump_regs(vcpu);
1160 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1161 ret = RESUME_HOST;
1162 break;
1163
1164 }
1165
1166skip_emul:
1167 local_irq_disable();
1168
1169 if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1170 kvm_mips_deliver_interrupts(vcpu, cause);
1171
1172 if (!(ret & RESUME_HOST)) {
d116e812 1173 /* Only check for signals if not already exiting to userspace */
669e846e
SL		 1174 if (signal_pending(current)) {
1175 run->exit_reason = KVM_EXIT_INTR;
1176 ret = (-EINTR << 2) | RESUME_HOST;
1177 ++vcpu->stat.signal_exits;
1178 trace_kvm_exit(vcpu, SIGNAL_EXITS);
1179 }
1180 }
1181
98e91b84
JH		 1182 if (ret == RESUME_GUEST) {
1183 /*
1184 * If FPU is enabled (i.e. the guest's FPU context is live),
1185 * restore FCR31.
1186 *
1187 * This should be before returning to the guest exception
1188 * vector, as it may well cause an FP exception if there are
1189 * pending exception bits unmasked. (see
1190 * kvm_mips_csr_die_notifier() for how that is handled).
1191 */
1192 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1193 read_c0_status() & ST0_CU1)
1194 __kvm_restore_fcsr(&vcpu->arch);
1195 }
1196
c4c6f2ca
JH		 1197 /* Disable HTW before returning to guest or host */
1198 htw_stop();
1199
669e846e
SL		 1200 return ret;
1201}
1202
98e91b84
JH		 1203/* Enable FPU for guest and restore context */
1204void kvm_own_fpu(struct kvm_vcpu *vcpu)
1205{
1206 struct mips_coproc *cop0 = vcpu->arch.cop0;
1207 unsigned int sr, cfg5;
1208
1209 preempt_disable();
1210
1211 /*
1212 * Enable FPU for guest
1213 * We set FR and FRE according to guest context
1214 */
1215 sr = kvm_read_c0_guest_status(cop0);
1216 change_c0_status(ST0_CU1 | ST0_FR, sr);
1217 if (cpu_has_fre) {
1218 cfg5 = kvm_read_c0_guest_config5(cop0);
1219 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1220 }
1221 enable_fpu_hazard();
1222
1223 /* If guest FPU state not active, restore it now */
1224 if (!(vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)) {
1225 __kvm_restore_fpu(&vcpu->arch);
1226 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_FPU;
1227 }
1228
1229 preempt_enable();
1230}
1231
1232/* Drop FPU without saving it */
1233void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1234{
1235 preempt_disable();
1236 if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) {
1237 clear_c0_status(ST0_CU1 | ST0_FR);
1238 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_FPU;
1239 }
1240 preempt_enable();
1241}
1242
1243/* Save and disable FPU */
1244void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1245{
1246 /*
1247 * FPU gets disabled in root context (hardware) when it is disabled in
1248 * guest context (software), but the register state in the hardware may
1249 * still be in use. This is why we explicitly re-enable the hardware
1250 * before saving.
1251 */
1252
1253 preempt_disable();
1254 if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) {
1255 set_c0_status(ST0_CU1);
1256 enable_fpu_hazard();
1257
1258 __kvm_save_fpu(&vcpu->arch);
1259 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_FPU;
1260
1261 /* Disable FPU */
1262 clear_c0_status(ST0_CU1 | ST0_FR);
1263 }
1264 preempt_enable();
1265}
1266
1267/*
1268 * Step over a specific ctc1 to FCSR which is used to restore guest FCSR state
1269 * and may trigger a "harmless" FP exception if cause bits are set in the value
1270 * being written.
1271 */
1272static int kvm_mips_csr_die_notify(struct notifier_block *self,
1273 unsigned long cmd, void *ptr)
1274{
1275 struct die_args *args = (struct die_args *)ptr;
1276 struct pt_regs *regs = args->regs;
1277 unsigned long pc;
1278
1279 /* Only interested in FPE */
1280 if (cmd != DIE_FP)
1281 return NOTIFY_DONE;
1282
1283 /* Return immediately if guest context isn't active */
1284 if (!(current->flags & PF_VCPU))
1285 return NOTIFY_DONE;
1286
1287 /* Should never get here from user mode */
1288 BUG_ON(user_mode(regs));
1289
1290 pc = instruction_pointer(regs);
1291 switch (cmd) {
1292 case DIE_FP:
1293 /* match 2nd instruction in __kvm_restore_fcsr */
1294 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1295 return NOTIFY_DONE;
1296 break;
1297 }
1298
1299 /* Move PC forward a little and continue executing */
1300 instruction_pointer(regs) += 4;
1301
1302 return NOTIFY_STOP;
1303}
1304
1305static struct notifier_block kvm_mips_csr_die_notifier = {
1306 .notifier_call = kvm_mips_csr_die_notify,
1307};
1308
669e846e
SL		 1309int __init kvm_mips_init(void)
1310{
1311 int ret;
1312
1313 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1314
1315 if (ret)
1316 return ret;
1317
98e91b84
JH		 1318 register_die_notifier(&kvm_mips_csr_die_notifier);
1319
d116e812
DCZ		 1320 /*
1321 * On MIPS, kernel modules are executed from "mapped space", which
1322 * requires TLBs. The TLB handling code is statically linked with
d7d5b05f 1323 * the rest of the kernel (tlb.c) to avoid the possibility of
d116e812
DCZ		 1324 * double faulting. The issue is that the TLB code references
1325 * routines that are part of the the KVM module, which are only
1326 * available once the module is loaded.
669e846e
SL		 1327 */
1328 kvm_mips_gfn_to_pfn = gfn_to_pfn;
1329 kvm_mips_release_pfn_clean = kvm_release_pfn_clean;
1330 kvm_mips_is_error_pfn = is_error_pfn;
1331
669e846e
SL		 1332 return 0;
1333}
1334
1335void __exit kvm_mips_exit(void)
1336{
1337 kvm_exit();
1338
1339 kvm_mips_gfn_to_pfn = NULL;
1340 kvm_mips_release_pfn_clean = NULL;
1341 kvm_mips_is_error_pfn = NULL;
98e91b84
JH		 1342
1343 unregister_die_notifier(&kvm_mips_csr_die_notifier);
669e846e
SL		 1344}
1345
1346module_init(kvm_mips_init);
1347module_exit(kvm_mips_exit);
1348
1349EXPORT_TRACEPOINT_SYMBOL(kvm_exit);
Linux kernel - Deliverables
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