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MIPS: uasm: Add r6 MUL encoding
[deliverable/linux.git] / arch / mips / kvm / mips.c
CommitLineData
669e846e
SL		 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * KVM/MIPS: MIPS specific KVM APIs
7 *
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
d116e812 10 */
669e846e 11
05108709 12#include <linux/bitops.h>
669e846e
SL		 13#include <linux/errno.h>
14#include <linux/err.h>
98e91b84 15#include <linux/kdebug.h>
669e846e
SL		 16#include <linux/module.h>
17#include <linux/vmalloc.h>
18#include <linux/fs.h>
19#include <linux/bootmem.h>
f798217d 20#include <asm/fpu.h>
669e846e
SL		 21#include <asm/page.h>
22#include <asm/cacheflush.h>
23#include <asm/mmu_context.h>
c4c6f2ca 24#include <asm/pgtable.h>
669e846e
SL		 25
26#include <linux/kvm_host.h>
27
d7d5b05f
DCZ		 28#include "interrupt.h"
29#include "commpage.h"
669e846e
SL		 30
31#define CREATE_TRACE_POINTS
32#include "trace.h"
33
34#ifndef VECTORSPACING
35#define VECTORSPACING 0x100 /* for EI/VI mode */
36#endif
37
d116e812 38#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
669e846e 39struct kvm_stats_debugfs_item debugfs_entries[] = {
d116e812
DCZ		 40 { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU },
41 { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU },
42 { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU },
43 { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU },
44 { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
45 { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU },
46 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU },
47 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU },
48 { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU },
49 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU },
50 { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU },
51 { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU },
52 { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU },
0a560427 53 { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU },
c2537ed9 54 { "msa_fpe", VCPU_STAT(msa_fpe_exits), KVM_STAT_VCPU },
1c0cd66a 55 { "fpe", VCPU_STAT(fpe_exits), KVM_STAT_VCPU },
c2537ed9 56 { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
d116e812 57 { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
f7819512 58 { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
62bea5bf 59 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU },
3491caf2 60 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU },
d116e812 61 { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU },
669e846e
SL		 62 {NULL}
63};
64
65static int kvm_mips_reset_vcpu(struct kvm_vcpu *vcpu)
66{
67 int i;
d116e812 68
669e846e
SL		 69 for_each_possible_cpu(i) {
70 vcpu->arch.guest_kernel_asid[i] = 0;
71 vcpu->arch.guest_user_asid[i] = 0;
72 }
d116e812 73
669e846e
SL		 74 return 0;
75}
76
d116e812
DCZ		 77/*
78 * XXXKYMA: We are simulatoring a processor that has the WII bit set in
79 * Config7, so we are "runnable" if interrupts are pending
669e846e
SL		 80 */
81int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
82{
83 return !!(vcpu->arch.pending_exceptions);
84}
85
86int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
87{
88 return 1;
89}
90
13a34e06 91int kvm_arch_hardware_enable(void)
669e846e
SL		 92{
93 return 0;
94}
95
669e846e
SL		 96int kvm_arch_hardware_setup(void)
97{
98 return 0;
99}
100
669e846e
SL		 101void kvm_arch_check_processor_compat(void *rtn)
102{
d98403a5 103 *(int *)rtn = 0;
669e846e
SL		 104}
105
106static void kvm_mips_init_tlbs(struct kvm *kvm)
107{
108 unsigned long wired;
109
d116e812
DCZ		 110 /*
111 * Add a wired entry to the TLB, it is used to map the commpage to
112 * the Guest kernel
113 */
669e846e
SL		 114 wired = read_c0_wired();
115 write_c0_wired(wired + 1);
116 mtc0_tlbw_hazard();
117 kvm->arch.commpage_tlb = wired;
118
119 kvm_debug("[%d] commpage TLB: %d\n", smp_processor_id(),
120 kvm->arch.commpage_tlb);
121}
122
123static void kvm_mips_init_vm_percpu(void *arg)
124{
125 struct kvm *kvm = (struct kvm *)arg;
126
127 kvm_mips_init_tlbs(kvm);
128 kvm_mips_callbacks->vm_init(kvm);
129
130}
131
132int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
133{
134 if (atomic_inc_return(&kvm_mips_instance) == 1) {
6e95bfd2
JH		 135 kvm_debug("%s: 1st KVM instance, setup host TLB parameters\n",
136 __func__);
669e846e
SL		 137 on_each_cpu(kvm_mips_init_vm_percpu, kvm, 1);
138 }
139
669e846e
SL		 140 return 0;
141}
142
143void kvm_mips_free_vcpus(struct kvm *kvm)
144{
145 unsigned int i;
146 struct kvm_vcpu *vcpu;
147
148 /* Put the pages we reserved for the guest pmap */
149 for (i = 0; i < kvm->arch.guest_pmap_npages; i++) {
150 if (kvm->arch.guest_pmap[i] != KVM_INVALID_PAGE)
9befad23 151 kvm_release_pfn_clean(kvm->arch.guest_pmap[i]);
669e846e 152 }
c6c0a663 153 kfree(kvm->arch.guest_pmap);
669e846e
SL		 154
155 kvm_for_each_vcpu(i, vcpu, kvm) {
156 kvm_arch_vcpu_free(vcpu);
157 }
158
159 mutex_lock(&kvm->lock);
160
161 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
162 kvm->vcpus[i] = NULL;
163
164 atomic_set(&kvm->online_vcpus, 0);
165
166 mutex_unlock(&kvm->lock);
167}
168
669e846e
SL		 169static void kvm_mips_uninit_tlbs(void *arg)
170{
171 /* Restore wired count */
172 write_c0_wired(0);
173 mtc0_tlbw_hazard();
174 /* Clear out all the TLBs */
175 kvm_local_flush_tlb_all();
176}
177
178void kvm_arch_destroy_vm(struct kvm *kvm)
179{
180 kvm_mips_free_vcpus(kvm);
181
182 /* If this is the last instance, restore wired count */
183 if (atomic_dec_return(&kvm_mips_instance) == 0) {
6e95bfd2
JH		 184 kvm_debug("%s: last KVM instance, restoring TLB parameters\n",
185 __func__);
669e846e
SL		 186 on_each_cpu(kvm_mips_uninit_tlbs, NULL, 1);
187 }
188}
189
d116e812
DCZ		 190long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
191 unsigned long arg)
669e846e 192{
ed829857 193 return -ENOIOCTLCMD;
669e846e
SL		 194}
195
5587027c
AK		 196int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
197 unsigned long npages)
669e846e
SL		 198{
199 return 0;
200}
201
202int kvm_arch_prepare_memory_region(struct kvm *kvm,
d116e812 203 struct kvm_memory_slot *memslot,
09170a49 204 const struct kvm_userspace_memory_region *mem,
d116e812 205 enum kvm_mr_change change)
669e846e
SL		 206{
207 return 0;
208}
209
210void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 211 const struct kvm_userspace_memory_region *mem,
d116e812 212 const struct kvm_memory_slot *old,
f36f3f28 213 const struct kvm_memory_slot *new,
d116e812 214 enum kvm_mr_change change)
669e846e
SL		 215{
216 unsigned long npages = 0;
d98403a5 217 int i;
669e846e
SL		 218
219 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
220 __func__, kvm, mem->slot, mem->guest_phys_addr,
221 mem->memory_size, mem->userspace_addr);
222
223 /* Setup Guest PMAP table */
224 if (!kvm->arch.guest_pmap) {
225 if (mem->slot == 0)
226 npages = mem->memory_size >> PAGE_SHIFT;
227
228 if (npages) {
229 kvm->arch.guest_pmap_npages = npages;
230 kvm->arch.guest_pmap =
231 kzalloc(npages * sizeof(unsigned long), GFP_KERNEL);
232
233 if (!kvm->arch.guest_pmap) {
f7fdcb60 234 kvm_err("Failed to allocate guest PMAP\n");
d98403a5 235 return;
669e846e
SL		 236 }
237
6e95bfd2
JH		 238 kvm_debug("Allocated space for Guest PMAP Table (%ld pages) @ %p\n",
239 npages, kvm->arch.guest_pmap);
669e846e
SL		 240
241 /* Now setup the page table */
d116e812 242 for (i = 0; i < npages; i++)
669e846e 243 kvm->arch.guest_pmap[i] = KVM_INVALID_PAGE;
669e846e
SL		 244 }
245 }
669e846e
SL		 246}
247
669e846e
SL		 248struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
249{
669e846e
SL		 250 int err, size, offset;
251 void *gebase;
252 int i;
253
254 struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
255
256 if (!vcpu) {
257 err = -ENOMEM;
258 goto out;
259 }
260
261 err = kvm_vcpu_init(vcpu, kvm, id);
262
263 if (err)
264 goto out_free_cpu;
265
6e95bfd2 266 kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
669e846e 267
d116e812
DCZ		 268 /*
269 * Allocate space for host mode exception handlers that handle
669e846e
SL		 270 * guest mode exits
271 */
d116e812 272 if (cpu_has_veic || cpu_has_vint)
669e846e 273 size = 0x200 + VECTORSPACING * 64;
d116e812 274 else
7006e2df 275 size = 0x4000;
669e846e 276
669e846e
SL		 277 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
278
279 if (!gebase) {
280 err = -ENOMEM;
585bb8f9 281 goto out_uninit_cpu;
669e846e 282 }
6e95bfd2
JH		 283 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
284 ALIGN(size, PAGE_SIZE), gebase);
669e846e
SL		 285
286 /* Save new ebase */
287 vcpu->arch.guest_ebase = gebase;
288
289 /* Copy L1 Guest Exception handler to correct offset */
290
291 /* TLB Refill, EXL = 0 */
292 memcpy(gebase, mips32_exception,
293 mips32_exceptionEnd - mips32_exception);
294
295 /* General Exception Entry point */
296 memcpy(gebase + 0x180, mips32_exception,
297 mips32_exceptionEnd - mips32_exception);
298
299 /* For vectored interrupts poke the exception code @ all offsets 0-7 */
300 for (i = 0; i < 8; i++) {
301 kvm_debug("L1 Vectored handler @ %p\n",
302 gebase + 0x200 + (i * VECTORSPACING));
303 memcpy(gebase + 0x200 + (i * VECTORSPACING), mips32_exception,
304 mips32_exceptionEnd - mips32_exception);
305 }
306
307 /* General handler, relocate to unmapped space for sanity's sake */
308 offset = 0x2000;
6e95bfd2
JH		 309 kvm_debug("Installing KVM Exception handlers @ %p, %#x bytes\n",
310 gebase + offset,
311 mips32_GuestExceptionEnd - mips32_GuestException);
669e846e
SL		 312
313 memcpy(gebase + offset, mips32_GuestException,
314 mips32_GuestExceptionEnd - mips32_GuestException);
315
797179bc
JH		 316#ifdef MODULE
317 offset += mips32_GuestExceptionEnd - mips32_GuestException;
318 memcpy(gebase + offset, (char *)__kvm_mips_vcpu_run,
319 __kvm_mips_vcpu_run_end - (char *)__kvm_mips_vcpu_run);
320 vcpu->arch.vcpu_run = gebase + offset;
321#else
322 vcpu->arch.vcpu_run = __kvm_mips_vcpu_run;
323#endif
324
669e846e 325 /* Invalidate the icache for these ranges */
facaaec1
JH		 326 local_flush_icache_range((unsigned long)gebase,
327 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
669e846e 328
d116e812
DCZ		 329 /*
330 * Allocate comm page for guest kernel, a TLB will be reserved for
331 * mapping GVA @ 0xFFFF8000 to this page
332 */
669e846e
SL		 333 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
334
335 if (!vcpu->arch.kseg0_commpage) {
336 err = -ENOMEM;
337 goto out_free_gebase;
338 }
339
6e95bfd2 340 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
669e846e
SL		 341 kvm_mips_commpage_init(vcpu);
342
343 /* Init */
344 vcpu->arch.last_sched_cpu = -1;
345
346 /* Start off the timer */
e30492bb 347 kvm_mips_init_count(vcpu);
669e846e
SL		 348
349 return vcpu;
350
351out_free_gebase:
352 kfree(gebase);
353
585bb8f9
JH		 354out_uninit_cpu:
355 kvm_vcpu_uninit(vcpu);
356
669e846e
SL		 357out_free_cpu:
358 kfree(vcpu);
359
360out:
361 return ERR_PTR(err);
362}
363
364void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
365{
366 hrtimer_cancel(&vcpu->arch.comparecount_timer);
367
368 kvm_vcpu_uninit(vcpu);
369
370 kvm_mips_dump_stats(vcpu);
371
c6c0a663
JH		 372 kfree(vcpu->arch.guest_ebase);
373 kfree(vcpu->arch.kseg0_commpage);
8c9eb041 374 kfree(vcpu);
669e846e
SL		 375}
376
377void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
378{
379 kvm_arch_vcpu_free(vcpu);
380}
381
d116e812
DCZ		 382int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
383 struct kvm_guest_debug *dbg)
669e846e 384{
ed829857 385 return -ENOIOCTLCMD;
669e846e
SL		 386}
387
388int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
389{
390 int r = 0;
391 sigset_t sigsaved;
392
393 if (vcpu->sigset_active)
394 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
395
396 if (vcpu->mmio_needed) {
397 if (!vcpu->mmio_is_write)
398 kvm_mips_complete_mmio_load(vcpu, run);
399 vcpu->mmio_needed = 0;
400 }
401
f798217d
JH		 402 lose_fpu(1);
403
044f0f03 404 local_irq_disable();
669e846e
SL		 405 /* Check if we have any exceptions/interrupts pending */
406 kvm_mips_deliver_interrupts(vcpu,
407 kvm_read_c0_guest_cause(vcpu->arch.cop0));
408
6edaa530 409 guest_enter_irqoff();
669e846e 410
c4c6f2ca
JH		 411 /* Disable hardware page table walking while in guest */
412 htw_stop();
413
93258604 414 trace_kvm_enter(vcpu);
797179bc 415 r = vcpu->arch.vcpu_run(run, vcpu);
93258604 416 trace_kvm_out(vcpu);
669e846e 417
c4c6f2ca
JH		 418 /* Re-enable HTW before enabling interrupts */
419 htw_start();
420
6edaa530 421 guest_exit_irqoff();
669e846e
SL		 422 local_irq_enable();
423
424 if (vcpu->sigset_active)
425 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
426
427 return r;
428}
429
d116e812
DCZ		 430int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
431 struct kvm_mips_interrupt *irq)
669e846e
SL		 432{
433 int intr = (int)irq->irq;
434 struct kvm_vcpu *dvcpu = NULL;
435
436 if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
437 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
438 (int)intr);
439
440 if (irq->cpu == -1)
441 dvcpu = vcpu;
442 else
443 dvcpu = vcpu->kvm->vcpus[irq->cpu];
444
445 if (intr == 2 || intr == 3 || intr == 4) {
446 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
447
448 } else if (intr == -2 || intr == -3 || intr == -4) {
449 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
450 } else {
451 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
452 irq->cpu, irq->irq);
453 return -EINVAL;
454 }
455
456 dvcpu->arch.wait = 0;
457
8577370f
MT		 458 if (swait_active(&dvcpu->wq))
459 swake_up(&dvcpu->wq);
669e846e
SL		 460
461 return 0;
462}
463
d116e812
DCZ		 464int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
465 struct kvm_mp_state *mp_state)
669e846e 466{
ed829857 467 return -ENOIOCTLCMD;
669e846e
SL		 468}
469
d116e812
DCZ		 470int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
471 struct kvm_mp_state *mp_state)
669e846e 472{
ed829857 473 return -ENOIOCTLCMD;
669e846e
SL		 474}
475
4c73fb2b
DD		 476static u64 kvm_mips_get_one_regs[] = {
477 KVM_REG_MIPS_R0,
478 KVM_REG_MIPS_R1,
479 KVM_REG_MIPS_R2,
480 KVM_REG_MIPS_R3,
481 KVM_REG_MIPS_R4,
482 KVM_REG_MIPS_R5,
483 KVM_REG_MIPS_R6,
484 KVM_REG_MIPS_R7,
485 KVM_REG_MIPS_R8,
486 KVM_REG_MIPS_R9,
487 KVM_REG_MIPS_R10,
488 KVM_REG_MIPS_R11,
489 KVM_REG_MIPS_R12,
490 KVM_REG_MIPS_R13,
491 KVM_REG_MIPS_R14,
492 KVM_REG_MIPS_R15,
493 KVM_REG_MIPS_R16,
494 KVM_REG_MIPS_R17,
495 KVM_REG_MIPS_R18,
496 KVM_REG_MIPS_R19,
497 KVM_REG_MIPS_R20,
498 KVM_REG_MIPS_R21,
499 KVM_REG_MIPS_R22,
500 KVM_REG_MIPS_R23,
501 KVM_REG_MIPS_R24,
502 KVM_REG_MIPS_R25,
503 KVM_REG_MIPS_R26,
504 KVM_REG_MIPS_R27,
505 KVM_REG_MIPS_R28,
506 KVM_REG_MIPS_R29,
507 KVM_REG_MIPS_R30,
508 KVM_REG_MIPS_R31,
509
510 KVM_REG_MIPS_HI,
511 KVM_REG_MIPS_LO,
512 KVM_REG_MIPS_PC,
513
514 KVM_REG_MIPS_CP0_INDEX,
515 KVM_REG_MIPS_CP0_CONTEXT,
7767b7d2 516 KVM_REG_MIPS_CP0_USERLOCAL,
4c73fb2b
DD		 517 KVM_REG_MIPS_CP0_PAGEMASK,
518 KVM_REG_MIPS_CP0_WIRED,
16fd5c1d 519 KVM_REG_MIPS_CP0_HWRENA,
4c73fb2b 520 KVM_REG_MIPS_CP0_BADVADDR,
f8be02da 521 KVM_REG_MIPS_CP0_COUNT,
4c73fb2b 522 KVM_REG_MIPS_CP0_ENTRYHI,
f8be02da 523 KVM_REG_MIPS_CP0_COMPARE,
4c73fb2b
DD		 524 KVM_REG_MIPS_CP0_STATUS,
525 KVM_REG_MIPS_CP0_CAUSE,
fb6df0cd 526 KVM_REG_MIPS_CP0_EPC,
1068eaaf 527 KVM_REG_MIPS_CP0_PRID,
4c73fb2b
DD		 528 KVM_REG_MIPS_CP0_CONFIG,
529 KVM_REG_MIPS_CP0_CONFIG1,
530 KVM_REG_MIPS_CP0_CONFIG2,
531 KVM_REG_MIPS_CP0_CONFIG3,
c771607a
JH		 532 KVM_REG_MIPS_CP0_CONFIG4,
533 KVM_REG_MIPS_CP0_CONFIG5,
4c73fb2b 534 KVM_REG_MIPS_CP0_CONFIG7,
f8239342
JH		 535 KVM_REG_MIPS_CP0_ERROREPC,
536
537 KVM_REG_MIPS_COUNT_CTL,
538 KVM_REG_MIPS_COUNT_RESUME,
f74a8e22 539 KVM_REG_MIPS_COUNT_HZ,
4c73fb2b
DD		 540};
541
e5775930
JH		 542static u64 kvm_mips_get_one_regs_fpu[] = {
543 KVM_REG_MIPS_FCR_IR,
544 KVM_REG_MIPS_FCR_CSR,
545};
546
547static u64 kvm_mips_get_one_regs_msa[] = {
548 KVM_REG_MIPS_MSA_IR,
549 KVM_REG_MIPS_MSA_CSR,
550};
551
05108709
JH		 552static u64 kvm_mips_get_one_regs_kscratch[] = {
553 KVM_REG_MIPS_CP0_KSCRATCH1,
554 KVM_REG_MIPS_CP0_KSCRATCH2,
555 KVM_REG_MIPS_CP0_KSCRATCH3,
556 KVM_REG_MIPS_CP0_KSCRATCH4,
557 KVM_REG_MIPS_CP0_KSCRATCH5,
558 KVM_REG_MIPS_CP0_KSCRATCH6,
559};
560
f5c43bd4
JH		 561static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
562{
563 unsigned long ret;
564
565 ret = ARRAY_SIZE(kvm_mips_get_one_regs);
e5775930
JH		 566 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
567 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48;
568 /* odd doubles */
569 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64)
570 ret += 16;
571 }
572 if (kvm_mips_guest_can_have_msa(&vcpu->arch))
573 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32;
05108709 574 ret += __arch_hweight8(vcpu->arch.kscratch_enabled);
f5c43bd4
JH		 575 ret += kvm_mips_callbacks->num_regs(vcpu);
576
577 return ret;
578}
579
580static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
581{
e5775930
JH		 582 u64 index;
583 unsigned int i;
584
f5c43bd4
JH		 585 if (copy_to_user(indices, kvm_mips_get_one_regs,
586 sizeof(kvm_mips_get_one_regs)))
587 return -EFAULT;
588 indices += ARRAY_SIZE(kvm_mips_get_one_regs);
589
e5775930
JH		 590 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
591 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu,
592 sizeof(kvm_mips_get_one_regs_fpu)))
593 return -EFAULT;
594 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu);
595
596 for (i = 0; i < 32; ++i) {
597 index = KVM_REG_MIPS_FPR_32(i);
598 if (copy_to_user(indices, &index, sizeof(index)))
599 return -EFAULT;
600 ++indices;
601
602 /* skip odd doubles if no F64 */
603 if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
604 continue;
605
606 index = KVM_REG_MIPS_FPR_64(i);
607 if (copy_to_user(indices, &index, sizeof(index)))
608 return -EFAULT;
609 ++indices;
610 }
611 }
612
613 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) {
614 if (copy_to_user(indices, kvm_mips_get_one_regs_msa,
615 sizeof(kvm_mips_get_one_regs_msa)))
616 return -EFAULT;
617 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa);
618
619 for (i = 0; i < 32; ++i) {
620 index = KVM_REG_MIPS_VEC_128(i);
621 if (copy_to_user(indices, &index, sizeof(index)))
622 return -EFAULT;
623 ++indices;
624 }
625 }
626
05108709
JH		 627 for (i = 0; i < 6; ++i) {
628 if (!(vcpu->arch.kscratch_enabled & BIT(i + 2)))
629 continue;
630
631 if (copy_to_user(indices, &kvm_mips_get_one_regs_kscratch[i],
632 sizeof(kvm_mips_get_one_regs_kscratch[i])))
633 return -EFAULT;
634 ++indices;
635 }
636
f5c43bd4
JH		 637 return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
638}
639
4c73fb2b
DD		 640static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
641 const struct kvm_one_reg *reg)
642{
4c73fb2b 643 struct mips_coproc *cop0 = vcpu->arch.cop0;
379245cd 644 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
f8be02da 645 int ret;
4c73fb2b 646 s64 v;
ab86bd60 647 s64 vs[2];
379245cd 648 unsigned int idx;
4c73fb2b
DD		 649
650 switch (reg->id) {
379245cd 651 /* General purpose registers */
4c73fb2b
DD		 652 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
653 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
654 break;
655 case KVM_REG_MIPS_HI:
656 v = (long)vcpu->arch.hi;
657 break;
658 case KVM_REG_MIPS_LO:
659 v = (long)vcpu->arch.lo;
660 break;
661 case KVM_REG_MIPS_PC:
662 v = (long)vcpu->arch.pc;
663 break;
664
379245cd
JH		 665 /* Floating point registers */
666 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
667 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
668 return -EINVAL;
669 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
670 /* Odd singles in top of even double when FR=0 */
671 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
672 v = get_fpr32(&fpu->fpr[idx], 0);
673 else
674 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
675 break;
676 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
677 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
678 return -EINVAL;
679 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
680 /* Can't access odd doubles in FR=0 mode */
681 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
682 return -EINVAL;
683 v = get_fpr64(&fpu->fpr[idx], 0);
684 break;
685 case KVM_REG_MIPS_FCR_IR:
686 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
687 return -EINVAL;
688 v = boot_cpu_data.fpu_id;
689 break;
690 case KVM_REG_MIPS_FCR_CSR:
691 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
692 return -EINVAL;
693 v = fpu->fcr31;
694 break;
695
ab86bd60
JH		 696 /* MIPS SIMD Architecture (MSA) registers */
697 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
698 if (!kvm_mips_guest_has_msa(&vcpu->arch))
699 return -EINVAL;
700 /* Can't access MSA registers in FR=0 mode */
701 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
702 return -EINVAL;
703 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
704#ifdef CONFIG_CPU_LITTLE_ENDIAN
705 /* least significant byte first */
706 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
707 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
708#else
709 /* most significant byte first */
710 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
711 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
712#endif
713 break;
714 case KVM_REG_MIPS_MSA_IR:
715 if (!kvm_mips_guest_has_msa(&vcpu->arch))
716 return -EINVAL;
717 v = boot_cpu_data.msa_id;
718 break;
719 case KVM_REG_MIPS_MSA_CSR:
720 if (!kvm_mips_guest_has_msa(&vcpu->arch))
721 return -EINVAL;
722 v = fpu->msacsr;
723 break;
724
379245cd 725 /* Co-processor 0 registers */
4c73fb2b
DD		 726 case KVM_REG_MIPS_CP0_INDEX:
727 v = (long)kvm_read_c0_guest_index(cop0);
728 break;
729 case KVM_REG_MIPS_CP0_CONTEXT:
730 v = (long)kvm_read_c0_guest_context(cop0);
731 break;
7767b7d2
JH		 732 case KVM_REG_MIPS_CP0_USERLOCAL:
733 v = (long)kvm_read_c0_guest_userlocal(cop0);
734 break;
4c73fb2b
DD		 735 case KVM_REG_MIPS_CP0_PAGEMASK:
736 v = (long)kvm_read_c0_guest_pagemask(cop0);
737 break;
738 case KVM_REG_MIPS_CP0_WIRED:
739 v = (long)kvm_read_c0_guest_wired(cop0);
740 break;
16fd5c1d
JH		 741 case KVM_REG_MIPS_CP0_HWRENA:
742 v = (long)kvm_read_c0_guest_hwrena(cop0);
743 break;
4c73fb2b
DD		 744 case KVM_REG_MIPS_CP0_BADVADDR:
745 v = (long)kvm_read_c0_guest_badvaddr(cop0);
746 break;
747 case KVM_REG_MIPS_CP0_ENTRYHI:
748 v = (long)kvm_read_c0_guest_entryhi(cop0);
749 break;
f8be02da
JH		 750 case KVM_REG_MIPS_CP0_COMPARE:
751 v = (long)kvm_read_c0_guest_compare(cop0);
752 break;
4c73fb2b
DD		 753 case KVM_REG_MIPS_CP0_STATUS:
754 v = (long)kvm_read_c0_guest_status(cop0);
755 break;
756 case KVM_REG_MIPS_CP0_CAUSE:
757 v = (long)kvm_read_c0_guest_cause(cop0);
758 break;
fb6df0cd
JH		 759 case KVM_REG_MIPS_CP0_EPC:
760 v = (long)kvm_read_c0_guest_epc(cop0);
761 break;
1068eaaf
JH		 762 case KVM_REG_MIPS_CP0_PRID:
763 v = (long)kvm_read_c0_guest_prid(cop0);
764 break;
4c73fb2b
DD		 765 case KVM_REG_MIPS_CP0_CONFIG:
766 v = (long)kvm_read_c0_guest_config(cop0);
767 break;
768 case KVM_REG_MIPS_CP0_CONFIG1:
769 v = (long)kvm_read_c0_guest_config1(cop0);
770 break;
771 case KVM_REG_MIPS_CP0_CONFIG2:
772 v = (long)kvm_read_c0_guest_config2(cop0);
773 break;
774 case KVM_REG_MIPS_CP0_CONFIG3:
775 v = (long)kvm_read_c0_guest_config3(cop0);
776 break;
c771607a
JH		 777 case KVM_REG_MIPS_CP0_CONFIG4:
778 v = (long)kvm_read_c0_guest_config4(cop0);
779 break;
780 case KVM_REG_MIPS_CP0_CONFIG5:
781 v = (long)kvm_read_c0_guest_config5(cop0);
782 break;
4c73fb2b
DD		 783 case KVM_REG_MIPS_CP0_CONFIG7:
784 v = (long)kvm_read_c0_guest_config7(cop0);
785 break;
e93d4c15
JH		 786 case KVM_REG_MIPS_CP0_ERROREPC:
787 v = (long)kvm_read_c0_guest_errorepc(cop0);
788 break;
05108709
JH		 789 case KVM_REG_MIPS_CP0_KSCRATCH1 ... KVM_REG_MIPS_CP0_KSCRATCH6:
790 idx = reg->id - KVM_REG_MIPS_CP0_KSCRATCH1 + 2;
791 if (!(vcpu->arch.kscratch_enabled & BIT(idx)))
792 return -EINVAL;
793 switch (idx) {
794 case 2:
795 v = (long)kvm_read_c0_guest_kscratch1(cop0);
796 break;
797 case 3:
798 v = (long)kvm_read_c0_guest_kscratch2(cop0);
799 break;
800 case 4:
801 v = (long)kvm_read_c0_guest_kscratch3(cop0);
802 break;
803 case 5:
804 v = (long)kvm_read_c0_guest_kscratch4(cop0);
805 break;
806 case 6:
807 v = (long)kvm_read_c0_guest_kscratch5(cop0);
808 break;
809 case 7:
810 v = (long)kvm_read_c0_guest_kscratch6(cop0);
811 break;
812 }
813 break;
f8be02da 814 /* registers to be handled specially */
cc68d22f 815 default:
f8be02da
JH		 816 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
817 if (ret)
818 return ret;
819 break;
4c73fb2b 820 }
681865d4
DD		 821 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
822 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
d116e812 823
681865d4
DD		 824 return put_user(v, uaddr64);
825 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
826 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
827 u32 v32 = (u32)v;
d116e812 828
681865d4 829 return put_user(v32, uaddr32);
ab86bd60
JH		 830 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
831 void __user *uaddr = (void __user *)(long)reg->addr;
832
0178fd7d 833 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
681865d4
DD		 834 } else {
835 return -EINVAL;
836 }
4c73fb2b
DD		 837}
838
839static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
840 const struct kvm_one_reg *reg)
841{
4c73fb2b 842 struct mips_coproc *cop0 = vcpu->arch.cop0;
379245cd
JH		 843 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
844 s64 v;
ab86bd60 845 s64 vs[2];
379245cd 846 unsigned int idx;
4c73fb2b 847
681865d4
DD		 848 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
849 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
850
851 if (get_user(v, uaddr64) != 0)
852 return -EFAULT;
853 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
854 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
855 s32 v32;
856
857 if (get_user(v32, uaddr32) != 0)
858 return -EFAULT;
859 v = (s64)v32;
ab86bd60
JH		 860 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
861 void __user *uaddr = (void __user *)(long)reg->addr;
862
0178fd7d 863 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
681865d4
DD		 864 } else {
865 return -EINVAL;
866 }
4c73fb2b
DD		 867
868 switch (reg->id) {
379245cd 869 /* General purpose registers */
4c73fb2b
DD		 870 case KVM_REG_MIPS_R0:
871 /* Silently ignore requests to set $0 */
872 break;
873 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
874 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
875 break;
876 case KVM_REG_MIPS_HI:
877 vcpu->arch.hi = v;
878 break;
879 case KVM_REG_MIPS_LO:
880 vcpu->arch.lo = v;
881 break;
882 case KVM_REG_MIPS_PC:
883 vcpu->arch.pc = v;
884 break;
885
379245cd
JH		 886 /* Floating point registers */
887 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
888 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
889 return -EINVAL;
890 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
891 /* Odd singles in top of even double when FR=0 */
892 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
893 set_fpr32(&fpu->fpr[idx], 0, v);
894 else
895 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
896 break;
897 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
898 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
899 return -EINVAL;
900 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
901 /* Can't access odd doubles in FR=0 mode */
902 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
903 return -EINVAL;
904 set_fpr64(&fpu->fpr[idx], 0, v);
905 break;
906 case KVM_REG_MIPS_FCR_IR:
907 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
908 return -EINVAL;
909 /* Read-only */
910 break;
911 case KVM_REG_MIPS_FCR_CSR:
912 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
913 return -EINVAL;
914 fpu->fcr31 = v;
915 break;
916
ab86bd60
JH		 917 /* MIPS SIMD Architecture (MSA) registers */
918 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
919 if (!kvm_mips_guest_has_msa(&vcpu->arch))
920 return -EINVAL;
921 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
922#ifdef CONFIG_CPU_LITTLE_ENDIAN
923 /* least significant byte first */
924 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
925 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
926#else
927 /* most significant byte first */
928 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
929 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
930#endif
931 break;
932 case KVM_REG_MIPS_MSA_IR:
933 if (!kvm_mips_guest_has_msa(&vcpu->arch))
934 return -EINVAL;
935 /* Read-only */
936 break;
937 case KVM_REG_MIPS_MSA_CSR:
938 if (!kvm_mips_guest_has_msa(&vcpu->arch))
939 return -EINVAL;
940 fpu->msacsr = v;
941 break;
942
379245cd 943 /* Co-processor 0 registers */
4c73fb2b
DD		 944 case KVM_REG_MIPS_CP0_INDEX:
945 kvm_write_c0_guest_index(cop0, v);
946 break;
947 case KVM_REG_MIPS_CP0_CONTEXT:
948 kvm_write_c0_guest_context(cop0, v);
949 break;
7767b7d2
JH		 950 case KVM_REG_MIPS_CP0_USERLOCAL:
951 kvm_write_c0_guest_userlocal(cop0, v);
952 break;
4c73fb2b
DD		 953 case KVM_REG_MIPS_CP0_PAGEMASK:
954 kvm_write_c0_guest_pagemask(cop0, v);
955 break;
956 case KVM_REG_MIPS_CP0_WIRED:
957 kvm_write_c0_guest_wired(cop0, v);
958 break;
16fd5c1d
JH		 959 case KVM_REG_MIPS_CP0_HWRENA:
960 kvm_write_c0_guest_hwrena(cop0, v);
961 break;
4c73fb2b
DD		 962 case KVM_REG_MIPS_CP0_BADVADDR:
963 kvm_write_c0_guest_badvaddr(cop0, v);
964 break;
965 case KVM_REG_MIPS_CP0_ENTRYHI:
966 kvm_write_c0_guest_entryhi(cop0, v);
967 break;
968 case KVM_REG_MIPS_CP0_STATUS:
969 kvm_write_c0_guest_status(cop0, v);
970 break;
fb6df0cd
JH		 971 case KVM_REG_MIPS_CP0_EPC:
972 kvm_write_c0_guest_epc(cop0, v);
973 break;
1068eaaf
JH		 974 case KVM_REG_MIPS_CP0_PRID:
975 kvm_write_c0_guest_prid(cop0, v);
976 break;
4c73fb2b
DD		 977 case KVM_REG_MIPS_CP0_ERROREPC:
978 kvm_write_c0_guest_errorepc(cop0, v);
979 break;
05108709
JH		 980 case KVM_REG_MIPS_CP0_KSCRATCH1 ... KVM_REG_MIPS_CP0_KSCRATCH6:
981 idx = reg->id - KVM_REG_MIPS_CP0_KSCRATCH1 + 2;
982 if (!(vcpu->arch.kscratch_enabled & BIT(idx)))
983 return -EINVAL;
984 switch (idx) {
985 case 2:
986 kvm_write_c0_guest_kscratch1(cop0, v);
987 break;
988 case 3:
989 kvm_write_c0_guest_kscratch2(cop0, v);
990 break;
991 case 4:
992 kvm_write_c0_guest_kscratch3(cop0, v);
993 break;
994 case 5:
995 kvm_write_c0_guest_kscratch4(cop0, v);
996 break;
997 case 6:
998 kvm_write_c0_guest_kscratch5(cop0, v);
999 break;
1000 case 7:
1001 kvm_write_c0_guest_kscratch6(cop0, v);
1002 break;
1003 }
1004 break;
f8be02da 1005 /* registers to be handled specially */
4c73fb2b 1006 default:
cc68d22f 1007 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
4c73fb2b
DD		 1008 }
1009 return 0;
1010}
1011
5fafd874
JH		 1012static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
1013 struct kvm_enable_cap *cap)
1014{
1015 int r = 0;
1016
1017 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
1018 return -EINVAL;
1019 if (cap->flags)
1020 return -EINVAL;
1021 if (cap->args[0])
1022 return -EINVAL;
1023
1024 switch (cap->cap) {
1025 case KVM_CAP_MIPS_FPU:
1026 vcpu->arch.fpu_enabled = true;
1027 break;
d952bd07
JH		 1028 case KVM_CAP_MIPS_MSA:
1029 vcpu->arch.msa_enabled = true;
1030 break;
5fafd874
JH		 1031 default:
1032 r = -EINVAL;
1033 break;
1034 }
1035
1036 return r;
1037}
1038
d116e812
DCZ		 1039long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
1040 unsigned long arg)
669e846e
SL		 1041{
1042 struct kvm_vcpu *vcpu = filp->private_data;
1043 void __user *argp = (void __user *)arg;
1044 long r;
669e846e
SL		 1045
1046 switch (ioctl) {
4c73fb2b
DD		 1047 case KVM_SET_ONE_REG:
1048 case KVM_GET_ONE_REG: {
1049 struct kvm_one_reg reg;
d116e812 1050
4c73fb2b
DD		 1051 if (copy_from_user(&reg, argp, sizeof(reg)))
1052 return -EFAULT;
1053 if (ioctl == KVM_SET_ONE_REG)
1054 return kvm_mips_set_reg(vcpu, &reg);
1055 else
1056 return kvm_mips_get_reg(vcpu, &reg);
1057 }
1058 case KVM_GET_REG_LIST: {
1059 struct kvm_reg_list __user *user_list = argp;
4c73fb2b
DD		 1060 struct kvm_reg_list reg_list;
1061 unsigned n;
1062
1063 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
1064 return -EFAULT;
1065 n = reg_list.n;
f5c43bd4 1066 reg_list.n = kvm_mips_num_regs(vcpu);
4c73fb2b
DD		 1067 if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
1068 return -EFAULT;
1069 if (n < reg_list.n)
1070 return -E2BIG;
f5c43bd4 1071 return kvm_mips_copy_reg_indices(vcpu, user_list->reg);
4c73fb2b 1072 }
669e846e
SL		 1073 case KVM_NMI:
1074 /* Treat the NMI as a CPU reset */
1075 r = kvm_mips_reset_vcpu(vcpu);
1076 break;
1077 case KVM_INTERRUPT:
1078 {
1079 struct kvm_mips_interrupt irq;
d116e812 1080
669e846e
SL		 1081 r = -EFAULT;
1082 if (copy_from_user(&irq, argp, sizeof(irq)))
1083 goto out;
1084
669e846e
SL		 1085 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
1086 irq.irq);
1087
1088 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1089 break;
1090 }
5fafd874
JH		 1091 case KVM_ENABLE_CAP: {
1092 struct kvm_enable_cap cap;
1093
1094 r = -EFAULT;
1095 if (copy_from_user(&cap, argp, sizeof(cap)))
1096 goto out;
1097 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
1098 break;
1099 }
669e846e 1100 default:
4c73fb2b 1101 r = -ENOIOCTLCMD;
669e846e
SL		 1102 }
1103
1104out:
1105 return r;
1106}
1107
d116e812 1108/* Get (and clear) the dirty memory log for a memory slot. */
669e846e
SL		 1109int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
1110{
9f6b8029 1111 struct kvm_memslots *slots;
669e846e
SL		 1112 struct kvm_memory_slot *memslot;
1113 unsigned long ga, ga_end;
1114 int is_dirty = 0;
1115 int r;
1116 unsigned long n;
1117
1118 mutex_lock(&kvm->slots_lock);
1119
1120 r = kvm_get_dirty_log(kvm, log, &is_dirty);
1121 if (r)
1122 goto out;
1123
1124 /* If nothing is dirty, don't bother messing with page tables. */
1125 if (is_dirty) {
9f6b8029
PB		 1126 slots = kvm_memslots(kvm);
1127 memslot = id_to_memslot(slots, log->slot);
669e846e
SL		 1128
1129 ga = memslot->base_gfn << PAGE_SHIFT;
1130 ga_end = ga + (memslot->npages << PAGE_SHIFT);
1131
6ad78a5c
DCZ		 1132 kvm_info("%s: dirty, ga: %#lx, ga_end %#lx\n", __func__, ga,
1133 ga_end);
669e846e
SL		 1134
1135 n = kvm_dirty_bitmap_bytes(memslot);
1136 memset(memslot->dirty_bitmap, 0, n);
1137 }
1138
1139 r = 0;
1140out:
1141 mutex_unlock(&kvm->slots_lock);
1142 return r;
1143
1144}
1145
1146long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1147{
1148 long r;
1149
1150 switch (ioctl) {
1151 default:
ed829857 1152 r = -ENOIOCTLCMD;
669e846e
SL		 1153 }
1154
1155 return r;
1156}
1157
1158int kvm_arch_init(void *opaque)
1159{
669e846e
SL		 1160 if (kvm_mips_callbacks) {
1161 kvm_err("kvm: module already exists\n");
1162 return -EEXIST;
1163 }
1164
d98403a5 1165 return kvm_mips_emulation_init(&kvm_mips_callbacks);
669e846e
SL		 1166}
1167
1168void kvm_arch_exit(void)
1169{
1170 kvm_mips_callbacks = NULL;
1171}
1172
d116e812
DCZ		 1173int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1174 struct kvm_sregs *sregs)
669e846e 1175{
ed829857 1176 return -ENOIOCTLCMD;
669e846e
SL		 1177}
1178
d116e812
DCZ		 1179int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1180 struct kvm_sregs *sregs)
669e846e 1181{
ed829857 1182 return -ENOIOCTLCMD;
669e846e
SL		 1183}
1184
31928aa5 1185void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
669e846e 1186{
669e846e
SL		 1187}
1188
1189int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1190{
ed829857 1191 return -ENOIOCTLCMD;
669e846e
SL		 1192}
1193
1194int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1195{
ed829857 1196 return -ENOIOCTLCMD;
669e846e
SL		 1197}
1198
1199int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1200{
1201 return VM_FAULT_SIGBUS;
1202}
1203
784aa3d7 1204int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
669e846e
SL		 1205{
1206 int r;
1207
1208 switch (ext) {
4c73fb2b 1209 case KVM_CAP_ONE_REG:
5fafd874 1210 case KVM_CAP_ENABLE_CAP:
4c73fb2b
DD		 1211 r = 1;
1212 break;
669e846e
SL		 1213 case KVM_CAP_COALESCED_MMIO:
1214 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1215 break;
5fafd874 1216 case KVM_CAP_MIPS_FPU:
556f2a52
JH		 1217 /* We don't handle systems with inconsistent cpu_has_fpu */
1218 r = !!raw_cpu_has_fpu;
5fafd874 1219 break;
d952bd07
JH		 1220 case KVM_CAP_MIPS_MSA:
1221 /*
1222 * We don't support MSA vector partitioning yet:
1223 * 1) It would require explicit support which can't be tested
1224 * yet due to lack of support in current hardware.
1225 * 2) It extends the state that would need to be saved/restored
1226 * by e.g. QEMU for migration.
1227 *
1228 * When vector partitioning hardware becomes available, support
1229 * could be added by requiring a flag when enabling
1230 * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1231 * to save/restore the appropriate extra state.
1232 */
1233 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1234 break;
669e846e
SL		 1235 default:
1236 r = 0;
1237 break;
1238 }
1239 return r;
669e846e
SL		 1240}
1241
1242int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1243{
1244 return kvm_mips_pending_timer(vcpu);
1245}
1246
1247int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1248{
1249 int i;
1250 struct mips_coproc *cop0;
1251
1252 if (!vcpu)
1253 return -1;
1254
6ad78a5c
DCZ		 1255 kvm_debug("VCPU Register Dump:\n");
1256 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1257 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
669e846e
SL		 1258
1259 for (i = 0; i < 32; i += 4) {
6ad78a5c 1260 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
669e846e
SL		 1261 vcpu->arch.gprs[i],
1262 vcpu->arch.gprs[i + 1],
1263 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1264 }
6ad78a5c
DCZ		 1265 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1266 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
669e846e
SL		 1267
1268 cop0 = vcpu->arch.cop0;
6ad78a5c
DCZ		 1269 kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n",
1270 kvm_read_c0_guest_status(cop0),
1271 kvm_read_c0_guest_cause(cop0));
669e846e 1272
6ad78a5c 1273 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
669e846e
SL		 1274
1275 return 0;
1276}
1277
1278int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1279{
1280 int i;
1281
8d17dd04 1282 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
bf32ebf6 1283 vcpu->arch.gprs[i] = regs->gpr[i];
8d17dd04 1284 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
669e846e
SL		 1285 vcpu->arch.hi = regs->hi;
1286 vcpu->arch.lo = regs->lo;
1287 vcpu->arch.pc = regs->pc;
1288
4c73fb2b 1289 return 0;
669e846e
SL		 1290}
1291
1292int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1293{
1294 int i;
1295
8d17dd04 1296 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
bf32ebf6 1297 regs->gpr[i] = vcpu->arch.gprs[i];
669e846e
SL		 1298
1299 regs->hi = vcpu->arch.hi;
1300 regs->lo = vcpu->arch.lo;
1301 regs->pc = vcpu->arch.pc;
1302
4c73fb2b 1303 return 0;
669e846e
SL		 1304}
1305
0fae34f4 1306static void kvm_mips_comparecount_func(unsigned long data)
669e846e
SL		 1307{
1308 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1309
1310 kvm_mips_callbacks->queue_timer_int(vcpu);
1311
1312 vcpu->arch.wait = 0;
8577370f
MT		 1313 if (swait_active(&vcpu->wq))
1314 swake_up(&vcpu->wq);
669e846e
SL		 1315}
1316
d116e812 1317/* low level hrtimer wake routine */
0fae34f4 1318static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
669e846e
SL		 1319{
1320 struct kvm_vcpu *vcpu;
1321
1322 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1323 kvm_mips_comparecount_func((unsigned long) vcpu);
e30492bb 1324 return kvm_mips_count_timeout(vcpu);
669e846e
SL		 1325}
1326
1327int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1328{
1329 kvm_mips_callbacks->vcpu_init(vcpu);
1330 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1331 HRTIMER_MODE_REL);
1332 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
669e846e
SL		 1333 return 0;
1334}
1335
d116e812
DCZ		 1336int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1337 struct kvm_translation *tr)
669e846e
SL		 1338{
1339 return 0;
1340}
1341
1342/* Initial guest state */
1343int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1344{
1345 return kvm_mips_callbacks->vcpu_setup(vcpu);
1346}
1347
d116e812 1348static void kvm_mips_set_c0_status(void)
669e846e 1349{
8cffd197 1350 u32 status = read_c0_status();
669e846e 1351
669e846e
SL		 1352 if (cpu_has_dsp)
1353 status |= (ST0_MX);
1354
1355 write_c0_status(status);
1356 ehb();
1357}
1358
1359/*
1360 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1361 */
1362int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1363{
8cffd197
JH		 1364 u32 cause = vcpu->arch.host_cp0_cause;
1365 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1366 u32 __user *opc = (u32 __user *) vcpu->arch.pc;
669e846e
SL		 1367 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1368 enum emulation_result er = EMULATE_DONE;
1369 int ret = RESUME_GUEST;
1370
c4c6f2ca
JH		 1371 /* re-enable HTW before enabling interrupts */
1372 htw_start();
1373
669e846e
SL		 1374 /* Set a default exit reason */
1375 run->exit_reason = KVM_EXIT_UNKNOWN;
1376 run->ready_for_interrupt_injection = 1;
1377
d116e812
DCZ		 1378 /*
1379 * Set the appropriate status bits based on host CPU features,
1380 * before we hit the scheduler
1381 */
669e846e
SL		 1382 kvm_mips_set_c0_status();
1383
1384 local_irq_enable();
1385
1386 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1387 cause, opc, run, vcpu);
1e09e86a 1388 trace_kvm_exit(vcpu, exccode);
669e846e 1389
d116e812
DCZ		 1390 /*
1391 * Do a privilege check, if in UM most of these exit conditions end up
669e846e
SL		 1392 * causing an exception to be delivered to the Guest Kernel
1393 */
1394 er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1395 if (er == EMULATE_PRIV_FAIL) {
1396 goto skip_emul;
1397 } else if (er == EMULATE_FAIL) {
1398 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1399 ret = RESUME_HOST;
1400 goto skip_emul;
1401 }
1402
1403 switch (exccode) {
16d100db
JH		 1404 case EXCCODE_INT:
1405 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
669e846e
SL		 1406
1407 ++vcpu->stat.int_exits;
669e846e 1408
d116e812 1409 if (need_resched())
669e846e 1410 cond_resched();
669e846e
SL		 1411
1412 ret = RESUME_GUEST;
1413 break;
1414
16d100db
JH		 1415 case EXCCODE_CPU:
1416 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
669e846e
SL		 1417
1418 ++vcpu->stat.cop_unusable_exits;
669e846e
SL		 1419 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1420 /* XXXKYMA: Might need to return to user space */
d116e812 1421 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
669e846e 1422 ret = RESUME_HOST;
669e846e
SL		 1423 break;
1424
16d100db 1425 case EXCCODE_MOD:
669e846e 1426 ++vcpu->stat.tlbmod_exits;
669e846e
SL		 1427 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1428 break;
1429
16d100db 1430 case EXCCODE_TLBS:
d116e812
DCZ		 1431 kvm_debug("TLB ST fault: cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n",
1432 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1433 badvaddr);
669e846e
SL		 1434
1435 ++vcpu->stat.tlbmiss_st_exits;
669e846e
SL		 1436 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1437 break;
1438
16d100db 1439 case EXCCODE_TLBL:
669e846e
SL		 1440 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1441 cause, opc, badvaddr);
1442
1443 ++vcpu->stat.tlbmiss_ld_exits;
669e846e
SL		 1444 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1445 break;
1446
16d100db 1447 case EXCCODE_ADES:
669e846e 1448 ++vcpu->stat.addrerr_st_exits;
669e846e
SL		 1449 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1450 break;
1451
16d100db 1452 case EXCCODE_ADEL:
669e846e 1453 ++vcpu->stat.addrerr_ld_exits;
669e846e
SL		 1454 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1455 break;
1456
16d100db 1457 case EXCCODE_SYS:
669e846e 1458 ++vcpu->stat.syscall_exits;
669e846e
SL		 1459 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1460 break;
1461
16d100db 1462 case EXCCODE_RI:
669e846e 1463 ++vcpu->stat.resvd_inst_exits;
669e846e
SL		 1464 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1465 break;
1466
16d100db 1467 case EXCCODE_BP:
669e846e 1468 ++vcpu->stat.break_inst_exits;
669e846e
SL		 1469 ret = kvm_mips_callbacks->handle_break(vcpu);
1470 break;
1471
16d100db 1472 case EXCCODE_TR:
0a560427 1473 ++vcpu->stat.trap_inst_exits;
0a560427
JH		 1474 ret = kvm_mips_callbacks->handle_trap(vcpu);
1475 break;
1476
16d100db 1477 case EXCCODE_MSAFPE:
c2537ed9 1478 ++vcpu->stat.msa_fpe_exits;
c2537ed9
JH		 1479 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1480 break;
1481
16d100db 1482 case EXCCODE_FPE:
1c0cd66a 1483 ++vcpu->stat.fpe_exits;
1c0cd66a
JH		 1484 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1485 break;
1486
16d100db 1487 case EXCCODE_MSADIS:
c2537ed9 1488 ++vcpu->stat.msa_disabled_exits;
98119ad5
JH		 1489 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1490 break;
1491
669e846e 1492 default:
d116e812
DCZ		 1493 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#lx\n",
1494 exccode, opc, kvm_get_inst(opc, vcpu), badvaddr,
1495 kvm_read_c0_guest_status(vcpu->arch.cop0));
669e846e
SL		 1496 kvm_arch_vcpu_dump_regs(vcpu);
1497 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1498 ret = RESUME_HOST;
1499 break;
1500
1501 }
1502
1503skip_emul:
1504 local_irq_disable();
1505
1506 if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1507 kvm_mips_deliver_interrupts(vcpu, cause);
1508
1509 if (!(ret & RESUME_HOST)) {
d116e812 1510 /* Only check for signals if not already exiting to userspace */
669e846e
SL		 1511 if (signal_pending(current)) {
1512 run->exit_reason = KVM_EXIT_INTR;
1513 ret = (-EINTR << 2) | RESUME_HOST;
1514 ++vcpu->stat.signal_exits;
1e09e86a 1515 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
669e846e
SL		 1516 }
1517 }
1518
98e91b84 1519 if (ret == RESUME_GUEST) {
93258604
JH		 1520 trace_kvm_reenter(vcpu);
1521
98e91b84 1522 /*
539cb89f
JH		 1523 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1524 * is live), restore FCR31 / MSACSR.
98e91b84
JH		 1525 *
1526 * This should be before returning to the guest exception
539cb89f
JH		 1527 * vector, as it may well cause an [MSA] FP exception if there
1528 * are pending exception bits unmasked. (see
98e91b84
JH		 1529 * kvm_mips_csr_die_notifier() for how that is handled).
1530 */
1531 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1532 read_c0_status() & ST0_CU1)
1533 __kvm_restore_fcsr(&vcpu->arch);
539cb89f
JH		 1534
1535 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1536 read_c0_config5() & MIPS_CONF5_MSAEN)
1537 __kvm_restore_msacsr(&vcpu->arch);
98e91b84
JH		 1538 }
1539
c4c6f2ca
JH		 1540 /* Disable HTW before returning to guest or host */
1541 htw_stop();
1542
669e846e
SL		 1543 return ret;
1544}
1545
98e91b84
JH		 1546/* Enable FPU for guest and restore context */
1547void kvm_own_fpu(struct kvm_vcpu *vcpu)
1548{
1549 struct mips_coproc *cop0 = vcpu->arch.cop0;
1550 unsigned int sr, cfg5;
1551
1552 preempt_disable();
1553
539cb89f
JH		 1554 sr = kvm_read_c0_guest_status(cop0);
1555
1556 /*
1557 * If MSA state is already live, it is undefined how it interacts with
1558 * FR=0 FPU state, and we don't want to hit reserved instruction
1559 * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1560 * play it safe and save it first.
1561 *
1562 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1563 * get called when guest CU1 is set, however we can't trust the guest
1564 * not to clobber the status register directly via the commpage.
1565 */
1566 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
f943176a 1567 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
539cb89f
JH		 1568 kvm_lose_fpu(vcpu);
1569
98e91b84
JH		 1570 /*
1571 * Enable FPU for guest
1572 * We set FR and FRE according to guest context
1573 */
98e91b84
JH		 1574 change_c0_status(ST0_CU1 | ST0_FR, sr);
1575 if (cpu_has_fre) {
1576 cfg5 = kvm_read_c0_guest_config5(cop0);
1577 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1578 }
1579 enable_fpu_hazard();
1580
1581 /* If guest FPU state not active, restore it now */
f943176a 1582 if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
98e91b84 1583 __kvm_restore_fpu(&vcpu->arch);
f943176a 1584 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
04ebebf4
JH		 1585 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1586 } else {
1587 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
98e91b84
JH		 1588 }
1589
1590 preempt_enable();
1591}
1592
539cb89f
JH		 1593#ifdef CONFIG_CPU_HAS_MSA
1594/* Enable MSA for guest and restore context */
1595void kvm_own_msa(struct kvm_vcpu *vcpu)
1596{
1597 struct mips_coproc *cop0 = vcpu->arch.cop0;
1598 unsigned int sr, cfg5;
1599
1600 preempt_disable();
1601
1602 /*
1603 * Enable FPU if enabled in guest, since we're restoring FPU context
1604 * anyway. We set FR and FRE according to guest context.
1605 */
1606 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1607 sr = kvm_read_c0_guest_status(cop0);
1608
1609 /*
1610 * If FR=0 FPU state is already live, it is undefined how it
1611 * interacts with MSA state, so play it safe and save it first.
1612 */
1613 if (!(sr & ST0_FR) &&
f943176a
JH		 1614 (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1615 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
539cb89f
JH		 1616 kvm_lose_fpu(vcpu);
1617
1618 change_c0_status(ST0_CU1 | ST0_FR, sr);
1619 if (sr & ST0_CU1 && cpu_has_fre) {
1620 cfg5 = kvm_read_c0_guest_config5(cop0);
1621 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1622 }
1623 }
1624
1625 /* Enable MSA for guest */
1626 set_c0_config5(MIPS_CONF5_MSAEN);
1627 enable_fpu_hazard();
1628
f943176a
JH		 1629 switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1630 case KVM_MIPS_AUX_FPU:
539cb89f
JH		 1631 /*
1632 * Guest FPU state already loaded, only restore upper MSA state
1633 */
1634 __kvm_restore_msa_upper(&vcpu->arch);
f943176a 1635 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
04ebebf4 1636 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
539cb89f
JH		 1637 break;
1638 case 0:
1639 /* Neither FPU or MSA already active, restore full MSA state */
1640 __kvm_restore_msa(&vcpu->arch);
f943176a 1641 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
539cb89f 1642 if (kvm_mips_guest_has_fpu(&vcpu->arch))
f943176a 1643 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
04ebebf4
JH		 1644 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1645 KVM_TRACE_AUX_FPU_MSA);
539cb89f
JH		 1646 break;
1647 default:
04ebebf4 1648 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
539cb89f
JH		 1649 break;
1650 }
1651
1652 preempt_enable();
1653}
1654#endif
1655
1656/* Drop FPU & MSA without saving it */
98e91b84
JH		 1657void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1658{
1659 preempt_disable();
f943176a 1660 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
539cb89f 1661 disable_msa();
04ebebf4 1662 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
f943176a 1663 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
539cb89f 1664 }
f943176a 1665 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
98e91b84 1666 clear_c0_status(ST0_CU1 | ST0_FR);
04ebebf4 1667 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
f943176a 1668 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
98e91b84
JH		 1669 }
1670 preempt_enable();
1671}
1672
539cb89f 1673/* Save and disable FPU & MSA */
98e91b84
JH		 1674void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1675{
1676 /*
539cb89f
JH		 1677 * FPU & MSA get disabled in root context (hardware) when it is disabled
1678 * in guest context (software), but the register state in the hardware
1679 * may still be in use. This is why we explicitly re-enable the hardware
98e91b84
JH		 1680 * before saving.
1681 */
1682
1683 preempt_disable();
f943176a 1684 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
539cb89f
JH		 1685 set_c0_config5(MIPS_CONF5_MSAEN);
1686 enable_fpu_hazard();
1687
1688 __kvm_save_msa(&vcpu->arch);
04ebebf4 1689 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
539cb89f
JH		 1690
1691 /* Disable MSA & FPU */
1692 disable_msa();
f943176a 1693 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
539cb89f 1694 clear_c0_status(ST0_CU1 | ST0_FR);
4ac33429
JH		 1695 disable_fpu_hazard();
1696 }
f943176a
JH		 1697 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1698 } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
98e91b84
JH		 1699 set_c0_status(ST0_CU1);
1700 enable_fpu_hazard();
1701
1702 __kvm_save_fpu(&vcpu->arch);
f943176a 1703 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
04ebebf4 1704 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
98e91b84
JH		 1705
1706 /* Disable FPU */
1707 clear_c0_status(ST0_CU1 | ST0_FR);
4ac33429 1708 disable_fpu_hazard();
98e91b84
JH		 1709 }
1710 preempt_enable();
1711}
1712
1713/*
539cb89f
JH		 1714 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1715 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1716 * exception if cause bits are set in the value being written.
98e91b84
JH		 1717 */
1718static int kvm_mips_csr_die_notify(struct notifier_block *self,
1719 unsigned long cmd, void *ptr)
1720{
1721 struct die_args *args = (struct die_args *)ptr;
1722 struct pt_regs *regs = args->regs;
1723 unsigned long pc;
1724
539cb89f
JH		 1725 /* Only interested in FPE and MSAFPE */
1726 if (cmd != DIE_FP && cmd != DIE_MSAFP)
98e91b84
JH		 1727 return NOTIFY_DONE;
1728
1729 /* Return immediately if guest context isn't active */
1730 if (!(current->flags & PF_VCPU))
1731 return NOTIFY_DONE;
1732
1733 /* Should never get here from user mode */
1734 BUG_ON(user_mode(regs));
1735
1736 pc = instruction_pointer(regs);
1737 switch (cmd) {
1738 case DIE_FP:
1739 /* match 2nd instruction in __kvm_restore_fcsr */
1740 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1741 return NOTIFY_DONE;
1742 break;
539cb89f
JH		 1743 case DIE_MSAFP:
1744 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1745 if (!cpu_has_msa ||
1746 pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1747 pc > (unsigned long)&__kvm_restore_msacsr + 8)
1748 return NOTIFY_DONE;
1749 break;
98e91b84
JH		 1750 }
1751
1752 /* Move PC forward a little and continue executing */
1753 instruction_pointer(regs) += 4;
1754
1755 return NOTIFY_STOP;
1756}
1757
1758static struct notifier_block kvm_mips_csr_die_notifier = {
1759 .notifier_call = kvm_mips_csr_die_notify,
1760};
1761
2db9d233 1762static int __init kvm_mips_init(void)
669e846e
SL		 1763{
1764 int ret;
1765
1766 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1767
1768 if (ret)
1769 return ret;
1770
98e91b84
JH		 1771 register_die_notifier(&kvm_mips_csr_die_notifier);
1772
669e846e
SL		 1773 return 0;
1774}
1775
2db9d233 1776static void __exit kvm_mips_exit(void)
669e846e
SL		 1777{
1778 kvm_exit();
1779
98e91b84 1780 unregister_die_notifier(&kvm_mips_csr_die_notifier);
669e846e
SL		 1781}
1782
1783module_init(kvm_mips_init);
1784module_exit(kvm_mips_exit);
1785
1786EXPORT_TRACEPOINT_SYMBOL(kvm_exit);
Linux kernel - Deliverables
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