[deliverable/linux.git] / arch / mips / kvm / stats.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * KVM/MIPS: COP0 access histogram
 *
 * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
 * Authors: Sanjay Lal <sanjayl@kymasys.com>
 */

#include <linux/kvm_host.h>

char *kvm_mips_exit_types_str[MAX_KVM_MIPS_EXIT_TYPES] = {
	"WAIT",
	"CACHE",
	"Signal",
	"Interrupt",
	"COP0/1 Unusable",
	"TLB Mod",
	"TLB Miss (LD)",
	"TLB Miss (ST)",
	"Address Err (ST)",
	"Address Error (LD)",
	"System Call",
	"Reserved Inst",
	"Break Inst",
	"Trap Inst",
	"MSA FPE",
	"FPE",
	"MSA Disabled",
	"D-Cache Flushes",
};

char *kvm_cop0_str[N_MIPS_COPROC_REGS] = {
	"Index",
	"Random",
	"EntryLo0",
	"EntryLo1",
	"Context",
	"PG Mask",
	"Wired",
	"HWREna",
	"BadVAddr",
	"Count",
	"EntryHI",
	"Compare",
	"Status",
	"Cause",
	"EXC PC",
	"PRID",
	"Config",
	"LLAddr",
	"Watch Lo",
	"Watch Hi",
	"X Context",
	"Reserved",
	"Impl Dep",
	"Debug",
	"DEPC",
	"PerfCnt",
	"ErrCtl",
	"CacheErr",
	"TagLo",
	"TagHi",
	"ErrorEPC",
	"DESAVE"
};

void kvm_mips_dump_stats(struct kvm_vcpu *vcpu)
{
#ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
	int i, j;

	kvm_info("\nKVM VCPU[%d] COP0 Access Profile:\n", vcpu->vcpu_id);
	for (i = 0; i < N_MIPS_COPROC_REGS; i++) {
		for (j = 0; j < N_MIPS_COPROC_SEL; j++) {
			if (vcpu->arch.cop0->stat[i][j])
				kvm_info("%s[%d]: %lu\n", kvm_cop0_str[i], j,
					 vcpu->arch.cop0->stat[i][j]);
		}
	}
#endif
}
Commit	Line	Data
3c20ef52	1	/*
d116e812 DCZ	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* KVM/MIPS: COP0 access histogram
	7	*
	8	* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
	9	* Authors: Sanjay Lal <sanjayl@kymasys.com>
	10	*/
3c20ef52 SL	11
	12	#include <linux/kvm_host.h>
	13
	14	char *kvm_mips_exit_types_str[MAX_KVM_MIPS_EXIT_TYPES] = {
	15	"WAIT",
	16	"CACHE",
	17	"Signal",
	18	"Interrupt",
	19	"COP0/1 Unusable",
	20	"TLB Mod",
	21	"TLB Miss (LD)",
	22	"TLB Miss (ST)",
	23	"Address Err (ST)",
	24	"Address Error (LD)",
	25	"System Call",
	26	"Reserved Inst",
	27	"Break Inst",
0a560427	28	"Trap Inst",
c2537ed9	29	"MSA FPE",
1c0cd66a	30	"FPE",
c2537ed9	31	"MSA Disabled",
3c20ef52 SL	32	"D-Cache Flushes",
	33	};
	34
	35	char *kvm_cop0_str[N_MIPS_COPROC_REGS] = {
	36	"Index",
	37	"Random",
	38	"EntryLo0",
	39	"EntryLo1",
	40	"Context",
	41	"PG Mask",
	42	"Wired",
	43	"HWREna",
	44	"BadVAddr",
	45	"Count",
	46	"EntryHI",
	47	"Compare",
	48	"Status",
	49	"Cause",
	50	"EXC PC",
	51	"PRID",
	52	"Config",
	53	"LLAddr",
	54	"Watch Lo",
	55	"Watch Hi",
	56	"X Context",
	57	"Reserved",
	58	"Impl Dep",
	59	"Debug",
	60	"DEPC",
	61	"PerfCnt",
	62	"ErrCtl",
	63	"CacheErr",
	64	"TagLo",
	65	"TagHi",
	66	"ErrorEPC",
	67	"DESAVE"
	68	};
	69
d98403a5	70	void kvm_mips_dump_stats(struct kvm_vcpu *vcpu)
3c20ef52 SL	71	{
	72	#ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
	73	int i, j;
	74
6ad78a5c	75	kvm_info("\nKVM VCPU[%d] COP0 Access Profile:\n", vcpu->vcpu_id);
3c20ef52 SL	76	for (i = 0; i < N_MIPS_COPROC_REGS; i++) {
	77	for (j = 0; j < N_MIPS_COPROC_SEL; j++) {
	78	if (vcpu->arch.cop0->stat[i][j])
6ad78a5c DCZ	79	kvm_info("%s[%d]: %lu\n", kvm_cop0_str[i], j,
6ad78a5c DCZ	80	vcpu->arch.cop0->stat[i][j]);
3c20ef52 SL	81	}
	82	}
	83	#endif
3c20ef52	84	}