projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| d41ced01 JC |
1 | /* |
| 2 | * This program is free software; you can redistribute it and/or modify it | |
| 3 | * under the terms of the GNU General Public License version 2 as published | |
| 4 | * by the Free Software Foundation. | |
| 5 | * | |
| 6 | * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com> | |
| 97b92108 | 7 | * Copyright (C) 2012 John Crispin <john@phrozen.org> |
| d41ced01 JC |
8 | */ |
| 9 | ||
| 10 | #include <linux/kernel.h> | |
| f8cd170d JC |
11 | #include <asm/cacheflush.h> |
| 12 | #include <asm/traps.h> | |
| d41ced01 JC |
13 | #include <asm/io.h> |
| 14 | ||
| 15 | #include <lantiq_soc.h> | |
| 16 | ||
| 17 | #include "../prom.h" | |
| 18 | ||
| 19 | #define SOC_FALCON "Falcon" | |
| 20 | #define SOC_FALCON_D "Falcon-D" | |
| 21 | #define SOC_FALCON_V "Falcon-V" | |
| 22 | #define SOC_FALCON_M "Falcon-M" | |
| 23 | ||
| 24 | #define COMP_FALCON "lantiq,falcon" | |
| 25 | ||
| 26 | #define PART_SHIFT 12 | |
| 27 | #define PART_MASK 0x0FFFF000 | |
| 28 | #define REV_SHIFT 28 | |
| 29 | #define REV_MASK 0xF0000000 | |
| 30 | #define SREV_SHIFT 22 | |
| 31 | #define SREV_MASK 0x03C00000 | |
| 32 | #define TYPE_SHIFT 26 | |
| 33 | #define TYPE_MASK 0x3C000000 | |
| 34 | ||
| 35 | /* reset, nmi and ejtag exception vectors */ | |
| 36 | #define BOOT_REG_BASE (KSEG1 | 0x1F200000) | |
| 37 | #define BOOT_RVEC (BOOT_REG_BASE | 0x00) | |
| 38 | #define BOOT_NVEC (BOOT_REG_BASE | 0x04) | |
| 39 | #define BOOT_EVEC (BOOT_REG_BASE | 0x08) | |
| 40 | ||
| 41 | void __init ltq_soc_nmi_setup(void) | |
| 42 | { | |
| 43 | extern void (*nmi_handler)(void); | |
| 44 | ||
| 45 | ltq_w32((unsigned long)&nmi_handler, (void *)BOOT_NVEC); | |
| 46 | } | |
| 47 | ||
| 48 | void __init ltq_soc_ejtag_setup(void) | |
| 49 | { | |
| 50 | extern void (*ejtag_debug_handler)(void); | |
| 51 | ||
| 52 | ltq_w32((unsigned long)&ejtag_debug_handler, (void *)BOOT_EVEC); | |
| 53 | } | |
| 54 | ||
| 55 | void __init ltq_soc_detect(struct ltq_soc_info *i) | |
| 56 | { | |
| 57 | u32 type; | |
| 58 | i->partnum = (ltq_r32(FALCON_CHIPID) & PART_MASK) >> PART_SHIFT; | |
| 59 | i->rev = (ltq_r32(FALCON_CHIPID) & REV_MASK) >> REV_SHIFT; | |
| 60 | i->srev = ((ltq_r32(FALCON_CHIPCONF) & SREV_MASK) >> SREV_SHIFT); | |
| 61 | i->compatible = COMP_FALCON; | |
| 62 | i->type = SOC_TYPE_FALCON; | |
| 63 | sprintf(i->rev_type, "%c%d%d", (i->srev & 0x4) ? ('B') : ('A'), | |
| 64 | i->rev & 0x7, (i->srev & 0x3) + 1); | |
| 65 | ||
| 66 | switch (i->partnum) { | |
| 67 | case SOC_ID_FALCON: | |
| 68 | type = (ltq_r32(FALCON_CHIPTYPE) & TYPE_MASK) >> TYPE_SHIFT; | |
| 69 | switch (type) { | |
| 70 | case 0: | |
| 71 | i->name = SOC_FALCON_D; | |
| 72 | break; | |
| 73 | case 1: | |
| 74 | i->name = SOC_FALCON_V; | |
| 75 | break; | |
| 76 | case 2: | |
| 77 | i->name = SOC_FALCON_M; | |
| 78 | break; | |
| 79 | default: | |
| 80 | i->name = SOC_FALCON; | |
| 81 | break; | |
| 82 | } | |
| 83 | break; | |
| 84 | ||
| 85 | default: | |
| 86 | unreachable(); | |
| 87 | break; | |
| 88 | } | |
| f8cd170d JC |
89 | |
| 90 | board_nmi_handler_setup = ltq_soc_nmi_setup; | |
| 91 | board_ejtag_handler_setup = ltq_soc_ejtag_setup; | |
| d41ced01 | 92 | } |