Commit | Line | Data |
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171bb2f1 JC |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify it | |
3 | * under the terms of the GNU General Public License version 2 as published | |
4 | * by the Free Software Foundation. | |
5 | * | |
97b92108 | 6 | * Copyright (C) 2010 John Crispin <john@phrozen.org> |
171bb2f1 JC |
7 | */ |
8 | ||
4af92e7a | 9 | #include <linux/export.h> |
171bb2f1 | 10 | #include <linux/clk.h> |
a9188bc1 | 11 | #include <linux/bootmem.h> |
a0392222 | 12 | #include <linux/of_platform.h> |
a9188bc1 JC |
13 | #include <linux/of_fdt.h> |
14 | ||
171bb2f1 JC |
15 | #include <asm/bootinfo.h> |
16 | #include <asm/time.h> | |
089a49b6 | 17 | #include <asm/prom.h> |
171bb2f1 JC |
18 | |
19 | #include <lantiq.h> | |
20 | ||
21 | #include "prom.h" | |
22 | #include "clk.h" | |
23 | ||
a0392222 JC |
24 | /* access to the ebu needs to be locked between different drivers */ |
25 | DEFINE_SPINLOCK(ebu_lock); | |
26 | EXPORT_SYMBOL_GPL(ebu_lock); | |
171bb2f1 | 27 | |
a0392222 JC |
28 | /* |
29 | * this struct is filled by the soc specific detection code and holds | |
30 | * information about the specific soc type, revision and name | |
31 | */ | |
32 | static struct ltq_soc_info soc_info; | |
171bb2f1 | 33 | |
171bb2f1 JC |
34 | const char *get_system_type(void) |
35 | { | |
36 | return soc_info.sys_type; | |
37 | } | |
38 | ||
e8b8ca8c JC |
39 | int ltq_soc_type(void) |
40 | { | |
41 | return soc_info.type; | |
42 | } | |
43 | ||
aa816c1b | 44 | void __init prom_free_prom_memory(void) |
171bb2f1 JC |
45 | { |
46 | } | |
47 | ||
48 | static void __init prom_init_cmdline(void) | |
49 | { | |
50 | int argc = fw_arg0; | |
51 | char **argv = (char **) KSEG1ADDR(fw_arg1); | |
52 | int i; | |
53 | ||
730fa039 TL |
54 | arcs_cmdline[0] = '\0'; |
55 | ||
171bb2f1 | 56 | for (i = 0; i < argc; i++) { |
730fa039 | 57 | char *p = (char *) KSEG1ADDR(argv[i]); |
171bb2f1 | 58 | |
730fa039 | 59 | if (CPHYSADDR(p) && *p) { |
171bb2f1 JC |
60 | strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); |
61 | strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); | |
62 | } | |
63 | } | |
64 | } | |
65 | ||
a0392222 | 66 | void __init plat_mem_setup(void) |
171bb2f1 | 67 | { |
84f47cf4 HM |
68 | void *dtb; |
69 | ||
a0392222 JC |
70 | ioport_resource.start = IOPORT_RESOURCE_START; |
71 | ioport_resource.end = IOPORT_RESOURCE_END; | |
72 | iomem_resource.start = IOMEM_RESOURCE_START; | |
73 | iomem_resource.end = IOMEM_RESOURCE_END; | |
74 | ||
75 | set_io_port_base((unsigned long) KSEG1); | |
76 | ||
15f37e15 JG |
77 | if (fw_passed_dtb) /* UHI interface */ |
78 | dtb = (void *)fw_passed_dtb; | |
84f47cf4 HM |
79 | else if (__dtb_start != __dtb_end) |
80 | dtb = (void *)__dtb_start; | |
81 | else | |
82 | panic("no dtb found"); | |
83 | ||
a0392222 | 84 | /* |
84f47cf4 | 85 | * Load the devicetree. This causes the chosen node to be |
a0392222 JC |
86 | * parsed resulting in our memory appearing |
87 | */ | |
84f47cf4 | 88 | __dt_setup_arch(dtb); |
a0392222 | 89 | } |
171bb2f1 | 90 | |
a9188bc1 JC |
91 | void __init device_tree_init(void) |
92 | { | |
10fbdaab | 93 | unflatten_and_copy_device_tree(); |
a9188bc1 JC |
94 | } |
95 | ||
a0392222 JC |
96 | void __init prom_init(void) |
97 | { | |
98 | /* call the soc specific detetcion code and get it to fill soc_info */ | |
171bb2f1 | 99 | ltq_soc_detect(&soc_info); |
a0392222 JC |
100 | snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s", |
101 | soc_info.name, soc_info.rev_type); | |
171bb2f1 JC |
102 | soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0'; |
103 | pr_info("SoC: %s\n", soc_info.sys_type); | |
104 | prom_init_cmdline(); | |
a8d096ef JC |
105 | |
106 | #if defined(CONFIG_MIPS_MT_SMP) | |
107 | if (register_vsmp_smp_ops()) | |
108 | panic("failed to register_vsmp_smp_ops()"); | |
109 | #endif | |
171bb2f1 | 110 | } |
a0392222 JC |
111 | |
112 | int __init plat_of_setup(void) | |
113 | { | |
84988c06 | 114 | return __dt_register_buses(soc_info.compatible, "simple-bus"); |
a0392222 JC |
115 | } |
116 | ||
117 | arch_initcall(plat_of_setup); |