[deliverable/linux.git] / arch / mips / lib / dump_tlb.c

/*
 * Dump R4x00 TLB for debugging purposes.
 *
 * Copyright (C) 1994, 1995 by Waldorf Electronics, written by Ralf Baechle.
 * Copyright (C) 1999 by Silicon Graphics, Inc.
 */
#include <linux/kernel.h>
#include <linux/mm.h>

#include <asm/hazards.h>
#include <asm/mipsregs.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/tlbdebug.h>

void dump_tlb_regs(void)
{
	const int field = 2 * sizeof(unsigned long);

	pr_info("Index    : %0x\n", read_c0_index());
	pr_info("PageMask : %0x\n", read_c0_pagemask());
	if (cpu_has_guestid)
		pr_info("GuestCtl1: %0x\n", read_c0_guestctl1());
	pr_info("EntryHi  : %0*lx\n", field, read_c0_entryhi());
	pr_info("EntryLo0 : %0*lx\n", field, read_c0_entrylo0());
	pr_info("EntryLo1 : %0*lx\n", field, read_c0_entrylo1());
	pr_info("Wired    : %0x\n", read_c0_wired());
	switch (current_cpu_type()) {
	case CPU_R10000:
	case CPU_R12000:
	case CPU_R14000:
	case CPU_R16000:
		pr_info("FrameMask: %0x\n", read_c0_framemask());
		break;
	}
	if (cpu_has_small_pages || cpu_has_rixi || cpu_has_xpa)
		pr_info("PageGrain: %0x\n", read_c0_pagegrain());
	if (cpu_has_htw) {
		pr_info("PWField  : %0*lx\n", field, read_c0_pwfield());
		pr_info("PWSize   : %0*lx\n", field, read_c0_pwsize());
		pr_info("PWCtl    : %0x\n", read_c0_pwctl());
	}
}

static inline const char *msk2str(unsigned int mask)
{
	switch (mask) {
	case PM_4K:	return "4kb";
	case PM_16K:	return "16kb";
	case PM_64K:	return "64kb";
	case PM_256K:	return "256kb";
#ifdef CONFIG_CPU_CAVIUM_OCTEON
	case PM_8K:	return "8kb";
	case PM_32K:	return "32kb";
	case PM_128K:	return "128kb";
	case PM_512K:	return "512kb";
	case PM_2M:	return "2Mb";
	case PM_8M:	return "8Mb";
	case PM_32M:	return "32Mb";
#endif
#ifndef CONFIG_CPU_VR41XX
	case PM_1M:	return "1Mb";
	case PM_4M:	return "4Mb";
	case PM_16M:	return "16Mb";
	case PM_64M:	return "64Mb";
	case PM_256M:	return "256Mb";
	case PM_1G:	return "1Gb";
#endif
	}
	return "";
}

static void dump_tlb(int first, int last)
{
	unsigned long s_entryhi, entryhi, asid;
	unsigned long long entrylo0, entrylo1, pa;
	unsigned int s_index, s_pagemask, s_guestctl1 = 0;
	unsigned int pagemask, guestctl1 = 0, c0, c1, i;
	unsigned long asidmask = cpu_asid_mask(&current_cpu_data);
	int asidwidth = DIV_ROUND_UP(ilog2(asidmask) + 1, 4);
#ifdef CONFIG_32BIT
	bool xpa = cpu_has_xpa && (read_c0_pagegrain() & PG_ELPA);
	int pwidth = xpa ? 11 : 8;
	int vwidth = 8;
#else
	bool xpa = false;
	int pwidth = 11;
	int vwidth = 11;
#endif

	s_pagemask = read_c0_pagemask();
	s_entryhi = read_c0_entryhi();
	s_index = read_c0_index();
	asid = s_entryhi & asidmask;
	if (cpu_has_guestid)
		s_guestctl1 = read_c0_guestctl1();

	for (i = first; i <= last; i++) {
		write_c0_index(i);
		mtc0_tlbr_hazard();
		tlb_read();
		tlb_read_hazard();
		pagemask = read_c0_pagemask();
		entryhi	 = read_c0_entryhi();
		entrylo0 = read_c0_entrylo0();
		entrylo1 = read_c0_entrylo1();
		if (cpu_has_guestid)
			guestctl1 = read_c0_guestctl1();

		/* EHINV bit marks entire entry as invalid */
		if (cpu_has_tlbinv && entryhi & MIPS_ENTRYHI_EHINV)
			continue;
		/*
		 * Prior to tlbinv, unused entries have a virtual address of
		 * CKSEG0.
		 */
		if ((entryhi & ~0x1ffffUL) == CKSEG0)
			continue;
		/*
		 * ASID takes effect in absence of G (global) bit.
		 * We check both G bits, even though architecturally they should
		 * match one another, because some revisions of the SB1 core may
		 * leave only a single G bit set after a machine check exception
		 * due to duplicate TLB entry.
		 */
		if (!((entrylo0 | entrylo1) & ENTRYLO_G) &&
		    (entryhi & asidmask) != asid)
			continue;

		/*
		 * Only print entries in use
		 */
		printk("Index: %2d pgmask=%s ", i, msk2str(pagemask));

		c0 = (entrylo0 & ENTRYLO_C) >> ENTRYLO_C_SHIFT;
		c1 = (entrylo1 & ENTRYLO_C) >> ENTRYLO_C_SHIFT;

		printk("va=%0*lx asid=%0*lx",
		       vwidth, (entryhi & ~0x1fffUL),
		       asidwidth, entryhi & asidmask);
		if (cpu_has_guestid)
			printk(" gid=%02lx",
			       (guestctl1 & MIPS_GCTL1_RID)
					>> MIPS_GCTL1_RID_SHIFT);
		/* RI/XI are in awkward places, so mask them off separately */
		pa = entrylo0 & ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI);
		if (xpa)
			pa |= (unsigned long long)readx_c0_entrylo0() << 30;
		pa = (pa << 6) & PAGE_MASK;
		printk("\n\t[");
		if (cpu_has_rixi)
			printk("ri=%d xi=%d ",
			       (entrylo0 & MIPS_ENTRYLO_RI) ? 1 : 0,
			       (entrylo0 & MIPS_ENTRYLO_XI) ? 1 : 0);
		printk("pa=%0*llx c=%d d=%d v=%d g=%d] [",
		       pwidth, pa, c0,
		       (entrylo0 & ENTRYLO_D) ? 1 : 0,
		       (entrylo0 & ENTRYLO_V) ? 1 : 0,
		       (entrylo0 & ENTRYLO_G) ? 1 : 0);
		/* RI/XI are in awkward places, so mask them off separately */
		pa = entrylo1 & ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI);
		if (xpa)
			pa |= (unsigned long long)readx_c0_entrylo1() << 30;
		pa = (pa << 6) & PAGE_MASK;
		if (cpu_has_rixi)
			printk("ri=%d xi=%d ",
			       (entrylo1 & MIPS_ENTRYLO_RI) ? 1 : 0,
			       (entrylo1 & MIPS_ENTRYLO_XI) ? 1 : 0);
		printk("pa=%0*llx c=%d d=%d v=%d g=%d]\n",
		       pwidth, pa, c1,
		       (entrylo1 & ENTRYLO_D) ? 1 : 0,
		       (entrylo1 & ENTRYLO_V) ? 1 : 0,
		       (entrylo1 & ENTRYLO_G) ? 1 : 0);
	}
	printk("\n");

	write_c0_entryhi(s_entryhi);
	write_c0_index(s_index);
	write_c0_pagemask(s_pagemask);
	if (cpu_has_guestid)
		write_c0_guestctl1(s_guestctl1);
}

void dump_tlb_all(void)
{
	dump_tlb(0, current_cpu_data.tlbsize - 1);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Dump R4x00 TLB for debugging purposes.
	3	*
	4	* Copyright (C) 1994, 1995 by Waldorf Electronics, written by Ralf Baechle.
	5	* Copyright (C) 1999 by Silicon Graphics, Inc.
	6	*/
1da177e4 LT	7	#include <linux/kernel.h>
1da177e4 LT	8	#include <linux/mm.h>
1da177e4	9
137877e4	10	#include <asm/hazards.h>
1da177e4 LT	11	#include <asm/mipsregs.h>
	12	#include <asm/page.h>
	13	#include <asm/pgtable.h>
40df3831	14	#include <asm/tlbdebug.h>
1da177e4	15
3c865dd9 JH	16	void dump_tlb_regs(void)
	17	{
	18	const int field = 2 * sizeof(unsigned long);
	19
	20	pr_info("Index : %0x\n", read_c0_index());
	21	pr_info("PageMask : %0x\n", read_c0_pagemask());
4b62fad5 JH	22	if (cpu_has_guestid)
4b62fad5 JH	23	pr_info("GuestCtl1: %0x\n", read_c0_guestctl1());
3c865dd9 JH	24	pr_info("EntryHi : %0*lx\n", field, read_c0_entryhi());
	25	pr_info("EntryLo0 : %0*lx\n", field, read_c0_entrylo0());
	26	pr_info("EntryLo1 : %0*lx\n", field, read_c0_entrylo1());
	27	pr_info("Wired : %0x\n", read_c0_wired());
9bd860ca JH	28	switch (current_cpu_type()) {
	29	case CPU_R10000:
	30	case CPU_R12000:
	31	case CPU_R14000:
	32	case CPU_R16000:
	33	pr_info("FrameMask: %0x\n", read_c0_framemask());
	34	break;
	35	}
5d3c3c7d JH	36	if (cpu_has_small_pages \|\| cpu_has_rixi \|\| cpu_has_xpa)
5d3c3c7d JH	37	pr_info("PageGrain: %0x\n", read_c0_pagegrain());
3c865dd9 JH	38	if (cpu_has_htw) {
	39	pr_info("PWField : %0*lx\n", field, read_c0_pwfield());
	40	pr_info("PWSize : %0*lx\n", field, read_c0_pwsize());
	41	pr_info("PWCtl : %0x\n", read_c0_pwctl());
	42	}
	43	}
	44
1da177e4 LT	45	static inline const char *msk2str(unsigned int mask)
	46	{
	47	switch (mask) {
	48	case PM_4K: return "4kb";
	49	case PM_16K: return "16kb";
	50	case PM_64K: return "64kb";
	51	case PM_256K: return "256kb";
c52399be RB	52	#ifdef CONFIG_CPU_CAVIUM_OCTEON
	53	case PM_8K: return "8kb";
	54	case PM_32K: return "32kb";
	55	case PM_128K: return "128kb";
	56	case PM_512K: return "512kb";
	57	case PM_2M: return "2Mb";
	58	case PM_8M: return "8Mb";
	59	case PM_32M: return "32Mb";
	60	#endif
1da177e4 LT	61	#ifndef CONFIG_CPU_VR41XX
	62	case PM_1M: return "1Mb";
	63	case PM_4M: return "4Mb";
	64	case PM_16M: return "16Mb";
	65	case PM_64M: return "64Mb";
	66	case PM_256M: return "256Mb";
542c1020	67	case PM_1G: return "1Gb";
1da177e4 LT	68	#endif
1da177e4 LT	69	}
4becef1d	70	return "";
1da177e4 LT	71	}
1da177e4 LT	72
69ed25b8	73	static void dump_tlb(int first, int last)
1da177e4	74	{
4becef1d	75	unsigned long s_entryhi, entryhi, asid;
c2bc435e	76	unsigned long long entrylo0, entrylo1, pa;
382208dc JH	77	unsigned int s_index, s_pagemask, s_guestctl1 = 0;
382208dc JH	78	unsigned int pagemask, guestctl1 = 0, c0, c1, i;
4edf00a4 PB	79	unsigned long asidmask = cpu_asid_mask(&current_cpu_data);
4edf00a4 PB	80	int asidwidth = DIV_ROUND_UP(ilog2(asidmask) + 1, 4);
d1ce483e	81	#ifdef CONFIG_32BIT
24ca1d98 JH	82	bool xpa = cpu_has_xpa && (read_c0_pagegrain() & PG_ELPA);
	83	int pwidth = xpa ? 11 : 8;
	84	int vwidth = 8;
d1ce483e	85	#else
24ca1d98 JH	86	bool xpa = false;
	87	int pwidth = 11;
	88	int vwidth = 11;
d1ce483e	89	#endif
1da177e4	90
01422ff4	91	s_pagemask = read_c0_pagemask();
1da177e4 LT	92	s_entryhi = read_c0_entryhi();
1da177e4 LT	93	s_index = read_c0_index();
4edf00a4	94	asid = s_entryhi & asidmask;
382208dc JH	95	if (cpu_has_guestid)
382208dc JH	96	s_guestctl1 = read_c0_guestctl1();
1da177e4 LT	97
	98	for (i = first; i <= last; i++) {
	99	write_c0_index(i);
137877e4	100	mtc0_tlbr_hazard();
1da177e4	101	tlb_read();
137877e4	102	tlb_read_hazard();
1da177e4	103	pagemask = read_c0_pagemask();
70342287	104	entryhi = read_c0_entryhi();
1da177e4 LT	105	entrylo0 = read_c0_entrylo0();
1da177e4 LT	106	entrylo1 = read_c0_entrylo1();
382208dc JH	107	if (cpu_has_guestid)
382208dc JH	108	guestctl1 = read_c0_guestctl1();
1da177e4	109
decebccd JH	110	/* EHINV bit marks entire entry as invalid */
	111	if (cpu_has_tlbinv && entryhi & MIPS_ENTRYHI_EHINV)
	112	continue;
d1ce483e JH	113	/*
	114	* Prior to tlbinv, unused entries have a virtual address of
	115	* CKSEG0.
	116	*/
	117	if ((entryhi & ~0x1ffffUL) == CKSEG0)
	118	continue;
48269c78 JH	119	/*
	120	* ASID takes effect in absence of G (global) bit.
	121	* We check both G bits, even though architecturally they should
	122	* match one another, because some revisions of the SB1 core may
	123	* leave only a single G bit set after a machine check exception
	124	* due to duplicate TLB entry.
	125	*/
bae637a2	126	if (!((entrylo0 \| entrylo1) & ENTRYLO_G) &&
4edf00a4	127	(entryhi & asidmask) != asid)
d1ce483e JH	128	continue;
	129
	130	/*
	131	* Only print entries in use
	132	*/
	133	printk("Index: %2d pgmask=%s ", i, msk2str(pagemask));
1da177e4	134
bae637a2 JH	135	c0 = (entrylo0 & ENTRYLO_C) >> ENTRYLO_C_SHIFT;
bae637a2 JH	136	c1 = (entrylo1 & ENTRYLO_C) >> ENTRYLO_C_SHIFT;
1da177e4	137
382208dc	138	printk("va=%0lx asid=%0lx",
24ca1d98	139	vwidth, (entryhi & ~0x1fffUL),
4edf00a4	140	asidwidth, entryhi & asidmask);
382208dc JH	141	if (cpu_has_guestid)
	142	printk(" gid=%02lx",
	143	(guestctl1 & MIPS_GCTL1_RID)
	144	>> MIPS_GCTL1_RID_SHIFT);
c2bc435e JH	145	/* RI/XI are in awkward places, so mask them off separately */
c2bc435e JH	146	pa = entrylo0 & ~(MIPS_ENTRYLO_RI \| MIPS_ENTRYLO_XI);
24ca1d98 JH	147	if (xpa)
24ca1d98 JH	148	pa \|= (unsigned long long)readx_c0_entrylo0() << 30;
c2bc435e	149	pa = (pa << 6) & PAGE_MASK;
382208dc	150	printk("\n\t[");
c2bc435e JH	151	if (cpu_has_rixi)
	152	printk("ri=%d xi=%d ",
	153	(entrylo0 & MIPS_ENTRYLO_RI) ? 1 : 0,
	154	(entrylo0 & MIPS_ENTRYLO_XI) ? 1 : 0);
	155	printk("pa=%0*llx c=%d d=%d v=%d g=%d] [",
24ca1d98	156	pwidth, pa, c0,
bae637a2 JH	157	(entrylo0 & ENTRYLO_D) ? 1 : 0,
	158	(entrylo0 & ENTRYLO_V) ? 1 : 0,
	159	(entrylo0 & ENTRYLO_G) ? 1 : 0);
c2bc435e JH	160	/* RI/XI are in awkward places, so mask them off separately */
c2bc435e JH	161	pa = entrylo1 & ~(MIPS_ENTRYLO_RI \| MIPS_ENTRYLO_XI);
24ca1d98 JH	162	if (xpa)
24ca1d98 JH	163	pa \|= (unsigned long long)readx_c0_entrylo1() << 30;
c2bc435e JH	164	pa = (pa << 6) & PAGE_MASK;
	165	if (cpu_has_rixi)
	166	printk("ri=%d xi=%d ",
	167	(entrylo1 & MIPS_ENTRYLO_RI) ? 1 : 0,
	168	(entrylo1 & MIPS_ENTRYLO_XI) ? 1 : 0);
	169	printk("pa=%0*llx c=%d d=%d v=%d g=%d]\n",
24ca1d98	170	pwidth, pa, c1,
bae637a2 JH	171	(entrylo1 & ENTRYLO_D) ? 1 : 0,
	172	(entrylo1 & ENTRYLO_V) ? 1 : 0,
	173	(entrylo1 & ENTRYLO_G) ? 1 : 0);
1da177e4 LT	174	}
	175	printk("\n");
	176
	177	write_c0_entryhi(s_entryhi);
	178	write_c0_index(s_index);
01422ff4	179	write_c0_pagemask(s_pagemask);
382208dc JH	180	if (cpu_has_guestid)
382208dc JH	181	write_c0_guestctl1(s_guestctl1);
1da177e4 LT	182	}
	183
	184	void dump_tlb_all(void)
	185	{
	186	dump_tlb(0, current_cpu_data.tlbsize - 1);
	187	}