[deliverable/linux.git] / arch / mips / lib / dump_tlb.c

/*
 * Dump R4x00 TLB for debugging purposes.
 *
 * Copyright (C) 1994, 1995 by Waldorf Electronics, written by Ralf Baechle.
 * Copyright (C) 1999 by Silicon Graphics, Inc.
 */
#include <linux/kernel.h>
#include <linux/mm.h>

#include <asm/mipsregs.h>
#include <asm/page.h>
#include <asm/pgtable.h>

static inline const char *msk2str(unsigned int mask)
{
	switch (mask) {
	case PM_4K:	return "4kb";
	case PM_16K:	return "16kb";
	case PM_64K:	return "64kb";
	case PM_256K:	return "256kb";
#ifndef CONFIG_CPU_VR41XX
	case PM_1M:	return "1Mb";
	case PM_4M:	return "4Mb";
	case PM_16M:	return "16Mb";
	case PM_64M:	return "64Mb";
	case PM_256M:	return "256Mb";
#endif
	}
	return "";
}

#define BARRIER()					\
	__asm__ __volatile__(				\
		".set\tnoreorder\n\t"			\
		"nop;nop;nop;nop;nop;nop;nop\n\t"	\
		".set\treorder");

static void dump_tlb(int first, int last)
{
	unsigned long s_entryhi, entryhi, asid;
	unsigned long long entrylo0, entrylo1;
	unsigned int s_index, pagemask, c0, c1, i;

	s_entryhi = read_c0_entryhi();
	s_index = read_c0_index();
	asid = s_entryhi & 0xff;

	for (i = first; i <= last; i++) {
		write_c0_index(i);
		BARRIER();
		tlb_read();
		BARRIER();
		pagemask = read_c0_pagemask();
		entryhi  = read_c0_entryhi();
		entrylo0 = read_c0_entrylo0();
		entrylo1 = read_c0_entrylo1();

		/* Unused entries have a virtual address of CKSEG0.  */
		if ((entryhi & ~0x1ffffUL) != CKSEG0
		    && (entryhi & 0xff) == asid) {
#ifdef CONFIG_32BIT
			int width = 8;
#else
			int width = 11;
#endif
			/*
			 * Only print entries in use
			 */
			printk("Index: %2d pgmask=%s ", i, msk2str(pagemask));

			c0 = (entrylo0 >> 3) & 7;
			c1 = (entrylo1 >> 3) & 7;

			printk("va=%0*lx asid=%02lx\n",
			       width, (entryhi & ~0x1fffUL),
			       entryhi & 0xff);
			printk("\t[pa=%0*llx c=%d d=%d v=%d g=%d] ",
			       width,
			       (entrylo0 << 6) & PAGE_MASK, c0,
			       (entrylo0 & 4) ? 1 : 0,
			       (entrylo0 & 2) ? 1 : 0,
			       (entrylo0 & 1) ? 1 : 0);
			printk("[pa=%0*llx c=%d d=%d v=%d g=%d]\n",
			       width,
			       (entrylo1 << 6) & PAGE_MASK, c1,
			       (entrylo1 & 4) ? 1 : 0,
			       (entrylo1 & 2) ? 1 : 0,
			       (entrylo1 & 1) ? 1 : 0);
		}
	}
	printk("\n");

	write_c0_entryhi(s_entryhi);
	write_c0_index(s_index);
}

void dump_tlb_all(void)
{
	dump_tlb(0, current_cpu_data.tlbsize - 1);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Dump R4x00 TLB for debugging purposes.
	3	*
	4	* Copyright (C) 1994, 1995 by Waldorf Electronics, written by Ralf Baechle.
	5	* Copyright (C) 1999 by Silicon Graphics, Inc.
	6	*/
1da177e4 LT	7	#include <linux/kernel.h>
1da177e4 LT	8	#include <linux/mm.h>
1da177e4	9
1da177e4 LT	10	#include <asm/mipsregs.h>
	11	#include <asm/page.h>
	12	#include <asm/pgtable.h>
	13
	14	static inline const char *msk2str(unsigned int mask)
	15	{
	16	switch (mask) {
	17	case PM_4K: return "4kb";
	18	case PM_16K: return "16kb";
	19	case PM_64K: return "64kb";
	20	case PM_256K: return "256kb";
	21	#ifndef CONFIG_CPU_VR41XX
	22	case PM_1M: return "1Mb";
	23	case PM_4M: return "4Mb";
	24	case PM_16M: return "16Mb";
	25	case PM_64M: return "64Mb";
	26	case PM_256M: return "256Mb";
	27	#endif
	28	}
4becef1d	29	return "";
1da177e4 LT	30	}
	31
	32	#define BARRIER() \
	33	__asm__ __volatile__( \
	34	".set\tnoreorder\n\t" \
	35	"nop;nop;nop;nop;nop;nop;nop\n\t" \
	36	".set\treorder");
	37
69ed25b8	38	static void dump_tlb(int first, int last)
1da177e4	39	{
4becef1d AN	40	unsigned long s_entryhi, entryhi, asid;
4becef1d AN	41	unsigned long long entrylo0, entrylo1;
1da177e4 LT	42	unsigned int s_index, pagemask, c0, c1, i;
	43
	44	s_entryhi = read_c0_entryhi();
	45	s_index = read_c0_index();
	46	asid = s_entryhi & 0xff;
	47
	48	for (i = first; i <= last; i++) {
	49	write_c0_index(i);
	50	BARRIER();
	51	tlb_read();
	52	BARRIER();
	53	pagemask = read_c0_pagemask();
	54	entryhi = read_c0_entryhi();
	55	entrylo0 = read_c0_entrylo0();
	56	entrylo1 = read_c0_entrylo1();
	57
	58	/* Unused entries have a virtual address of CKSEG0. */
	59	if ((entryhi & ~0x1ffffUL) != CKSEG0
	60	&& (entryhi & 0xff) == asid) {
4becef1d AN	61	#ifdef CONFIG_32BIT
	62	int width = 8;
	63	#else
	64	int width = 11;
	65	#endif
1da177e4 LT	66	/*
	67	* Only print entries in use
	68	*/
	69	printk("Index: %2d pgmask=%s ", i, msk2str(pagemask));
	70
	71	c0 = (entrylo0 >> 3) & 7;
	72	c1 = (entrylo1 >> 3) & 7;
	73
4becef1d AN	74	printk("va=%0*lx asid=%02lx\n",
4becef1d AN	75	width, (entryhi & ~0x1fffUL),
1da177e4	76	entryhi & 0xff);
4becef1d AN	77	printk("\t[pa=%0*llx c=%d d=%d v=%d g=%d] ",
4becef1d AN	78	width,
1da177e4 LT	79	(entrylo0 << 6) & PAGE_MASK, c0,
	80	(entrylo0 & 4) ? 1 : 0,
	81	(entrylo0 & 2) ? 1 : 0,
4becef1d AN	82	(entrylo0 & 1) ? 1 : 0);
	83	printk("[pa=%0*llx c=%d d=%d v=%d g=%d]\n",
	84	width,
1da177e4 LT	85	(entrylo1 << 6) & PAGE_MASK, c1,
	86	(entrylo1 & 4) ? 1 : 0,
	87	(entrylo1 & 2) ? 1 : 0,
4becef1d	88	(entrylo1 & 1) ? 1 : 0);
1da177e4 LT	89	}
	90	}
	91	printk("\n");
	92
	93	write_c0_entryhi(s_entryhi);
	94	write_c0_index(s_index);
	95	}
	96
	97	void dump_tlb_all(void)
	98	{
	99	dump_tlb(0, current_cpu_data.tlbsize - 1);
	100	}