[deliverable/linux.git] / arch / mips / lib / dump_tlb.c

/*
 * Dump R4x00 TLB for debugging purposes.
 *
 * Copyright (C) 1994, 1995 by Waldorf Electronics, written by Ralf Baechle.
 * Copyright (C) 1999 by Silicon Graphics, Inc.
 */
#include <linux/kernel.h>
#include <linux/mm.h>

#include <asm/mipsregs.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/tlbdebug.h>

static inline const char *msk2str(unsigned int mask)
{
	switch (mask) {
	case PM_4K:	return "4kb";
	case PM_16K:	return "16kb";
	case PM_64K:	return "64kb";
	case PM_256K:	return "256kb";
#ifndef CONFIG_CPU_VR41XX
	case PM_1M:	return "1Mb";
	case PM_4M:	return "4Mb";
	case PM_16M:	return "16Mb";
	case PM_64M:	return "64Mb";
	case PM_256M:	return "256Mb";
	case PM_1G:	return "1Gb";
#endif
	}
	return "";
}

#define BARRIER()					\
	__asm__ __volatile__(				\
		".set\tnoreorder\n\t"			\
		"nop;nop;nop;nop;nop;nop;nop\n\t"	\
		".set\treorder");

static void dump_tlb(int first, int last)
{
	unsigned long s_entryhi, entryhi, asid;
	unsigned long long entrylo0, entrylo1;
	unsigned int s_index, pagemask, c0, c1, i;

	s_entryhi = read_c0_entryhi();
	s_index = read_c0_index();
	asid = s_entryhi & 0xff;

	for (i = first; i <= last; i++) {
		write_c0_index(i);
		BARRIER();
		tlb_read();
		BARRIER();
		pagemask = read_c0_pagemask();
		entryhi  = read_c0_entryhi();
		entrylo0 = read_c0_entrylo0();
		entrylo1 = read_c0_entrylo1();

		/* Unused entries have a virtual address of CKSEG0.  */
		if ((entryhi & ~0x1ffffUL) != CKSEG0
		    && (entryhi & 0xff) == asid) {
#ifdef CONFIG_32BIT
			int width = 8;
#else
			int width = 11;
#endif
			/*
			 * Only print entries in use
			 */
			printk("Index: %2d pgmask=%s ", i, msk2str(pagemask));

			c0 = (entrylo0 >> 3) & 7;
			c1 = (entrylo1 >> 3) & 7;

			printk("va=%0*lx asid=%02lx\n",
			       width, (entryhi & ~0x1fffUL),
			       entryhi & 0xff);
			printk("\t[pa=%0*llx c=%d d=%d v=%d g=%d] ",
			       width,
			       (entrylo0 << 6) & PAGE_MASK, c0,
			       (entrylo0 & 4) ? 1 : 0,
			       (entrylo0 & 2) ? 1 : 0,
			       (entrylo0 & 1) ? 1 : 0);
			printk("[pa=%0*llx c=%d d=%d v=%d g=%d]\n",
			       width,
			       (entrylo1 << 6) & PAGE_MASK, c1,
			       (entrylo1 & 4) ? 1 : 0,
			       (entrylo1 & 2) ? 1 : 0,
			       (entrylo1 & 1) ? 1 : 0);
		}
	}
	printk("\n");

	write_c0_entryhi(s_entryhi);
	write_c0_index(s_index);
}

void dump_tlb_all(void)
{
	dump_tlb(0, current_cpu_data.tlbsize - 1);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Dump R4x00 TLB for debugging purposes.
	3	*
	4	* Copyright (C) 1994, 1995 by Waldorf Electronics, written by Ralf Baechle.
	5	* Copyright (C) 1999 by Silicon Graphics, Inc.
	6	*/
1da177e4 LT	7	#include <linux/kernel.h>
1da177e4 LT	8	#include <linux/mm.h>
1da177e4	9
1da177e4 LT	10	#include <asm/mipsregs.h>
	11	#include <asm/page.h>
	12	#include <asm/pgtable.h>
40df3831	13	#include <asm/tlbdebug.h>
1da177e4 LT	14
	15	static inline const char *msk2str(unsigned int mask)
	16	{
	17	switch (mask) {
	18	case PM_4K: return "4kb";
	19	case PM_16K: return "16kb";
	20	case PM_64K: return "64kb";
	21	case PM_256K: return "256kb";
	22	#ifndef CONFIG_CPU_VR41XX
	23	case PM_1M: return "1Mb";
	24	case PM_4M: return "4Mb";
	25	case PM_16M: return "16Mb";
	26	case PM_64M: return "64Mb";
	27	case PM_256M: return "256Mb";
542c1020	28	case PM_1G: return "1Gb";
1da177e4 LT	29	#endif
1da177e4 LT	30	}
4becef1d	31	return "";
1da177e4 LT	32	}
	33
	34	#define BARRIER() \
	35	__asm__ __volatile__( \
	36	".set\tnoreorder\n\t" \
	37	"nop;nop;nop;nop;nop;nop;nop\n\t" \
	38	".set\treorder");
	39
69ed25b8	40	static void dump_tlb(int first, int last)
1da177e4	41	{
4becef1d AN	42	unsigned long s_entryhi, entryhi, asid;
4becef1d AN	43	unsigned long long entrylo0, entrylo1;
1da177e4 LT	44	unsigned int s_index, pagemask, c0, c1, i;
	45
	46	s_entryhi = read_c0_entryhi();
	47	s_index = read_c0_index();
	48	asid = s_entryhi & 0xff;
	49
	50	for (i = first; i <= last; i++) {
	51	write_c0_index(i);
	52	BARRIER();
	53	tlb_read();
	54	BARRIER();
	55	pagemask = read_c0_pagemask();
	56	entryhi = read_c0_entryhi();
	57	entrylo0 = read_c0_entrylo0();
	58	entrylo1 = read_c0_entrylo1();
	59
	60	/* Unused entries have a virtual address of CKSEG0. */
	61	if ((entryhi & ~0x1ffffUL) != CKSEG0
	62	&& (entryhi & 0xff) == asid) {
4becef1d AN	63	#ifdef CONFIG_32BIT
	64	int width = 8;
	65	#else
	66	int width = 11;
	67	#endif
1da177e4 LT	68	/*
	69	* Only print entries in use
	70	*/
	71	printk("Index: %2d pgmask=%s ", i, msk2str(pagemask));
	72
	73	c0 = (entrylo0 >> 3) & 7;
	74	c1 = (entrylo1 >> 3) & 7;
	75
4becef1d AN	76	printk("va=%0*lx asid=%02lx\n",
4becef1d AN	77	width, (entryhi & ~0x1fffUL),
1da177e4	78	entryhi & 0xff);
4becef1d AN	79	printk("\t[pa=%0*llx c=%d d=%d v=%d g=%d] ",
4becef1d AN	80	width,
1da177e4 LT	81	(entrylo0 << 6) & PAGE_MASK, c0,
	82	(entrylo0 & 4) ? 1 : 0,
	83	(entrylo0 & 2) ? 1 : 0,
4becef1d AN	84	(entrylo0 & 1) ? 1 : 0);
	85	printk("[pa=%0*llx c=%d d=%d v=%d g=%d]\n",
	86	width,
1da177e4 LT	87	(entrylo1 << 6) & PAGE_MASK, c1,
	88	(entrylo1 & 4) ? 1 : 0,
	89	(entrylo1 & 2) ? 1 : 0,
4becef1d	90	(entrylo1 & 1) ? 1 : 0);
1da177e4 LT	91	}
	92	}
	93	printk("\n");
	94
	95	write_c0_entryhi(s_entryhi);
	96	write_c0_index(s_index);
	97	}
	98
	99	void dump_tlb_all(void)
	100	{
	101	dump_tlb(0, current_cpu_data.tlbsize - 1);
	102	}