Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
140c1729 | 2 | * Implement the default iomap interfaces |
1da177e4 | 3 | * |
140c1729 RB |
4 | * (C) Copyright 2004 Linus Torvalds |
5 | * (C) Copyright 2006 Ralf Baechle <ralf@linux-mips.org> | |
6 | * (C) Copyright 2007 MIPS Technologies, Inc. | |
7 | * written by Ralf Baechle <ralf@linux-mips.org> | |
8 | */ | |
140c1729 RB |
9 | #include <linux/module.h> |
10 | #include <asm/io.h> | |
11 | ||
12 | /* | |
13 | * Read/write from/to an (offsettable) iomem cookie. It might be a PIO | |
14 | * access or a MMIO access, these functions don't care. The info is | |
15 | * encoded in the hardware mapping set up by the mapping functions | |
16 | * (or the cookie itself, depending on implementation and hw). | |
1da177e4 | 17 | * |
140c1729 RB |
18 | * The generic routines don't assume any hardware mappings, and just |
19 | * encode the PIO/MMIO as part of the cookie. They coldly assume that | |
20 | * the MMIO IO mappings are not in the low address range. | |
1da177e4 | 21 | * |
140c1729 RB |
22 | * Architectures for which this is not true can't use this generic |
23 | * implementation and should do their own copy. | |
1da177e4 | 24 | */ |
1da177e4 | 25 | |
140c1729 | 26 | #define PIO_MASK 0x0ffffUL |
1da177e4 | 27 | |
140c1729 | 28 | unsigned int ioread8(void __iomem *addr) |
1da177e4 | 29 | { |
140c1729 RB |
30 | return readb(addr); |
31 | } | |
1da177e4 | 32 | |
140c1729 | 33 | EXPORT_SYMBOL(ioread8); |
1da177e4 | 34 | |
140c1729 RB |
35 | unsigned int ioread16(void __iomem *addr) |
36 | { | |
37 | return readw(addr); | |
1da177e4 LT |
38 | } |
39 | ||
140c1729 RB |
40 | EXPORT_SYMBOL(ioread16); |
41 | ||
42 | unsigned int ioread16be(void __iomem *addr) | |
1da177e4 | 43 | { |
140c1729 | 44 | return be16_to_cpu(__raw_readw(addr)); |
1da177e4 | 45 | } |
1da177e4 | 46 | |
140c1729 RB |
47 | EXPORT_SYMBOL(ioread16be); |
48 | ||
49 | unsigned int ioread32(void __iomem *addr) | |
1da177e4 | 50 | { |
140c1729 RB |
51 | return readl(addr); |
52 | } | |
1da177e4 | 53 | |
140c1729 | 54 | EXPORT_SYMBOL(ioread32); |
1da177e4 | 55 | |
140c1729 RB |
56 | unsigned int ioread32be(void __iomem *addr) |
57 | { | |
58 | return be32_to_cpu(__raw_readl(addr)); | |
59 | } | |
1da177e4 | 60 | |
140c1729 RB |
61 | EXPORT_SYMBOL(ioread32be); |
62 | ||
63 | void iowrite8(u8 val, void __iomem *addr) | |
64 | { | |
65 | writeb(val, addr); | |
66 | } | |
1da177e4 | 67 | |
140c1729 RB |
68 | EXPORT_SYMBOL(iowrite8); |
69 | ||
70 | void iowrite16(u16 val, void __iomem *addr) | |
71 | { | |
72 | writew(val, addr); | |
73 | } | |
74 | ||
75 | EXPORT_SYMBOL(iowrite16); | |
76 | ||
77 | void iowrite16be(u16 val, void __iomem *addr) | |
78 | { | |
79 | __raw_writew(cpu_to_be16(val), addr); | |
80 | } | |
81 | ||
82 | EXPORT_SYMBOL(iowrite16be); | |
83 | ||
84 | void iowrite32(u32 val, void __iomem *addr) | |
85 | { | |
86 | writel(val, addr); | |
87 | } | |
88 | ||
89 | EXPORT_SYMBOL(iowrite32); | |
90 | ||
91 | void iowrite32be(u32 val, void __iomem *addr) | |
92 | { | |
93 | __raw_writel(cpu_to_be32(val), addr); | |
94 | } | |
95 | ||
96 | EXPORT_SYMBOL(iowrite32be); | |
97 | ||
98 | /* | |
99 | * These are the "repeat MMIO read/write" functions. | |
0845bb72 MC |
100 | * Note the "__mem" accesses, since we want to convert |
101 | * to CPU byte order if the host bus happens to not match the | |
102 | * endianness of PCI/ISA (see mach-generic/mangle-port.h). | |
140c1729 RB |
103 | */ |
104 | static inline void mmio_insb(void __iomem *addr, u8 *dst, int count) | |
105 | { | |
106 | while (--count >= 0) { | |
0845bb72 | 107 | u8 data = __mem_readb(addr); |
140c1729 RB |
108 | *dst = data; |
109 | dst++; | |
1da177e4 | 110 | } |
140c1729 | 111 | } |
1da177e4 | 112 | |
140c1729 RB |
113 | static inline void mmio_insw(void __iomem *addr, u16 *dst, int count) |
114 | { | |
115 | while (--count >= 0) { | |
0845bb72 | 116 | u16 data = __mem_readw(addr); |
140c1729 RB |
117 | *dst = data; |
118 | dst++; | |
119 | } | |
1da177e4 LT |
120 | } |
121 | ||
140c1729 | 122 | static inline void mmio_insl(void __iomem *addr, u32 *dst, int count) |
1da177e4 | 123 | { |
140c1729 | 124 | while (--count >= 0) { |
0845bb72 | 125 | u32 data = __mem_readl(addr); |
140c1729 RB |
126 | *dst = data; |
127 | dst++; | |
128 | } | |
1da177e4 | 129 | } |
140c1729 RB |
130 | |
131 | static inline void mmio_outsb(void __iomem *addr, const u8 *src, int count) | |
132 | { | |
133 | while (--count >= 0) { | |
0845bb72 | 134 | __mem_writeb(*src, addr); |
140c1729 RB |
135 | src++; |
136 | } | |
137 | } | |
138 | ||
139 | static inline void mmio_outsw(void __iomem *addr, const u16 *src, int count) | |
140 | { | |
141 | while (--count >= 0) { | |
0845bb72 | 142 | __mem_writew(*src, addr); |
140c1729 RB |
143 | src++; |
144 | } | |
145 | } | |
146 | ||
147 | static inline void mmio_outsl(void __iomem *addr, const u32 *src, int count) | |
148 | { | |
149 | while (--count >= 0) { | |
0845bb72 | 150 | __mem_writel(*src, addr); |
140c1729 RB |
151 | src++; |
152 | } | |
153 | } | |
154 | ||
155 | void ioread8_rep(void __iomem *addr, void *dst, unsigned long count) | |
156 | { | |
157 | mmio_insb(addr, dst, count); | |
158 | } | |
159 | ||
160 | EXPORT_SYMBOL(ioread8_rep); | |
161 | ||
162 | void ioread16_rep(void __iomem *addr, void *dst, unsigned long count) | |
163 | { | |
164 | mmio_insw(addr, dst, count); | |
165 | } | |
166 | ||
167 | EXPORT_SYMBOL(ioread16_rep); | |
168 | ||
169 | void ioread32_rep(void __iomem *addr, void *dst, unsigned long count) | |
170 | { | |
171 | mmio_insl(addr, dst, count); | |
172 | } | |
173 | ||
174 | EXPORT_SYMBOL(ioread32_rep); | |
175 | ||
176 | void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count) | |
177 | { | |
178 | mmio_outsb(addr, src, count); | |
179 | } | |
180 | ||
181 | EXPORT_SYMBOL(iowrite8_rep); | |
182 | ||
183 | void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count) | |
184 | { | |
185 | mmio_outsw(addr, src, count); | |
186 | } | |
187 | ||
188 | EXPORT_SYMBOL(iowrite16_rep); | |
189 | ||
190 | void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count) | |
191 | { | |
192 | mmio_outsl(addr, src, count); | |
193 | } | |
194 | ||
195 | EXPORT_SYMBOL(iowrite32_rep); | |
196 | ||
197 | /* | |
198 | * Create a virtual mapping cookie for an IO port range | |
199 | * | |
200 | * This uses the same mapping are as the in/out family which has to be setup | |
201 | * by the platform initialization code. | |
202 | * | |
203 | * Just to make matters somewhat more interesting on MIPS systems with | |
204 | * multiple host bridge each will have it's own ioport address space. | |
205 | */ | |
206 | static void __iomem *ioport_map_legacy(unsigned long port, unsigned int nr) | |
207 | { | |
208 | return (void __iomem *) (mips_io_port_base + port); | |
209 | } | |
210 | ||
211 | void __iomem *ioport_map(unsigned long port, unsigned int nr) | |
212 | { | |
213 | if (port > PIO_MASK) | |
214 | return NULL; | |
215 | ||
216 | return ioport_map_legacy(port, nr); | |
217 | } | |
218 | ||
219 | EXPORT_SYMBOL(ioport_map); | |
220 | ||
221 | void ioport_unmap(void __iomem *addr) | |
222 | { | |
223 | /* Nothing to do */ | |
224 | } | |
225 | ||
226 | EXPORT_SYMBOL(ioport_unmap); |