[deliverable/linux.git] / arch / mips / loongson / lemote-2f / clock.c

/*
 * Copyright (C) 2006 - 2008 Lemote Inc. & Insititute of Computing Technology
 * Author: Yanhua, yanh@lemote.com
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/clk.h>
#include <linux/cpufreq.h>
#include <linux/errno.h>
#include <linux/export.h>
#include <linux/list.h>
#include <linux/mutex.h>
#include <linux/spinlock.h>

#include <asm/clock.h>
#include <asm/mach-loongson/loongson.h>

static LIST_HEAD(clock_list);
static DEFINE_SPINLOCK(clock_lock);
static DEFINE_MUTEX(clock_list_sem);

/* Minimum CLK support */
enum {
	DC_ZERO, DC_25PT = 2, DC_37PT, DC_50PT, DC_62PT, DC_75PT,
	DC_87PT, DC_DISABLE, DC_RESV
};

struct cpufreq_frequency_table loongson2_clockmod_table[] = {
	{0, DC_RESV, CPUFREQ_ENTRY_INVALID},
	{0, DC_ZERO, CPUFREQ_ENTRY_INVALID},
	{0, DC_25PT, 0},
	{0, DC_37PT, 0},
	{0, DC_50PT, 0},
	{0, DC_62PT, 0},
	{0, DC_75PT, 0},
	{0, DC_87PT, 0},
	{0, DC_DISABLE, 0},
	{0, DC_RESV, CPUFREQ_TABLE_END},
};
EXPORT_SYMBOL_GPL(loongson2_clockmod_table);

static struct clk cpu_clk = {
	.name = "cpu_clk",
	.flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
	.rate = 800000000,
};

struct clk *clk_get(struct device *dev, const char *id)
{
	return &cpu_clk;
}
EXPORT_SYMBOL(clk_get);

static void propagate_rate(struct clk *clk)
{
	struct clk *clkp;

	list_for_each_entry(clkp, &clock_list, node) {
		if (likely(clkp->parent != clk))
			continue;
		if (likely(clkp->ops && clkp->ops->recalc))
			clkp->ops->recalc(clkp);
		if (unlikely(clkp->flags & CLK_RATE_PROPAGATES))
			propagate_rate(clkp);
	}
}

int clk_enable(struct clk *clk)
{
	return 0;
}
EXPORT_SYMBOL(clk_enable);

void clk_disable(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_disable);

unsigned long clk_get_rate(struct clk *clk)
{
	return (unsigned long)clk->rate;
}
EXPORT_SYMBOL(clk_get_rate);

void clk_put(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_put);

int clk_set_rate(struct clk *clk, unsigned long rate)
{
	unsigned int rate_khz = rate / 1000;
	struct cpufreq_frequency_table *pos;
	int ret = 0;
	int regval;

	if (likely(clk->ops && clk->ops->set_rate)) {
		unsigned long flags;

		spin_lock_irqsave(&clock_lock, flags);
		ret = clk->ops->set_rate(clk, rate, 0);
		spin_unlock_irqrestore(&clock_lock, flags);
	}

	if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
		propagate_rate(clk);

	cpufreq_for_each_valid_entry(pos, loongson2_clockmod_table)
		if (rate_khz == pos->frequency)
			break;
	if (rate_khz != pos->frequency)
		return -ENOTSUPP;

	clk->rate = rate;

	regval = LOONGSON_CHIPCFG(0);
	regval = (regval & ~0x7) | (pos->driver_data - 1);
	LOONGSON_CHIPCFG(0) = regval;

	return ret;
}
EXPORT_SYMBOL_GPL(clk_set_rate);

long clk_round_rate(struct clk *clk, unsigned long rate)
{
	if (likely(clk->ops && clk->ops->round_rate)) {
		unsigned long flags, rounded;

		spin_lock_irqsave(&clock_lock, flags);
		rounded = clk->ops->round_rate(clk, rate);
		spin_unlock_irqrestore(&clock_lock, flags);

		return rounded;
	}

	return rate;
}
EXPORT_SYMBOL_GPL(clk_round_rate);
Commit	Line	Data
f8ede0f7 WZ	1	/*
	2	* Copyright (C) 2006 - 2008 Lemote Inc. & Insititute of Computing Technology
	3	* Author: Yanhua, yanh@lemote.com
	4	*
	5	* This file is subject to the terms and conditions of the GNU General Public
	6	* License. See the file "COPYING" in the main directory of this archive
	7	* for more details.
	8	*/
95cf1468	9	#include <linux/clk.h>
f8ede0f7	10	#include <linux/cpufreq.h>
95cf1468 RB	11	#include <linux/errno.h>
95cf1468 RB	12	#include <linux/export.h>
95cf1468 RB	13	#include <linux/list.h>
	14	#include <linux/mutex.h>
	15	#include <linux/spinlock.h>
f8ede0f7 WZ	16
f8ede0f7 WZ	17	#include <asm/clock.h>
95cf1468	18	#include <asm/mach-loongson/loongson.h>
f8ede0f7 WZ	19
	20	static LIST_HEAD(clock_list);
	21	static DEFINE_SPINLOCK(clock_lock);
	22	static DEFINE_MUTEX(clock_list_sem);
	23
	24	/* Minimum CLK support */
	25	enum {
	26	DC_ZERO, DC_25PT = 2, DC_37PT, DC_50PT, DC_62PT, DC_75PT,
	27	DC_87PT, DC_DISABLE, DC_RESV
	28	};
	29
	30	struct cpufreq_frequency_table loongson2_clockmod_table[] = {
7f4b0461 VK	31	{0, DC_RESV, CPUFREQ_ENTRY_INVALID},
	32	{0, DC_ZERO, CPUFREQ_ENTRY_INVALID},
	33	{0, DC_25PT, 0},
	34	{0, DC_37PT, 0},
	35	{0, DC_50PT, 0},
	36	{0, DC_62PT, 0},
	37	{0, DC_75PT, 0},
	38	{0, DC_87PT, 0},
	39	{0, DC_DISABLE, 0},
	40	{0, DC_RESV, CPUFREQ_TABLE_END},
f8ede0f7 WZ	41	};
	42	EXPORT_SYMBOL_GPL(loongson2_clockmod_table);
	43
	44	static struct clk cpu_clk = {
	45	.name = "cpu_clk",
	46	.flags = CLK_ALWAYS_ENABLED \| CLK_RATE_PROPAGATES,
	47	.rate = 800000000,
	48	};
	49
	50	struct clk clk_get(struct device dev, const char *id)
	51	{
	52	return &cpu_clk;
	53	}
	54	EXPORT_SYMBOL(clk_get);
	55
	56	static void propagate_rate(struct clk *clk)
	57	{
	58	struct clk *clkp;
	59
	60	list_for_each_entry(clkp, &clock_list, node) {
	61	if (likely(clkp->parent != clk))
	62	continue;
	63	if (likely(clkp->ops && clkp->ops->recalc))
	64	clkp->ops->recalc(clkp);
	65	if (unlikely(clkp->flags & CLK_RATE_PROPAGATES))
	66	propagate_rate(clkp);
	67	}
	68	}
	69
	70	int clk_enable(struct clk *clk)
	71	{
	72	return 0;
	73	}
	74	EXPORT_SYMBOL(clk_enable);
	75
	76	void clk_disable(struct clk *clk)
	77	{
	78	}
	79	EXPORT_SYMBOL(clk_disable);
	80
	81	unsigned long clk_get_rate(struct clk *clk)
	82	{
	83	return (unsigned long)clk->rate;
	84	}
	85	EXPORT_SYMBOL(clk_get_rate);
	86
	87	void clk_put(struct clk *clk)
	88	{
	89	}
	90	EXPORT_SYMBOL(clk_put);
	91
	92	int clk_set_rate(struct clk *clk, unsigned long rate)
f8ede0f7	93	{
aa08ed55	94	unsigned int rate_khz = rate / 1000;
4966ee40	95	struct cpufreq_frequency_table *pos;
f8ede0f7 WZ	96	int ret = 0;
f8ede0f7 WZ	97	int regval;
f8ede0f7 WZ	98
	99	if (likely(clk->ops && clk->ops->set_rate)) {
	100	unsigned long flags;
	101
	102	spin_lock_irqsave(&clock_lock, flags);
95cf1468	103	ret = clk->ops->set_rate(clk, rate, 0);
f8ede0f7 WZ	104	spin_unlock_irqrestore(&clock_lock, flags);
	105	}
	106
	107	if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
	108	propagate_rate(clk);
	109
4966ee40	110	cpufreq_for_each_valid_entry(pos, loongson2_clockmod_table)
aa08ed55	111	if (rate_khz == pos->frequency)
f8ede0f7	112	break;
aa08ed55	113	if (rate_khz != pos->frequency)
f8ede0f7 WZ	114	return -ENOTSUPP;
	115
	116	clk->rate = rate;
	117
140e39c1	118	regval = LOONGSON_CHIPCFG(0);
4966ee40	119	regval = (regval & ~0x7) \| (pos->driver_data - 1);
140e39c1	120	LOONGSON_CHIPCFG(0) = regval;
f8ede0f7 WZ	121
	122	return ret;
	123	}
95cf1468	124	EXPORT_SYMBOL_GPL(clk_set_rate);
f8ede0f7 WZ	125
	126	long clk_round_rate(struct clk *clk, unsigned long rate)
	127	{
	128	if (likely(clk->ops && clk->ops->round_rate)) {
	129	unsigned long flags, rounded;
	130
	131	spin_lock_irqsave(&clock_lock, flags);
	132	rounded = clk->ops->round_rate(clk, rate);
	133	spin_unlock_irqrestore(&clock_lock, flags);
	134
	135	return rounded;
	136	}
	137
	138	return rate;
	139	}
	140	EXPORT_SYMBOL_GPL(clk_round_rate);