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MIPS: math-emu: Add mfhc1 & mthc1 support.
[deliverable/linux.git] / arch / mips / math-emu / cp1emu.c
CommitLineData
1da177e4
LT		 1/*
2 * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
1da177e4
LT		 6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
26 *
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware fpu at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
32 *
33 * Note if you know that you won't have an fpu, then you'll get much
34 * better performance by compiling with -msoft-float!
35 */
36#include <linux/sched.h>
b6ee75ed 37#include <linux/module.h>
83fd38ca 38#include <linux/debugfs.h>
7f788d2d 39#include <linux/perf_event.h>
1da177e4
LT		 40
41#include <asm/inst.h>
42#include <asm/bootinfo.h>
1da177e4
LT		 43#include <asm/processor.h>
44#include <asm/ptrace.h>
45#include <asm/signal.h>
46#include <asm/mipsregs.h>
47#include <asm/fpu_emulator.h>
102cedc3 48#include <asm/fpu.h>
1da177e4
LT		 49#include <asm/uaccess.h>
50#include <asm/branch.h>
51
52#include "ieee754.h"
1da177e4
LT		 53
54/* Strap kernel emulator for full MIPS IV emulation */
55
56#ifdef __mips
57#undef __mips
58#endif
59#define __mips 4
60
61/* Function which emulates a floating point instruction. */
62
eae89076 63static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
1da177e4
LT		 64 mips_instruction);
65
66#if __mips >= 4 && __mips != 32
67static int fpux_emu(struct pt_regs *,
515b029d 68 struct mips_fpu_struct *, mips_instruction, void *__user *);
1da177e4
LT		 69#endif
70
eae89076 71/* Further private data for which no space exists in mips_fpu_struct */
1da177e4 72
b6ee75ed
DD		 73#ifdef CONFIG_DEBUG_FS
74DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
75#endif
1da177e4
LT		 76
77/* Control registers */
78
79#define FPCREG_RID 0 /* $0 = revision id */
80#define FPCREG_CSR 31 /* $31 = csr */
81
95e8f634
SM		 82/* Determine rounding mode from the RM bits of the FCSR */
83#define modeindex(v) ((v) & FPU_CSR_RM)
84
102cedc3
LY		 85/* microMIPS bitfields */
86#define MM_POOL32A_MINOR_MASK 0x3f
87#define MM_POOL32A_MINOR_SHIFT 0x6
88#define MM_MIPS32_COND_FC 0x30
89
1da177e4
LT		 90/* Convert Mips rounding mode (0..3) to IEEE library modes. */
91static const unsigned char ieee_rm[4] = {
cd21dfcf
RB		 92 [FPU_CSR_RN] = IEEE754_RN,
93 [FPU_CSR_RZ] = IEEE754_RZ,
94 [FPU_CSR_RU] = IEEE754_RU,
95 [FPU_CSR_RD] = IEEE754_RD,
96};
97/* Convert IEEE library modes to Mips rounding mode (0..3). */
98static const unsigned char mips_rm[4] = {
99 [IEEE754_RN] = FPU_CSR_RN,
100 [IEEE754_RZ] = FPU_CSR_RZ,
101 [IEEE754_RD] = FPU_CSR_RD,
102 [IEEE754_RU] = FPU_CSR_RU,
1da177e4
LT		 103};
104
105#if __mips >= 4
106/* convert condition code register number to csr bit */
107static const unsigned int fpucondbit[8] = {
108 FPU_CSR_COND0,
109 FPU_CSR_COND1,
110 FPU_CSR_COND2,
111 FPU_CSR_COND3,
112 FPU_CSR_COND4,
113 FPU_CSR_COND5,
114 FPU_CSR_COND6,
115 FPU_CSR_COND7
116};
117#endif
118
102cedc3
LY		 119/* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
120static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7};
121
122/* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
123static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
124static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
125static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
126static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
127
128/*
129 * This functions translates a 32-bit microMIPS instruction
130 * into a 32-bit MIPS32 instruction. Returns 0 on success
131 * and SIGILL otherwise.
132 */
133static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
134{
135 union mips_instruction insn = *insn_ptr;
136 union mips_instruction mips32_insn = insn;
137 int func, fmt, op;
138
139 switch (insn.mm_i_format.opcode) {
140 case mm_ldc132_op:
141 mips32_insn.mm_i_format.opcode = ldc1_op;
142 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
143 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
144 break;
145 case mm_lwc132_op:
146 mips32_insn.mm_i_format.opcode = lwc1_op;
147 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
148 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
149 break;
150 case mm_sdc132_op:
151 mips32_insn.mm_i_format.opcode = sdc1_op;
152 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
153 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
154 break;
155 case mm_swc132_op:
156 mips32_insn.mm_i_format.opcode = swc1_op;
157 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
158 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
159 break;
160 case mm_pool32i_op:
161 /* NOTE: offset is << by 1 if in microMIPS mode. */
162 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
163 (insn.mm_i_format.rt == mm_bc1t_op)) {
164 mips32_insn.fb_format.opcode = cop1_op;
165 mips32_insn.fb_format.bc = bc_op;
166 mips32_insn.fb_format.flag =
167 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
168 } else
169 return SIGILL;
170 break;
171 case mm_pool32f_op:
172 switch (insn.mm_fp0_format.func) {
173 case mm_32f_01_op:
174 case mm_32f_11_op:
175 case mm_32f_02_op:
176 case mm_32f_12_op:
177 case mm_32f_41_op:
178 case mm_32f_51_op:
179 case mm_32f_42_op:
180 case mm_32f_52_op:
181 op = insn.mm_fp0_format.func;
182 if (op == mm_32f_01_op)
183 func = madd_s_op;
184 else if (op == mm_32f_11_op)
185 func = madd_d_op;
186 else if (op == mm_32f_02_op)
187 func = nmadd_s_op;
188 else if (op == mm_32f_12_op)
189 func = nmadd_d_op;
190 else if (op == mm_32f_41_op)
191 func = msub_s_op;
192 else if (op == mm_32f_51_op)
193 func = msub_d_op;
194 else if (op == mm_32f_42_op)
195 func = nmsub_s_op;
196 else
197 func = nmsub_d_op;
198 mips32_insn.fp6_format.opcode = cop1x_op;
199 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
200 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
201 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
202 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
203 mips32_insn.fp6_format.func = func;
204 break;
205 case mm_32f_10_op:
206 func = -1; /* Invalid */
207 op = insn.mm_fp5_format.op & 0x7;
208 if (op == mm_ldxc1_op)
209 func = ldxc1_op;
210 else if (op == mm_sdxc1_op)
211 func = sdxc1_op;
212 else if (op == mm_lwxc1_op)
213 func = lwxc1_op;
214 else if (op == mm_swxc1_op)
215 func = swxc1_op;
216
217 if (func != -1) {
218 mips32_insn.r_format.opcode = cop1x_op;
219 mips32_insn.r_format.rs =
220 insn.mm_fp5_format.base;
221 mips32_insn.r_format.rt =
222 insn.mm_fp5_format.index;
223 mips32_insn.r_format.rd = 0;
224 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
225 mips32_insn.r_format.func = func;
226 } else
227 return SIGILL;
228 break;
229 case mm_32f_40_op:
230 op = -1; /* Invalid */
231 if (insn.mm_fp2_format.op == mm_fmovt_op)
232 op = 1;
233 else if (insn.mm_fp2_format.op == mm_fmovf_op)
234 op = 0;
235 if (op != -1) {
236 mips32_insn.fp0_format.opcode = cop1_op;
237 mips32_insn.fp0_format.fmt =
238 sdps_format[insn.mm_fp2_format.fmt];
239 mips32_insn.fp0_format.ft =
240 (insn.mm_fp2_format.cc<<2) + op;
241 mips32_insn.fp0_format.fs =
242 insn.mm_fp2_format.fs;
243 mips32_insn.fp0_format.fd =
244 insn.mm_fp2_format.fd;
245 mips32_insn.fp0_format.func = fmovc_op;
246 } else
247 return SIGILL;
248 break;
249 case mm_32f_60_op:
250 func = -1; /* Invalid */
251 if (insn.mm_fp0_format.op == mm_fadd_op)
252 func = fadd_op;
253 else if (insn.mm_fp0_format.op == mm_fsub_op)
254 func = fsub_op;
255 else if (insn.mm_fp0_format.op == mm_fmul_op)
256 func = fmul_op;
257 else if (insn.mm_fp0_format.op == mm_fdiv_op)
258 func = fdiv_op;
259 if (func != -1) {
260 mips32_insn.fp0_format.opcode = cop1_op;
261 mips32_insn.fp0_format.fmt =
262 sdps_format[insn.mm_fp0_format.fmt];
263 mips32_insn.fp0_format.ft =
264 insn.mm_fp0_format.ft;
265 mips32_insn.fp0_format.fs =
266 insn.mm_fp0_format.fs;
267 mips32_insn.fp0_format.fd =
268 insn.mm_fp0_format.fd;
269 mips32_insn.fp0_format.func = func;
270 } else
271 return SIGILL;
272 break;
273 case mm_32f_70_op:
274 func = -1; /* Invalid */
275 if (insn.mm_fp0_format.op == mm_fmovn_op)
276 func = fmovn_op;
277 else if (insn.mm_fp0_format.op == mm_fmovz_op)
278 func = fmovz_op;
279 if (func != -1) {
280 mips32_insn.fp0_format.opcode = cop1_op;
281 mips32_insn.fp0_format.fmt =
282 sdps_format[insn.mm_fp0_format.fmt];
283 mips32_insn.fp0_format.ft =
284 insn.mm_fp0_format.ft;
285 mips32_insn.fp0_format.fs =
286 insn.mm_fp0_format.fs;
287 mips32_insn.fp0_format.fd =
288 insn.mm_fp0_format.fd;
289 mips32_insn.fp0_format.func = func;
290 } else
291 return SIGILL;
292 break;
293 case mm_32f_73_op: /* POOL32FXF */
294 switch (insn.mm_fp1_format.op) {
295 case mm_movf0_op:
296 case mm_movf1_op:
297 case mm_movt0_op:
298 case mm_movt1_op:
299 if ((insn.mm_fp1_format.op & 0x7f) ==
300 mm_movf0_op)
301 op = 0;
302 else
303 op = 1;
304 mips32_insn.r_format.opcode = spec_op;
305 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
306 mips32_insn.r_format.rt =
307 (insn.mm_fp4_format.cc << 2) + op;
308 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
309 mips32_insn.r_format.re = 0;
310 mips32_insn.r_format.func = movc_op;
311 break;
312 case mm_fcvtd0_op:
313 case mm_fcvtd1_op:
314 case mm_fcvts0_op:
315 case mm_fcvts1_op:
316 if ((insn.mm_fp1_format.op & 0x7f) ==
317 mm_fcvtd0_op) {
318 func = fcvtd_op;
319 fmt = swl_format[insn.mm_fp3_format.fmt];
320 } else {
321 func = fcvts_op;
322 fmt = dwl_format[insn.mm_fp3_format.fmt];
323 }
324 mips32_insn.fp0_format.opcode = cop1_op;
325 mips32_insn.fp0_format.fmt = fmt;
326 mips32_insn.fp0_format.ft = 0;
327 mips32_insn.fp0_format.fs =
328 insn.mm_fp3_format.fs;
329 mips32_insn.fp0_format.fd =
330 insn.mm_fp3_format.rt;
331 mips32_insn.fp0_format.func = func;
332 break;
333 case mm_fmov0_op:
334 case mm_fmov1_op:
335 case mm_fabs0_op:
336 case mm_fabs1_op:
337 case mm_fneg0_op:
338 case mm_fneg1_op:
339 if ((insn.mm_fp1_format.op & 0x7f) ==
340 mm_fmov0_op)
341 func = fmov_op;
342 else if ((insn.mm_fp1_format.op & 0x7f) ==
343 mm_fabs0_op)
344 func = fabs_op;
345 else
346 func = fneg_op;
347 mips32_insn.fp0_format.opcode = cop1_op;
348 mips32_insn.fp0_format.fmt =
349 sdps_format[insn.mm_fp3_format.fmt];
350 mips32_insn.fp0_format.ft = 0;
351 mips32_insn.fp0_format.fs =
352 insn.mm_fp3_format.fs;
353 mips32_insn.fp0_format.fd =
354 insn.mm_fp3_format.rt;
355 mips32_insn.fp0_format.func = func;
356 break;
357 case mm_ffloorl_op:
358 case mm_ffloorw_op:
359 case mm_fceill_op:
360 case mm_fceilw_op:
361 case mm_ftruncl_op:
362 case mm_ftruncw_op:
363 case mm_froundl_op:
364 case mm_froundw_op:
365 case mm_fcvtl_op:
366 case mm_fcvtw_op:
367 if (insn.mm_fp1_format.op == mm_ffloorl_op)
368 func = ffloorl_op;
369 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
370 func = ffloor_op;
371 else if (insn.mm_fp1_format.op == mm_fceill_op)
372 func = fceill_op;
373 else if (insn.mm_fp1_format.op == mm_fceilw_op)
374 func = fceil_op;
375 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
376 func = ftruncl_op;
377 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
378 func = ftrunc_op;
379 else if (insn.mm_fp1_format.op == mm_froundl_op)
380 func = froundl_op;
381 else if (insn.mm_fp1_format.op == mm_froundw_op)
382 func = fround_op;
383 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
384 func = fcvtl_op;
385 else
386 func = fcvtw_op;
387 mips32_insn.fp0_format.opcode = cop1_op;
388 mips32_insn.fp0_format.fmt =
389 sd_format[insn.mm_fp1_format.fmt];
390 mips32_insn.fp0_format.ft = 0;
391 mips32_insn.fp0_format.fs =
392 insn.mm_fp1_format.fs;
393 mips32_insn.fp0_format.fd =
394 insn.mm_fp1_format.rt;
395 mips32_insn.fp0_format.func = func;
396 break;
397 case mm_frsqrt_op:
398 case mm_fsqrt_op:
399 case mm_frecip_op:
400 if (insn.mm_fp1_format.op == mm_frsqrt_op)
401 func = frsqrt_op;
402 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
403 func = fsqrt_op;
404 else
405 func = frecip_op;
406 mips32_insn.fp0_format.opcode = cop1_op;
407 mips32_insn.fp0_format.fmt =
408 sdps_format[insn.mm_fp1_format.fmt];
409 mips32_insn.fp0_format.ft = 0;
410 mips32_insn.fp0_format.fs =
411 insn.mm_fp1_format.fs;
412 mips32_insn.fp0_format.fd =
413 insn.mm_fp1_format.rt;
414 mips32_insn.fp0_format.func = func;
415 break;
416 case mm_mfc1_op:
417 case mm_mtc1_op:
418 case mm_cfc1_op:
419 case mm_ctc1_op:
420 if (insn.mm_fp1_format.op == mm_mfc1_op)
421 op = mfc_op;
422 else if (insn.mm_fp1_format.op == mm_mtc1_op)
423 op = mtc_op;
424 else if (insn.mm_fp1_format.op == mm_cfc1_op)
425 op = cfc_op;
426 else
427 op = ctc_op;
428 mips32_insn.fp1_format.opcode = cop1_op;
429 mips32_insn.fp1_format.op = op;
430 mips32_insn.fp1_format.rt =
431 insn.mm_fp1_format.rt;
432 mips32_insn.fp1_format.fs =
433 insn.mm_fp1_format.fs;
434 mips32_insn.fp1_format.fd = 0;
435 mips32_insn.fp1_format.func = 0;
436 break;
437 default:
438 return SIGILL;
102cedc3
LY		 439 }
440 break;
441 case mm_32f_74_op: /* c.cond.fmt */
442 mips32_insn.fp0_format.opcode = cop1_op;
443 mips32_insn.fp0_format.fmt =
444 sdps_format[insn.mm_fp4_format.fmt];
445 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
446 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
447 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
448 mips32_insn.fp0_format.func =
449 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
450 break;
451 default:
452 return SIGILL;
102cedc3
LY		 453 }
454 break;
455 default:
456 return SIGILL;
102cedc3
LY		 457 }
458
459 *insn_ptr = mips32_insn;
460 return 0;
461}
462
463int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
464 unsigned long *contpc)
465{
466 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
467 int bc_false = 0;
468 unsigned int fcr31;
469 unsigned int bit;
470
fe6d2909
DD		 471 if (!cpu_has_mmips)
472 return 0;
473
102cedc3
LY		 474 switch (insn.mm_i_format.opcode) {
475 case mm_pool32a_op:
476 if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) ==
477 mm_pool32axf_op) {
478 switch (insn.mm_i_format.simmediate >>
479 MM_POOL32A_MINOR_SHIFT) {
480 case mm_jalr_op:
481 case mm_jalrhb_op:
482 case mm_jalrs_op:
483 case mm_jalrshb_op:
484 if (insn.mm_i_format.rt != 0) /* Not mm_jr */
485 regs->regs[insn.mm_i_format.rt] =
486 regs->cp0_epc +
487 dec_insn.pc_inc +
488 dec_insn.next_pc_inc;
489 *contpc = regs->regs[insn.mm_i_format.rs];
490 return 1;
102cedc3
LY		 491 }
492 }
493 break;
494 case mm_pool32i_op:
495 switch (insn.mm_i_format.rt) {
496 case mm_bltzals_op:
497 case mm_bltzal_op:
498 regs->regs[31] = regs->cp0_epc +
499 dec_insn.pc_inc +
500 dec_insn.next_pc_inc;
501 /* Fall through */
502 case mm_bltz_op:
503 if ((long)regs->regs[insn.mm_i_format.rs] < 0)
504 *contpc = regs->cp0_epc +
505 dec_insn.pc_inc +
506 (insn.mm_i_format.simmediate << 1);
507 else
508 *contpc = regs->cp0_epc +
509 dec_insn.pc_inc +
510 dec_insn.next_pc_inc;
511 return 1;
102cedc3
LY		 512 case mm_bgezals_op:
513 case mm_bgezal_op:
514 regs->regs[31] = regs->cp0_epc +
515 dec_insn.pc_inc +
516 dec_insn.next_pc_inc;
517 /* Fall through */
518 case mm_bgez_op:
519 if ((long)regs->regs[insn.mm_i_format.rs] >= 0)
520 *contpc = regs->cp0_epc +
521 dec_insn.pc_inc +
522 (insn.mm_i_format.simmediate << 1);
523 else
524 *contpc = regs->cp0_epc +
525 dec_insn.pc_inc +
526 dec_insn.next_pc_inc;
527 return 1;
102cedc3
LY		 528 case mm_blez_op:
529 if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
530 *contpc = regs->cp0_epc +
531 dec_insn.pc_inc +
532 (insn.mm_i_format.simmediate << 1);
533 else
534 *contpc = regs->cp0_epc +
535 dec_insn.pc_inc +
536 dec_insn.next_pc_inc;
537 return 1;
102cedc3
LY		 538 case mm_bgtz_op:
539 if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
540 *contpc = regs->cp0_epc +
541 dec_insn.pc_inc +
542 (insn.mm_i_format.simmediate << 1);
543 else
544 *contpc = regs->cp0_epc +
545 dec_insn.pc_inc +
546 dec_insn.next_pc_inc;
547 return 1;
102cedc3
LY		 548 case mm_bc2f_op:
549 case mm_bc1f_op:
550 bc_false = 1;
551 /* Fall through */
552 case mm_bc2t_op:
553 case mm_bc1t_op:
554 preempt_disable();
555 if (is_fpu_owner())
556 asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
557 else
558 fcr31 = current->thread.fpu.fcr31;
559 preempt_enable();
560
561 if (bc_false)
562 fcr31 = ~fcr31;
563
564 bit = (insn.mm_i_format.rs >> 2);
565 bit += (bit != 0);
566 bit += 23;
567 if (fcr31 & (1 << bit))
568 *contpc = regs->cp0_epc +
569 dec_insn.pc_inc +
570 (insn.mm_i_format.simmediate << 1);
571 else
572 *contpc = regs->cp0_epc +
573 dec_insn.pc_inc + dec_insn.next_pc_inc;
574 return 1;
102cedc3
LY		 575 }
576 break;
577 case mm_pool16c_op:
578 switch (insn.mm_i_format.rt) {
579 case mm_jalr16_op:
580 case mm_jalrs16_op:
581 regs->regs[31] = regs->cp0_epc +
582 dec_insn.pc_inc + dec_insn.next_pc_inc;
583 /* Fall through */
584 case mm_jr16_op:
585 *contpc = regs->regs[insn.mm_i_format.rs];
586 return 1;
102cedc3
LY		 587 }
588 break;
589 case mm_beqz16_op:
590 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0)
591 *contpc = regs->cp0_epc +
592 dec_insn.pc_inc +
593 (insn.mm_b1_format.simmediate << 1);
594 else
595 *contpc = regs->cp0_epc +
596 dec_insn.pc_inc + dec_insn.next_pc_inc;
597 return 1;
102cedc3
LY		 598 case mm_bnez16_op:
599 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0)
600 *contpc = regs->cp0_epc +
601 dec_insn.pc_inc +
602 (insn.mm_b1_format.simmediate << 1);
603 else
604 *contpc = regs->cp0_epc +
605 dec_insn.pc_inc + dec_insn.next_pc_inc;
606 return 1;
102cedc3
LY		 607 case mm_b16_op:
608 *contpc = regs->cp0_epc + dec_insn.pc_inc +
609 (insn.mm_b0_format.simmediate << 1);
610 return 1;
102cedc3
LY		 611 case mm_beq32_op:
612 if (regs->regs[insn.mm_i_format.rs] ==
613 regs->regs[insn.mm_i_format.rt])
614 *contpc = regs->cp0_epc +
615 dec_insn.pc_inc +
616 (insn.mm_i_format.simmediate << 1);
617 else
618 *contpc = regs->cp0_epc +
619 dec_insn.pc_inc +
620 dec_insn.next_pc_inc;
621 return 1;
102cedc3
LY		 622 case mm_bne32_op:
623 if (regs->regs[insn.mm_i_format.rs] !=
624 regs->regs[insn.mm_i_format.rt])
625 *contpc = regs->cp0_epc +
626 dec_insn.pc_inc +
627 (insn.mm_i_format.simmediate << 1);
628 else
629 *contpc = regs->cp0_epc +
630 dec_insn.pc_inc + dec_insn.next_pc_inc;
631 return 1;
102cedc3
LY		 632 case mm_jalx32_op:
633 regs->regs[31] = regs->cp0_epc +
634 dec_insn.pc_inc + dec_insn.next_pc_inc;
635 *contpc = regs->cp0_epc + dec_insn.pc_inc;
636 *contpc >>= 28;
637 *contpc <<= 28;
638 *contpc |= (insn.j_format.target << 2);
639 return 1;
102cedc3
LY		 640 case mm_jals32_op:
641 case mm_jal32_op:
642 regs->regs[31] = regs->cp0_epc +
643 dec_insn.pc_inc + dec_insn.next_pc_inc;
644 /* Fall through */
645 case mm_j32_op:
646 *contpc = regs->cp0_epc + dec_insn.pc_inc;
647 *contpc >>= 27;
648 *contpc <<= 27;
649 *contpc |= (insn.j_format.target << 1);
650 set_isa16_mode(*contpc);
651 return 1;
102cedc3
LY		 652 }
653 return 0;
654}
1da177e4
LT		 655
656/*
657 * Redundant with logic already in kernel/branch.c,
658 * embedded in compute_return_epc. At some point,
659 * a single subroutine should be used across both
660 * modules.
661 */
102cedc3
LY		 662static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
663 unsigned long *contpc)
1da177e4 664{
102cedc3
LY		 665 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
666 unsigned int fcr31;
667 unsigned int bit = 0;
668
669 switch (insn.i_format.opcode) {
1da177e4 670 case spec_op:
102cedc3 671 switch (insn.r_format.func) {
1da177e4 672 case jalr_op:
102cedc3
LY		 673 regs->regs[insn.r_format.rd] =
674 regs->cp0_epc + dec_insn.pc_inc +
675 dec_insn.next_pc_inc;
676 /* Fall through */
1da177e4 677 case jr_op:
102cedc3 678 *contpc = regs->regs[insn.r_format.rs];
1da177e4
LT		 679 return 1;
680 }
681 break;
1da177e4 682 case bcond_op:
102cedc3
LY		 683 switch (insn.i_format.rt) {
684 case bltzal_op:
685 case bltzall_op:
686 regs->regs[31] = regs->cp0_epc +
687 dec_insn.pc_inc +
688 dec_insn.next_pc_inc;
689 /* Fall through */
1da177e4 690 case bltz_op:
1da177e4 691 case bltzl_op:
102cedc3
LY		 692 if ((long)regs->regs[insn.i_format.rs] < 0)
693 *contpc = regs->cp0_epc +
694 dec_insn.pc_inc +
695 (insn.i_format.simmediate << 2);
696 else
697 *contpc = regs->cp0_epc +
698 dec_insn.pc_inc +
699 dec_insn.next_pc_inc;
700 return 1;
1da177e4 701 case bgezal_op:
1da177e4 702 case bgezall_op:
102cedc3
LY		 703 regs->regs[31] = regs->cp0_epc +
704 dec_insn.pc_inc +
705 dec_insn.next_pc_inc;
706 /* Fall through */
707 case bgez_op:
708 case bgezl_op:
709 if ((long)regs->regs[insn.i_format.rs] >= 0)
710 *contpc = regs->cp0_epc +
711 dec_insn.pc_inc +
712 (insn.i_format.simmediate << 2);
713 else
714 *contpc = regs->cp0_epc +
715 dec_insn.pc_inc +
716 dec_insn.next_pc_inc;
1da177e4
LT		 717 return 1;
718 }
719 break;
1da177e4 720 case jalx_op:
102cedc3
LY		 721 set_isa16_mode(bit);
722 case jal_op:
723 regs->regs[31] = regs->cp0_epc +
724 dec_insn.pc_inc +
725 dec_insn.next_pc_inc;
726 /* Fall through */
727 case j_op:
728 *contpc = regs->cp0_epc + dec_insn.pc_inc;
729 *contpc >>= 28;
730 *contpc <<= 28;
731 *contpc |= (insn.j_format.target << 2);
732 /* Set microMIPS mode bit: XOR for jalx. */
733 *contpc ^= bit;
734 return 1;
1da177e4 735 case beq_op:
1da177e4 736 case beql_op:
102cedc3
LY		 737 if (regs->regs[insn.i_format.rs] ==
738 regs->regs[insn.i_format.rt])
739 *contpc = regs->cp0_epc +
740 dec_insn.pc_inc +
741 (insn.i_format.simmediate << 2);
742 else
743 *contpc = regs->cp0_epc +
744 dec_insn.pc_inc +
745 dec_insn.next_pc_inc;
746 return 1;
102cedc3 747 case bne_op:
1da177e4 748 case bnel_op:
102cedc3
LY		 749 if (regs->regs[insn.i_format.rs] !=
750 regs->regs[insn.i_format.rt])
751 *contpc = regs->cp0_epc +
752 dec_insn.pc_inc +
753 (insn.i_format.simmediate << 2);
754 else
755 *contpc = regs->cp0_epc +
756 dec_insn.pc_inc +
757 dec_insn.next_pc_inc;
758 return 1;
102cedc3 759 case blez_op:
1da177e4 760 case blezl_op:
102cedc3
LY		 761 if ((long)regs->regs[insn.i_format.rs] <= 0)
762 *contpc = regs->cp0_epc +
763 dec_insn.pc_inc +
764 (insn.i_format.simmediate << 2);
765 else
766 *contpc = regs->cp0_epc +
767 dec_insn.pc_inc +
768 dec_insn.next_pc_inc;
769 return 1;
102cedc3 770 case bgtz_op:
1da177e4 771 case bgtzl_op:
102cedc3
LY		 772 if ((long)regs->regs[insn.i_format.rs] > 0)
773 *contpc = regs->cp0_epc +
774 dec_insn.pc_inc +
775 (insn.i_format.simmediate << 2);
776 else
777 *contpc = regs->cp0_epc +
778 dec_insn.pc_inc +
779 dec_insn.next_pc_inc;
1da177e4 780 return 1;
c26d4219
DD		 781#ifdef CONFIG_CPU_CAVIUM_OCTEON
782 case lwc2_op: /* This is bbit0 on Octeon */
783 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
784 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
785 else
786 *contpc = regs->cp0_epc + 8;
787 return 1;
788 case ldc2_op: /* This is bbit032 on Octeon */
789 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
790 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
791 else
792 *contpc = regs->cp0_epc + 8;
793 return 1;
794 case swc2_op: /* This is bbit1 on Octeon */
795 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
796 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
797 else
798 *contpc = regs->cp0_epc + 8;
799 return 1;
800 case sdc2_op: /* This is bbit132 on Octeon */
801 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
802 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
803 else
804 *contpc = regs->cp0_epc + 8;
805 return 1;
806#endif
1da177e4
LT		 807 case cop0_op:
808 case cop1_op:
809 case cop2_op:
810 case cop1x_op:
102cedc3
LY		 811 if (insn.i_format.rs == bc_op) {
812 preempt_disable();
813 if (is_fpu_owner())
814 asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
815 else
816 fcr31 = current->thread.fpu.fcr31;
817 preempt_enable();
818
819 bit = (insn.i_format.rt >> 2);
820 bit += (bit != 0);
821 bit += 23;
822 switch (insn.i_format.rt & 3) {
823 case 0: /* bc1f */
824 case 2: /* bc1fl */
825 if (~fcr31 & (1 << bit))
826 *contpc = regs->cp0_epc +
827 dec_insn.pc_inc +
828 (insn.i_format.simmediate << 2);
829 else
830 *contpc = regs->cp0_epc +
831 dec_insn.pc_inc +
832 dec_insn.next_pc_inc;
833 return 1;
102cedc3
LY		 834 case 1: /* bc1t */
835 case 3: /* bc1tl */
836 if (fcr31 & (1 << bit))
837 *contpc = regs->cp0_epc +
838 dec_insn.pc_inc +
839 (insn.i_format.simmediate << 2);
840 else
841 *contpc = regs->cp0_epc +
842 dec_insn.pc_inc +
843 dec_insn.next_pc_inc;
844 return 1;
102cedc3
LY		 845 }
846 }
1da177e4
LT		 847 break;
848 }
1da177e4
LT		 849 return 0;
850}
851
852/*
853 * In the Linux kernel, we support selection of FPR format on the
70342287 854 * basis of the Status.FR bit. If an FPU is not present, the FR bit
da0bac33 855 * is hardwired to zero, which would imply a 32-bit FPU even for
51d943f0
RB		 856 * 64-bit CPUs so we rather look at TIF_32BIT_REGS.
857 * FPU emu is slow and bulky and optimizing this function offers fairly
858 * sizeable benefits so we try to be clever and make this function return
859 * a constant whenever possible, that is on 64-bit kernels without O32
860 * compatibility enabled and on 32-bit kernels.
1da177e4 861 */
da0bac33
DD		 862static inline int cop1_64bit(struct pt_regs *xcp)
863{
51d943f0
RB		 864#if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32)
865 return 1;
866#elif defined(CONFIG_64BIT) && defined(CONFIG_MIPS32_O32)
da0bac33 867 return !test_thread_flag(TIF_32BIT_REGS);
1da177e4 868#else
da0bac33 869 return 0;
1da177e4 870#endif
da0bac33
DD		 871}
872
873#define SIFROMREG(si, x) ((si) = cop1_64bit(xcp) || !(x & 1) ? \
874 (int)ctx->fpr[x] : (int)(ctx->fpr[x & ~1] >> 32))
1da177e4 875
da0bac33
DD		 876#define SITOREG(si, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = \
877 cop1_64bit(xcp) || !(x & 1) ? \
1da177e4
LT		 878 ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \
879 ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32)
880
1ac94400
LY		 881#define SIFROMHREG(si, x) ((si) = (int)(ctx->fpr[x] >> 32))
882#define SITOHREG(si, x) (ctx->fpr[x] = \
883 ctx->fpr[x] << 32 >> 32 | (u64)(si) << 32)
884
da0bac33
DD		 885#define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)])
886#define DITOREG(di, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di))
1da177e4 887
21a151d8
RB		 888#define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
889#define SPTOREG(sp, x) SITOREG((sp).bits, x)
890#define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
891#define DPTOREG(dp, x) DITOREG((dp).bits, x)
1da177e4
LT		 892
893/*
894 * Emulate the single floating point instruction pointed at by EPC.
895 * Two instructions if the instruction is in a branch delay slot.
896 */
897
515b029d 898static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
102cedc3 899 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
1da177e4
LT		 900{
901 mips_instruction ir;
102cedc3 902 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
1da177e4 903 unsigned int cond;
102cedc3 904 int pc_inc;
1da177e4
LT		 905
906 /* XXX NEC Vr54xx bug workaround */
102cedc3
LY		 907 if (xcp->cp0_cause & CAUSEF_BD) {
908 if (dec_insn.micro_mips_mode) {
909 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
910 xcp->cp0_cause &= ~CAUSEF_BD;
911 } else {
912 if (!isBranchInstr(xcp, dec_insn, &contpc))
913 xcp->cp0_cause &= ~CAUSEF_BD;
914 }
915 }
1da177e4
LT		 916
917 if (xcp->cp0_cause & CAUSEF_BD) {
918 /*
919 * The instruction to be emulated is in a branch delay slot
70342287 920 * which means that we have to emulate the branch instruction
1da177e4
LT		 921 * BEFORE we do the cop1 instruction.
922 *
923 * This branch could be a COP1 branch, but in that case we
924 * would have had a trap for that instruction, and would not
925 * come through this route.
926 *
927 * Linux MIPS branch emulator operates on context, updating the
928 * cp0_epc.
929 */
102cedc3
LY		 930 ir = dec_insn.next_insn; /* process delay slot instr */
931 pc_inc = dec_insn.next_pc_inc;
932 } else {
933 ir = dec_insn.insn; /* process current instr */
934 pc_inc = dec_insn.pc_inc;
935 }
1da177e4 936
102cedc3
LY		 937 /*
938 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
939 * instructions, we want to convert microMIPS FPU instructions
940 * into MIPS32 instructions so that we could reuse all of the
941 * FPU emulation code.
942 *
943 * NOTE: We cannot do this for branch instructions since they
944 * are not a subset. Example: Cannot emulate a 16-bit
945 * aligned target address with a MIPS32 instruction.
946 */
947 if (dec_insn.micro_mips_mode) {
948 /*
949 * If next instruction is a 16-bit instruction, then it
950 * it cannot be a FPU instruction. This could happen
951 * since we can be called for non-FPU instructions.
952 */
953 if ((pc_inc == 2) ||
954 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
955 == SIGILL))
1da177e4 956 return SIGILL;
1da177e4
LT		 957 }
958
959 emul:
a8b0ca17 960 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
b6ee75ed 961 MIPS_FPU_EMU_INC_STATS(emulated);
1da177e4 962 switch (MIPSInst_OPCODE(ir)) {
1da177e4 963 case ldc1_op:{
3fccc015 964 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1da177e4
LT		 965 MIPSInst_SIMM(ir));
966 u64 val;
967
b6ee75ed 968 MIPS_FPU_EMU_INC_STATS(loads);
515b029d
DD		 969
970 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
b6ee75ed 971 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 972 *fault_addr = va;
1da177e4
LT		 973 return SIGBUS;
974 }
515b029d
DD		 975 if (__get_user(val, va)) {
976 MIPS_FPU_EMU_INC_STATS(errors);
977 *fault_addr = va;
978 return SIGSEGV;
979 }
1da177e4
LT		 980 DITOREG(val, MIPSInst_RT(ir));
981 break;
982 }
983
984 case sdc1_op:{
3fccc015 985 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1da177e4
LT		 986 MIPSInst_SIMM(ir));
987 u64 val;
988
b6ee75ed 989 MIPS_FPU_EMU_INC_STATS(stores);
1da177e4 990 DIFROMREG(val, MIPSInst_RT(ir));
515b029d 991 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
b6ee75ed 992 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 993 *fault_addr = va;
1da177e4
LT		 994 return SIGBUS;
995 }
515b029d
DD		 996 if (__put_user(val, va)) {
997 MIPS_FPU_EMU_INC_STATS(errors);
998 *fault_addr = va;
999 return SIGSEGV;
1000 }
1da177e4
LT		 1001 break;
1002 }
1da177e4
LT		 1003
1004 case lwc1_op:{
3fccc015 1005 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1da177e4
LT		 1006 MIPSInst_SIMM(ir));
1007 u32 val;
1008
b6ee75ed 1009 MIPS_FPU_EMU_INC_STATS(loads);
515b029d 1010 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
b6ee75ed 1011 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1012 *fault_addr = va;
1da177e4
LT		 1013 return SIGBUS;
1014 }
515b029d
DD		 1015 if (__get_user(val, va)) {
1016 MIPS_FPU_EMU_INC_STATS(errors);
1017 *fault_addr = va;
1018 return SIGSEGV;
1019 }
1da177e4
LT		 1020 SITOREG(val, MIPSInst_RT(ir));
1021 break;
1022 }
1023
1024 case swc1_op:{
3fccc015 1025 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1da177e4
LT		 1026 MIPSInst_SIMM(ir));
1027 u32 val;
1028
b6ee75ed 1029 MIPS_FPU_EMU_INC_STATS(stores);
1da177e4 1030 SIFROMREG(val, MIPSInst_RT(ir));
515b029d 1031 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
b6ee75ed 1032 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1033 *fault_addr = va;
1da177e4
LT		 1034 return SIGBUS;
1035 }
515b029d
DD		 1036 if (__put_user(val, va)) {
1037 MIPS_FPU_EMU_INC_STATS(errors);
1038 *fault_addr = va;
1039 return SIGSEGV;
1040 }
1da177e4
LT		 1041 break;
1042 }
1043
1044 case cop1_op:
1045 switch (MIPSInst_RS(ir)) {
1046
4b724efd 1047#if defined(__mips64)
1da177e4
LT		 1048 case dmfc_op:
1049 /* copregister fs -> gpr[rt] */
1050 if (MIPSInst_RT(ir) != 0) {
1051 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1052 MIPSInst_RD(ir));
1053 }
1054 break;
1055
1056 case dmtc_op:
1057 /* copregister fs <- rt */
1058 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1059 break;
1060#endif
1061
1ac94400
LY		 1062 case mfhc_op:
1063 if (!cpu_has_mips_r2)
1064 goto sigill;
1065
1066 /* copregister rd -> gpr[rt] */
1067 if (MIPSInst_RT(ir) != 0) {
1068 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1069 MIPSInst_RD(ir));
1070 }
1071 break;
1072
1073 case mthc_op:
1074 if (!cpu_has_mips_r2)
1075 goto sigill;
1076
1077 /* copregister rd <- gpr[rt] */
1078 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1079 break;
1080
1da177e4
LT		 1081 case mfc_op:
1082 /* copregister rd -> gpr[rt] */
1da177e4
LT		 1083 if (MIPSInst_RT(ir) != 0) {
1084 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1085 MIPSInst_RD(ir));
1086 }
1087 break;
1088
1089 case mtc_op:
1090 /* copregister rd <- rt */
1da177e4
LT		 1091 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1092 break;
1093
1094 case cfc_op:{
1095 /* cop control register rd -> gpr[rt] */
1096 u32 value;
1097
1da177e4
LT		 1098 if (MIPSInst_RD(ir) == FPCREG_CSR) {
1099 value = ctx->fcr31;
3f135530
SM		 1100 value = (value & ~FPU_CSR_RM) |
1101 mips_rm[modeindex(value)];
1da177e4
LT		 1102#ifdef CSRTRACE
1103 printk("%p gpr[%d]<-csr=%08x\n",
333d1f67 1104 (void *) (xcp->cp0_epc),
1da177e4
LT		 1105 MIPSInst_RT(ir), value);
1106#endif
1107 }
1108 else if (MIPSInst_RD(ir) == FPCREG_RID)
1109 value = 0;
1110 else
1111 value = 0;
1112 if (MIPSInst_RT(ir))
1113 xcp->regs[MIPSInst_RT(ir)] = value;
1114 break;
1115 }
1116
1117 case ctc_op:{
1118 /* copregister rd <- rt */
1119 u32 value;
1120
1121 if (MIPSInst_RT(ir) == 0)
1122 value = 0;
1123 else
1124 value = xcp->regs[MIPSInst_RT(ir)];
1125
1126 /* we only have one writable control reg
1127 */
1128 if (MIPSInst_RD(ir) == FPCREG_CSR) {
1129#ifdef CSRTRACE
1130 printk("%p gpr[%d]->csr=%08x\n",
333d1f67 1131 (void *) (xcp->cp0_epc),
1da177e4
LT		 1132 MIPSInst_RT(ir), value);
1133#endif
95e8f634
SM		 1134
1135 /*
1136 * Don't write reserved bits,
1137 * and convert to ieee library modes
1138 */
1139 ctx->fcr31 = (value &
1140 ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
1141 ieee_rm[modeindex(value)];
1da177e4
LT		 1142 }
1143 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1144 return SIGFPE;
1145 }
1146 break;
1147 }
1148
1149 case bc_op:{
1150 int likely = 0;
1151
1152 if (xcp->cp0_cause & CAUSEF_BD)
1153 return SIGILL;
1154
1155#if __mips >= 4
1156 cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2];
1157#else
1158 cond = ctx->fcr31 & FPU_CSR_COND;
1159#endif
1160 switch (MIPSInst_RT(ir) & 3) {
1161 case bcfl_op:
1162 likely = 1;
1163 case bcf_op:
1164 cond = !cond;
1165 break;
1166 case bctl_op:
1167 likely = 1;
1168 case bct_op:
1169 break;
1170 default:
1171 /* thats an illegal instruction */
1172 return SIGILL;
1173 }
1174
1175 xcp->cp0_cause |= CAUSEF_BD;
1176 if (cond) {
1177 /* branch taken: emulate dslot
1178 * instruction
1179 */
102cedc3
LY		 1180 xcp->cp0_epc += dec_insn.pc_inc;
1181
1182 contpc = MIPSInst_SIMM(ir);
1183 ir = dec_insn.next_insn;
1184 if (dec_insn.micro_mips_mode) {
1185 contpc = (xcp->cp0_epc + (contpc << 1));
1186
1187 /* If 16-bit instruction, not FPU. */
1188 if ((dec_insn.next_pc_inc == 2) ||
1189 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1190
1191 /*
1192 * Since this instruction will
1193 * be put on the stack with
1194 * 32-bit words, get around
1195 * this problem by putting a
1196 * NOP16 as the second one.
1197 */
1198 if (dec_insn.next_pc_inc == 2)
1199 ir = (ir & (~0xffff)) | MM_NOP16;
1200
1201 /*
1202 * Single step the non-CP1
1203 * instruction in the dslot.
1204 */
1205 return mips_dsemul(xcp, ir, contpc);
1206 }
1207 } else
1208 contpc = (xcp->cp0_epc + (contpc << 2));
1da177e4
LT		 1209
1210 switch (MIPSInst_OPCODE(ir)) {
1211 case lwc1_op:
1212 case swc1_op:
4b724efd 1213#if (__mips >= 2 || defined(__mips64))
1da177e4
LT		 1214 case ldc1_op:
1215 case sdc1_op:
1216#endif
1217 case cop1_op:
1218#if __mips >= 4 && __mips != 32
1219 case cop1x_op:
1220#endif
1221 /* its one of ours */
1222 goto emul;
1223#if __mips >= 4
1224 case spec_op:
1225 if (MIPSInst_FUNC(ir) == movc_op)
1226 goto emul;
1227 break;
1228#endif
1229 }
1230
1231 /*
1232 * Single step the non-cp1
1233 * instruction in the dslot
1234 */
e70dfc10 1235 return mips_dsemul(xcp, ir, contpc);
1da177e4
LT		 1236 }
1237 else {
1238 /* branch not taken */
1239 if (likely) {
1240 /*
1241 * branch likely nullifies
1242 * dslot if not taken
1243 */
102cedc3
LY		 1244 xcp->cp0_epc += dec_insn.pc_inc;
1245 contpc += dec_insn.pc_inc;
1da177e4
LT		 1246 /*
1247 * else continue & execute
1248 * dslot as normal insn
1249 */
1250 }
1251 }
1252 break;
1253 }
1254
1255 default:
1256 if (!(MIPSInst_RS(ir) & 0x10))
1257 return SIGILL;
1258 {
1259 int sig;
1260
1261 /* a real fpu computation instruction */
1262 if ((sig = fpu_emu(xcp, ctx, ir)))
1263 return sig;
1264 }
1265 }
1266 break;
1267
1268#if __mips >= 4 && __mips != 32
1269 case cop1x_op:{
515b029d
DD		 1270 int sig = fpux_emu(xcp, ctx, ir, fault_addr);
1271 if (sig)
1da177e4
LT		 1272 return sig;
1273 break;
1274 }
1275#endif
1276
1277#if __mips >= 4
1278 case spec_op:
1279 if (MIPSInst_FUNC(ir) != movc_op)
1280 return SIGILL;
1281 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1282 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1283 xcp->regs[MIPSInst_RD(ir)] =
1284 xcp->regs[MIPSInst_RS(ir)];
1285 break;
1286#endif
1287
1288 default:
1ac94400 1289sigill:
1da177e4
LT		 1290 return SIGILL;
1291 }
1292
1293 /* we did it !! */
e70dfc10 1294 xcp->cp0_epc = contpc;
1da177e4 1295 xcp->cp0_cause &= ~CAUSEF_BD;
333d1f67 1296
1da177e4
LT		 1297 return 0;
1298}
1299
1300/*
1301 * Conversion table from MIPS compare ops 48-63
1302 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1303 */
1304static const unsigned char cmptab[8] = {
1305 0, /* cmp_0 (sig) cmp_sf */
1306 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1307 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1308 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1309 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1310 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1311 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1312 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1313};
1314
1315
1316#if __mips >= 4 && __mips != 32
1317
1318/*
1319 * Additional MIPS4 instructions
1320 */
1321
1322#define DEF3OP(name, p, f1, f2, f3) \
49a89efb 1323static ieee754##p fpemu_##p##_##name(ieee754##p r, ieee754##p s, \
1da177e4
LT		 1324 ieee754##p t) \
1325{ \
cd21dfcf 1326 struct _ieee754_csr ieee754_csr_save; \
49a89efb 1327 s = f1(s, t); \
1da177e4 1328 ieee754_csr_save = ieee754_csr; \
49a89efb 1329 s = f2(s, r); \
1da177e4
LT		 1330 ieee754_csr_save.cx |= ieee754_csr.cx; \
1331 ieee754_csr_save.sx |= ieee754_csr.sx; \
49a89efb 1332 s = f3(s); \
1da177e4
LT		 1333 ieee754_csr.cx |= ieee754_csr_save.cx; \
1334 ieee754_csr.sx |= ieee754_csr_save.sx; \
1335 return s; \
1336}
1337
1338static ieee754dp fpemu_dp_recip(ieee754dp d)
1339{
1340 return ieee754dp_div(ieee754dp_one(0), d);
1341}
1342
1343static ieee754dp fpemu_dp_rsqrt(ieee754dp d)
1344{
1345 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1346}
1347
1348static ieee754sp fpemu_sp_recip(ieee754sp s)
1349{
1350 return ieee754sp_div(ieee754sp_one(0), s);
1351}
1352
1353static ieee754sp fpemu_sp_rsqrt(ieee754sp s)
1354{
1355 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1356}
1357
21a151d8
RB		 1358DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1359DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1da177e4
LT		 1360DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1361DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
21a151d8
RB		 1362DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1363DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1da177e4
LT		 1364DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1365DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1366
eae89076 1367static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
515b029d 1368 mips_instruction ir, void *__user *fault_addr)
1da177e4
LT		 1369{
1370 unsigned rcsr = 0; /* resulting csr */
1371
b6ee75ed 1372 MIPS_FPU_EMU_INC_STATS(cp1xops);
1da177e4
LT		 1373
1374 switch (MIPSInst_FMA_FFMT(ir)) {
1375 case s_fmt:{ /* 0 */
1376
1377 ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp);
1378 ieee754sp fd, fr, fs, ft;
3fccc015 1379 u32 __user *va;
1da177e4
LT		 1380 u32 val;
1381
1382 switch (MIPSInst_FUNC(ir)) {
1383 case lwxc1_op:
3fccc015 1384 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1da177e4
LT		 1385 xcp->regs[MIPSInst_FT(ir)]);
1386
b6ee75ed 1387 MIPS_FPU_EMU_INC_STATS(loads);
515b029d 1388 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
b6ee75ed 1389 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1390 *fault_addr = va;
1da177e4
LT		 1391 return SIGBUS;
1392 }
515b029d
DD		 1393 if (__get_user(val, va)) {
1394 MIPS_FPU_EMU_INC_STATS(errors);
1395 *fault_addr = va;
1396 return SIGSEGV;
1397 }
1da177e4
LT		 1398 SITOREG(val, MIPSInst_FD(ir));
1399 break;
1400
1401 case swxc1_op:
3fccc015 1402 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1da177e4
LT		 1403 xcp->regs[MIPSInst_FT(ir)]);
1404
b6ee75ed 1405 MIPS_FPU_EMU_INC_STATS(stores);
1da177e4
LT		 1406
1407 SIFROMREG(val, MIPSInst_FS(ir));
515b029d 1408 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
b6ee75ed 1409 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1410 *fault_addr = va;
1da177e4
LT		 1411 return SIGBUS;
1412 }
515b029d
DD		 1413 if (put_user(val, va)) {
1414 MIPS_FPU_EMU_INC_STATS(errors);
1415 *fault_addr = va;
1416 return SIGSEGV;
1417 }
1da177e4
LT		 1418 break;
1419
1420 case madd_s_op:
1421 handler = fpemu_sp_madd;
1422 goto scoptop;
1423 case msub_s_op:
1424 handler = fpemu_sp_msub;
1425 goto scoptop;
1426 case nmadd_s_op:
1427 handler = fpemu_sp_nmadd;
1428 goto scoptop;
1429 case nmsub_s_op:
1430 handler = fpemu_sp_nmsub;
1431 goto scoptop;
1432
1433 scoptop:
1434 SPFROMREG(fr, MIPSInst_FR(ir));
1435 SPFROMREG(fs, MIPSInst_FS(ir));
1436 SPFROMREG(ft, MIPSInst_FT(ir));
1437 fd = (*handler) (fr, fs, ft);
1438 SPTOREG(fd, MIPSInst_FD(ir));
1439
1440 copcsr:
1441 if (ieee754_cxtest(IEEE754_INEXACT))
1442 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1443 if (ieee754_cxtest(IEEE754_UNDERFLOW))
1444 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1445 if (ieee754_cxtest(IEEE754_OVERFLOW))
1446 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1447 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
1448 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1449
1450 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1da177e4
LT		 1451 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1452 /*printk ("SIGFPE: fpu csr = %08x\n",
1453 ctx->fcr31); */
1454 return SIGFPE;
1455 }
1456
1457 break;
1458
1459 default:
1460 return SIGILL;
1461 }
1462 break;
1463 }
1464
1da177e4
LT		 1465 case d_fmt:{ /* 1 */
1466 ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp);
1467 ieee754dp fd, fr, fs, ft;
3fccc015 1468 u64 __user *va;
1da177e4
LT		 1469 u64 val;
1470
1471 switch (MIPSInst_FUNC(ir)) {
1472 case ldxc1_op:
3fccc015 1473 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1da177e4
LT		 1474 xcp->regs[MIPSInst_FT(ir)]);
1475
b6ee75ed 1476 MIPS_FPU_EMU_INC_STATS(loads);
515b029d 1477 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
b6ee75ed 1478 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1479 *fault_addr = va;
1da177e4
LT		 1480 return SIGBUS;
1481 }
515b029d
DD		 1482 if (__get_user(val, va)) {
1483 MIPS_FPU_EMU_INC_STATS(errors);
1484 *fault_addr = va;
1485 return SIGSEGV;
1486 }
1da177e4
LT		 1487 DITOREG(val, MIPSInst_FD(ir));
1488 break;
1489
1490 case sdxc1_op:
3fccc015 1491 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1da177e4
LT		 1492 xcp->regs[MIPSInst_FT(ir)]);
1493
b6ee75ed 1494 MIPS_FPU_EMU_INC_STATS(stores);
1da177e4 1495 DIFROMREG(val, MIPSInst_FS(ir));
515b029d 1496 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
b6ee75ed 1497 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1498 *fault_addr = va;
1da177e4
LT		 1499 return SIGBUS;
1500 }
515b029d
DD		 1501 if (__put_user(val, va)) {
1502 MIPS_FPU_EMU_INC_STATS(errors);
1503 *fault_addr = va;
1504 return SIGSEGV;
1505 }
1da177e4
LT		 1506 break;
1507
1508 case madd_d_op:
1509 handler = fpemu_dp_madd;
1510 goto dcoptop;
1511 case msub_d_op:
1512 handler = fpemu_dp_msub;
1513 goto dcoptop;
1514 case nmadd_d_op:
1515 handler = fpemu_dp_nmadd;
1516 goto dcoptop;
1517 case nmsub_d_op:
1518 handler = fpemu_dp_nmsub;
1519 goto dcoptop;
1520
1521 dcoptop:
1522 DPFROMREG(fr, MIPSInst_FR(ir));
1523 DPFROMREG(fs, MIPSInst_FS(ir));
1524 DPFROMREG(ft, MIPSInst_FT(ir));
1525 fd = (*handler) (fr, fs, ft);
1526 DPTOREG(fd, MIPSInst_FD(ir));
1527 goto copcsr;
1528
1529 default:
1530 return SIGILL;
1531 }
1532 break;
1533 }
1da177e4
LT		 1534
1535 case 0x7: /* 7 */
1536 if (MIPSInst_FUNC(ir) != pfetch_op) {
1537 return SIGILL;
1538 }
1539 /* ignore prefx operation */
1540 break;
1541
1542 default:
1543 return SIGILL;
1544 }
1545
1546 return 0;
1547}
1548#endif
1549
1550
1551
1552/*
1553 * Emulate a single COP1 arithmetic instruction.
1554 */
eae89076 1555static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1da177e4
LT		 1556 mips_instruction ir)
1557{
1558 int rfmt; /* resulting format */
1559 unsigned rcsr = 0; /* resulting csr */
1560 unsigned cond;
1561 union {
1562 ieee754dp d;
1563 ieee754sp s;
1564 int w;
766160c2 1565#ifdef __mips64
1da177e4
LT		 1566 s64 l;
1567#endif
1568 } rv; /* resulting value */
1569
b6ee75ed 1570 MIPS_FPU_EMU_INC_STATS(cp1ops);
1da177e4
LT		 1571 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1572 case s_fmt:{ /* 0 */
1573 union {
1574 ieee754sp(*b) (ieee754sp, ieee754sp);
1575 ieee754sp(*u) (ieee754sp);
1576 } handler;
1577
1578 switch (MIPSInst_FUNC(ir)) {
1579 /* binary ops */
1580 case fadd_op:
1581 handler.b = ieee754sp_add;
1582 goto scopbop;
1583 case fsub_op:
1584 handler.b = ieee754sp_sub;
1585 goto scopbop;
1586 case fmul_op:
1587 handler.b = ieee754sp_mul;
1588 goto scopbop;
1589 case fdiv_op:
1590 handler.b = ieee754sp_div;
1591 goto scopbop;
1592
1593 /* unary ops */
587cb98f 1594#if __mips >= 2 || defined(__mips64)
1da177e4
LT		 1595 case fsqrt_op:
1596 handler.u = ieee754sp_sqrt;
1597 goto scopuop;
1598#endif
1599#if __mips >= 4 && __mips != 32
1600 case frsqrt_op:
1601 handler.u = fpemu_sp_rsqrt;
1602 goto scopuop;
1603 case frecip_op:
1604 handler.u = fpemu_sp_recip;
1605 goto scopuop;
1606#endif
1607#if __mips >= 4
1608 case fmovc_op:
1609 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1610 if (((ctx->fcr31 & cond) != 0) !=
1611 ((MIPSInst_FT(ir) & 1) != 0))
1612 return 0;
1613 SPFROMREG(rv.s, MIPSInst_FS(ir));
1614 break;
1615 case fmovz_op:
1616 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1617 return 0;
1618 SPFROMREG(rv.s, MIPSInst_FS(ir));
1619 break;
1620 case fmovn_op:
1621 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1622 return 0;
1623 SPFROMREG(rv.s, MIPSInst_FS(ir));
1624 break;
1625#endif
1626 case fabs_op:
1627 handler.u = ieee754sp_abs;
1628 goto scopuop;
1629 case fneg_op:
1630 handler.u = ieee754sp_neg;
1631 goto scopuop;
1632 case fmov_op:
1633 /* an easy one */
1634 SPFROMREG(rv.s, MIPSInst_FS(ir));
1635 goto copcsr;
1636
1637 /* binary op on handler */
1638 scopbop:
1639 {
1640 ieee754sp fs, ft;
1641
1642 SPFROMREG(fs, MIPSInst_FS(ir));
1643 SPFROMREG(ft, MIPSInst_FT(ir));
1644
1645 rv.s = (*handler.b) (fs, ft);
1646 goto copcsr;
1647 }
1648 scopuop:
1649 {
1650 ieee754sp fs;
1651
1652 SPFROMREG(fs, MIPSInst_FS(ir));
1653 rv.s = (*handler.u) (fs);
1654 goto copcsr;
1655 }
1656 copcsr:
1657 if (ieee754_cxtest(IEEE754_INEXACT))
1658 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1659 if (ieee754_cxtest(IEEE754_UNDERFLOW))
1660 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1661 if (ieee754_cxtest(IEEE754_OVERFLOW))
1662 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1663 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE))
1664 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1665 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
1666 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1667 break;
1668
1669 /* unary conv ops */
1670 case fcvts_op:
1671 return SIGILL; /* not defined */
1672 case fcvtd_op:{
1da177e4
LT		 1673 ieee754sp fs;
1674
1675 SPFROMREG(fs, MIPSInst_FS(ir));
1676 rv.d = ieee754dp_fsp(fs);
1677 rfmt = d_fmt;
1678 goto copcsr;
1679 }
1da177e4
LT		 1680 case fcvtw_op:{
1681 ieee754sp fs;
1682
1683 SPFROMREG(fs, MIPSInst_FS(ir));
1684 rv.w = ieee754sp_tint(fs);
1685 rfmt = w_fmt;
1686 goto copcsr;
1687 }
1688
587cb98f 1689#if __mips >= 2 || defined(__mips64)
1da177e4
LT		 1690 case fround_op:
1691 case ftrunc_op:
1692 case fceil_op:
1693 case ffloor_op:{
1694 unsigned int oldrm = ieee754_csr.rm;
1695 ieee754sp fs;
1696
1697 SPFROMREG(fs, MIPSInst_FS(ir));
3f135530 1698 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1da177e4
LT		 1699 rv.w = ieee754sp_tint(fs);
1700 ieee754_csr.rm = oldrm;
1701 rfmt = w_fmt;
1702 goto copcsr;
1703 }
1704#endif /* __mips >= 2 */
1705
4b724efd 1706#if defined(__mips64)
1da177e4
LT		 1707 case fcvtl_op:{
1708 ieee754sp fs;
1709
1710 SPFROMREG(fs, MIPSInst_FS(ir));
1711 rv.l = ieee754sp_tlong(fs);
1712 rfmt = l_fmt;
1713 goto copcsr;
1714 }
1715
1716 case froundl_op:
1717 case ftruncl_op:
1718 case fceill_op:
1719 case ffloorl_op:{
1720 unsigned int oldrm = ieee754_csr.rm;
1721 ieee754sp fs;
1722
1723 SPFROMREG(fs, MIPSInst_FS(ir));
3f135530 1724 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1da177e4
LT		 1725 rv.l = ieee754sp_tlong(fs);
1726 ieee754_csr.rm = oldrm;
1727 rfmt = l_fmt;
1728 goto copcsr;
1729 }
4b724efd 1730#endif /* defined(__mips64) */
1da177e4
LT		 1731
1732 default:
1733 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1734 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1735 ieee754sp fs, ft;
1736
1737 SPFROMREG(fs, MIPSInst_FS(ir));
1738 SPFROMREG(ft, MIPSInst_FT(ir));
1739 rv.w = ieee754sp_cmp(fs, ft,
1740 cmptab[cmpop & 0x7], cmpop & 0x8);
1741 rfmt = -1;
1742 if ((cmpop & 0x8) && ieee754_cxtest
1743 (IEEE754_INVALID_OPERATION))
1744 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1745 else
1746 goto copcsr;
1747
1748 }
1749 else {
1750 return SIGILL;
1751 }
1752 break;
1753 }
1754 break;
1755 }
1756
1da177e4
LT		 1757 case d_fmt:{
1758 union {
1759 ieee754dp(*b) (ieee754dp, ieee754dp);
1760 ieee754dp(*u) (ieee754dp);
1761 } handler;
1762
1763 switch (MIPSInst_FUNC(ir)) {
1764 /* binary ops */
1765 case fadd_op:
1766 handler.b = ieee754dp_add;
1767 goto dcopbop;
1768 case fsub_op:
1769 handler.b = ieee754dp_sub;
1770 goto dcopbop;
1771 case fmul_op:
1772 handler.b = ieee754dp_mul;
1773 goto dcopbop;
1774 case fdiv_op:
1775 handler.b = ieee754dp_div;
1776 goto dcopbop;
1777
1778 /* unary ops */
587cb98f 1779#if __mips >= 2 || defined(__mips64)
1da177e4
LT		 1780 case fsqrt_op:
1781 handler.u = ieee754dp_sqrt;
1782 goto dcopuop;
1783#endif
1784#if __mips >= 4 && __mips != 32
1785 case frsqrt_op:
1786 handler.u = fpemu_dp_rsqrt;
1787 goto dcopuop;
1788 case frecip_op:
1789 handler.u = fpemu_dp_recip;
1790 goto dcopuop;
1791#endif
1792#if __mips >= 4
1793 case fmovc_op:
1794 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1795 if (((ctx->fcr31 & cond) != 0) !=
1796 ((MIPSInst_FT(ir) & 1) != 0))
1797 return 0;
1798 DPFROMREG(rv.d, MIPSInst_FS(ir));
1799 break;
1800 case fmovz_op:
1801 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1802 return 0;
1803 DPFROMREG(rv.d, MIPSInst_FS(ir));
1804 break;
1805 case fmovn_op:
1806 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1807 return 0;
1808 DPFROMREG(rv.d, MIPSInst_FS(ir));
1809 break;
1810#endif
1811 case fabs_op:
1812 handler.u = ieee754dp_abs;
1813 goto dcopuop;
1814
1815 case fneg_op:
1816 handler.u = ieee754dp_neg;
1817 goto dcopuop;
1818
1819 case fmov_op:
1820 /* an easy one */
1821 DPFROMREG(rv.d, MIPSInst_FS(ir));
1822 goto copcsr;
1823
1824 /* binary op on handler */
1825 dcopbop:{
1826 ieee754dp fs, ft;
1827
1828 DPFROMREG(fs, MIPSInst_FS(ir));
1829 DPFROMREG(ft, MIPSInst_FT(ir));
1830
1831 rv.d = (*handler.b) (fs, ft);
1832 goto copcsr;
1833 }
1834 dcopuop:{
1835 ieee754dp fs;
1836
1837 DPFROMREG(fs, MIPSInst_FS(ir));
1838 rv.d = (*handler.u) (fs);
1839 goto copcsr;
1840 }
1841
1842 /* unary conv ops */
1843 case fcvts_op:{
1844 ieee754dp fs;
1845
1846 DPFROMREG(fs, MIPSInst_FS(ir));
1847 rv.s = ieee754sp_fdp(fs);
1848 rfmt = s_fmt;
1849 goto copcsr;
1850 }
1851 case fcvtd_op:
1852 return SIGILL; /* not defined */
1853
1854 case fcvtw_op:{
1855 ieee754dp fs;
1856
1857 DPFROMREG(fs, MIPSInst_FS(ir));
1858 rv.w = ieee754dp_tint(fs); /* wrong */
1859 rfmt = w_fmt;
1860 goto copcsr;
1861 }
1862
587cb98f 1863#if __mips >= 2 || defined(__mips64)
1da177e4
LT		 1864 case fround_op:
1865 case ftrunc_op:
1866 case fceil_op:
1867 case ffloor_op:{
1868 unsigned int oldrm = ieee754_csr.rm;
1869 ieee754dp fs;
1870
1871 DPFROMREG(fs, MIPSInst_FS(ir));
3f135530 1872 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1da177e4
LT		 1873 rv.w = ieee754dp_tint(fs);
1874 ieee754_csr.rm = oldrm;
1875 rfmt = w_fmt;
1876 goto copcsr;
1877 }
1878#endif
1879
4b724efd 1880#if defined(__mips64)
1da177e4
LT		 1881 case fcvtl_op:{
1882 ieee754dp fs;
1883
1884 DPFROMREG(fs, MIPSInst_FS(ir));
1885 rv.l = ieee754dp_tlong(fs);
1886 rfmt = l_fmt;
1887 goto copcsr;
1888 }
1889
1890 case froundl_op:
1891 case ftruncl_op:
1892 case fceill_op:
1893 case ffloorl_op:{
1894 unsigned int oldrm = ieee754_csr.rm;
1895 ieee754dp fs;
1896
1897 DPFROMREG(fs, MIPSInst_FS(ir));
3f135530 1898 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1da177e4
LT		 1899 rv.l = ieee754dp_tlong(fs);
1900 ieee754_csr.rm = oldrm;
1901 rfmt = l_fmt;
1902 goto copcsr;
1903 }
4b724efd 1904#endif /* __mips >= 3 */
1da177e4
LT		 1905
1906 default:
1907 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1908 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1909 ieee754dp fs, ft;
1910
1911 DPFROMREG(fs, MIPSInst_FS(ir));
1912 DPFROMREG(ft, MIPSInst_FT(ir));
1913 rv.w = ieee754dp_cmp(fs, ft,
1914 cmptab[cmpop & 0x7], cmpop & 0x8);
1915 rfmt = -1;
1916 if ((cmpop & 0x8)
1917 &&
1918 ieee754_cxtest
1919 (IEEE754_INVALID_OPERATION))
1920 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1921 else
1922 goto copcsr;
1923
1924 }
1925 else {
1926 return SIGILL;
1927 }
1928 break;
1929 }
1930 break;
1931 }
1da177e4
LT		 1932
1933 case w_fmt:{
1934 ieee754sp fs;
1935
1936 switch (MIPSInst_FUNC(ir)) {
1937 case fcvts_op:
1938 /* convert word to single precision real */
1939 SPFROMREG(fs, MIPSInst_FS(ir));
1940 rv.s = ieee754sp_fint(fs.bits);
1941 rfmt = s_fmt;
1942 goto copcsr;
1da177e4
LT		 1943 case fcvtd_op:
1944 /* convert word to double precision real */
1945 SPFROMREG(fs, MIPSInst_FS(ir));
1946 rv.d = ieee754dp_fint(fs.bits);
1947 rfmt = d_fmt;
1948 goto copcsr;
1da177e4
LT		 1949 default:
1950 return SIGILL;
1951 }
1952 break;
1953 }
1954
4b724efd 1955#if defined(__mips64)
1da177e4
LT		 1956 case l_fmt:{
1957 switch (MIPSInst_FUNC(ir)) {
1958 case fcvts_op:
1959 /* convert long to single precision real */
1960 rv.s = ieee754sp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1961 rfmt = s_fmt;
1962 goto copcsr;
1963 case fcvtd_op:
1964 /* convert long to double precision real */
1965 rv.d = ieee754dp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1966 rfmt = d_fmt;
1967 goto copcsr;
1968 default:
1969 return SIGILL;
1970 }
1971 break;
1972 }
1973#endif
1974
1975 default:
1976 return SIGILL;
1977 }
1978
1979 /*
1980 * Update the fpu CSR register for this operation.
1981 * If an exception is required, generate a tidy SIGFPE exception,
1982 * without updating the result register.
1983 * Note: cause exception bits do not accumulate, they are rewritten
1984 * for each op; only the flag/sticky bits accumulate.
1985 */
1986 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1987 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1988 /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */
1989 return SIGFPE;
1990 }
1991
1992 /*
1993 * Now we can safely write the result back to the register file.
1994 */
1995 switch (rfmt) {
1996 case -1:{
1997#if __mips >= 4
1998 cond = fpucondbit[MIPSInst_FD(ir) >> 2];
1999#else
2000 cond = FPU_CSR_COND;
2001#endif
2002 if (rv.w)
2003 ctx->fcr31 |= cond;
2004 else
2005 ctx->fcr31 &= ~cond;
2006 break;
2007 }
1da177e4
LT		 2008 case d_fmt:
2009 DPTOREG(rv.d, MIPSInst_FD(ir));
2010 break;
1da177e4
LT		 2011 case s_fmt:
2012 SPTOREG(rv.s, MIPSInst_FD(ir));
2013 break;
2014 case w_fmt:
2015 SITOREG(rv.w, MIPSInst_FD(ir));
2016 break;
4b724efd 2017#if defined(__mips64)
1da177e4
LT		 2018 case l_fmt:
2019 DITOREG(rv.l, MIPSInst_FD(ir));
2020 break;
2021#endif
2022 default:
2023 return SIGILL;
2024 }
2025
2026 return 0;
2027}
2028
e04582b7 2029int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
515b029d 2030 int has_fpu, void *__user *fault_addr)
1da177e4 2031{
333d1f67 2032 unsigned long oldepc, prevepc;
102cedc3
LY		 2033 struct mm_decoded_insn dec_insn;
2034 u16 instr[4];
2035 u16 *instr_ptr;
1da177e4
LT		 2036 int sig = 0;
2037
2038 oldepc = xcp->cp0_epc;
2039 do {
2040 prevepc = xcp->cp0_epc;
2041
102cedc3
LY		 2042 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2043 /*
2044 * Get next 2 microMIPS instructions and convert them
2045 * into 32-bit instructions.
2046 */
2047 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2048 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2049 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2050 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2051 MIPS_FPU_EMU_INC_STATS(errors);
2052 return SIGBUS;
2053 }
2054 instr_ptr = instr;
2055
2056 /* Get first instruction. */
2057 if (mm_insn_16bit(*instr_ptr)) {
2058 /* Duplicate the half-word. */
2059 dec_insn.insn = (*instr_ptr << 16) |
2060 (*instr_ptr);
2061 /* 16-bit instruction. */
2062 dec_insn.pc_inc = 2;
2063 instr_ptr += 1;
2064 } else {
2065 dec_insn.insn = (*instr_ptr << 16) |
2066 *(instr_ptr+1);
2067 /* 32-bit instruction. */
2068 dec_insn.pc_inc = 4;
2069 instr_ptr += 2;
2070 }
2071 /* Get second instruction. */
2072 if (mm_insn_16bit(*instr_ptr)) {
2073 /* Duplicate the half-word. */
2074 dec_insn.next_insn = (*instr_ptr << 16) |
2075 (*instr_ptr);
2076 /* 16-bit instruction. */
2077 dec_insn.next_pc_inc = 2;
2078 } else {
2079 dec_insn.next_insn = (*instr_ptr << 16) |
2080 *(instr_ptr+1);
2081 /* 32-bit instruction. */
2082 dec_insn.next_pc_inc = 4;
2083 }
2084 dec_insn.micro_mips_mode = 1;
2085 } else {
2086 if ((get_user(dec_insn.insn,
2087 (mips_instruction __user *) xcp->cp0_epc)) ||
2088 (get_user(dec_insn.next_insn,
2089 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2090 MIPS_FPU_EMU_INC_STATS(errors);
2091 return SIGBUS;
2092 }
2093 dec_insn.pc_inc = 4;
2094 dec_insn.next_pc_inc = 4;
2095 dec_insn.micro_mips_mode = 0;
515b029d 2096 }
102cedc3
LY		 2097
2098 if ((dec_insn.insn == 0) ||
2099 ((dec_insn.pc_inc == 2) &&
2100 ((dec_insn.insn & 0xffff) == MM_NOP16)))
2101 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
1da177e4 2102 else {
cd21dfcf
RB		 2103 /*
2104 * The 'ieee754_csr' is an alias of
70342287
RB		 2105 * ctx->fcr31. No need to copy ctx->fcr31 to
2106 * ieee754_csr. But ieee754_csr.rm is ieee
cd21dfcf
RB		 2107 * library modes. (not mips rounding mode)
2108 */
2109 /* convert to ieee library modes */
2110 ieee754_csr.rm = ieee_rm[ieee754_csr.rm];
102cedc3 2111 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
cd21dfcf
RB		 2112 /* revert to mips rounding mode */
2113 ieee754_csr.rm = mips_rm[ieee754_csr.rm];
1da177e4
LT		 2114 }
2115
e04582b7 2116 if (has_fpu)
1da177e4
LT		 2117 break;
2118 if (sig)
2119 break;
2120
2121 cond_resched();
2122 } while (xcp->cp0_epc > prevepc);
2123
2124 /* SIGILL indicates a non-fpu instruction */
2125 if (sig == SIGILL && xcp->cp0_epc != oldepc)
2126 /* but if epc has advanced, then ignore it */
2127 sig = 0;
2128
2129 return sig;
2130}
83fd38ca
AN		 2131
2132#ifdef CONFIG_DEBUG_FS
b6ee75ed
DD		 2133
2134static int fpuemu_stat_get(void *data, u64 *val)
2135{
2136 int cpu;
2137 unsigned long sum = 0;
2138 for_each_online_cpu(cpu) {
2139 struct mips_fpu_emulator_stats *ps;
2140 local_t *pv;
2141 ps = &per_cpu(fpuemustats, cpu);
2142 pv = (void *)ps + (unsigned long)data;
2143 sum += local_read(pv);
2144 }
2145 *val = sum;
2146 return 0;
2147}
2148DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat, fpuemu_stat_get, NULL, "%llu\n");
2149
83fd38ca
AN		 2150extern struct dentry *mips_debugfs_dir;
2151static int __init debugfs_fpuemu(void)
2152{
2153 struct dentry *d, *dir;
83fd38ca
AN		 2154
2155 if (!mips_debugfs_dir)
2156 return -ENODEV;
2157 dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir);
ecab1f44
Z		 2158 if (!dir)
2159 return -ENOMEM;
b6ee75ed
DD		 2160
2161#define FPU_STAT_CREATE(M) \
2162 do { \
2163 d = debugfs_create_file(#M , S_IRUGO, dir, \
2164 (void *)offsetof(struct mips_fpu_emulator_stats, M), \
2165 &fops_fpuemu_stat); \
2166 if (!d) \
2167 return -ENOMEM; \
2168 } while (0)
2169
2170 FPU_STAT_CREATE(emulated);
2171 FPU_STAT_CREATE(loads);
2172 FPU_STAT_CREATE(stores);
2173 FPU_STAT_CREATE(cp1ops);
2174 FPU_STAT_CREATE(cp1xops);
2175 FPU_STAT_CREATE(errors);
2176
83fd38ca
AN		 2177 return 0;
2178}
2179__initcall(debugfs_fpuemu);
2180#endif
Linux kernel - Deliverables
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