Commit | Line | Data |
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1da177e4 | 1 | /* |
3f7cac41 | 2 | * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator |
1da177e4 LT |
3 | * |
4 | * MIPS floating point support | |
5 | * Copyright (C) 1994-2000 Algorithmics Ltd. | |
1da177e4 LT |
6 | * |
7 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
8 | * Copyright (C) 2000 MIPS Technologies, Inc. | |
9 | * | |
10 | * This program is free software; you can distribute it and/or modify it | |
11 | * under the terms of the GNU General Public License (Version 2) as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | * for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along | |
20 | * with this program; if not, write to the Free Software Foundation, Inc., | |
3f7cac41 | 21 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
1da177e4 LT |
22 | * |
23 | * A complete emulator for MIPS coprocessor 1 instructions. This is | |
24 | * required for #float(switch) or #float(trap), where it catches all | |
25 | * COP1 instructions via the "CoProcessor Unusable" exception. | |
26 | * | |
27 | * More surprisingly it is also required for #float(ieee), to help out | |
3f7cac41 | 28 | * the hardware FPU at the boundaries of the IEEE-754 representation |
1da177e4 LT |
29 | * (denormalised values, infinities, underflow, etc). It is made |
30 | * quite nasty because emulation of some non-COP1 instructions is | |
31 | * required, e.g. in branch delay slots. | |
32 | * | |
3f7cac41 | 33 | * Note if you know that you won't have an FPU, then you'll get much |
1da177e4 LT |
34 | * better performance by compiling with -msoft-float! |
35 | */ | |
36 | #include <linux/sched.h> | |
83fd38ca | 37 | #include <linux/debugfs.h> |
08a07904 | 38 | #include <linux/kconfig.h> |
85c51c51 | 39 | #include <linux/percpu-defs.h> |
7f788d2d | 40 | #include <linux/perf_event.h> |
1da177e4 | 41 | |
cd8ee345 | 42 | #include <asm/branch.h> |
1da177e4 | 43 | #include <asm/inst.h> |
1da177e4 LT |
44 | #include <asm/ptrace.h> |
45 | #include <asm/signal.h> | |
cd8ee345 RB |
46 | #include <asm/uaccess.h> |
47 | ||
48 | #include <asm/processor.h> | |
1da177e4 | 49 | #include <asm/fpu_emulator.h> |
102cedc3 | 50 | #include <asm/fpu.h> |
b0a668fb | 51 | #include <asm/mips-r2-to-r6-emul.h> |
1da177e4 LT |
52 | |
53 | #include "ieee754.h" | |
1da177e4 | 54 | |
1da177e4 LT |
55 | /* Function which emulates a floating point instruction. */ |
56 | ||
eae89076 | 57 | static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, |
1da177e4 LT |
58 | mips_instruction); |
59 | ||
1da177e4 | 60 | static int fpux_emu(struct pt_regs *, |
515b029d | 61 | struct mips_fpu_struct *, mips_instruction, void *__user *); |
1da177e4 | 62 | |
1da177e4 LT |
63 | /* Control registers */ |
64 | ||
65 | #define FPCREG_RID 0 /* $0 = revision id */ | |
66 | #define FPCREG_CSR 31 /* $31 = csr */ | |
67 | ||
1da177e4 | 68 | /* convert condition code register number to csr bit */ |
b0a668fb | 69 | const unsigned int fpucondbit[8] = { |
1da177e4 LT |
70 | FPU_CSR_COND0, |
71 | FPU_CSR_COND1, | |
72 | FPU_CSR_COND2, | |
73 | FPU_CSR_COND3, | |
74 | FPU_CSR_COND4, | |
75 | FPU_CSR_COND5, | |
76 | FPU_CSR_COND6, | |
77 | FPU_CSR_COND7 | |
78 | }; | |
1da177e4 | 79 | |
102cedc3 LY |
80 | /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */ |
81 | static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0}; | |
82 | static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0}; | |
83 | static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0}; | |
84 | static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0}; | |
85 | ||
86 | /* | |
87 | * This functions translates a 32-bit microMIPS instruction | |
88 | * into a 32-bit MIPS32 instruction. Returns 0 on success | |
89 | * and SIGILL otherwise. | |
90 | */ | |
91 | static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) | |
92 | { | |
93 | union mips_instruction insn = *insn_ptr; | |
94 | union mips_instruction mips32_insn = insn; | |
95 | int func, fmt, op; | |
96 | ||
97 | switch (insn.mm_i_format.opcode) { | |
98 | case mm_ldc132_op: | |
99 | mips32_insn.mm_i_format.opcode = ldc1_op; | |
100 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
101 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
102 | break; | |
103 | case mm_lwc132_op: | |
104 | mips32_insn.mm_i_format.opcode = lwc1_op; | |
105 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
106 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
107 | break; | |
108 | case mm_sdc132_op: | |
109 | mips32_insn.mm_i_format.opcode = sdc1_op; | |
110 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
111 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
112 | break; | |
113 | case mm_swc132_op: | |
114 | mips32_insn.mm_i_format.opcode = swc1_op; | |
115 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
116 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
117 | break; | |
118 | case mm_pool32i_op: | |
119 | /* NOTE: offset is << by 1 if in microMIPS mode. */ | |
120 | if ((insn.mm_i_format.rt == mm_bc1f_op) || | |
121 | (insn.mm_i_format.rt == mm_bc1t_op)) { | |
122 | mips32_insn.fb_format.opcode = cop1_op; | |
123 | mips32_insn.fb_format.bc = bc_op; | |
124 | mips32_insn.fb_format.flag = | |
125 | (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0; | |
126 | } else | |
127 | return SIGILL; | |
128 | break; | |
129 | case mm_pool32f_op: | |
130 | switch (insn.mm_fp0_format.func) { | |
131 | case mm_32f_01_op: | |
132 | case mm_32f_11_op: | |
133 | case mm_32f_02_op: | |
134 | case mm_32f_12_op: | |
135 | case mm_32f_41_op: | |
136 | case mm_32f_51_op: | |
137 | case mm_32f_42_op: | |
138 | case mm_32f_52_op: | |
139 | op = insn.mm_fp0_format.func; | |
140 | if (op == mm_32f_01_op) | |
141 | func = madd_s_op; | |
142 | else if (op == mm_32f_11_op) | |
143 | func = madd_d_op; | |
144 | else if (op == mm_32f_02_op) | |
145 | func = nmadd_s_op; | |
146 | else if (op == mm_32f_12_op) | |
147 | func = nmadd_d_op; | |
148 | else if (op == mm_32f_41_op) | |
149 | func = msub_s_op; | |
150 | else if (op == mm_32f_51_op) | |
151 | func = msub_d_op; | |
152 | else if (op == mm_32f_42_op) | |
153 | func = nmsub_s_op; | |
154 | else | |
155 | func = nmsub_d_op; | |
156 | mips32_insn.fp6_format.opcode = cop1x_op; | |
157 | mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr; | |
158 | mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft; | |
159 | mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs; | |
160 | mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd; | |
161 | mips32_insn.fp6_format.func = func; | |
162 | break; | |
163 | case mm_32f_10_op: | |
164 | func = -1; /* Invalid */ | |
165 | op = insn.mm_fp5_format.op & 0x7; | |
166 | if (op == mm_ldxc1_op) | |
167 | func = ldxc1_op; | |
168 | else if (op == mm_sdxc1_op) | |
169 | func = sdxc1_op; | |
170 | else if (op == mm_lwxc1_op) | |
171 | func = lwxc1_op; | |
172 | else if (op == mm_swxc1_op) | |
173 | func = swxc1_op; | |
174 | ||
175 | if (func != -1) { | |
176 | mips32_insn.r_format.opcode = cop1x_op; | |
177 | mips32_insn.r_format.rs = | |
178 | insn.mm_fp5_format.base; | |
179 | mips32_insn.r_format.rt = | |
180 | insn.mm_fp5_format.index; | |
181 | mips32_insn.r_format.rd = 0; | |
182 | mips32_insn.r_format.re = insn.mm_fp5_format.fd; | |
183 | mips32_insn.r_format.func = func; | |
184 | } else | |
185 | return SIGILL; | |
186 | break; | |
187 | case mm_32f_40_op: | |
188 | op = -1; /* Invalid */ | |
189 | if (insn.mm_fp2_format.op == mm_fmovt_op) | |
190 | op = 1; | |
191 | else if (insn.mm_fp2_format.op == mm_fmovf_op) | |
192 | op = 0; | |
193 | if (op != -1) { | |
194 | mips32_insn.fp0_format.opcode = cop1_op; | |
195 | mips32_insn.fp0_format.fmt = | |
196 | sdps_format[insn.mm_fp2_format.fmt]; | |
197 | mips32_insn.fp0_format.ft = | |
198 | (insn.mm_fp2_format.cc<<2) + op; | |
199 | mips32_insn.fp0_format.fs = | |
200 | insn.mm_fp2_format.fs; | |
201 | mips32_insn.fp0_format.fd = | |
202 | insn.mm_fp2_format.fd; | |
203 | mips32_insn.fp0_format.func = fmovc_op; | |
204 | } else | |
205 | return SIGILL; | |
206 | break; | |
207 | case mm_32f_60_op: | |
208 | func = -1; /* Invalid */ | |
209 | if (insn.mm_fp0_format.op == mm_fadd_op) | |
210 | func = fadd_op; | |
211 | else if (insn.mm_fp0_format.op == mm_fsub_op) | |
212 | func = fsub_op; | |
213 | else if (insn.mm_fp0_format.op == mm_fmul_op) | |
214 | func = fmul_op; | |
215 | else if (insn.mm_fp0_format.op == mm_fdiv_op) | |
216 | func = fdiv_op; | |
217 | if (func != -1) { | |
218 | mips32_insn.fp0_format.opcode = cop1_op; | |
219 | mips32_insn.fp0_format.fmt = | |
220 | sdps_format[insn.mm_fp0_format.fmt]; | |
221 | mips32_insn.fp0_format.ft = | |
222 | insn.mm_fp0_format.ft; | |
223 | mips32_insn.fp0_format.fs = | |
224 | insn.mm_fp0_format.fs; | |
225 | mips32_insn.fp0_format.fd = | |
226 | insn.mm_fp0_format.fd; | |
227 | mips32_insn.fp0_format.func = func; | |
228 | } else | |
229 | return SIGILL; | |
230 | break; | |
231 | case mm_32f_70_op: | |
232 | func = -1; /* Invalid */ | |
233 | if (insn.mm_fp0_format.op == mm_fmovn_op) | |
234 | func = fmovn_op; | |
235 | else if (insn.mm_fp0_format.op == mm_fmovz_op) | |
236 | func = fmovz_op; | |
237 | if (func != -1) { | |
238 | mips32_insn.fp0_format.opcode = cop1_op; | |
239 | mips32_insn.fp0_format.fmt = | |
240 | sdps_format[insn.mm_fp0_format.fmt]; | |
241 | mips32_insn.fp0_format.ft = | |
242 | insn.mm_fp0_format.ft; | |
243 | mips32_insn.fp0_format.fs = | |
244 | insn.mm_fp0_format.fs; | |
245 | mips32_insn.fp0_format.fd = | |
246 | insn.mm_fp0_format.fd; | |
247 | mips32_insn.fp0_format.func = func; | |
248 | } else | |
249 | return SIGILL; | |
250 | break; | |
251 | case mm_32f_73_op: /* POOL32FXF */ | |
252 | switch (insn.mm_fp1_format.op) { | |
253 | case mm_movf0_op: | |
254 | case mm_movf1_op: | |
255 | case mm_movt0_op: | |
256 | case mm_movt1_op: | |
257 | if ((insn.mm_fp1_format.op & 0x7f) == | |
258 | mm_movf0_op) | |
259 | op = 0; | |
260 | else | |
261 | op = 1; | |
262 | mips32_insn.r_format.opcode = spec_op; | |
263 | mips32_insn.r_format.rs = insn.mm_fp4_format.fs; | |
264 | mips32_insn.r_format.rt = | |
265 | (insn.mm_fp4_format.cc << 2) + op; | |
266 | mips32_insn.r_format.rd = insn.mm_fp4_format.rt; | |
267 | mips32_insn.r_format.re = 0; | |
268 | mips32_insn.r_format.func = movc_op; | |
269 | break; | |
270 | case mm_fcvtd0_op: | |
271 | case mm_fcvtd1_op: | |
272 | case mm_fcvts0_op: | |
273 | case mm_fcvts1_op: | |
274 | if ((insn.mm_fp1_format.op & 0x7f) == | |
275 | mm_fcvtd0_op) { | |
276 | func = fcvtd_op; | |
277 | fmt = swl_format[insn.mm_fp3_format.fmt]; | |
278 | } else { | |
279 | func = fcvts_op; | |
280 | fmt = dwl_format[insn.mm_fp3_format.fmt]; | |
281 | } | |
282 | mips32_insn.fp0_format.opcode = cop1_op; | |
283 | mips32_insn.fp0_format.fmt = fmt; | |
284 | mips32_insn.fp0_format.ft = 0; | |
285 | mips32_insn.fp0_format.fs = | |
286 | insn.mm_fp3_format.fs; | |
287 | mips32_insn.fp0_format.fd = | |
288 | insn.mm_fp3_format.rt; | |
289 | mips32_insn.fp0_format.func = func; | |
290 | break; | |
291 | case mm_fmov0_op: | |
292 | case mm_fmov1_op: | |
293 | case mm_fabs0_op: | |
294 | case mm_fabs1_op: | |
295 | case mm_fneg0_op: | |
296 | case mm_fneg1_op: | |
297 | if ((insn.mm_fp1_format.op & 0x7f) == | |
298 | mm_fmov0_op) | |
299 | func = fmov_op; | |
300 | else if ((insn.mm_fp1_format.op & 0x7f) == | |
301 | mm_fabs0_op) | |
302 | func = fabs_op; | |
303 | else | |
304 | func = fneg_op; | |
305 | mips32_insn.fp0_format.opcode = cop1_op; | |
306 | mips32_insn.fp0_format.fmt = | |
307 | sdps_format[insn.mm_fp3_format.fmt]; | |
308 | mips32_insn.fp0_format.ft = 0; | |
309 | mips32_insn.fp0_format.fs = | |
310 | insn.mm_fp3_format.fs; | |
311 | mips32_insn.fp0_format.fd = | |
312 | insn.mm_fp3_format.rt; | |
313 | mips32_insn.fp0_format.func = func; | |
314 | break; | |
315 | case mm_ffloorl_op: | |
316 | case mm_ffloorw_op: | |
317 | case mm_fceill_op: | |
318 | case mm_fceilw_op: | |
319 | case mm_ftruncl_op: | |
320 | case mm_ftruncw_op: | |
321 | case mm_froundl_op: | |
322 | case mm_froundw_op: | |
323 | case mm_fcvtl_op: | |
324 | case mm_fcvtw_op: | |
325 | if (insn.mm_fp1_format.op == mm_ffloorl_op) | |
326 | func = ffloorl_op; | |
327 | else if (insn.mm_fp1_format.op == mm_ffloorw_op) | |
328 | func = ffloor_op; | |
329 | else if (insn.mm_fp1_format.op == mm_fceill_op) | |
330 | func = fceill_op; | |
331 | else if (insn.mm_fp1_format.op == mm_fceilw_op) | |
332 | func = fceil_op; | |
333 | else if (insn.mm_fp1_format.op == mm_ftruncl_op) | |
334 | func = ftruncl_op; | |
335 | else if (insn.mm_fp1_format.op == mm_ftruncw_op) | |
336 | func = ftrunc_op; | |
337 | else if (insn.mm_fp1_format.op == mm_froundl_op) | |
338 | func = froundl_op; | |
339 | else if (insn.mm_fp1_format.op == mm_froundw_op) | |
340 | func = fround_op; | |
341 | else if (insn.mm_fp1_format.op == mm_fcvtl_op) | |
342 | func = fcvtl_op; | |
343 | else | |
344 | func = fcvtw_op; | |
345 | mips32_insn.fp0_format.opcode = cop1_op; | |
346 | mips32_insn.fp0_format.fmt = | |
347 | sd_format[insn.mm_fp1_format.fmt]; | |
348 | mips32_insn.fp0_format.ft = 0; | |
349 | mips32_insn.fp0_format.fs = | |
350 | insn.mm_fp1_format.fs; | |
351 | mips32_insn.fp0_format.fd = | |
352 | insn.mm_fp1_format.rt; | |
353 | mips32_insn.fp0_format.func = func; | |
354 | break; | |
355 | case mm_frsqrt_op: | |
356 | case mm_fsqrt_op: | |
357 | case mm_frecip_op: | |
358 | if (insn.mm_fp1_format.op == mm_frsqrt_op) | |
359 | func = frsqrt_op; | |
360 | else if (insn.mm_fp1_format.op == mm_fsqrt_op) | |
361 | func = fsqrt_op; | |
362 | else | |
363 | func = frecip_op; | |
364 | mips32_insn.fp0_format.opcode = cop1_op; | |
365 | mips32_insn.fp0_format.fmt = | |
366 | sdps_format[insn.mm_fp1_format.fmt]; | |
367 | mips32_insn.fp0_format.ft = 0; | |
368 | mips32_insn.fp0_format.fs = | |
369 | insn.mm_fp1_format.fs; | |
370 | mips32_insn.fp0_format.fd = | |
371 | insn.mm_fp1_format.rt; | |
372 | mips32_insn.fp0_format.func = func; | |
373 | break; | |
374 | case mm_mfc1_op: | |
375 | case mm_mtc1_op: | |
376 | case mm_cfc1_op: | |
377 | case mm_ctc1_op: | |
9355e59c SH |
378 | case mm_mfhc1_op: |
379 | case mm_mthc1_op: | |
102cedc3 LY |
380 | if (insn.mm_fp1_format.op == mm_mfc1_op) |
381 | op = mfc_op; | |
382 | else if (insn.mm_fp1_format.op == mm_mtc1_op) | |
383 | op = mtc_op; | |
384 | else if (insn.mm_fp1_format.op == mm_cfc1_op) | |
385 | op = cfc_op; | |
9355e59c | 386 | else if (insn.mm_fp1_format.op == mm_ctc1_op) |
102cedc3 | 387 | op = ctc_op; |
9355e59c SH |
388 | else if (insn.mm_fp1_format.op == mm_mfhc1_op) |
389 | op = mfhc_op; | |
390 | else | |
391 | op = mthc_op; | |
102cedc3 LY |
392 | mips32_insn.fp1_format.opcode = cop1_op; |
393 | mips32_insn.fp1_format.op = op; | |
394 | mips32_insn.fp1_format.rt = | |
395 | insn.mm_fp1_format.rt; | |
396 | mips32_insn.fp1_format.fs = | |
397 | insn.mm_fp1_format.fs; | |
398 | mips32_insn.fp1_format.fd = 0; | |
399 | mips32_insn.fp1_format.func = 0; | |
400 | break; | |
401 | default: | |
402 | return SIGILL; | |
102cedc3 LY |
403 | } |
404 | break; | |
405 | case mm_32f_74_op: /* c.cond.fmt */ | |
406 | mips32_insn.fp0_format.opcode = cop1_op; | |
407 | mips32_insn.fp0_format.fmt = | |
408 | sdps_format[insn.mm_fp4_format.fmt]; | |
409 | mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt; | |
410 | mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs; | |
411 | mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2; | |
412 | mips32_insn.fp0_format.func = | |
413 | insn.mm_fp4_format.cond | MM_MIPS32_COND_FC; | |
414 | break; | |
415 | default: | |
416 | return SIGILL; | |
102cedc3 LY |
417 | } |
418 | break; | |
419 | default: | |
420 | return SIGILL; | |
102cedc3 LY |
421 | } |
422 | ||
423 | *insn_ptr = mips32_insn; | |
424 | return 0; | |
425 | } | |
426 | ||
1da177e4 LT |
427 | /* |
428 | * Redundant with logic already in kernel/branch.c, | |
429 | * embedded in compute_return_epc. At some point, | |
430 | * a single subroutine should be used across both | |
431 | * modules. | |
432 | */ | |
102cedc3 LY |
433 | static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, |
434 | unsigned long *contpc) | |
1da177e4 | 435 | { |
102cedc3 LY |
436 | union mips_instruction insn = (union mips_instruction)dec_insn.insn; |
437 | unsigned int fcr31; | |
438 | unsigned int bit = 0; | |
439 | ||
440 | switch (insn.i_format.opcode) { | |
1da177e4 | 441 | case spec_op: |
102cedc3 | 442 | switch (insn.r_format.func) { |
1da177e4 | 443 | case jalr_op: |
102cedc3 LY |
444 | regs->regs[insn.r_format.rd] = |
445 | regs->cp0_epc + dec_insn.pc_inc + | |
446 | dec_insn.next_pc_inc; | |
447 | /* Fall through */ | |
1da177e4 | 448 | case jr_op: |
5f9f41c4 MC |
449 | /* For R6, JR already emulated in jalr_op */ |
450 | if (NO_R6EMU && insn.r_format.opcode == jr_op) | |
451 | break; | |
102cedc3 | 452 | *contpc = regs->regs[insn.r_format.rs]; |
1da177e4 LT |
453 | return 1; |
454 | } | |
455 | break; | |
1da177e4 | 456 | case bcond_op: |
102cedc3 LY |
457 | switch (insn.i_format.rt) { |
458 | case bltzal_op: | |
459 | case bltzall_op: | |
319824ea MC |
460 | if (NO_R6EMU && (insn.i_format.rs || |
461 | insn.i_format.rt == bltzall_op)) | |
462 | break; | |
463 | ||
102cedc3 LY |
464 | regs->regs[31] = regs->cp0_epc + |
465 | dec_insn.pc_inc + | |
466 | dec_insn.next_pc_inc; | |
467 | /* Fall through */ | |
1da177e4 | 468 | case bltzl_op: |
319824ea MC |
469 | if (NO_R6EMU) |
470 | break; | |
471 | case bltz_op: | |
102cedc3 LY |
472 | if ((long)regs->regs[insn.i_format.rs] < 0) |
473 | *contpc = regs->cp0_epc + | |
474 | dec_insn.pc_inc + | |
475 | (insn.i_format.simmediate << 2); | |
476 | else | |
477 | *contpc = regs->cp0_epc + | |
478 | dec_insn.pc_inc + | |
479 | dec_insn.next_pc_inc; | |
480 | return 1; | |
1da177e4 | 481 | case bgezal_op: |
1da177e4 | 482 | case bgezall_op: |
319824ea MC |
483 | if (NO_R6EMU && (insn.i_format.rs || |
484 | insn.i_format.rt == bgezall_op)) | |
485 | break; | |
486 | ||
102cedc3 LY |
487 | regs->regs[31] = regs->cp0_epc + |
488 | dec_insn.pc_inc + | |
489 | dec_insn.next_pc_inc; | |
490 | /* Fall through */ | |
102cedc3 | 491 | case bgezl_op: |
319824ea MC |
492 | if (NO_R6EMU) |
493 | break; | |
494 | case bgez_op: | |
102cedc3 LY |
495 | if ((long)regs->regs[insn.i_format.rs] >= 0) |
496 | *contpc = regs->cp0_epc + | |
497 | dec_insn.pc_inc + | |
498 | (insn.i_format.simmediate << 2); | |
499 | else | |
500 | *contpc = regs->cp0_epc + | |
501 | dec_insn.pc_inc + | |
502 | dec_insn.next_pc_inc; | |
1da177e4 LT |
503 | return 1; |
504 | } | |
505 | break; | |
1da177e4 | 506 | case jalx_op: |
102cedc3 LY |
507 | set_isa16_mode(bit); |
508 | case jal_op: | |
509 | regs->regs[31] = regs->cp0_epc + | |
510 | dec_insn.pc_inc + | |
511 | dec_insn.next_pc_inc; | |
512 | /* Fall through */ | |
513 | case j_op: | |
514 | *contpc = regs->cp0_epc + dec_insn.pc_inc; | |
515 | *contpc >>= 28; | |
516 | *contpc <<= 28; | |
517 | *contpc |= (insn.j_format.target << 2); | |
518 | /* Set microMIPS mode bit: XOR for jalx. */ | |
519 | *contpc ^= bit; | |
520 | return 1; | |
1da177e4 | 521 | case beql_op: |
319824ea MC |
522 | if (NO_R6EMU) |
523 | break; | |
524 | case beq_op: | |
102cedc3 LY |
525 | if (regs->regs[insn.i_format.rs] == |
526 | regs->regs[insn.i_format.rt]) | |
527 | *contpc = regs->cp0_epc + | |
528 | dec_insn.pc_inc + | |
529 | (insn.i_format.simmediate << 2); | |
530 | else | |
531 | *contpc = regs->cp0_epc + | |
532 | dec_insn.pc_inc + | |
533 | dec_insn.next_pc_inc; | |
534 | return 1; | |
1da177e4 | 535 | case bnel_op: |
319824ea MC |
536 | if (NO_R6EMU) |
537 | break; | |
538 | case bne_op: | |
102cedc3 LY |
539 | if (regs->regs[insn.i_format.rs] != |
540 | regs->regs[insn.i_format.rt]) | |
541 | *contpc = regs->cp0_epc + | |
542 | dec_insn.pc_inc + | |
543 | (insn.i_format.simmediate << 2); | |
544 | else | |
545 | *contpc = regs->cp0_epc + | |
546 | dec_insn.pc_inc + | |
547 | dec_insn.next_pc_inc; | |
548 | return 1; | |
1da177e4 | 549 | case blezl_op: |
319824ea MC |
550 | if (NO_R6EMU) |
551 | break; | |
552 | case blez_op: | |
a8ff66f5 MC |
553 | |
554 | /* | |
555 | * Compact branches for R6 for the | |
556 | * blez and blezl opcodes. | |
557 | * BLEZ | rs = 0 | rt != 0 == BLEZALC | |
558 | * BLEZ | rs = rt != 0 == BGEZALC | |
559 | * BLEZ | rs != 0 | rt != 0 == BGEUC | |
560 | * BLEZL | rs = 0 | rt != 0 == BLEZC | |
561 | * BLEZL | rs = rt != 0 == BGEZC | |
562 | * BLEZL | rs != 0 | rt != 0 == BGEC | |
563 | * | |
564 | * For real BLEZ{,L}, rt is always 0. | |
565 | */ | |
566 | if (cpu_has_mips_r6 && insn.i_format.rt) { | |
567 | if ((insn.i_format.opcode == blez_op) && | |
568 | ((!insn.i_format.rs && insn.i_format.rt) || | |
569 | (insn.i_format.rs == insn.i_format.rt))) | |
570 | regs->regs[31] = regs->cp0_epc + | |
571 | dec_insn.pc_inc; | |
572 | *contpc = regs->cp0_epc + dec_insn.pc_inc + | |
573 | dec_insn.next_pc_inc; | |
574 | ||
575 | return 1; | |
576 | } | |
102cedc3 LY |
577 | if ((long)regs->regs[insn.i_format.rs] <= 0) |
578 | *contpc = regs->cp0_epc + | |
579 | dec_insn.pc_inc + | |
580 | (insn.i_format.simmediate << 2); | |
581 | else | |
582 | *contpc = regs->cp0_epc + | |
583 | dec_insn.pc_inc + | |
584 | dec_insn.next_pc_inc; | |
585 | return 1; | |
1da177e4 | 586 | case bgtzl_op: |
319824ea MC |
587 | if (NO_R6EMU) |
588 | break; | |
589 | case bgtz_op: | |
f1b44067 MC |
590 | /* |
591 | * Compact branches for R6 for the | |
592 | * bgtz and bgtzl opcodes. | |
593 | * BGTZ | rs = 0 | rt != 0 == BGTZALC | |
594 | * BGTZ | rs = rt != 0 == BLTZALC | |
595 | * BGTZ | rs != 0 | rt != 0 == BLTUC | |
596 | * BGTZL | rs = 0 | rt != 0 == BGTZC | |
597 | * BGTZL | rs = rt != 0 == BLTZC | |
598 | * BGTZL | rs != 0 | rt != 0 == BLTC | |
599 | * | |
600 | * *ZALC varint for BGTZ &&& rt != 0 | |
601 | * For real GTZ{,L}, rt is always 0. | |
602 | */ | |
603 | if (cpu_has_mips_r6 && insn.i_format.rt) { | |
604 | if ((insn.i_format.opcode == blez_op) && | |
605 | ((!insn.i_format.rs && insn.i_format.rt) || | |
606 | (insn.i_format.rs == insn.i_format.rt))) | |
607 | regs->regs[31] = regs->cp0_epc + | |
608 | dec_insn.pc_inc; | |
609 | *contpc = regs->cp0_epc + dec_insn.pc_inc + | |
610 | dec_insn.next_pc_inc; | |
611 | ||
612 | return 1; | |
613 | } | |
614 | ||
102cedc3 LY |
615 | if ((long)regs->regs[insn.i_format.rs] > 0) |
616 | *contpc = regs->cp0_epc + | |
617 | dec_insn.pc_inc + | |
618 | (insn.i_format.simmediate << 2); | |
619 | else | |
620 | *contpc = regs->cp0_epc + | |
621 | dec_insn.pc_inc + | |
622 | dec_insn.next_pc_inc; | |
1da177e4 | 623 | return 1; |
c893ce38 | 624 | case cbcond0_op: |
10d962d5 | 625 | case cbcond1_op: |
c893ce38 MC |
626 | if (!cpu_has_mips_r6) |
627 | break; | |
628 | if (insn.i_format.rt && !insn.i_format.rs) | |
629 | regs->regs[31] = regs->cp0_epc + 4; | |
630 | *contpc = regs->cp0_epc + dec_insn.pc_inc + | |
631 | dec_insn.next_pc_inc; | |
632 | ||
633 | return 1; | |
c26d4219 DD |
634 | #ifdef CONFIG_CPU_CAVIUM_OCTEON |
635 | case lwc2_op: /* This is bbit0 on Octeon */ | |
636 | if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0) | |
637 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
638 | else | |
639 | *contpc = regs->cp0_epc + 8; | |
640 | return 1; | |
641 | case ldc2_op: /* This is bbit032 on Octeon */ | |
642 | if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0) | |
643 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
644 | else | |
645 | *contpc = regs->cp0_epc + 8; | |
646 | return 1; | |
647 | case swc2_op: /* This is bbit1 on Octeon */ | |
648 | if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) | |
649 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
650 | else | |
651 | *contpc = regs->cp0_epc + 8; | |
652 | return 1; | |
653 | case sdc2_op: /* This is bbit132 on Octeon */ | |
654 | if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) | |
655 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
656 | else | |
657 | *contpc = regs->cp0_epc + 8; | |
658 | return 1; | |
8467ca01 MC |
659 | #else |
660 | case bc6_op: | |
661 | /* | |
662 | * Only valid for MIPS R6 but we can still end up | |
663 | * here from a broken userland so just tell emulator | |
664 | * this is not a branch and let it break later on. | |
665 | */ | |
666 | if (!cpu_has_mips_r6) | |
667 | break; | |
668 | *contpc = regs->cp0_epc + dec_insn.pc_inc + | |
669 | dec_insn.next_pc_inc; | |
670 | ||
84fef630 MC |
671 | return 1; |
672 | case balc6_op: | |
673 | if (!cpu_has_mips_r6) | |
674 | break; | |
675 | regs->regs[31] = regs->cp0_epc + 4; | |
676 | *contpc = regs->cp0_epc + dec_insn.pc_inc + | |
677 | dec_insn.next_pc_inc; | |
678 | ||
69b9a2fd MC |
679 | return 1; |
680 | case beqzcjic_op: | |
681 | if (!cpu_has_mips_r6) | |
682 | break; | |
683 | *contpc = regs->cp0_epc + dec_insn.pc_inc + | |
684 | dec_insn.next_pc_inc; | |
685 | ||
28d6f93d MC |
686 | return 1; |
687 | case bnezcjialc_op: | |
688 | if (!cpu_has_mips_r6) | |
689 | break; | |
690 | if (!insn.i_format.rs) | |
691 | regs->regs[31] = regs->cp0_epc + 4; | |
692 | *contpc = regs->cp0_epc + dec_insn.pc_inc + | |
693 | dec_insn.next_pc_inc; | |
694 | ||
8467ca01 | 695 | return 1; |
c26d4219 | 696 | #endif |
1da177e4 LT |
697 | case cop0_op: |
698 | case cop1_op: | |
c8a34581 MC |
699 | /* Need to check for R6 bc1nez and bc1eqz branches */ |
700 | if (cpu_has_mips_r6 && | |
701 | ((insn.i_format.rs == bc1eqz_op) || | |
702 | (insn.i_format.rs == bc1nez_op))) { | |
703 | bit = 0; | |
704 | switch (insn.i_format.rs) { | |
705 | case bc1eqz_op: | |
706 | if (get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1) | |
707 | bit = 1; | |
708 | break; | |
709 | case bc1nez_op: | |
710 | if (!(get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)) | |
711 | bit = 1; | |
712 | break; | |
713 | } | |
714 | if (bit) | |
715 | *contpc = regs->cp0_epc + | |
716 | dec_insn.pc_inc + | |
717 | (insn.i_format.simmediate << 2); | |
718 | else | |
719 | *contpc = regs->cp0_epc + | |
720 | dec_insn.pc_inc + | |
721 | dec_insn.next_pc_inc; | |
722 | ||
723 | return 1; | |
724 | } | |
725 | /* R2/R6 compatible cop1 instruction. Fall through */ | |
1da177e4 LT |
726 | case cop2_op: |
727 | case cop1x_op: | |
102cedc3 LY |
728 | if (insn.i_format.rs == bc_op) { |
729 | preempt_disable(); | |
730 | if (is_fpu_owner()) | |
842dfc11 | 731 | fcr31 = read_32bit_cp1_register(CP1_STATUS); |
102cedc3 LY |
732 | else |
733 | fcr31 = current->thread.fpu.fcr31; | |
734 | preempt_enable(); | |
735 | ||
736 | bit = (insn.i_format.rt >> 2); | |
737 | bit += (bit != 0); | |
738 | bit += 23; | |
739 | switch (insn.i_format.rt & 3) { | |
740 | case 0: /* bc1f */ | |
741 | case 2: /* bc1fl */ | |
742 | if (~fcr31 & (1 << bit)) | |
743 | *contpc = regs->cp0_epc + | |
744 | dec_insn.pc_inc + | |
745 | (insn.i_format.simmediate << 2); | |
746 | else | |
747 | *contpc = regs->cp0_epc + | |
748 | dec_insn.pc_inc + | |
749 | dec_insn.next_pc_inc; | |
750 | return 1; | |
102cedc3 LY |
751 | case 1: /* bc1t */ |
752 | case 3: /* bc1tl */ | |
753 | if (fcr31 & (1 << bit)) | |
754 | *contpc = regs->cp0_epc + | |
755 | dec_insn.pc_inc + | |
756 | (insn.i_format.simmediate << 2); | |
757 | else | |
758 | *contpc = regs->cp0_epc + | |
759 | dec_insn.pc_inc + | |
760 | dec_insn.next_pc_inc; | |
761 | return 1; | |
102cedc3 LY |
762 | } |
763 | } | |
1da177e4 LT |
764 | break; |
765 | } | |
1da177e4 LT |
766 | return 0; |
767 | } | |
768 | ||
769 | /* | |
770 | * In the Linux kernel, we support selection of FPR format on the | |
70342287 | 771 | * basis of the Status.FR bit. If an FPU is not present, the FR bit |
da0bac33 | 772 | * is hardwired to zero, which would imply a 32-bit FPU even for |
597ce172 | 773 | * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS. |
51d943f0 RB |
774 | * FPU emu is slow and bulky and optimizing this function offers fairly |
775 | * sizeable benefits so we try to be clever and make this function return | |
776 | * a constant whenever possible, that is on 64-bit kernels without O32 | |
597ce172 | 777 | * compatibility enabled and on 32-bit without 64-bit FPU support. |
1da177e4 | 778 | */ |
da0bac33 DD |
779 | static inline int cop1_64bit(struct pt_regs *xcp) |
780 | { | |
08a07904 RB |
781 | if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32)) |
782 | return 1; | |
783 | else if (config_enabled(CONFIG_32BIT) && | |
784 | !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT)) | |
785 | return 0; | |
786 | ||
597ce172 | 787 | return !test_thread_flag(TIF_32BIT_FPREGS); |
da0bac33 DD |
788 | } |
789 | ||
4227a2d4 PB |
790 | static inline bool hybrid_fprs(void) |
791 | { | |
792 | return test_thread_flag(TIF_HYBRID_FPREGS); | |
793 | } | |
794 | ||
47fa0c02 RB |
795 | #define SIFROMREG(si, x) \ |
796 | do { \ | |
4227a2d4 | 797 | if (cop1_64bit(xcp) && !hybrid_fprs()) \ |
c8c0da6b | 798 | (si) = (int)get_fpr32(&ctx->fpr[x], 0); \ |
bbd426f5 | 799 | else \ |
c8c0da6b | 800 | (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \ |
bbd426f5 | 801 | } while (0) |
1da177e4 | 802 | |
47fa0c02 RB |
803 | #define SITOREG(si, x) \ |
804 | do { \ | |
4227a2d4 | 805 | if (cop1_64bit(xcp) && !hybrid_fprs()) { \ |
ef1c47af | 806 | unsigned i; \ |
bbd426f5 | 807 | set_fpr32(&ctx->fpr[x], 0, si); \ |
ef1c47af PB |
808 | for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ |
809 | set_fpr32(&ctx->fpr[x], i, 0); \ | |
810 | } else { \ | |
bbd426f5 | 811 | set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \ |
ef1c47af | 812 | } \ |
bbd426f5 | 813 | } while (0) |
1da177e4 | 814 | |
c8c0da6b | 815 | #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1)) |
ef1c47af | 816 | |
47fa0c02 RB |
817 | #define SITOHREG(si, x) \ |
818 | do { \ | |
ef1c47af PB |
819 | unsigned i; \ |
820 | set_fpr32(&ctx->fpr[x], 1, si); \ | |
821 | for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ | |
822 | set_fpr32(&ctx->fpr[x], i, 0); \ | |
823 | } while (0) | |
1ac94400 | 824 | |
47fa0c02 | 825 | #define DIFROMREG(di, x) \ |
bbd426f5 PB |
826 | ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0)) |
827 | ||
47fa0c02 RB |
828 | #define DITOREG(di, x) \ |
829 | do { \ | |
ef1c47af PB |
830 | unsigned fpr, i; \ |
831 | fpr = (x) & ~(cop1_64bit(xcp) == 0); \ | |
832 | set_fpr64(&ctx->fpr[fpr], 0, di); \ | |
833 | for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \ | |
834 | set_fpr64(&ctx->fpr[fpr], i, 0); \ | |
835 | } while (0) | |
1da177e4 | 836 | |
21a151d8 RB |
837 | #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x) |
838 | #define SPTOREG(sp, x) SITOREG((sp).bits, x) | |
839 | #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x) | |
840 | #define DPTOREG(dp, x) DITOREG((dp).bits, x) | |
1da177e4 | 841 | |
d4f5b088 MR |
842 | /* |
843 | * Emulate a CFC1 instruction. | |
844 | */ | |
845 | static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx, | |
846 | mips_instruction ir) | |
847 | { | |
848 | u32 value; | |
849 | ||
850 | if (MIPSInst_RD(ir) == FPCREG_CSR) { | |
851 | value = ctx->fcr31; | |
852 | pr_debug("%p gpr[%d]<-csr=%08x\n", | |
853 | (void *)xcp->cp0_epc, | |
854 | MIPSInst_RT(ir), value); | |
855 | } else if (MIPSInst_RD(ir) == FPCREG_RID) | |
856 | value = 0; | |
857 | else | |
858 | value = 0; | |
859 | if (MIPSInst_RT(ir)) | |
860 | xcp->regs[MIPSInst_RT(ir)] = value; | |
861 | } | |
862 | ||
863 | /* | |
864 | * Emulate a CTC1 instruction. | |
865 | */ | |
866 | static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx, | |
867 | mips_instruction ir) | |
868 | { | |
869 | u32 value; | |
870 | ||
871 | if (MIPSInst_RT(ir) == 0) | |
872 | value = 0; | |
873 | else | |
874 | value = xcp->regs[MIPSInst_RT(ir)]; | |
875 | ||
876 | /* we only have one writable control reg | |
877 | */ | |
878 | if (MIPSInst_RD(ir) == FPCREG_CSR) { | |
879 | pr_debug("%p gpr[%d]->csr=%08x\n", | |
880 | (void *)xcp->cp0_epc, | |
881 | MIPSInst_RT(ir), value); | |
882 | ||
883 | /* Don't write reserved bits. */ | |
884 | ctx->fcr31 = value & ~FPU_CSR_RSVD; | |
885 | } | |
886 | } | |
887 | ||
1da177e4 LT |
888 | /* |
889 | * Emulate the single floating point instruction pointed at by EPC. | |
890 | * Two instructions if the instruction is in a branch delay slot. | |
891 | */ | |
892 | ||
515b029d | 893 | static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
102cedc3 | 894 | struct mm_decoded_insn dec_insn, void *__user *fault_addr) |
1da177e4 | 895 | { |
102cedc3 | 896 | unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; |
3f7cac41 RB |
897 | unsigned int cond, cbit; |
898 | mips_instruction ir; | |
899 | int likely, pc_inc; | |
900 | u32 __user *wva; | |
901 | u64 __user *dva; | |
3f7cac41 RB |
902 | u32 wval; |
903 | u64 dval; | |
904 | int sig; | |
1da177e4 | 905 | |
70e4c234 RB |
906 | /* |
907 | * These are giving gcc a gentle hint about what to expect in | |
908 | * dec_inst in order to do better optimization. | |
909 | */ | |
910 | if (!cpu_has_mmips && dec_insn.micro_mips_mode) | |
911 | unreachable(); | |
912 | ||
1da177e4 | 913 | /* XXX NEC Vr54xx bug workaround */ |
e7e9cae5 | 914 | if (delay_slot(xcp)) { |
102cedc3 LY |
915 | if (dec_insn.micro_mips_mode) { |
916 | if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) | |
e7e9cae5 | 917 | clear_delay_slot(xcp); |
102cedc3 LY |
918 | } else { |
919 | if (!isBranchInstr(xcp, dec_insn, &contpc)) | |
e7e9cae5 | 920 | clear_delay_slot(xcp); |
102cedc3 LY |
921 | } |
922 | } | |
1da177e4 | 923 | |
e7e9cae5 | 924 | if (delay_slot(xcp)) { |
1da177e4 LT |
925 | /* |
926 | * The instruction to be emulated is in a branch delay slot | |
70342287 | 927 | * which means that we have to emulate the branch instruction |
1da177e4 LT |
928 | * BEFORE we do the cop1 instruction. |
929 | * | |
930 | * This branch could be a COP1 branch, but in that case we | |
931 | * would have had a trap for that instruction, and would not | |
932 | * come through this route. | |
933 | * | |
934 | * Linux MIPS branch emulator operates on context, updating the | |
935 | * cp0_epc. | |
936 | */ | |
102cedc3 LY |
937 | ir = dec_insn.next_insn; /* process delay slot instr */ |
938 | pc_inc = dec_insn.next_pc_inc; | |
939 | } else { | |
940 | ir = dec_insn.insn; /* process current instr */ | |
941 | pc_inc = dec_insn.pc_inc; | |
942 | } | |
1da177e4 | 943 | |
102cedc3 LY |
944 | /* |
945 | * Since microMIPS FPU instructios are a subset of MIPS32 FPU | |
946 | * instructions, we want to convert microMIPS FPU instructions | |
947 | * into MIPS32 instructions so that we could reuse all of the | |
948 | * FPU emulation code. | |
949 | * | |
950 | * NOTE: We cannot do this for branch instructions since they | |
951 | * are not a subset. Example: Cannot emulate a 16-bit | |
952 | * aligned target address with a MIPS32 instruction. | |
953 | */ | |
954 | if (dec_insn.micro_mips_mode) { | |
955 | /* | |
956 | * If next instruction is a 16-bit instruction, then it | |
957 | * it cannot be a FPU instruction. This could happen | |
958 | * since we can be called for non-FPU instructions. | |
959 | */ | |
960 | if ((pc_inc == 2) || | |
961 | (microMIPS32_to_MIPS32((union mips_instruction *)&ir) | |
962 | == SIGILL)) | |
1da177e4 | 963 | return SIGILL; |
1da177e4 LT |
964 | } |
965 | ||
3f7cac41 | 966 | emul: |
a8b0ca17 | 967 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0); |
b6ee75ed | 968 | MIPS_FPU_EMU_INC_STATS(emulated); |
1da177e4 | 969 | switch (MIPSInst_OPCODE(ir)) { |
3f7cac41 RB |
970 | case ldc1_op: |
971 | dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + | |
972 | MIPSInst_SIMM(ir)); | |
b6ee75ed | 973 | MIPS_FPU_EMU_INC_STATS(loads); |
515b029d | 974 | |
3f7cac41 | 975 | if (!access_ok(VERIFY_READ, dva, sizeof(u64))) { |
b6ee75ed | 976 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 977 | *fault_addr = dva; |
1da177e4 LT |
978 | return SIGBUS; |
979 | } | |
3f7cac41 | 980 | if (__get_user(dval, dva)) { |
515b029d | 981 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 982 | *fault_addr = dva; |
515b029d DD |
983 | return SIGSEGV; |
984 | } | |
3f7cac41 | 985 | DITOREG(dval, MIPSInst_RT(ir)); |
1da177e4 | 986 | break; |
1da177e4 | 987 | |
3f7cac41 RB |
988 | case sdc1_op: |
989 | dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + | |
990 | MIPSInst_SIMM(ir)); | |
b6ee75ed | 991 | MIPS_FPU_EMU_INC_STATS(stores); |
3f7cac41 RB |
992 | DIFROMREG(dval, MIPSInst_RT(ir)); |
993 | if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) { | |
b6ee75ed | 994 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 995 | *fault_addr = dva; |
1da177e4 LT |
996 | return SIGBUS; |
997 | } | |
3f7cac41 | 998 | if (__put_user(dval, dva)) { |
515b029d | 999 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 1000 | *fault_addr = dva; |
515b029d DD |
1001 | return SIGSEGV; |
1002 | } | |
1da177e4 | 1003 | break; |
1da177e4 | 1004 | |
3f7cac41 RB |
1005 | case lwc1_op: |
1006 | wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + | |
1007 | MIPSInst_SIMM(ir)); | |
b6ee75ed | 1008 | MIPS_FPU_EMU_INC_STATS(loads); |
3f7cac41 | 1009 | if (!access_ok(VERIFY_READ, wva, sizeof(u32))) { |
b6ee75ed | 1010 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 1011 | *fault_addr = wva; |
1da177e4 LT |
1012 | return SIGBUS; |
1013 | } | |
3f7cac41 | 1014 | if (__get_user(wval, wva)) { |
515b029d | 1015 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 1016 | *fault_addr = wva; |
515b029d DD |
1017 | return SIGSEGV; |
1018 | } | |
3f7cac41 | 1019 | SITOREG(wval, MIPSInst_RT(ir)); |
1da177e4 | 1020 | break; |
1da177e4 | 1021 | |
3f7cac41 RB |
1022 | case swc1_op: |
1023 | wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + | |
1024 | MIPSInst_SIMM(ir)); | |
b6ee75ed | 1025 | MIPS_FPU_EMU_INC_STATS(stores); |
3f7cac41 RB |
1026 | SIFROMREG(wval, MIPSInst_RT(ir)); |
1027 | if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) { | |
b6ee75ed | 1028 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 1029 | *fault_addr = wva; |
1da177e4 LT |
1030 | return SIGBUS; |
1031 | } | |
3f7cac41 | 1032 | if (__put_user(wval, wva)) { |
515b029d | 1033 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 1034 | *fault_addr = wva; |
515b029d DD |
1035 | return SIGSEGV; |
1036 | } | |
1da177e4 | 1037 | break; |
1da177e4 LT |
1038 | |
1039 | case cop1_op: | |
1040 | switch (MIPSInst_RS(ir)) { | |
1da177e4 | 1041 | case dmfc_op: |
08a07904 RB |
1042 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1043 | return SIGILL; | |
1044 | ||
1da177e4 LT |
1045 | /* copregister fs -> gpr[rt] */ |
1046 | if (MIPSInst_RT(ir) != 0) { | |
1047 | DIFROMREG(xcp->regs[MIPSInst_RT(ir)], | |
1048 | MIPSInst_RD(ir)); | |
1049 | } | |
1050 | break; | |
1051 | ||
1052 | case dmtc_op: | |
08a07904 RB |
1053 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1054 | return SIGILL; | |
1055 | ||
1da177e4 LT |
1056 | /* copregister fs <- rt */ |
1057 | DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); | |
1058 | break; | |
1da177e4 | 1059 | |
1ac94400 LY |
1060 | case mfhc_op: |
1061 | if (!cpu_has_mips_r2) | |
1062 | goto sigill; | |
1063 | ||
1064 | /* copregister rd -> gpr[rt] */ | |
1065 | if (MIPSInst_RT(ir) != 0) { | |
1066 | SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], | |
1067 | MIPSInst_RD(ir)); | |
1068 | } | |
1069 | break; | |
1070 | ||
1071 | case mthc_op: | |
1072 | if (!cpu_has_mips_r2) | |
1073 | goto sigill; | |
1074 | ||
1075 | /* copregister rd <- gpr[rt] */ | |
1076 | SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); | |
1077 | break; | |
1078 | ||
1da177e4 LT |
1079 | case mfc_op: |
1080 | /* copregister rd -> gpr[rt] */ | |
1da177e4 LT |
1081 | if (MIPSInst_RT(ir) != 0) { |
1082 | SIFROMREG(xcp->regs[MIPSInst_RT(ir)], | |
1083 | MIPSInst_RD(ir)); | |
1084 | } | |
1085 | break; | |
1086 | ||
1087 | case mtc_op: | |
1088 | /* copregister rd <- rt */ | |
1da177e4 LT |
1089 | SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); |
1090 | break; | |
1091 | ||
3f7cac41 | 1092 | case cfc_op: |
1da177e4 | 1093 | /* cop control register rd -> gpr[rt] */ |
d4f5b088 | 1094 | cop1_cfc(xcp, ctx, ir); |
1da177e4 | 1095 | break; |
1da177e4 | 1096 | |
3f7cac41 | 1097 | case ctc_op: |
1da177e4 | 1098 | /* copregister rd <- rt */ |
d4f5b088 | 1099 | cop1_ctc(xcp, ctx, ir); |
1da177e4 LT |
1100 | if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { |
1101 | return SIGFPE; | |
1102 | } | |
1103 | break; | |
1da177e4 | 1104 | |
3f7cac41 | 1105 | case bc_op: |
e7e9cae5 | 1106 | if (delay_slot(xcp)) |
1da177e4 LT |
1107 | return SIGILL; |
1108 | ||
08a07904 RB |
1109 | if (cpu_has_mips_4_5_r) |
1110 | cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; | |
1111 | else | |
1112 | cbit = FPU_CSR_COND; | |
1113 | cond = ctx->fcr31 & cbit; | |
1114 | ||
3f7cac41 | 1115 | likely = 0; |
1da177e4 LT |
1116 | switch (MIPSInst_RT(ir) & 3) { |
1117 | case bcfl_op: | |
2d83fea7 MR |
1118 | if (cpu_has_mips_2_3_4_5_r) |
1119 | likely = 1; | |
1120 | /* Fall through */ | |
1da177e4 LT |
1121 | case bcf_op: |
1122 | cond = !cond; | |
1123 | break; | |
1124 | case bctl_op: | |
2d83fea7 MR |
1125 | if (cpu_has_mips_2_3_4_5_r) |
1126 | likely = 1; | |
1127 | /* Fall through */ | |
1da177e4 LT |
1128 | case bct_op: |
1129 | break; | |
1da177e4 LT |
1130 | } |
1131 | ||
e7e9cae5 | 1132 | set_delay_slot(xcp); |
1da177e4 | 1133 | if (cond) { |
3f7cac41 RB |
1134 | /* |
1135 | * Branch taken: emulate dslot instruction | |
1da177e4 | 1136 | */ |
102cedc3 LY |
1137 | xcp->cp0_epc += dec_insn.pc_inc; |
1138 | ||
1139 | contpc = MIPSInst_SIMM(ir); | |
1140 | ir = dec_insn.next_insn; | |
1141 | if (dec_insn.micro_mips_mode) { | |
1142 | contpc = (xcp->cp0_epc + (contpc << 1)); | |
1143 | ||
1144 | /* If 16-bit instruction, not FPU. */ | |
1145 | if ((dec_insn.next_pc_inc == 2) || | |
1146 | (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) { | |
1147 | ||
1148 | /* | |
1149 | * Since this instruction will | |
1150 | * be put on the stack with | |
1151 | * 32-bit words, get around | |
1152 | * this problem by putting a | |
1153 | * NOP16 as the second one. | |
1154 | */ | |
1155 | if (dec_insn.next_pc_inc == 2) | |
1156 | ir = (ir & (~0xffff)) | MM_NOP16; | |
1157 | ||
1158 | /* | |
1159 | * Single step the non-CP1 | |
1160 | * instruction in the dslot. | |
1161 | */ | |
1162 | return mips_dsemul(xcp, ir, contpc); | |
1163 | } | |
1164 | } else | |
1165 | contpc = (xcp->cp0_epc + (contpc << 2)); | |
1da177e4 LT |
1166 | |
1167 | switch (MIPSInst_OPCODE(ir)) { | |
1168 | case lwc1_op: | |
1169 | case swc1_op: | |
08a07904 | 1170 | goto emul; |
3f7cac41 | 1171 | |
1da177e4 LT |
1172 | case ldc1_op: |
1173 | case sdc1_op: | |
2d83fea7 | 1174 | if (cpu_has_mips_2_3_4_5_r) |
08a07904 RB |
1175 | goto emul; |
1176 | ||
1177 | return SIGILL; | |
3f7cac41 | 1178 | |
1da177e4 | 1179 | case cop1_op: |
1da177e4 | 1180 | goto emul; |
3f7cac41 | 1181 | |
08a07904 | 1182 | case cop1x_op: |
2d83fea7 | 1183 | if (cpu_has_mips_4_5_64_r2_r6) |
08a07904 RB |
1184 | /* its one of ours */ |
1185 | goto emul; | |
1186 | ||
1187 | return SIGILL; | |
3f7cac41 | 1188 | |
1da177e4 | 1189 | case spec_op: |
2d83fea7 MR |
1190 | switch (MIPSInst_FUNC(ir)) { |
1191 | case movc_op: | |
1192 | if (cpu_has_mips_4_5_r) | |
1193 | goto emul; | |
08a07904 | 1194 | |
2d83fea7 MR |
1195 | return SIGILL; |
1196 | } | |
1da177e4 | 1197 | break; |
1da177e4 LT |
1198 | } |
1199 | ||
1200 | /* | |
1201 | * Single step the non-cp1 | |
1202 | * instruction in the dslot | |
1203 | */ | |
e70dfc10 | 1204 | return mips_dsemul(xcp, ir, contpc); |
3f7cac41 | 1205 | } else if (likely) { /* branch not taken */ |
5d77cf28 MR |
1206 | /* |
1207 | * branch likely nullifies | |
1208 | * dslot if not taken | |
1209 | */ | |
1210 | xcp->cp0_epc += dec_insn.pc_inc; | |
1211 | contpc += dec_insn.pc_inc; | |
1212 | /* | |
1213 | * else continue & execute | |
1214 | * dslot as normal insn | |
1215 | */ | |
1216 | } | |
1da177e4 | 1217 | break; |
1da177e4 LT |
1218 | |
1219 | default: | |
1220 | if (!(MIPSInst_RS(ir) & 0x10)) | |
1221 | return SIGILL; | |
1da177e4 | 1222 | |
3f7cac41 RB |
1223 | /* a real fpu computation instruction */ |
1224 | if ((sig = fpu_emu(xcp, ctx, ir))) | |
1225 | return sig; | |
1da177e4 LT |
1226 | } |
1227 | break; | |
1228 | ||
3f7cac41 | 1229 | case cop1x_op: |
2d83fea7 | 1230 | if (!cpu_has_mips_4_5_64_r2_r6) |
08a07904 RB |
1231 | return SIGILL; |
1232 | ||
1233 | sig = fpux_emu(xcp, ctx, ir, fault_addr); | |
515b029d | 1234 | if (sig) |
1da177e4 LT |
1235 | return sig; |
1236 | break; | |
1da177e4 | 1237 | |
1da177e4 | 1238 | case spec_op: |
08a07904 RB |
1239 | if (!cpu_has_mips_4_5_r) |
1240 | return SIGILL; | |
1241 | ||
1da177e4 LT |
1242 | if (MIPSInst_FUNC(ir) != movc_op) |
1243 | return SIGILL; | |
1244 | cond = fpucondbit[MIPSInst_RT(ir) >> 2]; | |
1245 | if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) | |
1246 | xcp->regs[MIPSInst_RD(ir)] = | |
1247 | xcp->regs[MIPSInst_RS(ir)]; | |
1248 | break; | |
1da177e4 | 1249 | default: |
1ac94400 | 1250 | sigill: |
1da177e4 LT |
1251 | return SIGILL; |
1252 | } | |
1253 | ||
1254 | /* we did it !! */ | |
e70dfc10 | 1255 | xcp->cp0_epc = contpc; |
e7e9cae5 | 1256 | clear_delay_slot(xcp); |
333d1f67 | 1257 | |
1da177e4 LT |
1258 | return 0; |
1259 | } | |
1260 | ||
1261 | /* | |
1262 | * Conversion table from MIPS compare ops 48-63 | |
1263 | * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig); | |
1264 | */ | |
1265 | static const unsigned char cmptab[8] = { | |
1266 | 0, /* cmp_0 (sig) cmp_sf */ | |
1267 | IEEE754_CUN, /* cmp_un (sig) cmp_ngle */ | |
1268 | IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */ | |
1269 | IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */ | |
1270 | IEEE754_CLT, /* cmp_olt (sig) cmp_lt */ | |
1271 | IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */ | |
1272 | IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */ | |
1273 | IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */ | |
1274 | }; | |
1275 | ||
1276 | ||
1da177e4 LT |
1277 | /* |
1278 | * Additional MIPS4 instructions | |
1279 | */ | |
1280 | ||
47fa0c02 RB |
1281 | #define DEF3OP(name, p, f1, f2, f3) \ |
1282 | static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \ | |
1283 | union ieee754##p s, union ieee754##p t) \ | |
1284 | { \ | |
1285 | struct _ieee754_csr ieee754_csr_save; \ | |
1286 | s = f1(s, t); \ | |
1287 | ieee754_csr_save = ieee754_csr; \ | |
1288 | s = f2(s, r); \ | |
1289 | ieee754_csr_save.cx |= ieee754_csr.cx; \ | |
1290 | ieee754_csr_save.sx |= ieee754_csr.sx; \ | |
1291 | s = f3(s); \ | |
1292 | ieee754_csr.cx |= ieee754_csr_save.cx; \ | |
1293 | ieee754_csr.sx |= ieee754_csr_save.sx; \ | |
1294 | return s; \ | |
1da177e4 LT |
1295 | } |
1296 | ||
2209bcb1 | 1297 | static union ieee754dp fpemu_dp_recip(union ieee754dp d) |
1da177e4 LT |
1298 | { |
1299 | return ieee754dp_div(ieee754dp_one(0), d); | |
1300 | } | |
1301 | ||
2209bcb1 | 1302 | static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d) |
1da177e4 LT |
1303 | { |
1304 | return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d)); | |
1305 | } | |
1306 | ||
2209bcb1 | 1307 | static union ieee754sp fpemu_sp_recip(union ieee754sp s) |
1da177e4 LT |
1308 | { |
1309 | return ieee754sp_div(ieee754sp_one(0), s); | |
1310 | } | |
1311 | ||
2209bcb1 | 1312 | static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s) |
1da177e4 LT |
1313 | { |
1314 | return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); | |
1315 | } | |
1316 | ||
21a151d8 RB |
1317 | DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, ); |
1318 | DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, ); | |
1da177e4 LT |
1319 | DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); |
1320 | DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); | |
21a151d8 RB |
1321 | DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, ); |
1322 | DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, ); | |
1da177e4 LT |
1323 | DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); |
1324 | DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); | |
1325 | ||
eae89076 | 1326 | static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
515b029d | 1327 | mips_instruction ir, void *__user *fault_addr) |
1da177e4 LT |
1328 | { |
1329 | unsigned rcsr = 0; /* resulting csr */ | |
1330 | ||
b6ee75ed | 1331 | MIPS_FPU_EMU_INC_STATS(cp1xops); |
1da177e4 LT |
1332 | |
1333 | switch (MIPSInst_FMA_FFMT(ir)) { | |
1334 | case s_fmt:{ /* 0 */ | |
1335 | ||
2209bcb1 RB |
1336 | union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp); |
1337 | union ieee754sp fd, fr, fs, ft; | |
3fccc015 | 1338 | u32 __user *va; |
1da177e4 LT |
1339 | u32 val; |
1340 | ||
1341 | switch (MIPSInst_FUNC(ir)) { | |
1342 | case lwxc1_op: | |
3fccc015 | 1343 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1344 | xcp->regs[MIPSInst_FT(ir)]); |
1345 | ||
b6ee75ed | 1346 | MIPS_FPU_EMU_INC_STATS(loads); |
515b029d | 1347 | if (!access_ok(VERIFY_READ, va, sizeof(u32))) { |
b6ee75ed | 1348 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1349 | *fault_addr = va; |
1da177e4 LT |
1350 | return SIGBUS; |
1351 | } | |
515b029d DD |
1352 | if (__get_user(val, va)) { |
1353 | MIPS_FPU_EMU_INC_STATS(errors); | |
1354 | *fault_addr = va; | |
1355 | return SIGSEGV; | |
1356 | } | |
1da177e4 LT |
1357 | SITOREG(val, MIPSInst_FD(ir)); |
1358 | break; | |
1359 | ||
1360 | case swxc1_op: | |
3fccc015 | 1361 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1362 | xcp->regs[MIPSInst_FT(ir)]); |
1363 | ||
b6ee75ed | 1364 | MIPS_FPU_EMU_INC_STATS(stores); |
1da177e4 LT |
1365 | |
1366 | SIFROMREG(val, MIPSInst_FS(ir)); | |
515b029d | 1367 | if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { |
b6ee75ed | 1368 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1369 | *fault_addr = va; |
1da177e4 LT |
1370 | return SIGBUS; |
1371 | } | |
515b029d DD |
1372 | if (put_user(val, va)) { |
1373 | MIPS_FPU_EMU_INC_STATS(errors); | |
1374 | *fault_addr = va; | |
1375 | return SIGSEGV; | |
1376 | } | |
1da177e4 LT |
1377 | break; |
1378 | ||
1379 | case madd_s_op: | |
1380 | handler = fpemu_sp_madd; | |
1381 | goto scoptop; | |
1382 | case msub_s_op: | |
1383 | handler = fpemu_sp_msub; | |
1384 | goto scoptop; | |
1385 | case nmadd_s_op: | |
1386 | handler = fpemu_sp_nmadd; | |
1387 | goto scoptop; | |
1388 | case nmsub_s_op: | |
1389 | handler = fpemu_sp_nmsub; | |
1390 | goto scoptop; | |
1391 | ||
1392 | scoptop: | |
1393 | SPFROMREG(fr, MIPSInst_FR(ir)); | |
1394 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1395 | SPFROMREG(ft, MIPSInst_FT(ir)); | |
1396 | fd = (*handler) (fr, fs, ft); | |
1397 | SPTOREG(fd, MIPSInst_FD(ir)); | |
1398 | ||
1399 | copcsr: | |
c4103526 DCZ |
1400 | if (ieee754_cxtest(IEEE754_INEXACT)) { |
1401 | MIPS_FPU_EMU_INC_STATS(ieee754_inexact); | |
1da177e4 | 1402 | rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; |
c4103526 DCZ |
1403 | } |
1404 | if (ieee754_cxtest(IEEE754_UNDERFLOW)) { | |
1405 | MIPS_FPU_EMU_INC_STATS(ieee754_underflow); | |
1da177e4 | 1406 | rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; |
c4103526 DCZ |
1407 | } |
1408 | if (ieee754_cxtest(IEEE754_OVERFLOW)) { | |
1409 | MIPS_FPU_EMU_INC_STATS(ieee754_overflow); | |
1da177e4 | 1410 | rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; |
c4103526 DCZ |
1411 | } |
1412 | if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { | |
1413 | MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); | |
1da177e4 | 1414 | rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; |
c4103526 | 1415 | } |
1da177e4 LT |
1416 | |
1417 | ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; | |
1da177e4 | 1418 | if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { |
3f7cac41 | 1419 | /*printk ("SIGFPE: FPU csr = %08x\n", |
1da177e4 LT |
1420 | ctx->fcr31); */ |
1421 | return SIGFPE; | |
1422 | } | |
1423 | ||
1424 | break; | |
1425 | ||
1426 | default: | |
1427 | return SIGILL; | |
1428 | } | |
1429 | break; | |
1430 | } | |
1431 | ||
1da177e4 | 1432 | case d_fmt:{ /* 1 */ |
2209bcb1 RB |
1433 | union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp); |
1434 | union ieee754dp fd, fr, fs, ft; | |
3fccc015 | 1435 | u64 __user *va; |
1da177e4 LT |
1436 | u64 val; |
1437 | ||
1438 | switch (MIPSInst_FUNC(ir)) { | |
1439 | case ldxc1_op: | |
3fccc015 | 1440 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1441 | xcp->regs[MIPSInst_FT(ir)]); |
1442 | ||
b6ee75ed | 1443 | MIPS_FPU_EMU_INC_STATS(loads); |
515b029d | 1444 | if (!access_ok(VERIFY_READ, va, sizeof(u64))) { |
b6ee75ed | 1445 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1446 | *fault_addr = va; |
1da177e4 LT |
1447 | return SIGBUS; |
1448 | } | |
515b029d DD |
1449 | if (__get_user(val, va)) { |
1450 | MIPS_FPU_EMU_INC_STATS(errors); | |
1451 | *fault_addr = va; | |
1452 | return SIGSEGV; | |
1453 | } | |
1da177e4 LT |
1454 | DITOREG(val, MIPSInst_FD(ir)); |
1455 | break; | |
1456 | ||
1457 | case sdxc1_op: | |
3fccc015 | 1458 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1459 | xcp->regs[MIPSInst_FT(ir)]); |
1460 | ||
b6ee75ed | 1461 | MIPS_FPU_EMU_INC_STATS(stores); |
1da177e4 | 1462 | DIFROMREG(val, MIPSInst_FS(ir)); |
515b029d | 1463 | if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { |
b6ee75ed | 1464 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1465 | *fault_addr = va; |
1da177e4 LT |
1466 | return SIGBUS; |
1467 | } | |
515b029d DD |
1468 | if (__put_user(val, va)) { |
1469 | MIPS_FPU_EMU_INC_STATS(errors); | |
1470 | *fault_addr = va; | |
1471 | return SIGSEGV; | |
1472 | } | |
1da177e4 LT |
1473 | break; |
1474 | ||
1475 | case madd_d_op: | |
1476 | handler = fpemu_dp_madd; | |
1477 | goto dcoptop; | |
1478 | case msub_d_op: | |
1479 | handler = fpemu_dp_msub; | |
1480 | goto dcoptop; | |
1481 | case nmadd_d_op: | |
1482 | handler = fpemu_dp_nmadd; | |
1483 | goto dcoptop; | |
1484 | case nmsub_d_op: | |
1485 | handler = fpemu_dp_nmsub; | |
1486 | goto dcoptop; | |
1487 | ||
1488 | dcoptop: | |
1489 | DPFROMREG(fr, MIPSInst_FR(ir)); | |
1490 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1491 | DPFROMREG(ft, MIPSInst_FT(ir)); | |
1492 | fd = (*handler) (fr, fs, ft); | |
1493 | DPTOREG(fd, MIPSInst_FD(ir)); | |
1494 | goto copcsr; | |
1495 | ||
1496 | default: | |
1497 | return SIGILL; | |
1498 | } | |
1499 | break; | |
1500 | } | |
1da177e4 | 1501 | |
51061b88 DCZ |
1502 | case 0x3: |
1503 | if (MIPSInst_FUNC(ir) != pfetch_op) | |
1da177e4 | 1504 | return SIGILL; |
51061b88 | 1505 | |
1da177e4 LT |
1506 | /* ignore prefx operation */ |
1507 | break; | |
1508 | ||
1509 | default: | |
1510 | return SIGILL; | |
1511 | } | |
1512 | ||
1513 | return 0; | |
1514 | } | |
1da177e4 LT |
1515 | |
1516 | ||
1517 | ||
1518 | /* | |
1519 | * Emulate a single COP1 arithmetic instruction. | |
1520 | */ | |
eae89076 | 1521 | static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
1da177e4 LT |
1522 | mips_instruction ir) |
1523 | { | |
1524 | int rfmt; /* resulting format */ | |
1525 | unsigned rcsr = 0; /* resulting csr */ | |
3f7cac41 RB |
1526 | unsigned int oldrm; |
1527 | unsigned int cbit; | |
1da177e4 LT |
1528 | unsigned cond; |
1529 | union { | |
2209bcb1 RB |
1530 | union ieee754dp d; |
1531 | union ieee754sp s; | |
1da177e4 | 1532 | int w; |
1da177e4 | 1533 | s64 l; |
1da177e4 | 1534 | } rv; /* resulting value */ |
3f7cac41 | 1535 | u64 bits; |
1da177e4 | 1536 | |
b6ee75ed | 1537 | MIPS_FPU_EMU_INC_STATS(cp1ops); |
1da177e4 | 1538 | switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { |
3f7cac41 | 1539 | case s_fmt: { /* 0 */ |
1da177e4 | 1540 | union { |
2209bcb1 RB |
1541 | union ieee754sp(*b) (union ieee754sp, union ieee754sp); |
1542 | union ieee754sp(*u) (union ieee754sp); | |
1da177e4 | 1543 | } handler; |
3f7cac41 | 1544 | union ieee754sp fs, ft; |
1da177e4 LT |
1545 | |
1546 | switch (MIPSInst_FUNC(ir)) { | |
1547 | /* binary ops */ | |
1548 | case fadd_op: | |
1549 | handler.b = ieee754sp_add; | |
1550 | goto scopbop; | |
1551 | case fsub_op: | |
1552 | handler.b = ieee754sp_sub; | |
1553 | goto scopbop; | |
1554 | case fmul_op: | |
1555 | handler.b = ieee754sp_mul; | |
1556 | goto scopbop; | |
1557 | case fdiv_op: | |
1558 | handler.b = ieee754sp_div; | |
1559 | goto scopbop; | |
1560 | ||
1561 | /* unary ops */ | |
1da177e4 | 1562 | case fsqrt_op: |
2d83fea7 | 1563 | if (!cpu_has_mips_2_3_4_5_r) |
08a07904 RB |
1564 | return SIGILL; |
1565 | ||
1da177e4 LT |
1566 | handler.u = ieee754sp_sqrt; |
1567 | goto scopuop; | |
3f7cac41 | 1568 | |
08a07904 RB |
1569 | /* |
1570 | * Note that on some MIPS IV implementations such as the | |
1571 | * R5000 and R8000 the FSQRT and FRECIP instructions do not | |
1572 | * achieve full IEEE-754 accuracy - however this emulator does. | |
1573 | */ | |
1da177e4 | 1574 | case frsqrt_op: |
2d83fea7 | 1575 | if (!cpu_has_mips_4_5_64_r2_r6) |
08a07904 RB |
1576 | return SIGILL; |
1577 | ||
1da177e4 LT |
1578 | handler.u = fpemu_sp_rsqrt; |
1579 | goto scopuop; | |
3f7cac41 | 1580 | |
1da177e4 | 1581 | case frecip_op: |
2d83fea7 | 1582 | if (!cpu_has_mips_4_5_64_r2_r6) |
08a07904 RB |
1583 | return SIGILL; |
1584 | ||
1da177e4 LT |
1585 | handler.u = fpemu_sp_recip; |
1586 | goto scopuop; | |
08a07904 | 1587 | |
1da177e4 | 1588 | case fmovc_op: |
08a07904 RB |
1589 | if (!cpu_has_mips_4_5_r) |
1590 | return SIGILL; | |
1591 | ||
1da177e4 LT |
1592 | cond = fpucondbit[MIPSInst_FT(ir) >> 2]; |
1593 | if (((ctx->fcr31 & cond) != 0) != | |
1594 | ((MIPSInst_FT(ir) & 1) != 0)) | |
1595 | return 0; | |
1596 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1597 | break; | |
3f7cac41 | 1598 | |
1da177e4 | 1599 | case fmovz_op: |
08a07904 RB |
1600 | if (!cpu_has_mips_4_5_r) |
1601 | return SIGILL; | |
1602 | ||
1da177e4 LT |
1603 | if (xcp->regs[MIPSInst_FT(ir)] != 0) |
1604 | return 0; | |
1605 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1606 | break; | |
3f7cac41 | 1607 | |
1da177e4 | 1608 | case fmovn_op: |
08a07904 RB |
1609 | if (!cpu_has_mips_4_5_r) |
1610 | return SIGILL; | |
1611 | ||
1da177e4 LT |
1612 | if (xcp->regs[MIPSInst_FT(ir)] == 0) |
1613 | return 0; | |
1614 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1615 | break; | |
3f7cac41 | 1616 | |
1da177e4 LT |
1617 | case fabs_op: |
1618 | handler.u = ieee754sp_abs; | |
1619 | goto scopuop; | |
3f7cac41 | 1620 | |
1da177e4 LT |
1621 | case fneg_op: |
1622 | handler.u = ieee754sp_neg; | |
1623 | goto scopuop; | |
3f7cac41 | 1624 | |
1da177e4 LT |
1625 | case fmov_op: |
1626 | /* an easy one */ | |
1627 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1628 | goto copcsr; | |
1629 | ||
1630 | /* binary op on handler */ | |
3f7cac41 RB |
1631 | scopbop: |
1632 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1633 | SPFROMREG(ft, MIPSInst_FT(ir)); | |
1da177e4 | 1634 | |
3f7cac41 RB |
1635 | rv.s = (*handler.b) (fs, ft); |
1636 | goto copcsr; | |
1637 | scopuop: | |
1638 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1639 | rv.s = (*handler.u) (fs); | |
1640 | goto copcsr; | |
1641 | copcsr: | |
c4103526 DCZ |
1642 | if (ieee754_cxtest(IEEE754_INEXACT)) { |
1643 | MIPS_FPU_EMU_INC_STATS(ieee754_inexact); | |
1da177e4 | 1644 | rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; |
c4103526 DCZ |
1645 | } |
1646 | if (ieee754_cxtest(IEEE754_UNDERFLOW)) { | |
1647 | MIPS_FPU_EMU_INC_STATS(ieee754_underflow); | |
1da177e4 | 1648 | rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; |
c4103526 DCZ |
1649 | } |
1650 | if (ieee754_cxtest(IEEE754_OVERFLOW)) { | |
1651 | MIPS_FPU_EMU_INC_STATS(ieee754_overflow); | |
1da177e4 | 1652 | rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; |
c4103526 DCZ |
1653 | } |
1654 | if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) { | |
1655 | MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv); | |
1da177e4 | 1656 | rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S; |
c4103526 DCZ |
1657 | } |
1658 | if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { | |
1659 | MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); | |
1da177e4 | 1660 | rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; |
c4103526 | 1661 | } |
1da177e4 LT |
1662 | break; |
1663 | ||
1664 | /* unary conv ops */ | |
1665 | case fcvts_op: | |
1666 | return SIGILL; /* not defined */ | |
1da177e4 | 1667 | |
3f7cac41 | 1668 | case fcvtd_op: |
1da177e4 LT |
1669 | SPFROMREG(fs, MIPSInst_FS(ir)); |
1670 | rv.d = ieee754dp_fsp(fs); | |
1671 | rfmt = d_fmt; | |
1672 | goto copcsr; | |
1da177e4 | 1673 | |
3f7cac41 | 1674 | case fcvtw_op: |
1da177e4 LT |
1675 | SPFROMREG(fs, MIPSInst_FS(ir)); |
1676 | rv.w = ieee754sp_tint(fs); | |
1677 | rfmt = w_fmt; | |
1678 | goto copcsr; | |
1da177e4 | 1679 | |
1da177e4 LT |
1680 | case fround_op: |
1681 | case ftrunc_op: | |
1682 | case fceil_op: | |
3f7cac41 | 1683 | case ffloor_op: |
2d83fea7 | 1684 | if (!cpu_has_mips_2_3_4_5_r) |
08a07904 RB |
1685 | return SIGILL; |
1686 | ||
3f7cac41 | 1687 | oldrm = ieee754_csr.rm; |
1da177e4 | 1688 | SPFROMREG(fs, MIPSInst_FS(ir)); |
2cfcf8a8 | 1689 | ieee754_csr.rm = MIPSInst_FUNC(ir); |
1da177e4 LT |
1690 | rv.w = ieee754sp_tint(fs); |
1691 | ieee754_csr.rm = oldrm; | |
1692 | rfmt = w_fmt; | |
1693 | goto copcsr; | |
1da177e4 | 1694 | |
3f7cac41 | 1695 | case fcvtl_op: |
2d83fea7 | 1696 | if (!cpu_has_mips_3_4_5_64_r2_r6) |
08a07904 RB |
1697 | return SIGILL; |
1698 | ||
1da177e4 LT |
1699 | SPFROMREG(fs, MIPSInst_FS(ir)); |
1700 | rv.l = ieee754sp_tlong(fs); | |
1701 | rfmt = l_fmt; | |
1702 | goto copcsr; | |
1da177e4 LT |
1703 | |
1704 | case froundl_op: | |
1705 | case ftruncl_op: | |
1706 | case fceill_op: | |
3f7cac41 | 1707 | case ffloorl_op: |
2d83fea7 | 1708 | if (!cpu_has_mips_3_4_5_64_r2_r6) |
08a07904 RB |
1709 | return SIGILL; |
1710 | ||
3f7cac41 | 1711 | oldrm = ieee754_csr.rm; |
1da177e4 | 1712 | SPFROMREG(fs, MIPSInst_FS(ir)); |
2cfcf8a8 | 1713 | ieee754_csr.rm = MIPSInst_FUNC(ir); |
1da177e4 LT |
1714 | rv.l = ieee754sp_tlong(fs); |
1715 | ieee754_csr.rm = oldrm; | |
1716 | rfmt = l_fmt; | |
1717 | goto copcsr; | |
1da177e4 LT |
1718 | |
1719 | default: | |
1720 | if (MIPSInst_FUNC(ir) >= fcmp_op) { | |
1721 | unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; | |
2209bcb1 | 1722 | union ieee754sp fs, ft; |
1da177e4 LT |
1723 | |
1724 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1725 | SPFROMREG(ft, MIPSInst_FT(ir)); | |
1726 | rv.w = ieee754sp_cmp(fs, ft, | |
1727 | cmptab[cmpop & 0x7], cmpop & 0x8); | |
1728 | rfmt = -1; | |
1729 | if ((cmpop & 0x8) && ieee754_cxtest | |
1730 | (IEEE754_INVALID_OPERATION)) | |
1731 | rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; | |
1732 | else | |
1733 | goto copcsr; | |
1734 | ||
3f7cac41 | 1735 | } else |
1da177e4 | 1736 | return SIGILL; |
1da177e4 LT |
1737 | break; |
1738 | } | |
1739 | break; | |
1740 | } | |
1741 | ||
3f7cac41 RB |
1742 | case d_fmt: { |
1743 | union ieee754dp fs, ft; | |
1da177e4 | 1744 | union { |
2209bcb1 RB |
1745 | union ieee754dp(*b) (union ieee754dp, union ieee754dp); |
1746 | union ieee754dp(*u) (union ieee754dp); | |
1da177e4 LT |
1747 | } handler; |
1748 | ||
1749 | switch (MIPSInst_FUNC(ir)) { | |
1750 | /* binary ops */ | |
1751 | case fadd_op: | |
1752 | handler.b = ieee754dp_add; | |
1753 | goto dcopbop; | |
1754 | case fsub_op: | |
1755 | handler.b = ieee754dp_sub; | |
1756 | goto dcopbop; | |
1757 | case fmul_op: | |
1758 | handler.b = ieee754dp_mul; | |
1759 | goto dcopbop; | |
1760 | case fdiv_op: | |
1761 | handler.b = ieee754dp_div; | |
1762 | goto dcopbop; | |
1763 | ||
1764 | /* unary ops */ | |
1da177e4 | 1765 | case fsqrt_op: |
08a07904 RB |
1766 | if (!cpu_has_mips_2_3_4_5_r) |
1767 | return SIGILL; | |
1768 | ||
1da177e4 LT |
1769 | handler.u = ieee754dp_sqrt; |
1770 | goto dcopuop; | |
08a07904 RB |
1771 | /* |
1772 | * Note that on some MIPS IV implementations such as the | |
1773 | * R5000 and R8000 the FSQRT and FRECIP instructions do not | |
1774 | * achieve full IEEE-754 accuracy - however this emulator does. | |
1775 | */ | |
1da177e4 | 1776 | case frsqrt_op: |
2d83fea7 | 1777 | if (!cpu_has_mips_4_5_64_r2_r6) |
08a07904 RB |
1778 | return SIGILL; |
1779 | ||
1da177e4 LT |
1780 | handler.u = fpemu_dp_rsqrt; |
1781 | goto dcopuop; | |
1782 | case frecip_op: | |
2d83fea7 | 1783 | if (!cpu_has_mips_4_5_64_r2_r6) |
08a07904 RB |
1784 | return SIGILL; |
1785 | ||
1da177e4 LT |
1786 | handler.u = fpemu_dp_recip; |
1787 | goto dcopuop; | |
1da177e4 | 1788 | case fmovc_op: |
08a07904 RB |
1789 | if (!cpu_has_mips_4_5_r) |
1790 | return SIGILL; | |
1791 | ||
1da177e4 LT |
1792 | cond = fpucondbit[MIPSInst_FT(ir) >> 2]; |
1793 | if (((ctx->fcr31 & cond) != 0) != | |
1794 | ((MIPSInst_FT(ir) & 1) != 0)) | |
1795 | return 0; | |
1796 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1797 | break; | |
1798 | case fmovz_op: | |
08a07904 RB |
1799 | if (!cpu_has_mips_4_5_r) |
1800 | return SIGILL; | |
1801 | ||
1da177e4 LT |
1802 | if (xcp->regs[MIPSInst_FT(ir)] != 0) |
1803 | return 0; | |
1804 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1805 | break; | |
1806 | case fmovn_op: | |
08a07904 RB |
1807 | if (!cpu_has_mips_4_5_r) |
1808 | return SIGILL; | |
1809 | ||
1da177e4 LT |
1810 | if (xcp->regs[MIPSInst_FT(ir)] == 0) |
1811 | return 0; | |
1812 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1813 | break; | |
1da177e4 LT |
1814 | case fabs_op: |
1815 | handler.u = ieee754dp_abs; | |
1816 | goto dcopuop; | |
1817 | ||
1818 | case fneg_op: | |
1819 | handler.u = ieee754dp_neg; | |
1820 | goto dcopuop; | |
1821 | ||
1822 | case fmov_op: | |
1823 | /* an easy one */ | |
1824 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1825 | goto copcsr; | |
1826 | ||
1827 | /* binary op on handler */ | |
3f7cac41 RB |
1828 | dcopbop: |
1829 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1830 | DPFROMREG(ft, MIPSInst_FT(ir)); | |
1da177e4 | 1831 | |
3f7cac41 RB |
1832 | rv.d = (*handler.b) (fs, ft); |
1833 | goto copcsr; | |
1834 | dcopuop: | |
1835 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1836 | rv.d = (*handler.u) (fs); | |
1837 | goto copcsr; | |
1da177e4 | 1838 | |
3f7cac41 RB |
1839 | /* |
1840 | * unary conv ops | |
1841 | */ | |
1842 | case fcvts_op: | |
1da177e4 LT |
1843 | DPFROMREG(fs, MIPSInst_FS(ir)); |
1844 | rv.s = ieee754sp_fdp(fs); | |
1845 | rfmt = s_fmt; | |
1846 | goto copcsr; | |
3f7cac41 | 1847 | |
1da177e4 LT |
1848 | case fcvtd_op: |
1849 | return SIGILL; /* not defined */ | |
1850 | ||
3f7cac41 | 1851 | case fcvtw_op: |
1da177e4 LT |
1852 | DPFROMREG(fs, MIPSInst_FS(ir)); |
1853 | rv.w = ieee754dp_tint(fs); /* wrong */ | |
1854 | rfmt = w_fmt; | |
1855 | goto copcsr; | |
1da177e4 | 1856 | |
1da177e4 LT |
1857 | case fround_op: |
1858 | case ftrunc_op: | |
1859 | case fceil_op: | |
3f7cac41 | 1860 | case ffloor_op: |
08a07904 RB |
1861 | if (!cpu_has_mips_2_3_4_5_r) |
1862 | return SIGILL; | |
1863 | ||
3f7cac41 | 1864 | oldrm = ieee754_csr.rm; |
1da177e4 | 1865 | DPFROMREG(fs, MIPSInst_FS(ir)); |
2cfcf8a8 | 1866 | ieee754_csr.rm = MIPSInst_FUNC(ir); |
1da177e4 LT |
1867 | rv.w = ieee754dp_tint(fs); |
1868 | ieee754_csr.rm = oldrm; | |
1869 | rfmt = w_fmt; | |
1870 | goto copcsr; | |
1da177e4 | 1871 | |
3f7cac41 | 1872 | case fcvtl_op: |
2d83fea7 | 1873 | if (!cpu_has_mips_3_4_5_64_r2_r6) |
08a07904 RB |
1874 | return SIGILL; |
1875 | ||
1da177e4 LT |
1876 | DPFROMREG(fs, MIPSInst_FS(ir)); |
1877 | rv.l = ieee754dp_tlong(fs); | |
1878 | rfmt = l_fmt; | |
1879 | goto copcsr; | |
1da177e4 LT |
1880 | |
1881 | case froundl_op: | |
1882 | case ftruncl_op: | |
1883 | case fceill_op: | |
3f7cac41 | 1884 | case ffloorl_op: |
2d83fea7 | 1885 | if (!cpu_has_mips_3_4_5_64_r2_r6) |
08a07904 RB |
1886 | return SIGILL; |
1887 | ||
3f7cac41 | 1888 | oldrm = ieee754_csr.rm; |
1da177e4 | 1889 | DPFROMREG(fs, MIPSInst_FS(ir)); |
2cfcf8a8 | 1890 | ieee754_csr.rm = MIPSInst_FUNC(ir); |
1da177e4 LT |
1891 | rv.l = ieee754dp_tlong(fs); |
1892 | ieee754_csr.rm = oldrm; | |
1893 | rfmt = l_fmt; | |
1894 | goto copcsr; | |
1da177e4 LT |
1895 | |
1896 | default: | |
1897 | if (MIPSInst_FUNC(ir) >= fcmp_op) { | |
1898 | unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; | |
2209bcb1 | 1899 | union ieee754dp fs, ft; |
1da177e4 LT |
1900 | |
1901 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1902 | DPFROMREG(ft, MIPSInst_FT(ir)); | |
1903 | rv.w = ieee754dp_cmp(fs, ft, | |
1904 | cmptab[cmpop & 0x7], cmpop & 0x8); | |
1905 | rfmt = -1; | |
1906 | if ((cmpop & 0x8) | |
1907 | && | |
1908 | ieee754_cxtest | |
1909 | (IEEE754_INVALID_OPERATION)) | |
1910 | rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; | |
1911 | else | |
1912 | goto copcsr; | |
1913 | ||
1914 | } | |
1915 | else { | |
1916 | return SIGILL; | |
1917 | } | |
1918 | break; | |
1919 | } | |
1920 | break; | |
1da177e4 | 1921 | |
3f7cac41 | 1922 | case w_fmt: |
1da177e4 LT |
1923 | switch (MIPSInst_FUNC(ir)) { |
1924 | case fcvts_op: | |
1925 | /* convert word to single precision real */ | |
1926 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1927 | rv.s = ieee754sp_fint(fs.bits); | |
1928 | rfmt = s_fmt; | |
1929 | goto copcsr; | |
1da177e4 LT |
1930 | case fcvtd_op: |
1931 | /* convert word to double precision real */ | |
1932 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1933 | rv.d = ieee754dp_fint(fs.bits); | |
1934 | rfmt = d_fmt; | |
1935 | goto copcsr; | |
1da177e4 LT |
1936 | default: |
1937 | return SIGILL; | |
1938 | } | |
1939 | break; | |
1940 | } | |
1941 | ||
3f7cac41 | 1942 | case l_fmt: |
08a07904 | 1943 | |
2d83fea7 | 1944 | if (!cpu_has_mips_3_4_5_64_r2_r6) |
08a07904 RB |
1945 | return SIGILL; |
1946 | ||
bbd426f5 PB |
1947 | DIFROMREG(bits, MIPSInst_FS(ir)); |
1948 | ||
1da177e4 LT |
1949 | switch (MIPSInst_FUNC(ir)) { |
1950 | case fcvts_op: | |
1951 | /* convert long to single precision real */ | |
bbd426f5 | 1952 | rv.s = ieee754sp_flong(bits); |
1da177e4 LT |
1953 | rfmt = s_fmt; |
1954 | goto copcsr; | |
1955 | case fcvtd_op: | |
1956 | /* convert long to double precision real */ | |
bbd426f5 | 1957 | rv.d = ieee754dp_flong(bits); |
1da177e4 LT |
1958 | rfmt = d_fmt; |
1959 | goto copcsr; | |
1960 | default: | |
1961 | return SIGILL; | |
1962 | } | |
1963 | break; | |
1da177e4 LT |
1964 | |
1965 | default: | |
1966 | return SIGILL; | |
1967 | } | |
1968 | ||
1969 | /* | |
1970 | * Update the fpu CSR register for this operation. | |
1971 | * If an exception is required, generate a tidy SIGFPE exception, | |
1972 | * without updating the result register. | |
1973 | * Note: cause exception bits do not accumulate, they are rewritten | |
1974 | * for each op; only the flag/sticky bits accumulate. | |
1975 | */ | |
1976 | ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; | |
1977 | if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { | |
3f7cac41 | 1978 | /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */ |
1da177e4 LT |
1979 | return SIGFPE; |
1980 | } | |
1981 | ||
1982 | /* | |
1983 | * Now we can safely write the result back to the register file. | |
1984 | */ | |
1985 | switch (rfmt) { | |
08a07904 RB |
1986 | case -1: |
1987 | ||
1988 | if (cpu_has_mips_4_5_r) | |
c3b9b945 | 1989 | cbit = fpucondbit[MIPSInst_FD(ir) >> 2]; |
08a07904 RB |
1990 | else |
1991 | cbit = FPU_CSR_COND; | |
1da177e4 | 1992 | if (rv.w) |
08a07904 | 1993 | ctx->fcr31 |= cbit; |
1da177e4 | 1994 | else |
08a07904 | 1995 | ctx->fcr31 &= ~cbit; |
1da177e4 | 1996 | break; |
08a07904 | 1997 | |
1da177e4 LT |
1998 | case d_fmt: |
1999 | DPTOREG(rv.d, MIPSInst_FD(ir)); | |
2000 | break; | |
1da177e4 LT |
2001 | case s_fmt: |
2002 | SPTOREG(rv.s, MIPSInst_FD(ir)); | |
2003 | break; | |
2004 | case w_fmt: | |
2005 | SITOREG(rv.w, MIPSInst_FD(ir)); | |
2006 | break; | |
1da177e4 | 2007 | case l_fmt: |
2d83fea7 | 2008 | if (!cpu_has_mips_3_4_5_64_r2_r6) |
08a07904 RB |
2009 | return SIGILL; |
2010 | ||
1da177e4 LT |
2011 | DITOREG(rv.l, MIPSInst_FD(ir)); |
2012 | break; | |
1da177e4 LT |
2013 | default: |
2014 | return SIGILL; | |
2015 | } | |
2016 | ||
2017 | return 0; | |
2018 | } | |
2019 | ||
e04582b7 | 2020 | int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
515b029d | 2021 | int has_fpu, void *__user *fault_addr) |
1da177e4 | 2022 | { |
333d1f67 | 2023 | unsigned long oldepc, prevepc; |
102cedc3 LY |
2024 | struct mm_decoded_insn dec_insn; |
2025 | u16 instr[4]; | |
2026 | u16 *instr_ptr; | |
1da177e4 LT |
2027 | int sig = 0; |
2028 | ||
2029 | oldepc = xcp->cp0_epc; | |
2030 | do { | |
2031 | prevepc = xcp->cp0_epc; | |
2032 | ||
102cedc3 LY |
2033 | if (get_isa16_mode(prevepc) && cpu_has_mmips) { |
2034 | /* | |
2035 | * Get next 2 microMIPS instructions and convert them | |
2036 | * into 32-bit instructions. | |
2037 | */ | |
2038 | if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) || | |
2039 | (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) || | |
2040 | (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) || | |
2041 | (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) { | |
2042 | MIPS_FPU_EMU_INC_STATS(errors); | |
2043 | return SIGBUS; | |
2044 | } | |
2045 | instr_ptr = instr; | |
2046 | ||
2047 | /* Get first instruction. */ | |
2048 | if (mm_insn_16bit(*instr_ptr)) { | |
2049 | /* Duplicate the half-word. */ | |
2050 | dec_insn.insn = (*instr_ptr << 16) | | |
2051 | (*instr_ptr); | |
2052 | /* 16-bit instruction. */ | |
2053 | dec_insn.pc_inc = 2; | |
2054 | instr_ptr += 1; | |
2055 | } else { | |
2056 | dec_insn.insn = (*instr_ptr << 16) | | |
2057 | *(instr_ptr+1); | |
2058 | /* 32-bit instruction. */ | |
2059 | dec_insn.pc_inc = 4; | |
2060 | instr_ptr += 2; | |
2061 | } | |
2062 | /* Get second instruction. */ | |
2063 | if (mm_insn_16bit(*instr_ptr)) { | |
2064 | /* Duplicate the half-word. */ | |
2065 | dec_insn.next_insn = (*instr_ptr << 16) | | |
2066 | (*instr_ptr); | |
2067 | /* 16-bit instruction. */ | |
2068 | dec_insn.next_pc_inc = 2; | |
2069 | } else { | |
2070 | dec_insn.next_insn = (*instr_ptr << 16) | | |
2071 | *(instr_ptr+1); | |
2072 | /* 32-bit instruction. */ | |
2073 | dec_insn.next_pc_inc = 4; | |
2074 | } | |
2075 | dec_insn.micro_mips_mode = 1; | |
2076 | } else { | |
2077 | if ((get_user(dec_insn.insn, | |
2078 | (mips_instruction __user *) xcp->cp0_epc)) || | |
2079 | (get_user(dec_insn.next_insn, | |
2080 | (mips_instruction __user *)(xcp->cp0_epc+4)))) { | |
2081 | MIPS_FPU_EMU_INC_STATS(errors); | |
2082 | return SIGBUS; | |
2083 | } | |
2084 | dec_insn.pc_inc = 4; | |
2085 | dec_insn.next_pc_inc = 4; | |
2086 | dec_insn.micro_mips_mode = 0; | |
515b029d | 2087 | } |
102cedc3 LY |
2088 | |
2089 | if ((dec_insn.insn == 0) || | |
2090 | ((dec_insn.pc_inc == 2) && | |
2091 | ((dec_insn.insn & 0xffff) == MM_NOP16))) | |
2092 | xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ | |
1da177e4 | 2093 | else { |
cd21dfcf | 2094 | /* |
2cfcf8a8 MR |
2095 | * The 'ieee754_csr' is an alias of ctx->fcr31. |
2096 | * No need to copy ctx->fcr31 to ieee754_csr. | |
cd21dfcf | 2097 | */ |
102cedc3 | 2098 | sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); |
1da177e4 LT |
2099 | } |
2100 | ||
e04582b7 | 2101 | if (has_fpu) |
1da177e4 LT |
2102 | break; |
2103 | if (sig) | |
2104 | break; | |
2105 | ||
2106 | cond_resched(); | |
2107 | } while (xcp->cp0_epc > prevepc); | |
2108 | ||
2109 | /* SIGILL indicates a non-fpu instruction */ | |
2110 | if (sig == SIGILL && xcp->cp0_epc != oldepc) | |
3f7cac41 | 2111 | /* but if EPC has advanced, then ignore it */ |
1da177e4 LT |
2112 | sig = 0; |
2113 | ||
2114 | return sig; | |
2115 | } |