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MIPS: math-emu: Cleanup coding style.
[deliverable/linux.git] / arch / mips / math-emu / cp1emu.c
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1da177e4 1/*
3f7cac41 2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
1da177e4
LT		 3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
1da177e4
LT		 6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
3f7cac41 21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1da177e4
LT		 22 *
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
26 *
27 * More surprisingly it is also required for #float(ieee), to help out
3f7cac41 28 * the hardware FPU at the boundaries of the IEEE-754 representation
1da177e4
LT		 29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
32 *
3f7cac41 33 * Note if you know that you won't have an FPU, then you'll get much
1da177e4
LT		 34 * better performance by compiling with -msoft-float!
35 */
36#include <linux/sched.h>
83fd38ca 37#include <linux/debugfs.h>
08a07904 38#include <linux/kconfig.h>
85c51c51 39#include <linux/percpu-defs.h>
7f788d2d 40#include <linux/perf_event.h>
1da177e4 41
cd8ee345 42#include <asm/branch.h>
1da177e4 43#include <asm/inst.h>
1da177e4
LT		 44#include <asm/ptrace.h>
45#include <asm/signal.h>
cd8ee345
RB		 46#include <asm/uaccess.h>
47
48#include <asm/processor.h>
1da177e4 49#include <asm/fpu_emulator.h>
102cedc3 50#include <asm/fpu.h>
1da177e4
LT		 51
52#include "ieee754.h"
1da177e4 53
1da177e4
LT		 54/* Function which emulates a floating point instruction. */
55
eae89076 56static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
1da177e4
LT		 57 mips_instruction);
58
1da177e4 59static int fpux_emu(struct pt_regs *,
515b029d 60 struct mips_fpu_struct *, mips_instruction, void *__user *);
1da177e4 61
1da177e4
LT		 62/* Control registers */
63
64#define FPCREG_RID 0 /* $0 = revision id */
65#define FPCREG_CSR 31 /* $31 = csr */
66
95e8f634
SM		 67/* Determine rounding mode from the RM bits of the FCSR */
68#define modeindex(v) ((v) & FPU_CSR_RM)
69
102cedc3
LY		 70/* microMIPS bitfields */
71#define MM_POOL32A_MINOR_MASK 0x3f
72#define MM_POOL32A_MINOR_SHIFT 0x6
73#define MM_MIPS32_COND_FC 0x30
74
3f7cac41 75/* Convert MIPS rounding mode (0..3) to IEEE library modes. */
1da177e4 76static const unsigned char ieee_rm[4] = {
cd21dfcf
RB		 77 [FPU_CSR_RN] = IEEE754_RN,
78 [FPU_CSR_RZ] = IEEE754_RZ,
79 [FPU_CSR_RU] = IEEE754_RU,
80 [FPU_CSR_RD] = IEEE754_RD,
81};
3f7cac41 82/* Convert IEEE library modes to MIPS rounding mode (0..3). */
cd21dfcf
RB		 83static const unsigned char mips_rm[4] = {
84 [IEEE754_RN] = FPU_CSR_RN,
85 [IEEE754_RZ] = FPU_CSR_RZ,
86 [IEEE754_RD] = FPU_CSR_RD,
87 [IEEE754_RU] = FPU_CSR_RU,
1da177e4
LT		 88};
89
1da177e4
LT		 90/* convert condition code register number to csr bit */
91static const unsigned int fpucondbit[8] = {
92 FPU_CSR_COND0,
93 FPU_CSR_COND1,
94 FPU_CSR_COND2,
95 FPU_CSR_COND3,
96 FPU_CSR_COND4,
97 FPU_CSR_COND5,
98 FPU_CSR_COND6,
99 FPU_CSR_COND7
100};
1da177e4 101
102cedc3
LY		 102/* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
103static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7};
104
105/* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
106static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
107static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
108static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
109static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
110
111/*
112 * This functions translates a 32-bit microMIPS instruction
113 * into a 32-bit MIPS32 instruction. Returns 0 on success
114 * and SIGILL otherwise.
115 */
116static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
117{
118 union mips_instruction insn = *insn_ptr;
119 union mips_instruction mips32_insn = insn;
120 int func, fmt, op;
121
122 switch (insn.mm_i_format.opcode) {
123 case mm_ldc132_op:
124 mips32_insn.mm_i_format.opcode = ldc1_op;
125 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
126 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
127 break;
128 case mm_lwc132_op:
129 mips32_insn.mm_i_format.opcode = lwc1_op;
130 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
131 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
132 break;
133 case mm_sdc132_op:
134 mips32_insn.mm_i_format.opcode = sdc1_op;
135 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
136 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
137 break;
138 case mm_swc132_op:
139 mips32_insn.mm_i_format.opcode = swc1_op;
140 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
141 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
142 break;
143 case mm_pool32i_op:
144 /* NOTE: offset is << by 1 if in microMIPS mode. */
145 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
146 (insn.mm_i_format.rt == mm_bc1t_op)) {
147 mips32_insn.fb_format.opcode = cop1_op;
148 mips32_insn.fb_format.bc = bc_op;
149 mips32_insn.fb_format.flag =
150 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
151 } else
152 return SIGILL;
153 break;
154 case mm_pool32f_op:
155 switch (insn.mm_fp0_format.func) {
156 case mm_32f_01_op:
157 case mm_32f_11_op:
158 case mm_32f_02_op:
159 case mm_32f_12_op:
160 case mm_32f_41_op:
161 case mm_32f_51_op:
162 case mm_32f_42_op:
163 case mm_32f_52_op:
164 op = insn.mm_fp0_format.func;
165 if (op == mm_32f_01_op)
166 func = madd_s_op;
167 else if (op == mm_32f_11_op)
168 func = madd_d_op;
169 else if (op == mm_32f_02_op)
170 func = nmadd_s_op;
171 else if (op == mm_32f_12_op)
172 func = nmadd_d_op;
173 else if (op == mm_32f_41_op)
174 func = msub_s_op;
175 else if (op == mm_32f_51_op)
176 func = msub_d_op;
177 else if (op == mm_32f_42_op)
178 func = nmsub_s_op;
179 else
180 func = nmsub_d_op;
181 mips32_insn.fp6_format.opcode = cop1x_op;
182 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
183 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
184 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
185 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
186 mips32_insn.fp6_format.func = func;
187 break;
188 case mm_32f_10_op:
189 func = -1; /* Invalid */
190 op = insn.mm_fp5_format.op & 0x7;
191 if (op == mm_ldxc1_op)
192 func = ldxc1_op;
193 else if (op == mm_sdxc1_op)
194 func = sdxc1_op;
195 else if (op == mm_lwxc1_op)
196 func = lwxc1_op;
197 else if (op == mm_swxc1_op)
198 func = swxc1_op;
199
200 if (func != -1) {
201 mips32_insn.r_format.opcode = cop1x_op;
202 mips32_insn.r_format.rs =
203 insn.mm_fp5_format.base;
204 mips32_insn.r_format.rt =
205 insn.mm_fp5_format.index;
206 mips32_insn.r_format.rd = 0;
207 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
208 mips32_insn.r_format.func = func;
209 } else
210 return SIGILL;
211 break;
212 case mm_32f_40_op:
213 op = -1; /* Invalid */
214 if (insn.mm_fp2_format.op == mm_fmovt_op)
215 op = 1;
216 else if (insn.mm_fp2_format.op == mm_fmovf_op)
217 op = 0;
218 if (op != -1) {
219 mips32_insn.fp0_format.opcode = cop1_op;
220 mips32_insn.fp0_format.fmt =
221 sdps_format[insn.mm_fp2_format.fmt];
222 mips32_insn.fp0_format.ft =
223 (insn.mm_fp2_format.cc<<2) + op;
224 mips32_insn.fp0_format.fs =
225 insn.mm_fp2_format.fs;
226 mips32_insn.fp0_format.fd =
227 insn.mm_fp2_format.fd;
228 mips32_insn.fp0_format.func = fmovc_op;
229 } else
230 return SIGILL;
231 break;
232 case mm_32f_60_op:
233 func = -1; /* Invalid */
234 if (insn.mm_fp0_format.op == mm_fadd_op)
235 func = fadd_op;
236 else if (insn.mm_fp0_format.op == mm_fsub_op)
237 func = fsub_op;
238 else if (insn.mm_fp0_format.op == mm_fmul_op)
239 func = fmul_op;
240 else if (insn.mm_fp0_format.op == mm_fdiv_op)
241 func = fdiv_op;
242 if (func != -1) {
243 mips32_insn.fp0_format.opcode = cop1_op;
244 mips32_insn.fp0_format.fmt =
245 sdps_format[insn.mm_fp0_format.fmt];
246 mips32_insn.fp0_format.ft =
247 insn.mm_fp0_format.ft;
248 mips32_insn.fp0_format.fs =
249 insn.mm_fp0_format.fs;
250 mips32_insn.fp0_format.fd =
251 insn.mm_fp0_format.fd;
252 mips32_insn.fp0_format.func = func;
253 } else
254 return SIGILL;
255 break;
256 case mm_32f_70_op:
257 func = -1; /* Invalid */
258 if (insn.mm_fp0_format.op == mm_fmovn_op)
259 func = fmovn_op;
260 else if (insn.mm_fp0_format.op == mm_fmovz_op)
261 func = fmovz_op;
262 if (func != -1) {
263 mips32_insn.fp0_format.opcode = cop1_op;
264 mips32_insn.fp0_format.fmt =
265 sdps_format[insn.mm_fp0_format.fmt];
266 mips32_insn.fp0_format.ft =
267 insn.mm_fp0_format.ft;
268 mips32_insn.fp0_format.fs =
269 insn.mm_fp0_format.fs;
270 mips32_insn.fp0_format.fd =
271 insn.mm_fp0_format.fd;
272 mips32_insn.fp0_format.func = func;
273 } else
274 return SIGILL;
275 break;
276 case mm_32f_73_op: /* POOL32FXF */
277 switch (insn.mm_fp1_format.op) {
278 case mm_movf0_op:
279 case mm_movf1_op:
280 case mm_movt0_op:
281 case mm_movt1_op:
282 if ((insn.mm_fp1_format.op & 0x7f) ==
283 mm_movf0_op)
284 op = 0;
285 else
286 op = 1;
287 mips32_insn.r_format.opcode = spec_op;
288 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
289 mips32_insn.r_format.rt =
290 (insn.mm_fp4_format.cc << 2) + op;
291 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
292 mips32_insn.r_format.re = 0;
293 mips32_insn.r_format.func = movc_op;
294 break;
295 case mm_fcvtd0_op:
296 case mm_fcvtd1_op:
297 case mm_fcvts0_op:
298 case mm_fcvts1_op:
299 if ((insn.mm_fp1_format.op & 0x7f) ==
300 mm_fcvtd0_op) {
301 func = fcvtd_op;
302 fmt = swl_format[insn.mm_fp3_format.fmt];
303 } else {
304 func = fcvts_op;
305 fmt = dwl_format[insn.mm_fp3_format.fmt];
306 }
307 mips32_insn.fp0_format.opcode = cop1_op;
308 mips32_insn.fp0_format.fmt = fmt;
309 mips32_insn.fp0_format.ft = 0;
310 mips32_insn.fp0_format.fs =
311 insn.mm_fp3_format.fs;
312 mips32_insn.fp0_format.fd =
313 insn.mm_fp3_format.rt;
314 mips32_insn.fp0_format.func = func;
315 break;
316 case mm_fmov0_op:
317 case mm_fmov1_op:
318 case mm_fabs0_op:
319 case mm_fabs1_op:
320 case mm_fneg0_op:
321 case mm_fneg1_op:
322 if ((insn.mm_fp1_format.op & 0x7f) ==
323 mm_fmov0_op)
324 func = fmov_op;
325 else if ((insn.mm_fp1_format.op & 0x7f) ==
326 mm_fabs0_op)
327 func = fabs_op;
328 else
329 func = fneg_op;
330 mips32_insn.fp0_format.opcode = cop1_op;
331 mips32_insn.fp0_format.fmt =
332 sdps_format[insn.mm_fp3_format.fmt];
333 mips32_insn.fp0_format.ft = 0;
334 mips32_insn.fp0_format.fs =
335 insn.mm_fp3_format.fs;
336 mips32_insn.fp0_format.fd =
337 insn.mm_fp3_format.rt;
338 mips32_insn.fp0_format.func = func;
339 break;
340 case mm_ffloorl_op:
341 case mm_ffloorw_op:
342 case mm_fceill_op:
343 case mm_fceilw_op:
344 case mm_ftruncl_op:
345 case mm_ftruncw_op:
346 case mm_froundl_op:
347 case mm_froundw_op:
348 case mm_fcvtl_op:
349 case mm_fcvtw_op:
350 if (insn.mm_fp1_format.op == mm_ffloorl_op)
351 func = ffloorl_op;
352 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
353 func = ffloor_op;
354 else if (insn.mm_fp1_format.op == mm_fceill_op)
355 func = fceill_op;
356 else if (insn.mm_fp1_format.op == mm_fceilw_op)
357 func = fceil_op;
358 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
359 func = ftruncl_op;
360 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
361 func = ftrunc_op;
362 else if (insn.mm_fp1_format.op == mm_froundl_op)
363 func = froundl_op;
364 else if (insn.mm_fp1_format.op == mm_froundw_op)
365 func = fround_op;
366 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
367 func = fcvtl_op;
368 else
369 func = fcvtw_op;
370 mips32_insn.fp0_format.opcode = cop1_op;
371 mips32_insn.fp0_format.fmt =
372 sd_format[insn.mm_fp1_format.fmt];
373 mips32_insn.fp0_format.ft = 0;
374 mips32_insn.fp0_format.fs =
375 insn.mm_fp1_format.fs;
376 mips32_insn.fp0_format.fd =
377 insn.mm_fp1_format.rt;
378 mips32_insn.fp0_format.func = func;
379 break;
380 case mm_frsqrt_op:
381 case mm_fsqrt_op:
382 case mm_frecip_op:
383 if (insn.mm_fp1_format.op == mm_frsqrt_op)
384 func = frsqrt_op;
385 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
386 func = fsqrt_op;
387 else
388 func = frecip_op;
389 mips32_insn.fp0_format.opcode = cop1_op;
390 mips32_insn.fp0_format.fmt =
391 sdps_format[insn.mm_fp1_format.fmt];
392 mips32_insn.fp0_format.ft = 0;
393 mips32_insn.fp0_format.fs =
394 insn.mm_fp1_format.fs;
395 mips32_insn.fp0_format.fd =
396 insn.mm_fp1_format.rt;
397 mips32_insn.fp0_format.func = func;
398 break;
399 case mm_mfc1_op:
400 case mm_mtc1_op:
401 case mm_cfc1_op:
402 case mm_ctc1_op:
9355e59c
SH		 403 case mm_mfhc1_op:
404 case mm_mthc1_op:
102cedc3
LY		 405 if (insn.mm_fp1_format.op == mm_mfc1_op)
406 op = mfc_op;
407 else if (insn.mm_fp1_format.op == mm_mtc1_op)
408 op = mtc_op;
409 else if (insn.mm_fp1_format.op == mm_cfc1_op)
410 op = cfc_op;
9355e59c 411 else if (insn.mm_fp1_format.op == mm_ctc1_op)
102cedc3 412 op = ctc_op;
9355e59c
SH		 413 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
414 op = mfhc_op;
415 else
416 op = mthc_op;
102cedc3
LY		 417 mips32_insn.fp1_format.opcode = cop1_op;
418 mips32_insn.fp1_format.op = op;
419 mips32_insn.fp1_format.rt =
420 insn.mm_fp1_format.rt;
421 mips32_insn.fp1_format.fs =
422 insn.mm_fp1_format.fs;
423 mips32_insn.fp1_format.fd = 0;
424 mips32_insn.fp1_format.func = 0;
425 break;
426 default:
427 return SIGILL;
102cedc3
LY		 428 }
429 break;
430 case mm_32f_74_op: /* c.cond.fmt */
431 mips32_insn.fp0_format.opcode = cop1_op;
432 mips32_insn.fp0_format.fmt =
433 sdps_format[insn.mm_fp4_format.fmt];
434 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
435 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
436 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
437 mips32_insn.fp0_format.func =
438 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
439 break;
440 default:
441 return SIGILL;
102cedc3
LY		 442 }
443 break;
444 default:
445 return SIGILL;
102cedc3
LY		 446 }
447
448 *insn_ptr = mips32_insn;
449 return 0;
450}
451
452int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
453 unsigned long *contpc)
454{
455 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
456 int bc_false = 0;
457 unsigned int fcr31;
458 unsigned int bit;
459
fe6d2909
DD		 460 if (!cpu_has_mmips)
461 return 0;
462
102cedc3
LY		 463 switch (insn.mm_i_format.opcode) {
464 case mm_pool32a_op:
465 if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) ==
466 mm_pool32axf_op) {
467 switch (insn.mm_i_format.simmediate >>
468 MM_POOL32A_MINOR_SHIFT) {
469 case mm_jalr_op:
470 case mm_jalrhb_op:
471 case mm_jalrs_op:
472 case mm_jalrshb_op:
473 if (insn.mm_i_format.rt != 0) /* Not mm_jr */
474 regs->regs[insn.mm_i_format.rt] =
475 regs->cp0_epc +
476 dec_insn.pc_inc +
477 dec_insn.next_pc_inc;
478 *contpc = regs->regs[insn.mm_i_format.rs];
479 return 1;
102cedc3
LY		 480 }
481 }
482 break;
483 case mm_pool32i_op:
484 switch (insn.mm_i_format.rt) {
485 case mm_bltzals_op:
486 case mm_bltzal_op:
487 regs->regs[31] = regs->cp0_epc +
488 dec_insn.pc_inc +
489 dec_insn.next_pc_inc;
490 /* Fall through */
491 case mm_bltz_op:
492 if ((long)regs->regs[insn.mm_i_format.rs] < 0)
493 *contpc = regs->cp0_epc +
494 dec_insn.pc_inc +
495 (insn.mm_i_format.simmediate << 1);
496 else
497 *contpc = regs->cp0_epc +
498 dec_insn.pc_inc +
499 dec_insn.next_pc_inc;
500 return 1;
102cedc3
LY		 501 case mm_bgezals_op:
502 case mm_bgezal_op:
503 regs->regs[31] = regs->cp0_epc +
504 dec_insn.pc_inc +
505 dec_insn.next_pc_inc;
506 /* Fall through */
507 case mm_bgez_op:
508 if ((long)regs->regs[insn.mm_i_format.rs] >= 0)
509 *contpc = regs->cp0_epc +
510 dec_insn.pc_inc +
511 (insn.mm_i_format.simmediate << 1);
512 else
513 *contpc = regs->cp0_epc +
514 dec_insn.pc_inc +
515 dec_insn.next_pc_inc;
516 return 1;
102cedc3
LY		 517 case mm_blez_op:
518 if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
519 *contpc = regs->cp0_epc +
520 dec_insn.pc_inc +
521 (insn.mm_i_format.simmediate << 1);
522 else
523 *contpc = regs->cp0_epc +
524 dec_insn.pc_inc +
525 dec_insn.next_pc_inc;
526 return 1;
102cedc3
LY		 527 case mm_bgtz_op:
528 if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
529 *contpc = regs->cp0_epc +
530 dec_insn.pc_inc +
531 (insn.mm_i_format.simmediate << 1);
532 else
533 *contpc = regs->cp0_epc +
534 dec_insn.pc_inc +
535 dec_insn.next_pc_inc;
536 return 1;
102cedc3
LY		 537 case mm_bc2f_op:
538 case mm_bc1f_op:
539 bc_false = 1;
540 /* Fall through */
541 case mm_bc2t_op:
542 case mm_bc1t_op:
543 preempt_disable();
544 if (is_fpu_owner())
545 asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
546 else
547 fcr31 = current->thread.fpu.fcr31;
548 preempt_enable();
549
550 if (bc_false)
551 fcr31 = ~fcr31;
552
553 bit = (insn.mm_i_format.rs >> 2);
554 bit += (bit != 0);
555 bit += 23;
556 if (fcr31 & (1 << bit))
557 *contpc = regs->cp0_epc +
558 dec_insn.pc_inc +
559 (insn.mm_i_format.simmediate << 1);
560 else
561 *contpc = regs->cp0_epc +
562 dec_insn.pc_inc + dec_insn.next_pc_inc;
563 return 1;
102cedc3
LY		 564 }
565 break;
566 case mm_pool16c_op:
567 switch (insn.mm_i_format.rt) {
568 case mm_jalr16_op:
569 case mm_jalrs16_op:
570 regs->regs[31] = regs->cp0_epc +
571 dec_insn.pc_inc + dec_insn.next_pc_inc;
572 /* Fall through */
573 case mm_jr16_op:
574 *contpc = regs->regs[insn.mm_i_format.rs];
575 return 1;
102cedc3
LY		 576 }
577 break;
578 case mm_beqz16_op:
579 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0)
580 *contpc = regs->cp0_epc +
581 dec_insn.pc_inc +
582 (insn.mm_b1_format.simmediate << 1);
583 else
584 *contpc = regs->cp0_epc +
585 dec_insn.pc_inc + dec_insn.next_pc_inc;
586 return 1;
102cedc3
LY		 587 case mm_bnez16_op:
588 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0)
589 *contpc = regs->cp0_epc +
590 dec_insn.pc_inc +
591 (insn.mm_b1_format.simmediate << 1);
592 else
593 *contpc = regs->cp0_epc +
594 dec_insn.pc_inc + dec_insn.next_pc_inc;
595 return 1;
102cedc3
LY		 596 case mm_b16_op:
597 *contpc = regs->cp0_epc + dec_insn.pc_inc +
598 (insn.mm_b0_format.simmediate << 1);
599 return 1;
102cedc3
LY		 600 case mm_beq32_op:
601 if (regs->regs[insn.mm_i_format.rs] ==
602 regs->regs[insn.mm_i_format.rt])
603 *contpc = regs->cp0_epc +
604 dec_insn.pc_inc +
605 (insn.mm_i_format.simmediate << 1);
606 else
607 *contpc = regs->cp0_epc +
608 dec_insn.pc_inc +
609 dec_insn.next_pc_inc;
610 return 1;
102cedc3
LY		 611 case mm_bne32_op:
612 if (regs->regs[insn.mm_i_format.rs] !=
613 regs->regs[insn.mm_i_format.rt])
614 *contpc = regs->cp0_epc +
615 dec_insn.pc_inc +
616 (insn.mm_i_format.simmediate << 1);
617 else
618 *contpc = regs->cp0_epc +
619 dec_insn.pc_inc + dec_insn.next_pc_inc;
620 return 1;
102cedc3
LY		 621 case mm_jalx32_op:
622 regs->regs[31] = regs->cp0_epc +
623 dec_insn.pc_inc + dec_insn.next_pc_inc;
624 *contpc = regs->cp0_epc + dec_insn.pc_inc;
625 *contpc >>= 28;
626 *contpc <<= 28;
627 *contpc |= (insn.j_format.target << 2);
628 return 1;
102cedc3
LY		 629 case mm_jals32_op:
630 case mm_jal32_op:
631 regs->regs[31] = regs->cp0_epc +
632 dec_insn.pc_inc + dec_insn.next_pc_inc;
633 /* Fall through */
634 case mm_j32_op:
635 *contpc = regs->cp0_epc + dec_insn.pc_inc;
636 *contpc >>= 27;
637 *contpc <<= 27;
638 *contpc |= (insn.j_format.target << 1);
639 set_isa16_mode(*contpc);
640 return 1;
102cedc3
LY		 641 }
642 return 0;
643}
1da177e4
LT		 644
645/*
646 * Redundant with logic already in kernel/branch.c,
647 * embedded in compute_return_epc. At some point,
648 * a single subroutine should be used across both
649 * modules.
650 */
102cedc3
LY		 651static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
652 unsigned long *contpc)
1da177e4 653{
102cedc3
LY		 654 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
655 unsigned int fcr31;
656 unsigned int bit = 0;
657
658 switch (insn.i_format.opcode) {
1da177e4 659 case spec_op:
102cedc3 660 switch (insn.r_format.func) {
1da177e4 661 case jalr_op:
102cedc3
LY		 662 regs->regs[insn.r_format.rd] =
663 regs->cp0_epc + dec_insn.pc_inc +
664 dec_insn.next_pc_inc;
665 /* Fall through */
1da177e4 666 case jr_op:
102cedc3 667 *contpc = regs->regs[insn.r_format.rs];
1da177e4
LT		 668 return 1;
669 }
670 break;
1da177e4 671 case bcond_op:
102cedc3
LY		 672 switch (insn.i_format.rt) {
673 case bltzal_op:
674 case bltzall_op:
675 regs->regs[31] = regs->cp0_epc +
676 dec_insn.pc_inc +
677 dec_insn.next_pc_inc;
678 /* Fall through */
1da177e4 679 case bltz_op:
1da177e4 680 case bltzl_op:
102cedc3
LY		 681 if ((long)regs->regs[insn.i_format.rs] < 0)
682 *contpc = regs->cp0_epc +
683 dec_insn.pc_inc +
684 (insn.i_format.simmediate << 2);
685 else
686 *contpc = regs->cp0_epc +
687 dec_insn.pc_inc +
688 dec_insn.next_pc_inc;
689 return 1;
1da177e4 690 case bgezal_op:
1da177e4 691 case bgezall_op:
102cedc3
LY		 692 regs->regs[31] = regs->cp0_epc +
693 dec_insn.pc_inc +
694 dec_insn.next_pc_inc;
695 /* Fall through */
696 case bgez_op:
697 case bgezl_op:
698 if ((long)regs->regs[insn.i_format.rs] >= 0)
699 *contpc = regs->cp0_epc +
700 dec_insn.pc_inc +
701 (insn.i_format.simmediate << 2);
702 else
703 *contpc = regs->cp0_epc +
704 dec_insn.pc_inc +
705 dec_insn.next_pc_inc;
1da177e4
LT		 706 return 1;
707 }
708 break;
1da177e4 709 case jalx_op:
102cedc3
LY		 710 set_isa16_mode(bit);
711 case jal_op:
712 regs->regs[31] = regs->cp0_epc +
713 dec_insn.pc_inc +
714 dec_insn.next_pc_inc;
715 /* Fall through */
716 case j_op:
717 *contpc = regs->cp0_epc + dec_insn.pc_inc;
718 *contpc >>= 28;
719 *contpc <<= 28;
720 *contpc |= (insn.j_format.target << 2);
721 /* Set microMIPS mode bit: XOR for jalx. */
722 *contpc ^= bit;
723 return 1;
1da177e4 724 case beq_op:
1da177e4 725 case beql_op:
102cedc3
LY		 726 if (regs->regs[insn.i_format.rs] ==
727 regs->regs[insn.i_format.rt])
728 *contpc = regs->cp0_epc +
729 dec_insn.pc_inc +
730 (insn.i_format.simmediate << 2);
731 else
732 *contpc = regs->cp0_epc +
733 dec_insn.pc_inc +
734 dec_insn.next_pc_inc;
735 return 1;
102cedc3 736 case bne_op:
1da177e4 737 case bnel_op:
102cedc3
LY		 738 if (regs->regs[insn.i_format.rs] !=
739 regs->regs[insn.i_format.rt])
740 *contpc = regs->cp0_epc +
741 dec_insn.pc_inc +
742 (insn.i_format.simmediate << 2);
743 else
744 *contpc = regs->cp0_epc +
745 dec_insn.pc_inc +
746 dec_insn.next_pc_inc;
747 return 1;
102cedc3 748 case blez_op:
1da177e4 749 case blezl_op:
102cedc3
LY		 750 if ((long)regs->regs[insn.i_format.rs] <= 0)
751 *contpc = regs->cp0_epc +
752 dec_insn.pc_inc +
753 (insn.i_format.simmediate << 2);
754 else
755 *contpc = regs->cp0_epc +
756 dec_insn.pc_inc +
757 dec_insn.next_pc_inc;
758 return 1;
102cedc3 759 case bgtz_op:
1da177e4 760 case bgtzl_op:
102cedc3
LY		 761 if ((long)regs->regs[insn.i_format.rs] > 0)
762 *contpc = regs->cp0_epc +
763 dec_insn.pc_inc +
764 (insn.i_format.simmediate << 2);
765 else
766 *contpc = regs->cp0_epc +
767 dec_insn.pc_inc +
768 dec_insn.next_pc_inc;
1da177e4 769 return 1;
c26d4219
DD		 770#ifdef CONFIG_CPU_CAVIUM_OCTEON
771 case lwc2_op: /* This is bbit0 on Octeon */
772 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
773 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
774 else
775 *contpc = regs->cp0_epc + 8;
776 return 1;
777 case ldc2_op: /* This is bbit032 on Octeon */
778 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
779 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
780 else
781 *contpc = regs->cp0_epc + 8;
782 return 1;
783 case swc2_op: /* This is bbit1 on Octeon */
784 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
785 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
786 else
787 *contpc = regs->cp0_epc + 8;
788 return 1;
789 case sdc2_op: /* This is bbit132 on Octeon */
790 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
791 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
792 else
793 *contpc = regs->cp0_epc + 8;
794 return 1;
795#endif
1da177e4
LT		 796 case cop0_op:
797 case cop1_op:
798 case cop2_op:
799 case cop1x_op:
102cedc3
LY		 800 if (insn.i_format.rs == bc_op) {
801 preempt_disable();
802 if (is_fpu_owner())
803 asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
804 else
805 fcr31 = current->thread.fpu.fcr31;
806 preempt_enable();
807
808 bit = (insn.i_format.rt >> 2);
809 bit += (bit != 0);
810 bit += 23;
811 switch (insn.i_format.rt & 3) {
812 case 0: /* bc1f */
813 case 2: /* bc1fl */
814 if (~fcr31 & (1 << bit))
815 *contpc = regs->cp0_epc +
816 dec_insn.pc_inc +
817 (insn.i_format.simmediate << 2);
818 else
819 *contpc = regs->cp0_epc +
820 dec_insn.pc_inc +
821 dec_insn.next_pc_inc;
822 return 1;
102cedc3
LY		 823 case 1: /* bc1t */
824 case 3: /* bc1tl */
825 if (fcr31 & (1 << bit))
826 *contpc = regs->cp0_epc +
827 dec_insn.pc_inc +
828 (insn.i_format.simmediate << 2);
829 else
830 *contpc = regs->cp0_epc +
831 dec_insn.pc_inc +
832 dec_insn.next_pc_inc;
833 return 1;
102cedc3
LY		 834 }
835 }
1da177e4
LT		 836 break;
837 }
1da177e4
LT		 838 return 0;
839}
840
841/*
842 * In the Linux kernel, we support selection of FPR format on the
70342287 843 * basis of the Status.FR bit. If an FPU is not present, the FR bit
da0bac33 844 * is hardwired to zero, which would imply a 32-bit FPU even for
597ce172 845 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
51d943f0
RB		 846 * FPU emu is slow and bulky and optimizing this function offers fairly
847 * sizeable benefits so we try to be clever and make this function return
848 * a constant whenever possible, that is on 64-bit kernels without O32
597ce172 849 * compatibility enabled and on 32-bit without 64-bit FPU support.
1da177e4 850 */
da0bac33
DD		 851static inline int cop1_64bit(struct pt_regs *xcp)
852{
08a07904
RB		 853 if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
854 return 1;
855 else if (config_enabled(CONFIG_32BIT) &&
856 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
857 return 0;
858
597ce172 859 return !test_thread_flag(TIF_32BIT_FPREGS);
da0bac33
DD		 860}
861
47fa0c02
RB		 862#define SIFROMREG(si, x) \
863do { \
bbd426f5
PB		 864 if (cop1_64bit(xcp)) \
865 (si) = get_fpr32(&ctx->fpr[x], 0); \
866 else \
867 (si) = get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
868} while (0)
1da177e4 869
47fa0c02
RB		 870#define SITOREG(si, x) \
871do { \
ef1c47af
PB		 872 if (cop1_64bit(xcp)) { \
873 unsigned i; \
bbd426f5 874 set_fpr32(&ctx->fpr[x], 0, si); \
ef1c47af
PB		 875 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
876 set_fpr32(&ctx->fpr[x], i, 0); \
877 } else { \
bbd426f5 878 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
ef1c47af 879 } \
bbd426f5 880} while (0)
1da177e4 881
bbd426f5 882#define SIFROMHREG(si, x) ((si) = get_fpr32(&ctx->fpr[x], 1))
ef1c47af 883
47fa0c02
RB		 884#define SITOHREG(si, x) \
885do { \
ef1c47af
PB		 886 unsigned i; \
887 set_fpr32(&ctx->fpr[x], 1, si); \
888 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
889 set_fpr32(&ctx->fpr[x], i, 0); \
890} while (0)
1ac94400 891
47fa0c02 892#define DIFROMREG(di, x) \
bbd426f5
PB		 893 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
894
47fa0c02
RB		 895#define DITOREG(di, x) \
896do { \
ef1c47af
PB		 897 unsigned fpr, i; \
898 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
899 set_fpr64(&ctx->fpr[fpr], 0, di); \
900 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
901 set_fpr64(&ctx->fpr[fpr], i, 0); \
902} while (0)
1da177e4 903
21a151d8
RB		 904#define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
905#define SPTOREG(sp, x) SITOREG((sp).bits, x)
906#define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
907#define DPTOREG(dp, x) DITOREG((dp).bits, x)
1da177e4
LT		 908
909/*
910 * Emulate the single floating point instruction pointed at by EPC.
911 * Two instructions if the instruction is in a branch delay slot.
912 */
913
515b029d 914static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
102cedc3 915 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
1da177e4 916{
102cedc3 917 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
3f7cac41
RB		 918 unsigned int cond, cbit;
919 mips_instruction ir;
920 int likely, pc_inc;
921 u32 __user *wva;
922 u64 __user *dva;
923 u32 value;
924 u32 wval;
925 u64 dval;
926 int sig;
1da177e4
LT		 927
928 /* XXX NEC Vr54xx bug workaround */
e7e9cae5 929 if (delay_slot(xcp)) {
102cedc3
LY		 930 if (dec_insn.micro_mips_mode) {
931 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
e7e9cae5 932 clear_delay_slot(xcp);
102cedc3
LY		 933 } else {
934 if (!isBranchInstr(xcp, dec_insn, &contpc))
e7e9cae5 935 clear_delay_slot(xcp);
102cedc3
LY		 936 }
937 }
1da177e4 938
e7e9cae5 939 if (delay_slot(xcp)) {
1da177e4
LT		 940 /*
941 * The instruction to be emulated is in a branch delay slot
70342287 942 * which means that we have to emulate the branch instruction
1da177e4
LT		 943 * BEFORE we do the cop1 instruction.
944 *
945 * This branch could be a COP1 branch, but in that case we
946 * would have had a trap for that instruction, and would not
947 * come through this route.
948 *
949 * Linux MIPS branch emulator operates on context, updating the
950 * cp0_epc.
951 */
102cedc3
LY		 952 ir = dec_insn.next_insn; /* process delay slot instr */
953 pc_inc = dec_insn.next_pc_inc;
954 } else {
955 ir = dec_insn.insn; /* process current instr */
956 pc_inc = dec_insn.pc_inc;
957 }
1da177e4 958
102cedc3
LY		 959 /*
960 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
961 * instructions, we want to convert microMIPS FPU instructions
962 * into MIPS32 instructions so that we could reuse all of the
963 * FPU emulation code.
964 *
965 * NOTE: We cannot do this for branch instructions since they
966 * are not a subset. Example: Cannot emulate a 16-bit
967 * aligned target address with a MIPS32 instruction.
968 */
969 if (dec_insn.micro_mips_mode) {
970 /*
971 * If next instruction is a 16-bit instruction, then it
972 * it cannot be a FPU instruction. This could happen
973 * since we can be called for non-FPU instructions.
974 */
975 if ((pc_inc == 2) ||
976 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
977 == SIGILL))
1da177e4 978 return SIGILL;
1da177e4
LT		 979 }
980
3f7cac41 981emul:
a8b0ca17 982 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
b6ee75ed 983 MIPS_FPU_EMU_INC_STATS(emulated);
1da177e4 984 switch (MIPSInst_OPCODE(ir)) {
3f7cac41
RB		 985 case ldc1_op:
986 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
987 MIPSInst_SIMM(ir));
b6ee75ed 988 MIPS_FPU_EMU_INC_STATS(loads);
515b029d 989
3f7cac41 990 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
b6ee75ed 991 MIPS_FPU_EMU_INC_STATS(errors);
3f7cac41 992 *fault_addr = dva;
1da177e4
LT		 993 return SIGBUS;
994 }
3f7cac41 995 if (__get_user(dval, dva)) {
515b029d 996 MIPS_FPU_EMU_INC_STATS(errors);
3f7cac41 997 *fault_addr = dva;
515b029d
DD		 998 return SIGSEGV;
999 }
3f7cac41 1000 DITOREG(dval, MIPSInst_RT(ir));
1da177e4 1001 break;
1da177e4 1002
3f7cac41
RB		 1003 case sdc1_op:
1004 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1005 MIPSInst_SIMM(ir));
b6ee75ed 1006 MIPS_FPU_EMU_INC_STATS(stores);
3f7cac41
RB		 1007 DIFROMREG(dval, MIPSInst_RT(ir));
1008 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
b6ee75ed 1009 MIPS_FPU_EMU_INC_STATS(errors);
3f7cac41 1010 *fault_addr = dva;
1da177e4
LT		 1011 return SIGBUS;
1012 }
3f7cac41 1013 if (__put_user(dval, dva)) {
515b029d 1014 MIPS_FPU_EMU_INC_STATS(errors);
3f7cac41 1015 *fault_addr = dva;
515b029d
DD		 1016 return SIGSEGV;
1017 }
1da177e4 1018 break;
1da177e4 1019
3f7cac41
RB		 1020 case lwc1_op:
1021 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1022 MIPSInst_SIMM(ir));
b6ee75ed 1023 MIPS_FPU_EMU_INC_STATS(loads);
3f7cac41 1024 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
b6ee75ed 1025 MIPS_FPU_EMU_INC_STATS(errors);
3f7cac41 1026 *fault_addr = wva;
1da177e4
LT		 1027 return SIGBUS;
1028 }
3f7cac41 1029 if (__get_user(wval, wva)) {
515b029d 1030 MIPS_FPU_EMU_INC_STATS(errors);
3f7cac41 1031 *fault_addr = wva;
515b029d
DD		 1032 return SIGSEGV;
1033 }
3f7cac41 1034 SITOREG(wval, MIPSInst_RT(ir));
1da177e4 1035 break;
1da177e4 1036
3f7cac41
RB		 1037 case swc1_op:
1038 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1039 MIPSInst_SIMM(ir));
b6ee75ed 1040 MIPS_FPU_EMU_INC_STATS(stores);
3f7cac41
RB		 1041 SIFROMREG(wval, MIPSInst_RT(ir));
1042 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
b6ee75ed 1043 MIPS_FPU_EMU_INC_STATS(errors);
3f7cac41 1044 *fault_addr = wva;
1da177e4
LT		 1045 return SIGBUS;
1046 }
3f7cac41 1047 if (__put_user(wval, wva)) {
515b029d 1048 MIPS_FPU_EMU_INC_STATS(errors);
3f7cac41 1049 *fault_addr = wva;
515b029d
DD		 1050 return SIGSEGV;
1051 }
1da177e4 1052 break;
1da177e4
LT		 1053
1054 case cop1_op:
1055 switch (MIPSInst_RS(ir)) {
1da177e4 1056 case dmfc_op:
08a07904
RB		 1057 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1058 return SIGILL;
1059
1da177e4
LT		 1060 /* copregister fs -> gpr[rt] */
1061 if (MIPSInst_RT(ir) != 0) {
1062 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1063 MIPSInst_RD(ir));
1064 }
1065 break;
1066
1067 case dmtc_op:
08a07904
RB		 1068 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1069 return SIGILL;
1070
1da177e4
LT		 1071 /* copregister fs <- rt */
1072 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1073 break;
1da177e4 1074
1ac94400
LY		 1075 case mfhc_op:
1076 if (!cpu_has_mips_r2)
1077 goto sigill;
1078
1079 /* copregister rd -> gpr[rt] */
1080 if (MIPSInst_RT(ir) != 0) {
1081 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1082 MIPSInst_RD(ir));
1083 }
1084 break;
1085
1086 case mthc_op:
1087 if (!cpu_has_mips_r2)
1088 goto sigill;
1089
1090 /* copregister rd <- gpr[rt] */
1091 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1092 break;
1093
1da177e4
LT		 1094 case mfc_op:
1095 /* copregister rd -> gpr[rt] */
1da177e4
LT		 1096 if (MIPSInst_RT(ir) != 0) {
1097 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1098 MIPSInst_RD(ir));
1099 }
1100 break;
1101
1102 case mtc_op:
1103 /* copregister rd <- rt */
1da177e4
LT		 1104 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1105 break;
1106
3f7cac41 1107 case cfc_op:
1da177e4 1108 /* cop control register rd -> gpr[rt] */
1da177e4
LT		 1109 if (MIPSInst_RD(ir) == FPCREG_CSR) {
1110 value = ctx->fcr31;
3f135530
SM		 1111 value = (value & ~FPU_CSR_RM) |
1112 mips_rm[modeindex(value)];
92df0f8b
RB		 1113 pr_debug("%p gpr[%d]<-csr=%08x\n",
1114 (void *) (xcp->cp0_epc),
1115 MIPSInst_RT(ir), value);
1da177e4
LT		 1116 }
1117 else if (MIPSInst_RD(ir) == FPCREG_RID)
1118 value = 0;
1119 else
1120 value = 0;
1121 if (MIPSInst_RT(ir))
1122 xcp->regs[MIPSInst_RT(ir)] = value;
1123 break;
1da177e4 1124
3f7cac41 1125 case ctc_op:
1da177e4 1126 /* copregister rd <- rt */
1da177e4
LT		 1127 if (MIPSInst_RT(ir) == 0)
1128 value = 0;
1129 else
1130 value = xcp->regs[MIPSInst_RT(ir)];
1131
1132 /* we only have one writable control reg
1133 */
1134 if (MIPSInst_RD(ir) == FPCREG_CSR) {
92df0f8b
RB		 1135 pr_debug("%p gpr[%d]->csr=%08x\n",
1136 (void *) (xcp->cp0_epc),
1137 MIPSInst_RT(ir), value);
95e8f634
SM		 1138
1139 /*
1140 * Don't write reserved bits,
1141 * and convert to ieee library modes
1142 */
1143 ctx->fcr31 = (value &
1144 ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
1145 ieee_rm[modeindex(value)];
1da177e4
LT		 1146 }
1147 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1148 return SIGFPE;
1149 }
1150 break;
1da177e4 1151
3f7cac41 1152 case bc_op:
e7e9cae5 1153 if (delay_slot(xcp))
1da177e4
LT		 1154 return SIGILL;
1155
08a07904
RB		 1156 if (cpu_has_mips_4_5_r)
1157 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1158 else
1159 cbit = FPU_CSR_COND;
1160 cond = ctx->fcr31 & cbit;
1161
3f7cac41 1162 likely = 0;
1da177e4
LT		 1163 switch (MIPSInst_RT(ir) & 3) {
1164 case bcfl_op:
1165 likely = 1;
1166 case bcf_op:
1167 cond = !cond;
1168 break;
1169 case bctl_op:
1170 likely = 1;
1171 case bct_op:
1172 break;
1173 default:
1174 /* thats an illegal instruction */
1175 return SIGILL;
1176 }
1177
e7e9cae5 1178 set_delay_slot(xcp);
1da177e4 1179 if (cond) {
3f7cac41
RB		 1180 /*
1181 * Branch taken: emulate dslot instruction
1da177e4 1182 */
102cedc3
LY		 1183 xcp->cp0_epc += dec_insn.pc_inc;
1184
1185 contpc = MIPSInst_SIMM(ir);
1186 ir = dec_insn.next_insn;
1187 if (dec_insn.micro_mips_mode) {
1188 contpc = (xcp->cp0_epc + (contpc << 1));
1189
1190 /* If 16-bit instruction, not FPU. */
1191 if ((dec_insn.next_pc_inc == 2) ||
1192 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1193
1194 /*
1195 * Since this instruction will
1196 * be put on the stack with
1197 * 32-bit words, get around
1198 * this problem by putting a
1199 * NOP16 as the second one.
1200 */
1201 if (dec_insn.next_pc_inc == 2)
1202 ir = (ir & (~0xffff)) | MM_NOP16;
1203
1204 /*
1205 * Single step the non-CP1
1206 * instruction in the dslot.
1207 */
1208 return mips_dsemul(xcp, ir, contpc);
1209 }
1210 } else
1211 contpc = (xcp->cp0_epc + (contpc << 2));
1da177e4
LT		 1212
1213 switch (MIPSInst_OPCODE(ir)) {
1214 case lwc1_op:
08a07904 1215 goto emul;
3f7cac41 1216
1da177e4 1217 case swc1_op:
08a07904 1218 goto emul;
3f7cac41 1219
1da177e4
LT		 1220 case ldc1_op:
1221 case sdc1_op:
08a07904
RB		 1222 if (cpu_has_mips_2_3_4_5 ||
1223 cpu_has_mips64)
1224 goto emul;
1225
1226 return SIGILL;
1227 goto emul;
3f7cac41 1228
1da177e4 1229 case cop1_op:
1da177e4 1230 goto emul;
3f7cac41 1231
08a07904
RB		 1232 case cop1x_op:
1233 if (cpu_has_mips_4_5 || cpu_has_mips64)
1234 /* its one of ours */
1235 goto emul;
1236
1237 return SIGILL;
3f7cac41 1238
1da177e4 1239 case spec_op:
08a07904
RB		 1240 if (!cpu_has_mips_4_5_r)
1241 return SIGILL;
1242
1da177e4
LT		 1243 if (MIPSInst_FUNC(ir) == movc_op)
1244 goto emul;
1245 break;
1da177e4
LT		 1246 }
1247
1248 /*
1249 * Single step the non-cp1
1250 * instruction in the dslot
1251 */
e70dfc10 1252 return mips_dsemul(xcp, ir, contpc);
3f7cac41 1253 } else if (likely) { /* branch not taken */
1da177e4
LT		 1254 /*
1255 * branch likely nullifies
1256 * dslot if not taken
1257 */
102cedc3
LY		 1258 xcp->cp0_epc += dec_insn.pc_inc;
1259 contpc += dec_insn.pc_inc;
1da177e4
LT		 1260 /*
1261 * else continue & execute
1262 * dslot as normal insn
1263 */
1264 }
1da177e4 1265 break;
1da177e4
LT		 1266
1267 default:
1268 if (!(MIPSInst_RS(ir) & 0x10))
1269 return SIGILL;
1da177e4 1270
3f7cac41
RB		 1271 /* a real fpu computation instruction */
1272 if ((sig = fpu_emu(xcp, ctx, ir)))
1273 return sig;
1da177e4
LT		 1274 }
1275 break;
1276
3f7cac41 1277 case cop1x_op:
08a07904
RB		 1278 if (!cpu_has_mips_4_5 && !cpu_has_mips64)
1279 return SIGILL;
1280
1281 sig = fpux_emu(xcp, ctx, ir, fault_addr);
515b029d 1282 if (sig)
1da177e4
LT		 1283 return sig;
1284 break;
1da177e4 1285
1da177e4 1286 case spec_op:
08a07904
RB		 1287 if (!cpu_has_mips_4_5_r)
1288 return SIGILL;
1289
1da177e4
LT		 1290 if (MIPSInst_FUNC(ir) != movc_op)
1291 return SIGILL;
1292 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1293 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1294 xcp->regs[MIPSInst_RD(ir)] =
1295 xcp->regs[MIPSInst_RS(ir)];
1296 break;
1da177e4 1297 default:
1ac94400 1298sigill:
1da177e4
LT		 1299 return SIGILL;
1300 }
1301
1302 /* we did it !! */
e70dfc10 1303 xcp->cp0_epc = contpc;
e7e9cae5 1304 clear_delay_slot(xcp);
333d1f67 1305
1da177e4
LT		 1306 return 0;
1307}
1308
1309/*
1310 * Conversion table from MIPS compare ops 48-63
1311 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1312 */
1313static const unsigned char cmptab[8] = {
1314 0, /* cmp_0 (sig) cmp_sf */
1315 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1316 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1317 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1318 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1319 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1320 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1321 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1322};
1323
1324
1da177e4
LT		 1325/*
1326 * Additional MIPS4 instructions
1327 */
1328
47fa0c02
RB		 1329#define DEF3OP(name, p, f1, f2, f3) \
1330static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1331 union ieee754##p s, union ieee754##p t) \
1332{ \
1333 struct _ieee754_csr ieee754_csr_save; \
1334 s = f1(s, t); \
1335 ieee754_csr_save = ieee754_csr; \
1336 s = f2(s, r); \
1337 ieee754_csr_save.cx |= ieee754_csr.cx; \
1338 ieee754_csr_save.sx |= ieee754_csr.sx; \
1339 s = f3(s); \
1340 ieee754_csr.cx |= ieee754_csr_save.cx; \
1341 ieee754_csr.sx |= ieee754_csr_save.sx; \
1342 return s; \
1da177e4
LT		 1343}
1344
2209bcb1 1345static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1da177e4
LT		 1346{
1347 return ieee754dp_div(ieee754dp_one(0), d);
1348}
1349
2209bcb1 1350static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1da177e4
LT		 1351{
1352 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1353}
1354
2209bcb1 1355static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1da177e4
LT		 1356{
1357 return ieee754sp_div(ieee754sp_one(0), s);
1358}
1359
2209bcb1 1360static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1da177e4
LT		 1361{
1362 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1363}
1364
21a151d8
RB		 1365DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1366DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1da177e4
LT		 1367DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1368DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
21a151d8
RB		 1369DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1370DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1da177e4
LT		 1371DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1372DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1373
eae89076 1374static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
515b029d 1375 mips_instruction ir, void *__user *fault_addr)
1da177e4
LT		 1376{
1377 unsigned rcsr = 0; /* resulting csr */
1378
b6ee75ed 1379 MIPS_FPU_EMU_INC_STATS(cp1xops);
1da177e4
LT		 1380
1381 switch (MIPSInst_FMA_FFMT(ir)) {
1382 case s_fmt:{ /* 0 */
1383
2209bcb1
RB		 1384 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1385 union ieee754sp fd, fr, fs, ft;
3fccc015 1386 u32 __user *va;
1da177e4
LT		 1387 u32 val;
1388
1389 switch (MIPSInst_FUNC(ir)) {
1390 case lwxc1_op:
3fccc015 1391 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1da177e4
LT		 1392 xcp->regs[MIPSInst_FT(ir)]);
1393
b6ee75ed 1394 MIPS_FPU_EMU_INC_STATS(loads);
515b029d 1395 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
b6ee75ed 1396 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1397 *fault_addr = va;
1da177e4
LT		 1398 return SIGBUS;
1399 }
515b029d
DD		 1400 if (__get_user(val, va)) {
1401 MIPS_FPU_EMU_INC_STATS(errors);
1402 *fault_addr = va;
1403 return SIGSEGV;
1404 }
1da177e4
LT		 1405 SITOREG(val, MIPSInst_FD(ir));
1406 break;
1407
1408 case swxc1_op:
3fccc015 1409 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1da177e4
LT		 1410 xcp->regs[MIPSInst_FT(ir)]);
1411
b6ee75ed 1412 MIPS_FPU_EMU_INC_STATS(stores);
1da177e4
LT		 1413
1414 SIFROMREG(val, MIPSInst_FS(ir));
515b029d 1415 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
b6ee75ed 1416 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1417 *fault_addr = va;
1da177e4
LT		 1418 return SIGBUS;
1419 }
515b029d
DD		 1420 if (put_user(val, va)) {
1421 MIPS_FPU_EMU_INC_STATS(errors);
1422 *fault_addr = va;
1423 return SIGSEGV;
1424 }
1da177e4
LT		 1425 break;
1426
1427 case madd_s_op:
1428 handler = fpemu_sp_madd;
1429 goto scoptop;
1430 case msub_s_op:
1431 handler = fpemu_sp_msub;
1432 goto scoptop;
1433 case nmadd_s_op:
1434 handler = fpemu_sp_nmadd;
1435 goto scoptop;
1436 case nmsub_s_op:
1437 handler = fpemu_sp_nmsub;
1438 goto scoptop;
1439
1440 scoptop:
1441 SPFROMREG(fr, MIPSInst_FR(ir));
1442 SPFROMREG(fs, MIPSInst_FS(ir));
1443 SPFROMREG(ft, MIPSInst_FT(ir));
1444 fd = (*handler) (fr, fs, ft);
1445 SPTOREG(fd, MIPSInst_FD(ir));
1446
1447 copcsr:
1448 if (ieee754_cxtest(IEEE754_INEXACT))
1449 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1450 if (ieee754_cxtest(IEEE754_UNDERFLOW))
1451 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1452 if (ieee754_cxtest(IEEE754_OVERFLOW))
1453 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1454 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
1455 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1456
1457 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1da177e4 1458 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
3f7cac41 1459 /*printk ("SIGFPE: FPU csr = %08x\n",
1da177e4
LT		 1460 ctx->fcr31); */
1461 return SIGFPE;
1462 }
1463
1464 break;
1465
1466 default:
1467 return SIGILL;
1468 }
1469 break;
1470 }
1471
1da177e4 1472 case d_fmt:{ /* 1 */
2209bcb1
RB		 1473 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1474 union ieee754dp fd, fr, fs, ft;
3fccc015 1475 u64 __user *va;
1da177e4
LT		 1476 u64 val;
1477
1478 switch (MIPSInst_FUNC(ir)) {
1479 case ldxc1_op:
3fccc015 1480 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1da177e4
LT		 1481 xcp->regs[MIPSInst_FT(ir)]);
1482
b6ee75ed 1483 MIPS_FPU_EMU_INC_STATS(loads);
515b029d 1484 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
b6ee75ed 1485 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1486 *fault_addr = va;
1da177e4
LT		 1487 return SIGBUS;
1488 }
515b029d
DD		 1489 if (__get_user(val, va)) {
1490 MIPS_FPU_EMU_INC_STATS(errors);
1491 *fault_addr = va;
1492 return SIGSEGV;
1493 }
1da177e4
LT		 1494 DITOREG(val, MIPSInst_FD(ir));
1495 break;
1496
1497 case sdxc1_op:
3fccc015 1498 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1da177e4
LT		 1499 xcp->regs[MIPSInst_FT(ir)]);
1500
b6ee75ed 1501 MIPS_FPU_EMU_INC_STATS(stores);
1da177e4 1502 DIFROMREG(val, MIPSInst_FS(ir));
515b029d 1503 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
b6ee75ed 1504 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1505 *fault_addr = va;
1da177e4
LT		 1506 return SIGBUS;
1507 }
515b029d
DD		 1508 if (__put_user(val, va)) {
1509 MIPS_FPU_EMU_INC_STATS(errors);
1510 *fault_addr = va;
1511 return SIGSEGV;
1512 }
1da177e4
LT		 1513 break;
1514
1515 case madd_d_op:
1516 handler = fpemu_dp_madd;
1517 goto dcoptop;
1518 case msub_d_op:
1519 handler = fpemu_dp_msub;
1520 goto dcoptop;
1521 case nmadd_d_op:
1522 handler = fpemu_dp_nmadd;
1523 goto dcoptop;
1524 case nmsub_d_op:
1525 handler = fpemu_dp_nmsub;
1526 goto dcoptop;
1527
1528 dcoptop:
1529 DPFROMREG(fr, MIPSInst_FR(ir));
1530 DPFROMREG(fs, MIPSInst_FS(ir));
1531 DPFROMREG(ft, MIPSInst_FT(ir));
1532 fd = (*handler) (fr, fs, ft);
1533 DPTOREG(fd, MIPSInst_FD(ir));
1534 goto copcsr;
1535
1536 default:
1537 return SIGILL;
1538 }
1539 break;
1540 }
1da177e4 1541
51061b88
DCZ		 1542 case 0x3:
1543 if (MIPSInst_FUNC(ir) != pfetch_op)
1da177e4 1544 return SIGILL;
51061b88 1545
1da177e4
LT		 1546 /* ignore prefx operation */
1547 break;
1548
1549 default:
1550 return SIGILL;
1551 }
1552
1553 return 0;
1554}
1da177e4
LT		 1555
1556
1557
1558/*
1559 * Emulate a single COP1 arithmetic instruction.
1560 */
eae89076 1561static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1da177e4
LT		 1562 mips_instruction ir)
1563{
1564 int rfmt; /* resulting format */
1565 unsigned rcsr = 0; /* resulting csr */
3f7cac41
RB		 1566 unsigned int oldrm;
1567 unsigned int cbit;
1da177e4
LT		 1568 unsigned cond;
1569 union {
2209bcb1
RB		 1570 union ieee754dp d;
1571 union ieee754sp s;
1da177e4 1572 int w;
1da177e4 1573 s64 l;
1da177e4 1574 } rv; /* resulting value */
3f7cac41 1575 u64 bits;
1da177e4 1576
b6ee75ed 1577 MIPS_FPU_EMU_INC_STATS(cp1ops);
1da177e4 1578 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
3f7cac41 1579 case s_fmt: { /* 0 */
1da177e4 1580 union {
2209bcb1
RB		 1581 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1582 union ieee754sp(*u) (union ieee754sp);
1da177e4 1583 } handler;
3f7cac41 1584 union ieee754sp fs, ft;
1da177e4
LT		 1585
1586 switch (MIPSInst_FUNC(ir)) {
1587 /* binary ops */
1588 case fadd_op:
1589 handler.b = ieee754sp_add;
1590 goto scopbop;
1591 case fsub_op:
1592 handler.b = ieee754sp_sub;
1593 goto scopbop;
1594 case fmul_op:
1595 handler.b = ieee754sp_mul;
1596 goto scopbop;
1597 case fdiv_op:
1598 handler.b = ieee754sp_div;
1599 goto scopbop;
1600
1601 /* unary ops */
1da177e4 1602 case fsqrt_op:
08a07904
RB		 1603 if (!cpu_has_mips_4_5_r)
1604 return SIGILL;
1605
1da177e4
LT		 1606 handler.u = ieee754sp_sqrt;
1607 goto scopuop;
3f7cac41 1608
08a07904
RB		 1609 /*
1610 * Note that on some MIPS IV implementations such as the
1611 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1612 * achieve full IEEE-754 accuracy - however this emulator does.
1613 */
1da177e4 1614 case frsqrt_op:
08a07904
RB		 1615 if (!cpu_has_mips_4_5_r2)
1616 return SIGILL;
1617
1da177e4
LT		 1618 handler.u = fpemu_sp_rsqrt;
1619 goto scopuop;
3f7cac41 1620
1da177e4 1621 case frecip_op:
08a07904
RB		 1622 if (!cpu_has_mips_4_5_r2)
1623 return SIGILL;
1624
1da177e4
LT		 1625 handler.u = fpemu_sp_recip;
1626 goto scopuop;
08a07904 1627
1da177e4 1628 case fmovc_op:
08a07904
RB		 1629 if (!cpu_has_mips_4_5_r)
1630 return SIGILL;
1631
1da177e4
LT		 1632 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1633 if (((ctx->fcr31 & cond) != 0) !=
1634 ((MIPSInst_FT(ir) & 1) != 0))
1635 return 0;
1636 SPFROMREG(rv.s, MIPSInst_FS(ir));
1637 break;
3f7cac41 1638
1da177e4 1639 case fmovz_op:
08a07904
RB		 1640 if (!cpu_has_mips_4_5_r)
1641 return SIGILL;
1642
1da177e4
LT		 1643 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1644 return 0;
1645 SPFROMREG(rv.s, MIPSInst_FS(ir));
1646 break;
3f7cac41 1647
1da177e4 1648 case fmovn_op:
08a07904
RB		 1649 if (!cpu_has_mips_4_5_r)
1650 return SIGILL;
1651
1da177e4
LT		 1652 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1653 return 0;
1654 SPFROMREG(rv.s, MIPSInst_FS(ir));
1655 break;
3f7cac41 1656
1da177e4
LT		 1657 case fabs_op:
1658 handler.u = ieee754sp_abs;
1659 goto scopuop;
3f7cac41 1660
1da177e4
LT		 1661 case fneg_op:
1662 handler.u = ieee754sp_neg;
1663 goto scopuop;
3f7cac41 1664
1da177e4
LT		 1665 case fmov_op:
1666 /* an easy one */
1667 SPFROMREG(rv.s, MIPSInst_FS(ir));
1668 goto copcsr;
1669
1670 /* binary op on handler */
3f7cac41
RB		 1671scopbop:
1672 SPFROMREG(fs, MIPSInst_FS(ir));
1673 SPFROMREG(ft, MIPSInst_FT(ir));
1da177e4 1674
3f7cac41
RB		 1675 rv.s = (*handler.b) (fs, ft);
1676 goto copcsr;
1677scopuop:
1678 SPFROMREG(fs, MIPSInst_FS(ir));
1679 rv.s = (*handler.u) (fs);
1680 goto copcsr;
1681copcsr:
1da177e4
LT		 1682 if (ieee754_cxtest(IEEE754_INEXACT))
1683 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1684 if (ieee754_cxtest(IEEE754_UNDERFLOW))
1685 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1686 if (ieee754_cxtest(IEEE754_OVERFLOW))
1687 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1688 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE))
1689 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1690 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
1691 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1692 break;
1693
1694 /* unary conv ops */
1695 case fcvts_op:
1696 return SIGILL; /* not defined */
1da177e4 1697
3f7cac41 1698 case fcvtd_op:
1da177e4
LT		 1699 SPFROMREG(fs, MIPSInst_FS(ir));
1700 rv.d = ieee754dp_fsp(fs);
1701 rfmt = d_fmt;
1702 goto copcsr;
1da177e4 1703
3f7cac41 1704 case fcvtw_op:
1da177e4
LT		 1705 SPFROMREG(fs, MIPSInst_FS(ir));
1706 rv.w = ieee754sp_tint(fs);
1707 rfmt = w_fmt;
1708 goto copcsr;
1da177e4 1709
1da177e4
LT		 1710 case fround_op:
1711 case ftrunc_op:
1712 case fceil_op:
3f7cac41 1713 case ffloor_op:
08a07904
RB		 1714 if (!cpu_has_mips_2_3_4_5 && !cpu_has_mips64)
1715 return SIGILL;
1716
3f7cac41 1717 oldrm = ieee754_csr.rm;
1da177e4 1718 SPFROMREG(fs, MIPSInst_FS(ir));
3f135530 1719 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1da177e4
LT		 1720 rv.w = ieee754sp_tint(fs);
1721 ieee754_csr.rm = oldrm;
1722 rfmt = w_fmt;
1723 goto copcsr;
1da177e4 1724
3f7cac41 1725 case fcvtl_op:
08a07904
RB		 1726 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1727 return SIGILL;
1728
1da177e4
LT		 1729 SPFROMREG(fs, MIPSInst_FS(ir));
1730 rv.l = ieee754sp_tlong(fs);
1731 rfmt = l_fmt;
1732 goto copcsr;
1da177e4
LT		 1733
1734 case froundl_op:
1735 case ftruncl_op:
1736 case fceill_op:
3f7cac41 1737 case ffloorl_op:
08a07904
RB		 1738 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1739 return SIGILL;
1740
3f7cac41 1741 oldrm = ieee754_csr.rm;
1da177e4 1742 SPFROMREG(fs, MIPSInst_FS(ir));
3f135530 1743 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1da177e4
LT		 1744 rv.l = ieee754sp_tlong(fs);
1745 ieee754_csr.rm = oldrm;
1746 rfmt = l_fmt;
1747 goto copcsr;
1da177e4
LT		 1748
1749 default:
1750 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1751 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2209bcb1 1752 union ieee754sp fs, ft;
1da177e4
LT		 1753
1754 SPFROMREG(fs, MIPSInst_FS(ir));
1755 SPFROMREG(ft, MIPSInst_FT(ir));
1756 rv.w = ieee754sp_cmp(fs, ft,
1757 cmptab[cmpop & 0x7], cmpop & 0x8);
1758 rfmt = -1;
1759 if ((cmpop & 0x8) && ieee754_cxtest
1760 (IEEE754_INVALID_OPERATION))
1761 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1762 else
1763 goto copcsr;
1764
3f7cac41 1765 } else
1da177e4 1766 return SIGILL;
1da177e4
LT		 1767 break;
1768 }
1769 break;
1770 }
1771
3f7cac41
RB		 1772 case d_fmt: {
1773 union ieee754dp fs, ft;
1da177e4 1774 union {
2209bcb1
RB		 1775 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
1776 union ieee754dp(*u) (union ieee754dp);
1da177e4
LT		 1777 } handler;
1778
1779 switch (MIPSInst_FUNC(ir)) {
1780 /* binary ops */
1781 case fadd_op:
1782 handler.b = ieee754dp_add;
1783 goto dcopbop;
1784 case fsub_op:
1785 handler.b = ieee754dp_sub;
1786 goto dcopbop;
1787 case fmul_op:
1788 handler.b = ieee754dp_mul;
1789 goto dcopbop;
1790 case fdiv_op:
1791 handler.b = ieee754dp_div;
1792 goto dcopbop;
1793
1794 /* unary ops */
1da177e4 1795 case fsqrt_op:
08a07904
RB		 1796 if (!cpu_has_mips_2_3_4_5_r)
1797 return SIGILL;
1798
1da177e4
LT		 1799 handler.u = ieee754dp_sqrt;
1800 goto dcopuop;
08a07904
RB		 1801 /*
1802 * Note that on some MIPS IV implementations such as the
1803 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1804 * achieve full IEEE-754 accuracy - however this emulator does.
1805 */
1da177e4 1806 case frsqrt_op:
08a07904
RB		 1807 if (!cpu_has_mips_4_5_r2)
1808 return SIGILL;
1809
1da177e4
LT		 1810 handler.u = fpemu_dp_rsqrt;
1811 goto dcopuop;
1812 case frecip_op:
08a07904
RB		 1813 if (!cpu_has_mips_4_5_r2)
1814 return SIGILL;
1815
1da177e4
LT		 1816 handler.u = fpemu_dp_recip;
1817 goto dcopuop;
1da177e4 1818 case fmovc_op:
08a07904
RB		 1819 if (!cpu_has_mips_4_5_r)
1820 return SIGILL;
1821
1da177e4
LT		 1822 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1823 if (((ctx->fcr31 & cond) != 0) !=
1824 ((MIPSInst_FT(ir) & 1) != 0))
1825 return 0;
1826 DPFROMREG(rv.d, MIPSInst_FS(ir));
1827 break;
1828 case fmovz_op:
08a07904
RB		 1829 if (!cpu_has_mips_4_5_r)
1830 return SIGILL;
1831
1da177e4
LT		 1832 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1833 return 0;
1834 DPFROMREG(rv.d, MIPSInst_FS(ir));
1835 break;
1836 case fmovn_op:
08a07904
RB		 1837 if (!cpu_has_mips_4_5_r)
1838 return SIGILL;
1839
1da177e4
LT		 1840 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1841 return 0;
1842 DPFROMREG(rv.d, MIPSInst_FS(ir));
1843 break;
1da177e4
LT		 1844 case fabs_op:
1845 handler.u = ieee754dp_abs;
1846 goto dcopuop;
1847
1848 case fneg_op:
1849 handler.u = ieee754dp_neg;
1850 goto dcopuop;
1851
1852 case fmov_op:
1853 /* an easy one */
1854 DPFROMREG(rv.d, MIPSInst_FS(ir));
1855 goto copcsr;
1856
1857 /* binary op on handler */
3f7cac41
RB		 1858dcopbop:
1859 DPFROMREG(fs, MIPSInst_FS(ir));
1860 DPFROMREG(ft, MIPSInst_FT(ir));
1da177e4 1861
3f7cac41
RB		 1862 rv.d = (*handler.b) (fs, ft);
1863 goto copcsr;
1864dcopuop:
1865 DPFROMREG(fs, MIPSInst_FS(ir));
1866 rv.d = (*handler.u) (fs);
1867 goto copcsr;
1da177e4 1868
3f7cac41
RB		 1869 /*
1870 * unary conv ops
1871 */
1872 case fcvts_op:
1da177e4
LT		 1873 DPFROMREG(fs, MIPSInst_FS(ir));
1874 rv.s = ieee754sp_fdp(fs);
1875 rfmt = s_fmt;
1876 goto copcsr;
3f7cac41 1877
1da177e4
LT		 1878 case fcvtd_op:
1879 return SIGILL; /* not defined */
1880
3f7cac41 1881 case fcvtw_op:
1da177e4
LT		 1882 DPFROMREG(fs, MIPSInst_FS(ir));
1883 rv.w = ieee754dp_tint(fs); /* wrong */
1884 rfmt = w_fmt;
1885 goto copcsr;
1da177e4 1886
1da177e4
LT		 1887 case fround_op:
1888 case ftrunc_op:
1889 case fceil_op:
3f7cac41 1890 case ffloor_op:
08a07904
RB		 1891 if (!cpu_has_mips_2_3_4_5_r)
1892 return SIGILL;
1893
3f7cac41 1894 oldrm = ieee754_csr.rm;
1da177e4 1895 DPFROMREG(fs, MIPSInst_FS(ir));
3f135530 1896 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1da177e4
LT		 1897 rv.w = ieee754dp_tint(fs);
1898 ieee754_csr.rm = oldrm;
1899 rfmt = w_fmt;
1900 goto copcsr;
1da177e4 1901
3f7cac41 1902 case fcvtl_op:
08a07904
RB		 1903 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1904 return SIGILL;
1905
1da177e4
LT		 1906 DPFROMREG(fs, MIPSInst_FS(ir));
1907 rv.l = ieee754dp_tlong(fs);
1908 rfmt = l_fmt;
1909 goto copcsr;
1da177e4
LT		 1910
1911 case froundl_op:
1912 case ftruncl_op:
1913 case fceill_op:
3f7cac41 1914 case ffloorl_op:
08a07904
RB		 1915 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1916 return SIGILL;
1917
3f7cac41 1918 oldrm = ieee754_csr.rm;
1da177e4 1919 DPFROMREG(fs, MIPSInst_FS(ir));
3f135530 1920 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1da177e4
LT		 1921 rv.l = ieee754dp_tlong(fs);
1922 ieee754_csr.rm = oldrm;
1923 rfmt = l_fmt;
1924 goto copcsr;
1da177e4
LT		 1925
1926 default:
1927 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1928 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2209bcb1 1929 union ieee754dp fs, ft;
1da177e4
LT		 1930
1931 DPFROMREG(fs, MIPSInst_FS(ir));
1932 DPFROMREG(ft, MIPSInst_FT(ir));
1933 rv.w = ieee754dp_cmp(fs, ft,
1934 cmptab[cmpop & 0x7], cmpop & 0x8);
1935 rfmt = -1;
1936 if ((cmpop & 0x8)
1937 &&
1938 ieee754_cxtest
1939 (IEEE754_INVALID_OPERATION))
1940 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1941 else
1942 goto copcsr;
1943
1944 }
1945 else {
1946 return SIGILL;
1947 }
1948 break;
1949 }
1950 break;
1da177e4 1951
3f7cac41 1952 case w_fmt:
1da177e4
LT		 1953 switch (MIPSInst_FUNC(ir)) {
1954 case fcvts_op:
1955 /* convert word to single precision real */
1956 SPFROMREG(fs, MIPSInst_FS(ir));
1957 rv.s = ieee754sp_fint(fs.bits);
1958 rfmt = s_fmt;
1959 goto copcsr;
1da177e4
LT		 1960 case fcvtd_op:
1961 /* convert word to double precision real */
1962 SPFROMREG(fs, MIPSInst_FS(ir));
1963 rv.d = ieee754dp_fint(fs.bits);
1964 rfmt = d_fmt;
1965 goto copcsr;
1da177e4
LT		 1966 default:
1967 return SIGILL;
1968 }
1969 break;
1970 }
1971
3f7cac41 1972 case l_fmt:
08a07904
RB		 1973
1974 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1975 return SIGILL;
1976
bbd426f5
PB		 1977 DIFROMREG(bits, MIPSInst_FS(ir));
1978
1da177e4
LT		 1979 switch (MIPSInst_FUNC(ir)) {
1980 case fcvts_op:
1981 /* convert long to single precision real */
bbd426f5 1982 rv.s = ieee754sp_flong(bits);
1da177e4
LT		 1983 rfmt = s_fmt;
1984 goto copcsr;
1985 case fcvtd_op:
1986 /* convert long to double precision real */
bbd426f5 1987 rv.d = ieee754dp_flong(bits);
1da177e4
LT		 1988 rfmt = d_fmt;
1989 goto copcsr;
1990 default:
1991 return SIGILL;
1992 }
1993 break;
1da177e4
LT		 1994
1995 default:
1996 return SIGILL;
1997 }
1998
1999 /*
2000 * Update the fpu CSR register for this operation.
2001 * If an exception is required, generate a tidy SIGFPE exception,
2002 * without updating the result register.
2003 * Note: cause exception bits do not accumulate, they are rewritten
2004 * for each op; only the flag/sticky bits accumulate.
2005 */
2006 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2007 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
3f7cac41 2008 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
1da177e4
LT		 2009 return SIGFPE;
2010 }
2011
2012 /*
2013 * Now we can safely write the result back to the register file.
2014 */
2015 switch (rfmt) {
08a07904
RB		 2016 case -1:
2017
2018 if (cpu_has_mips_4_5_r)
2019 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
2020 else
2021 cbit = FPU_CSR_COND;
1da177e4 2022 if (rv.w)
08a07904 2023 ctx->fcr31 |= cbit;
1da177e4 2024 else
08a07904 2025 ctx->fcr31 &= ~cbit;
1da177e4 2026 break;
08a07904 2027
1da177e4
LT		 2028 case d_fmt:
2029 DPTOREG(rv.d, MIPSInst_FD(ir));
2030 break;
1da177e4
LT		 2031 case s_fmt:
2032 SPTOREG(rv.s, MIPSInst_FD(ir));
2033 break;
2034 case w_fmt:
2035 SITOREG(rv.w, MIPSInst_FD(ir));
2036 break;
1da177e4 2037 case l_fmt:
08a07904
RB		 2038 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
2039 return SIGILL;
2040
1da177e4
LT		 2041 DITOREG(rv.l, MIPSInst_FD(ir));
2042 break;
1da177e4
LT		 2043 default:
2044 return SIGILL;
2045 }
2046
2047 return 0;
2048}
2049
e04582b7 2050int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
515b029d 2051 int has_fpu, void *__user *fault_addr)
1da177e4 2052{
333d1f67 2053 unsigned long oldepc, prevepc;
102cedc3
LY		 2054 struct mm_decoded_insn dec_insn;
2055 u16 instr[4];
2056 u16 *instr_ptr;
1da177e4
LT		 2057 int sig = 0;
2058
2059 oldepc = xcp->cp0_epc;
2060 do {
2061 prevepc = xcp->cp0_epc;
2062
102cedc3
LY		 2063 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2064 /*
2065 * Get next 2 microMIPS instructions and convert them
2066 * into 32-bit instructions.
2067 */
2068 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2069 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2070 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2071 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2072 MIPS_FPU_EMU_INC_STATS(errors);
2073 return SIGBUS;
2074 }
2075 instr_ptr = instr;
2076
2077 /* Get first instruction. */
2078 if (mm_insn_16bit(*instr_ptr)) {
2079 /* Duplicate the half-word. */
2080 dec_insn.insn = (*instr_ptr << 16) |
2081 (*instr_ptr);
2082 /* 16-bit instruction. */
2083 dec_insn.pc_inc = 2;
2084 instr_ptr += 1;
2085 } else {
2086 dec_insn.insn = (*instr_ptr << 16) |
2087 *(instr_ptr+1);
2088 /* 32-bit instruction. */
2089 dec_insn.pc_inc = 4;
2090 instr_ptr += 2;
2091 }
2092 /* Get second instruction. */
2093 if (mm_insn_16bit(*instr_ptr)) {
2094 /* Duplicate the half-word. */
2095 dec_insn.next_insn = (*instr_ptr << 16) |
2096 (*instr_ptr);
2097 /* 16-bit instruction. */
2098 dec_insn.next_pc_inc = 2;
2099 } else {
2100 dec_insn.next_insn = (*instr_ptr << 16) |
2101 *(instr_ptr+1);
2102 /* 32-bit instruction. */
2103 dec_insn.next_pc_inc = 4;
2104 }
2105 dec_insn.micro_mips_mode = 1;
2106 } else {
2107 if ((get_user(dec_insn.insn,
2108 (mips_instruction __user *) xcp->cp0_epc)) ||
2109 (get_user(dec_insn.next_insn,
2110 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2111 MIPS_FPU_EMU_INC_STATS(errors);
2112 return SIGBUS;
2113 }
2114 dec_insn.pc_inc = 4;
2115 dec_insn.next_pc_inc = 4;
2116 dec_insn.micro_mips_mode = 0;
515b029d 2117 }
102cedc3
LY		 2118
2119 if ((dec_insn.insn == 0) ||
2120 ((dec_insn.pc_inc == 2) &&
2121 ((dec_insn.insn & 0xffff) == MM_NOP16)))
2122 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
1da177e4 2123 else {
cd21dfcf
RB		 2124 /*
2125 * The 'ieee754_csr' is an alias of
70342287
RB		 2126 * ctx->fcr31. No need to copy ctx->fcr31 to
2127 * ieee754_csr. But ieee754_csr.rm is ieee
cd21dfcf
RB		 2128 * library modes. (not mips rounding mode)
2129 */
2130 /* convert to ieee library modes */
2131 ieee754_csr.rm = ieee_rm[ieee754_csr.rm];
102cedc3 2132 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
cd21dfcf
RB		 2133 /* revert to mips rounding mode */
2134 ieee754_csr.rm = mips_rm[ieee754_csr.rm];
1da177e4
LT		 2135 }
2136
e04582b7 2137 if (has_fpu)
1da177e4
LT		 2138 break;
2139 if (sig)
2140 break;
2141
2142 cond_resched();
2143 } while (xcp->cp0_epc > prevepc);
2144
2145 /* SIGILL indicates a non-fpu instruction */
2146 if (sig == SIGILL && xcp->cp0_epc != oldepc)
3f7cac41 2147 /* but if EPC has advanced, then ignore it */
1da177e4
LT		 2148 sig = 0;
2149
2150 return sig;
2151}
Linux kernel - Deliverables
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