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MIPS: math-emu: Add support for the MIPS R6 RINT FPU instruction
[deliverable/linux.git] / arch / mips / math-emu / cp1emu.c
CommitLineData
1da177e4 1/*
3f7cac41 2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
1da177e4
LT		 3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
1da177e4
LT		 6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
3f7cac41 21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1da177e4
LT		 22 *
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
26 *
27 * More surprisingly it is also required for #float(ieee), to help out
3f7cac41 28 * the hardware FPU at the boundaries of the IEEE-754 representation
1da177e4
LT		 29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
32 *
3f7cac41 33 * Note if you know that you won't have an FPU, then you'll get much
1da177e4
LT		 34 * better performance by compiling with -msoft-float!
35 */
36#include <linux/sched.h>
83fd38ca 37#include <linux/debugfs.h>
08a07904 38#include <linux/kconfig.h>
85c51c51 39#include <linux/percpu-defs.h>
7f788d2d 40#include <linux/perf_event.h>
1da177e4 41
cd8ee345 42#include <asm/branch.h>
1da177e4 43#include <asm/inst.h>
1da177e4
LT		 44#include <asm/ptrace.h>
45#include <asm/signal.h>
cd8ee345
RB		 46#include <asm/uaccess.h>
47
f6843626 48#include <asm/cpu-info.h>
cd8ee345 49#include <asm/processor.h>
1da177e4 50#include <asm/fpu_emulator.h>
102cedc3 51#include <asm/fpu.h>
b0a668fb 52#include <asm/mips-r2-to-r6-emul.h>
1da177e4
LT		 53
54#include "ieee754.h"
1da177e4 55
1da177e4
LT		 56/* Function which emulates a floating point instruction. */
57
eae89076 58static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
1da177e4
LT		 59 mips_instruction);
60
1da177e4 61static int fpux_emu(struct pt_regs *,
515b029d 62 struct mips_fpu_struct *, mips_instruction, void *__user *);
1da177e4 63
1da177e4
LT		 64/* Control registers */
65
66#define FPCREG_RID 0 /* $0 = revision id */
c491cfa2
MR		 67#define FPCREG_FCCR 25 /* $25 = fccr */
68#define FPCREG_FEXR 26 /* $26 = fexr */
69#define FPCREG_FENR 28 /* $28 = fenr */
1da177e4
LT		 70#define FPCREG_CSR 31 /* $31 = csr */
71
1da177e4 72/* convert condition code register number to csr bit */
b0a668fb 73const unsigned int fpucondbit[8] = {
c491cfa2 74 FPU_CSR_COND,
1da177e4
LT		 75 FPU_CSR_COND1,
76 FPU_CSR_COND2,
77 FPU_CSR_COND3,
78 FPU_CSR_COND4,
79 FPU_CSR_COND5,
80 FPU_CSR_COND6,
81 FPU_CSR_COND7
82};
1da177e4 83
102cedc3
LY		 84/* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
85static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
86static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
87static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
88static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
89
90/*
91 * This functions translates a 32-bit microMIPS instruction
92 * into a 32-bit MIPS32 instruction. Returns 0 on success
93 * and SIGILL otherwise.
94 */
95static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
96{
97 union mips_instruction insn = *insn_ptr;
98 union mips_instruction mips32_insn = insn;
99 int func, fmt, op;
100
101 switch (insn.mm_i_format.opcode) {
102 case mm_ldc132_op:
103 mips32_insn.mm_i_format.opcode = ldc1_op;
104 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
105 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
106 break;
107 case mm_lwc132_op:
108 mips32_insn.mm_i_format.opcode = lwc1_op;
109 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
110 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
111 break;
112 case mm_sdc132_op:
113 mips32_insn.mm_i_format.opcode = sdc1_op;
114 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
115 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
116 break;
117 case mm_swc132_op:
118 mips32_insn.mm_i_format.opcode = swc1_op;
119 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
120 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
121 break;
122 case mm_pool32i_op:
123 /* NOTE: offset is << by 1 if in microMIPS mode. */
124 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
125 (insn.mm_i_format.rt == mm_bc1t_op)) {
126 mips32_insn.fb_format.opcode = cop1_op;
127 mips32_insn.fb_format.bc = bc_op;
128 mips32_insn.fb_format.flag =
129 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
130 } else
131 return SIGILL;
132 break;
133 case mm_pool32f_op:
134 switch (insn.mm_fp0_format.func) {
135 case mm_32f_01_op:
136 case mm_32f_11_op:
137 case mm_32f_02_op:
138 case mm_32f_12_op:
139 case mm_32f_41_op:
140 case mm_32f_51_op:
141 case mm_32f_42_op:
142 case mm_32f_52_op:
143 op = insn.mm_fp0_format.func;
144 if (op == mm_32f_01_op)
145 func = madd_s_op;
146 else if (op == mm_32f_11_op)
147 func = madd_d_op;
148 else if (op == mm_32f_02_op)
149 func = nmadd_s_op;
150 else if (op == mm_32f_12_op)
151 func = nmadd_d_op;
152 else if (op == mm_32f_41_op)
153 func = msub_s_op;
154 else if (op == mm_32f_51_op)
155 func = msub_d_op;
156 else if (op == mm_32f_42_op)
157 func = nmsub_s_op;
158 else
159 func = nmsub_d_op;
160 mips32_insn.fp6_format.opcode = cop1x_op;
161 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
162 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
163 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
164 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
165 mips32_insn.fp6_format.func = func;
166 break;
167 case mm_32f_10_op:
168 func = -1; /* Invalid */
169 op = insn.mm_fp5_format.op & 0x7;
170 if (op == mm_ldxc1_op)
171 func = ldxc1_op;
172 else if (op == mm_sdxc1_op)
173 func = sdxc1_op;
174 else if (op == mm_lwxc1_op)
175 func = lwxc1_op;
176 else if (op == mm_swxc1_op)
177 func = swxc1_op;
178
179 if (func != -1) {
180 mips32_insn.r_format.opcode = cop1x_op;
181 mips32_insn.r_format.rs =
182 insn.mm_fp5_format.base;
183 mips32_insn.r_format.rt =
184 insn.mm_fp5_format.index;
185 mips32_insn.r_format.rd = 0;
186 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
187 mips32_insn.r_format.func = func;
188 } else
189 return SIGILL;
190 break;
191 case mm_32f_40_op:
192 op = -1; /* Invalid */
193 if (insn.mm_fp2_format.op == mm_fmovt_op)
194 op = 1;
195 else if (insn.mm_fp2_format.op == mm_fmovf_op)
196 op = 0;
197 if (op != -1) {
198 mips32_insn.fp0_format.opcode = cop1_op;
199 mips32_insn.fp0_format.fmt =
200 sdps_format[insn.mm_fp2_format.fmt];
201 mips32_insn.fp0_format.ft =
202 (insn.mm_fp2_format.cc<<2) + op;
203 mips32_insn.fp0_format.fs =
204 insn.mm_fp2_format.fs;
205 mips32_insn.fp0_format.fd =
206 insn.mm_fp2_format.fd;
207 mips32_insn.fp0_format.func = fmovc_op;
208 } else
209 return SIGILL;
210 break;
211 case mm_32f_60_op:
212 func = -1; /* Invalid */
213 if (insn.mm_fp0_format.op == mm_fadd_op)
214 func = fadd_op;
215 else if (insn.mm_fp0_format.op == mm_fsub_op)
216 func = fsub_op;
217 else if (insn.mm_fp0_format.op == mm_fmul_op)
218 func = fmul_op;
219 else if (insn.mm_fp0_format.op == mm_fdiv_op)
220 func = fdiv_op;
221 if (func != -1) {
222 mips32_insn.fp0_format.opcode = cop1_op;
223 mips32_insn.fp0_format.fmt =
224 sdps_format[insn.mm_fp0_format.fmt];
225 mips32_insn.fp0_format.ft =
226 insn.mm_fp0_format.ft;
227 mips32_insn.fp0_format.fs =
228 insn.mm_fp0_format.fs;
229 mips32_insn.fp0_format.fd =
230 insn.mm_fp0_format.fd;
231 mips32_insn.fp0_format.func = func;
232 } else
233 return SIGILL;
234 break;
235 case mm_32f_70_op:
236 func = -1; /* Invalid */
237 if (insn.mm_fp0_format.op == mm_fmovn_op)
238 func = fmovn_op;
239 else if (insn.mm_fp0_format.op == mm_fmovz_op)
240 func = fmovz_op;
241 if (func != -1) {
242 mips32_insn.fp0_format.opcode = cop1_op;
243 mips32_insn.fp0_format.fmt =
244 sdps_format[insn.mm_fp0_format.fmt];
245 mips32_insn.fp0_format.ft =
246 insn.mm_fp0_format.ft;
247 mips32_insn.fp0_format.fs =
248 insn.mm_fp0_format.fs;
249 mips32_insn.fp0_format.fd =
250 insn.mm_fp0_format.fd;
251 mips32_insn.fp0_format.func = func;
252 } else
253 return SIGILL;
254 break;
255 case mm_32f_73_op: /* POOL32FXF */
256 switch (insn.mm_fp1_format.op) {
257 case mm_movf0_op:
258 case mm_movf1_op:
259 case mm_movt0_op:
260 case mm_movt1_op:
261 if ((insn.mm_fp1_format.op & 0x7f) ==
262 mm_movf0_op)
263 op = 0;
264 else
265 op = 1;
266 mips32_insn.r_format.opcode = spec_op;
267 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
268 mips32_insn.r_format.rt =
269 (insn.mm_fp4_format.cc << 2) + op;
270 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
271 mips32_insn.r_format.re = 0;
272 mips32_insn.r_format.func = movc_op;
273 break;
274 case mm_fcvtd0_op:
275 case mm_fcvtd1_op:
276 case mm_fcvts0_op:
277 case mm_fcvts1_op:
278 if ((insn.mm_fp1_format.op & 0x7f) ==
279 mm_fcvtd0_op) {
280 func = fcvtd_op;
281 fmt = swl_format[insn.mm_fp3_format.fmt];
282 } else {
283 func = fcvts_op;
284 fmt = dwl_format[insn.mm_fp3_format.fmt];
285 }
286 mips32_insn.fp0_format.opcode = cop1_op;
287 mips32_insn.fp0_format.fmt = fmt;
288 mips32_insn.fp0_format.ft = 0;
289 mips32_insn.fp0_format.fs =
290 insn.mm_fp3_format.fs;
291 mips32_insn.fp0_format.fd =
292 insn.mm_fp3_format.rt;
293 mips32_insn.fp0_format.func = func;
294 break;
295 case mm_fmov0_op:
296 case mm_fmov1_op:
297 case mm_fabs0_op:
298 case mm_fabs1_op:
299 case mm_fneg0_op:
300 case mm_fneg1_op:
301 if ((insn.mm_fp1_format.op & 0x7f) ==
302 mm_fmov0_op)
303 func = fmov_op;
304 else if ((insn.mm_fp1_format.op & 0x7f) ==
305 mm_fabs0_op)
306 func = fabs_op;
307 else
308 func = fneg_op;
309 mips32_insn.fp0_format.opcode = cop1_op;
310 mips32_insn.fp0_format.fmt =
311 sdps_format[insn.mm_fp3_format.fmt];
312 mips32_insn.fp0_format.ft = 0;
313 mips32_insn.fp0_format.fs =
314 insn.mm_fp3_format.fs;
315 mips32_insn.fp0_format.fd =
316 insn.mm_fp3_format.rt;
317 mips32_insn.fp0_format.func = func;
318 break;
319 case mm_ffloorl_op:
320 case mm_ffloorw_op:
321 case mm_fceill_op:
322 case mm_fceilw_op:
323 case mm_ftruncl_op:
324 case mm_ftruncw_op:
325 case mm_froundl_op:
326 case mm_froundw_op:
327 case mm_fcvtl_op:
328 case mm_fcvtw_op:
329 if (insn.mm_fp1_format.op == mm_ffloorl_op)
330 func = ffloorl_op;
331 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
332 func = ffloor_op;
333 else if (insn.mm_fp1_format.op == mm_fceill_op)
334 func = fceill_op;
335 else if (insn.mm_fp1_format.op == mm_fceilw_op)
336 func = fceil_op;
337 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
338 func = ftruncl_op;
339 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
340 func = ftrunc_op;
341 else if (insn.mm_fp1_format.op == mm_froundl_op)
342 func = froundl_op;
343 else if (insn.mm_fp1_format.op == mm_froundw_op)
344 func = fround_op;
345 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
346 func = fcvtl_op;
347 else
348 func = fcvtw_op;
349 mips32_insn.fp0_format.opcode = cop1_op;
350 mips32_insn.fp0_format.fmt =
351 sd_format[insn.mm_fp1_format.fmt];
352 mips32_insn.fp0_format.ft = 0;
353 mips32_insn.fp0_format.fs =
354 insn.mm_fp1_format.fs;
355 mips32_insn.fp0_format.fd =
356 insn.mm_fp1_format.rt;
357 mips32_insn.fp0_format.func = func;
358 break;
359 case mm_frsqrt_op:
360 case mm_fsqrt_op:
361 case mm_frecip_op:
362 if (insn.mm_fp1_format.op == mm_frsqrt_op)
363 func = frsqrt_op;
364 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
365 func = fsqrt_op;
366 else
367 func = frecip_op;
368 mips32_insn.fp0_format.opcode = cop1_op;
369 mips32_insn.fp0_format.fmt =
370 sdps_format[insn.mm_fp1_format.fmt];
371 mips32_insn.fp0_format.ft = 0;
372 mips32_insn.fp0_format.fs =
373 insn.mm_fp1_format.fs;
374 mips32_insn.fp0_format.fd =
375 insn.mm_fp1_format.rt;
376 mips32_insn.fp0_format.func = func;
377 break;
378 case mm_mfc1_op:
379 case mm_mtc1_op:
380 case mm_cfc1_op:
381 case mm_ctc1_op:
9355e59c
SH		 382 case mm_mfhc1_op:
383 case mm_mthc1_op:
102cedc3
LY		 384 if (insn.mm_fp1_format.op == mm_mfc1_op)
385 op = mfc_op;
386 else if (insn.mm_fp1_format.op == mm_mtc1_op)
387 op = mtc_op;
388 else if (insn.mm_fp1_format.op == mm_cfc1_op)
389 op = cfc_op;
9355e59c 390 else if (insn.mm_fp1_format.op == mm_ctc1_op)
102cedc3 391 op = ctc_op;
9355e59c
SH		 392 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
393 op = mfhc_op;
394 else
395 op = mthc_op;
102cedc3
LY		 396 mips32_insn.fp1_format.opcode = cop1_op;
397 mips32_insn.fp1_format.op = op;
398 mips32_insn.fp1_format.rt =
399 insn.mm_fp1_format.rt;
400 mips32_insn.fp1_format.fs =
401 insn.mm_fp1_format.fs;
402 mips32_insn.fp1_format.fd = 0;
403 mips32_insn.fp1_format.func = 0;
404 break;
405 default:
406 return SIGILL;
102cedc3
LY		 407 }
408 break;
409 case mm_32f_74_op: /* c.cond.fmt */
410 mips32_insn.fp0_format.opcode = cop1_op;
411 mips32_insn.fp0_format.fmt =
412 sdps_format[insn.mm_fp4_format.fmt];
413 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
414 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
415 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
416 mips32_insn.fp0_format.func =
417 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
418 break;
419 default:
420 return SIGILL;
102cedc3
LY		 421 }
422 break;
423 default:
424 return SIGILL;
102cedc3
LY		 425 }
426
427 *insn_ptr = mips32_insn;
428 return 0;
429}
430
1da177e4
LT		 431/*
432 * Redundant with logic already in kernel/branch.c,
433 * embedded in compute_return_epc. At some point,
434 * a single subroutine should be used across both
435 * modules.
436 */
102cedc3
LY		 437static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
438 unsigned long *contpc)
1da177e4 439{
102cedc3
LY		 440 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
441 unsigned int fcr31;
442 unsigned int bit = 0;
443
444 switch (insn.i_format.opcode) {
1da177e4 445 case spec_op:
102cedc3 446 switch (insn.r_format.func) {
1da177e4 447 case jalr_op:
102cedc3
LY		 448 regs->regs[insn.r_format.rd] =
449 regs->cp0_epc + dec_insn.pc_inc +
450 dec_insn.next_pc_inc;
451 /* Fall through */
1da177e4 452 case jr_op:
5f9f41c4 453 /* For R6, JR already emulated in jalr_op */
143fefc8 454 if (NO_R6EMU && insn.r_format.func == jr_op)
5f9f41c4 455 break;
102cedc3 456 *contpc = regs->regs[insn.r_format.rs];
1da177e4
LT		 457 return 1;
458 }
459 break;
1da177e4 460 case bcond_op:
102cedc3
LY		 461 switch (insn.i_format.rt) {
462 case bltzal_op:
463 case bltzall_op:
319824ea
MC		 464 if (NO_R6EMU && (insn.i_format.rs ||
465 insn.i_format.rt == bltzall_op))
466 break;
467
102cedc3
LY		 468 regs->regs[31] = regs->cp0_epc +
469 dec_insn.pc_inc +
470 dec_insn.next_pc_inc;
471 /* Fall through */
1da177e4 472 case bltzl_op:
319824ea
MC		 473 if (NO_R6EMU)
474 break;
475 case bltz_op:
102cedc3
LY		 476 if ((long)regs->regs[insn.i_format.rs] < 0)
477 *contpc = regs->cp0_epc +
478 dec_insn.pc_inc +
479 (insn.i_format.simmediate << 2);
480 else
481 *contpc = regs->cp0_epc +
482 dec_insn.pc_inc +
483 dec_insn.next_pc_inc;
484 return 1;
1da177e4 485 case bgezal_op:
1da177e4 486 case bgezall_op:
319824ea
MC		 487 if (NO_R6EMU && (insn.i_format.rs ||
488 insn.i_format.rt == bgezall_op))
489 break;
490
102cedc3
LY		 491 regs->regs[31] = regs->cp0_epc +
492 dec_insn.pc_inc +
493 dec_insn.next_pc_inc;
494 /* Fall through */
102cedc3 495 case bgezl_op:
319824ea
MC		 496 if (NO_R6EMU)
497 break;
498 case bgez_op:
102cedc3
LY		 499 if ((long)regs->regs[insn.i_format.rs] >= 0)
500 *contpc = regs->cp0_epc +
501 dec_insn.pc_inc +
502 (insn.i_format.simmediate << 2);
503 else
504 *contpc = regs->cp0_epc +
505 dec_insn.pc_inc +
506 dec_insn.next_pc_inc;
1da177e4
LT		 507 return 1;
508 }
509 break;
1da177e4 510 case jalx_op:
102cedc3
LY		 511 set_isa16_mode(bit);
512 case jal_op:
513 regs->regs[31] = regs->cp0_epc +
514 dec_insn.pc_inc +
515 dec_insn.next_pc_inc;
516 /* Fall through */
517 case j_op:
518 *contpc = regs->cp0_epc + dec_insn.pc_inc;
519 *contpc >>= 28;
520 *contpc <<= 28;
521 *contpc |= (insn.j_format.target << 2);
522 /* Set microMIPS mode bit: XOR for jalx. */
523 *contpc ^= bit;
524 return 1;
1da177e4 525 case beql_op:
319824ea
MC		 526 if (NO_R6EMU)
527 break;
528 case beq_op:
102cedc3
LY		 529 if (regs->regs[insn.i_format.rs] ==
530 regs->regs[insn.i_format.rt])
531 *contpc = regs->cp0_epc +
532 dec_insn.pc_inc +
533 (insn.i_format.simmediate << 2);
534 else
535 *contpc = regs->cp0_epc +
536 dec_insn.pc_inc +
537 dec_insn.next_pc_inc;
538 return 1;
1da177e4 539 case bnel_op:
319824ea
MC		 540 if (NO_R6EMU)
541 break;
542 case bne_op:
102cedc3
LY		 543 if (regs->regs[insn.i_format.rs] !=
544 regs->regs[insn.i_format.rt])
545 *contpc = regs->cp0_epc +
546 dec_insn.pc_inc +
547 (insn.i_format.simmediate << 2);
548 else
549 *contpc = regs->cp0_epc +
550 dec_insn.pc_inc +
551 dec_insn.next_pc_inc;
552 return 1;
1da177e4 553 case blezl_op:
e9d92d22 554 if (!insn.i_format.rt && NO_R6EMU)
319824ea
MC		 555 break;
556 case blez_op:
a8ff66f5
MC		 557
558 /*
559 * Compact branches for R6 for the
560 * blez and blezl opcodes.
561 * BLEZ | rs = 0 | rt != 0 == BLEZALC
562 * BLEZ | rs = rt != 0 == BGEZALC
563 * BLEZ | rs != 0 | rt != 0 == BGEUC
564 * BLEZL | rs = 0 | rt != 0 == BLEZC
565 * BLEZL | rs = rt != 0 == BGEZC
566 * BLEZL | rs != 0 | rt != 0 == BGEC
567 *
568 * For real BLEZ{,L}, rt is always 0.
569 */
570 if (cpu_has_mips_r6 && insn.i_format.rt) {
571 if ((insn.i_format.opcode == blez_op) &&
572 ((!insn.i_format.rs && insn.i_format.rt) ||
573 (insn.i_format.rs == insn.i_format.rt)))
574 regs->regs[31] = regs->cp0_epc +
575 dec_insn.pc_inc;
576 *contpc = regs->cp0_epc + dec_insn.pc_inc +
577 dec_insn.next_pc_inc;
578
579 return 1;
580 }
102cedc3
LY		 581 if ((long)regs->regs[insn.i_format.rs] <= 0)
582 *contpc = regs->cp0_epc +
583 dec_insn.pc_inc +
584 (insn.i_format.simmediate << 2);
585 else
586 *contpc = regs->cp0_epc +
587 dec_insn.pc_inc +
588 dec_insn.next_pc_inc;
589 return 1;
1da177e4 590 case bgtzl_op:
e9d92d22 591 if (!insn.i_format.rt && NO_R6EMU)
319824ea
MC		 592 break;
593 case bgtz_op:
f1b44067
MC		 594 /*
595 * Compact branches for R6 for the
596 * bgtz and bgtzl opcodes.
597 * BGTZ | rs = 0 | rt != 0 == BGTZALC
598 * BGTZ | rs = rt != 0 == BLTZALC
599 * BGTZ | rs != 0 | rt != 0 == BLTUC
600 * BGTZL | rs = 0 | rt != 0 == BGTZC
601 * BGTZL | rs = rt != 0 == BLTZC
602 * BGTZL | rs != 0 | rt != 0 == BLTC
603 *
604 * *ZALC varint for BGTZ &&& rt != 0
605 * For real GTZ{,L}, rt is always 0.
606 */
607 if (cpu_has_mips_r6 && insn.i_format.rt) {
608 if ((insn.i_format.opcode == blez_op) &&
609 ((!insn.i_format.rs && insn.i_format.rt) ||
610 (insn.i_format.rs == insn.i_format.rt)))
611 regs->regs[31] = regs->cp0_epc +
612 dec_insn.pc_inc;
613 *contpc = regs->cp0_epc + dec_insn.pc_inc +
614 dec_insn.next_pc_inc;
615
616 return 1;
617 }
618
102cedc3
LY		 619 if ((long)regs->regs[insn.i_format.rs] > 0)
620 *contpc = regs->cp0_epc +
621 dec_insn.pc_inc +
622 (insn.i_format.simmediate << 2);
623 else
624 *contpc = regs->cp0_epc +
625 dec_insn.pc_inc +
626 dec_insn.next_pc_inc;
1da177e4 627 return 1;
c893ce38 628 case cbcond0_op:
10d962d5 629 case cbcond1_op:
c893ce38
MC		 630 if (!cpu_has_mips_r6)
631 break;
632 if (insn.i_format.rt && !insn.i_format.rs)
633 regs->regs[31] = regs->cp0_epc + 4;
634 *contpc = regs->cp0_epc + dec_insn.pc_inc +
635 dec_insn.next_pc_inc;
636
637 return 1;
c26d4219
DD		 638#ifdef CONFIG_CPU_CAVIUM_OCTEON
639 case lwc2_op: /* This is bbit0 on Octeon */
640 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
641 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
642 else
643 *contpc = regs->cp0_epc + 8;
644 return 1;
645 case ldc2_op: /* This is bbit032 on Octeon */
646 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
647 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
648 else
649 *contpc = regs->cp0_epc + 8;
650 return 1;
651 case swc2_op: /* This is bbit1 on Octeon */
652 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
653 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
654 else
655 *contpc = regs->cp0_epc + 8;
656 return 1;
657 case sdc2_op: /* This is bbit132 on Octeon */
658 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
659 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
660 else
661 *contpc = regs->cp0_epc + 8;
662 return 1;
8467ca01
MC		 663#else
664 case bc6_op:
665 /*
666 * Only valid for MIPS R6 but we can still end up
667 * here from a broken userland so just tell emulator
668 * this is not a branch and let it break later on.
669 */
670 if (!cpu_has_mips_r6)
671 break;
672 *contpc = regs->cp0_epc + dec_insn.pc_inc +
673 dec_insn.next_pc_inc;
674
84fef630
MC		 675 return 1;
676 case balc6_op:
677 if (!cpu_has_mips_r6)
678 break;
679 regs->regs[31] = regs->cp0_epc + 4;
680 *contpc = regs->cp0_epc + dec_insn.pc_inc +
681 dec_insn.next_pc_inc;
682
69b9a2fd
MC		 683 return 1;
684 case beqzcjic_op:
685 if (!cpu_has_mips_r6)
686 break;
687 *contpc = regs->cp0_epc + dec_insn.pc_inc +
688 dec_insn.next_pc_inc;
689
28d6f93d
MC		 690 return 1;
691 case bnezcjialc_op:
692 if (!cpu_has_mips_r6)
693 break;
694 if (!insn.i_format.rs)
695 regs->regs[31] = regs->cp0_epc + 4;
696 *contpc = regs->cp0_epc + dec_insn.pc_inc +
697 dec_insn.next_pc_inc;
698
8467ca01 699 return 1;
c26d4219 700#endif
1da177e4
LT		 701 case cop0_op:
702 case cop1_op:
c8a34581
MC		 703 /* Need to check for R6 bc1nez and bc1eqz branches */
704 if (cpu_has_mips_r6 &&
705 ((insn.i_format.rs == bc1eqz_op) ||
706 (insn.i_format.rs == bc1nez_op))) {
707 bit = 0;
708 switch (insn.i_format.rs) {
709 case bc1eqz_op:
710 if (get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)
711 bit = 1;
712 break;
713 case bc1nez_op:
714 if (!(get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1))
715 bit = 1;
716 break;
717 }
718 if (bit)
719 *contpc = regs->cp0_epc +
720 dec_insn.pc_inc +
721 (insn.i_format.simmediate << 2);
722 else
723 *contpc = regs->cp0_epc +
724 dec_insn.pc_inc +
725 dec_insn.next_pc_inc;
726
727 return 1;
728 }
729 /* R2/R6 compatible cop1 instruction. Fall through */
1da177e4
LT		 730 case cop2_op:
731 case cop1x_op:
102cedc3
LY		 732 if (insn.i_format.rs == bc_op) {
733 preempt_disable();
734 if (is_fpu_owner())
842dfc11 735 fcr31 = read_32bit_cp1_register(CP1_STATUS);
102cedc3
LY		 736 else
737 fcr31 = current->thread.fpu.fcr31;
738 preempt_enable();
739
740 bit = (insn.i_format.rt >> 2);
741 bit += (bit != 0);
742 bit += 23;
743 switch (insn.i_format.rt & 3) {
744 case 0: /* bc1f */
745 case 2: /* bc1fl */
746 if (~fcr31 & (1 << bit))
747 *contpc = regs->cp0_epc +
748 dec_insn.pc_inc +
749 (insn.i_format.simmediate << 2);
750 else
751 *contpc = regs->cp0_epc +
752 dec_insn.pc_inc +
753 dec_insn.next_pc_inc;
754 return 1;
102cedc3
LY		 755 case 1: /* bc1t */
756 case 3: /* bc1tl */
757 if (fcr31 & (1 << bit))
758 *contpc = regs->cp0_epc +
759 dec_insn.pc_inc +
760 (insn.i_format.simmediate << 2);
761 else
762 *contpc = regs->cp0_epc +
763 dec_insn.pc_inc +
764 dec_insn.next_pc_inc;
765 return 1;
102cedc3
LY		 766 }
767 }
1da177e4
LT		 768 break;
769 }
1da177e4
LT		 770 return 0;
771}
772
773/*
774 * In the Linux kernel, we support selection of FPR format on the
70342287 775 * basis of the Status.FR bit. If an FPU is not present, the FR bit
da0bac33 776 * is hardwired to zero, which would imply a 32-bit FPU even for
597ce172 777 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
51d943f0
RB		 778 * FPU emu is slow and bulky and optimizing this function offers fairly
779 * sizeable benefits so we try to be clever and make this function return
780 * a constant whenever possible, that is on 64-bit kernels without O32
597ce172 781 * compatibility enabled and on 32-bit without 64-bit FPU support.
1da177e4 782 */
da0bac33
DD		 783static inline int cop1_64bit(struct pt_regs *xcp)
784{
08a07904
RB		 785 if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
786 return 1;
787 else if (config_enabled(CONFIG_32BIT) &&
788 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
789 return 0;
790
597ce172 791 return !test_thread_flag(TIF_32BIT_FPREGS);
da0bac33
DD		 792}
793
4227a2d4
PB		 794static inline bool hybrid_fprs(void)
795{
796 return test_thread_flag(TIF_HYBRID_FPREGS);
797}
798
47fa0c02
RB		 799#define SIFROMREG(si, x) \
800do { \
4227a2d4 801 if (cop1_64bit(xcp) && !hybrid_fprs()) \
c8c0da6b 802 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \
bbd426f5 803 else \
c8c0da6b 804 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
bbd426f5 805} while (0)
1da177e4 806
47fa0c02
RB		 807#define SITOREG(si, x) \
808do { \
4227a2d4 809 if (cop1_64bit(xcp) && !hybrid_fprs()) { \
ef1c47af 810 unsigned i; \
bbd426f5 811 set_fpr32(&ctx->fpr[x], 0, si); \
ef1c47af
PB		 812 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
813 set_fpr32(&ctx->fpr[x], i, 0); \
814 } else { \
bbd426f5 815 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
ef1c47af 816 } \
bbd426f5 817} while (0)
1da177e4 818
c8c0da6b 819#define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
ef1c47af 820
47fa0c02
RB		 821#define SITOHREG(si, x) \
822do { \
ef1c47af
PB		 823 unsigned i; \
824 set_fpr32(&ctx->fpr[x], 1, si); \
825 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
826 set_fpr32(&ctx->fpr[x], i, 0); \
827} while (0)
1ac94400 828
47fa0c02 829#define DIFROMREG(di, x) \
bbd426f5
PB		 830 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
831
47fa0c02
RB		 832#define DITOREG(di, x) \
833do { \
ef1c47af
PB		 834 unsigned fpr, i; \
835 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
836 set_fpr64(&ctx->fpr[fpr], 0, di); \
837 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
838 set_fpr64(&ctx->fpr[fpr], i, 0); \
839} while (0)
1da177e4 840
21a151d8
RB		 841#define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
842#define SPTOREG(sp, x) SITOREG((sp).bits, x)
843#define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
844#define DPTOREG(dp, x) DITOREG((dp).bits, x)
1da177e4 845
d4f5b088
MR		 846/*
847 * Emulate a CFC1 instruction.
848 */
849static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
850 mips_instruction ir)
851{
c491cfa2
MR		 852 u32 fcr31 = ctx->fcr31;
853 u32 value = 0;
d4f5b088 854
c491cfa2
MR		 855 switch (MIPSInst_RD(ir)) {
856 case FPCREG_CSR:
857 value = fcr31;
d4f5b088 858 pr_debug("%p gpr[%d]<-csr=%08x\n",
c491cfa2
MR		 859 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
860 break;
861
862 case FPCREG_FENR:
863 if (!cpu_has_mips_r)
864 break;
865 value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
866 MIPS_FENR_FS;
867 value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM);
868 pr_debug("%p gpr[%d]<-enr=%08x\n",
869 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
870 break;
871
872 case FPCREG_FEXR:
873 if (!cpu_has_mips_r)
874 break;
875 value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
876 pr_debug("%p gpr[%d]<-exr=%08x\n",
877 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
878 break;
879
880 case FPCREG_FCCR:
881 if (!cpu_has_mips_r)
882 break;
883 value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
884 MIPS_FCCR_COND0;
885 value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
886 (MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0);
887 pr_debug("%p gpr[%d]<-ccr=%08x\n",
888 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
889 break;
890
891 case FPCREG_RID:
03dce595 892 value = boot_cpu_data.fpu_id;
c491cfa2
MR		 893 break;
894
895 default:
896 break;
897 }
898
d4f5b088
MR		 899 if (MIPSInst_RT(ir))
900 xcp->regs[MIPSInst_RT(ir)] = value;
901}
902
903/*
904 * Emulate a CTC1 instruction.
905 */
906static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
907 mips_instruction ir)
908{
c491cfa2 909 u32 fcr31 = ctx->fcr31;
d4f5b088 910 u32 value;
9b26616c 911 u32 mask;
d4f5b088
MR		 912
913 if (MIPSInst_RT(ir) == 0)
914 value = 0;
915 else
916 value = xcp->regs[MIPSInst_RT(ir)];
917
c491cfa2
MR		 918 switch (MIPSInst_RD(ir)) {
919 case FPCREG_CSR:
d4f5b088 920 pr_debug("%p gpr[%d]->csr=%08x\n",
c491cfa2 921 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
d4f5b088 922
9b26616c 923 /* Preserve read-only bits. */
03dce595 924 mask = boot_cpu_data.fpu_msk31;
9b26616c 925 fcr31 = (value & ~mask) | (fcr31 & mask);
c491cfa2
MR		 926 break;
927
928 case FPCREG_FENR:
929 if (!cpu_has_mips_r)
930 break;
931 pr_debug("%p gpr[%d]->enr=%08x\n",
932 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
933 fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM);
934 fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
935 FPU_CSR_FS;
936 fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM);
937 break;
938
939 case FPCREG_FEXR:
940 if (!cpu_has_mips_r)
941 break;
942 pr_debug("%p gpr[%d]->exr=%08x\n",
943 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
944 fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S);
945 fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
946 break;
947
948 case FPCREG_FCCR:
949 if (!cpu_has_mips_r)
950 break;
951 pr_debug("%p gpr[%d]->ccr=%08x\n",
952 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
953 fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND);
954 fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
955 FPU_CSR_COND;
956 fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
957 FPU_CSR_CONDX;
958 break;
959
960 default:
961 break;
d4f5b088 962 }
c491cfa2
MR		 963
964 ctx->fcr31 = fcr31;
d4f5b088
MR		 965}
966
1da177e4
LT		 967/*
968 * Emulate the single floating point instruction pointed at by EPC.
969 * Two instructions if the instruction is in a branch delay slot.
970 */
971
515b029d 972static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
102cedc3 973 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
1da177e4 974{
102cedc3 975 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
3f7cac41
RB		 976 unsigned int cond, cbit;
977 mips_instruction ir;
978 int likely, pc_inc;
979 u32 __user *wva;
980 u64 __user *dva;
3f7cac41
RB		 981 u32 wval;
982 u64 dval;
983 int sig;
1da177e4 984
70e4c234
RB		 985 /*
986 * These are giving gcc a gentle hint about what to expect in
987 * dec_inst in order to do better optimization.
988 */
989 if (!cpu_has_mmips && dec_insn.micro_mips_mode)
990 unreachable();
991
1da177e4 992 /* XXX NEC Vr54xx bug workaround */
e7e9cae5 993 if (delay_slot(xcp)) {
102cedc3
LY		 994 if (dec_insn.micro_mips_mode) {
995 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
e7e9cae5 996 clear_delay_slot(xcp);
102cedc3
LY		 997 } else {
998 if (!isBranchInstr(xcp, dec_insn, &contpc))
e7e9cae5 999 clear_delay_slot(xcp);
102cedc3
LY		 1000 }
1001 }
1da177e4 1002
e7e9cae5 1003 if (delay_slot(xcp)) {
1da177e4
LT		 1004 /*
1005 * The instruction to be emulated is in a branch delay slot
70342287 1006 * which means that we have to emulate the branch instruction
1da177e4
LT		 1007 * BEFORE we do the cop1 instruction.
1008 *
1009 * This branch could be a COP1 branch, but in that case we
1010 * would have had a trap for that instruction, and would not
1011 * come through this route.
1012 *
1013 * Linux MIPS branch emulator operates on context, updating the
1014 * cp0_epc.
1015 */
102cedc3
LY		 1016 ir = dec_insn.next_insn; /* process delay slot instr */
1017 pc_inc = dec_insn.next_pc_inc;
1018 } else {
1019 ir = dec_insn.insn; /* process current instr */
1020 pc_inc = dec_insn.pc_inc;
1021 }
1da177e4 1022
102cedc3
LY		 1023 /*
1024 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
1025 * instructions, we want to convert microMIPS FPU instructions
1026 * into MIPS32 instructions so that we could reuse all of the
1027 * FPU emulation code.
1028 *
1029 * NOTE: We cannot do this for branch instructions since they
1030 * are not a subset. Example: Cannot emulate a 16-bit
1031 * aligned target address with a MIPS32 instruction.
1032 */
1033 if (dec_insn.micro_mips_mode) {
1034 /*
1035 * If next instruction is a 16-bit instruction, then it
1036 * it cannot be a FPU instruction. This could happen
1037 * since we can be called for non-FPU instructions.
1038 */
1039 if ((pc_inc == 2) ||
1040 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
1041 == SIGILL))
1da177e4 1042 return SIGILL;
1da177e4
LT		 1043 }
1044
3f7cac41 1045emul:
a8b0ca17 1046 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
b6ee75ed 1047 MIPS_FPU_EMU_INC_STATS(emulated);
1da177e4 1048 switch (MIPSInst_OPCODE(ir)) {
3f7cac41
RB		 1049 case ldc1_op:
1050 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1051 MIPSInst_SIMM(ir));
b6ee75ed 1052 MIPS_FPU_EMU_INC_STATS(loads);
515b029d 1053
3f7cac41 1054 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
b6ee75ed 1055 MIPS_FPU_EMU_INC_STATS(errors);
3f7cac41 1056 *fault_addr = dva;
1da177e4
LT		 1057 return SIGBUS;
1058 }
3f7cac41 1059 if (__get_user(dval, dva)) {
515b029d 1060 MIPS_FPU_EMU_INC_STATS(errors);
3f7cac41 1061 *fault_addr = dva;
515b029d
DD		 1062 return SIGSEGV;
1063 }
3f7cac41 1064 DITOREG(dval, MIPSInst_RT(ir));
1da177e4 1065 break;
1da177e4 1066
3f7cac41
RB		 1067 case sdc1_op:
1068 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1069 MIPSInst_SIMM(ir));
b6ee75ed 1070 MIPS_FPU_EMU_INC_STATS(stores);
3f7cac41
RB		 1071 DIFROMREG(dval, MIPSInst_RT(ir));
1072 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
b6ee75ed 1073 MIPS_FPU_EMU_INC_STATS(errors);
3f7cac41 1074 *fault_addr = dva;
1da177e4
LT		 1075 return SIGBUS;
1076 }
3f7cac41 1077 if (__put_user(dval, dva)) {
515b029d 1078 MIPS_FPU_EMU_INC_STATS(errors);
3f7cac41 1079 *fault_addr = dva;
515b029d
DD		 1080 return SIGSEGV;
1081 }
1da177e4 1082 break;
1da177e4 1083
3f7cac41
RB		 1084 case lwc1_op:
1085 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1086 MIPSInst_SIMM(ir));
b6ee75ed 1087 MIPS_FPU_EMU_INC_STATS(loads);
3f7cac41 1088 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
b6ee75ed 1089 MIPS_FPU_EMU_INC_STATS(errors);
3f7cac41 1090 *fault_addr = wva;
1da177e4
LT		 1091 return SIGBUS;
1092 }
3f7cac41 1093 if (__get_user(wval, wva)) {
515b029d 1094 MIPS_FPU_EMU_INC_STATS(errors);
3f7cac41 1095 *fault_addr = wva;
515b029d
DD		 1096 return SIGSEGV;
1097 }
3f7cac41 1098 SITOREG(wval, MIPSInst_RT(ir));
1da177e4 1099 break;
1da177e4 1100
3f7cac41
RB		 1101 case swc1_op:
1102 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1103 MIPSInst_SIMM(ir));
b6ee75ed 1104 MIPS_FPU_EMU_INC_STATS(stores);
3f7cac41
RB		 1105 SIFROMREG(wval, MIPSInst_RT(ir));
1106 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
b6ee75ed 1107 MIPS_FPU_EMU_INC_STATS(errors);
3f7cac41 1108 *fault_addr = wva;
1da177e4
LT		 1109 return SIGBUS;
1110 }
3f7cac41 1111 if (__put_user(wval, wva)) {
515b029d 1112 MIPS_FPU_EMU_INC_STATS(errors);
3f7cac41 1113 *fault_addr = wva;
515b029d
DD		 1114 return SIGSEGV;
1115 }
1da177e4 1116 break;
1da177e4
LT		 1117
1118 case cop1_op:
1119 switch (MIPSInst_RS(ir)) {
1da177e4 1120 case dmfc_op:
08a07904
RB		 1121 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1122 return SIGILL;
1123
1da177e4
LT		 1124 /* copregister fs -> gpr[rt] */
1125 if (MIPSInst_RT(ir) != 0) {
1126 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1127 MIPSInst_RD(ir));
1128 }
1129 break;
1130
1131 case dmtc_op:
08a07904
RB		 1132 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1133 return SIGILL;
1134
1da177e4
LT		 1135 /* copregister fs <- rt */
1136 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1137 break;
1da177e4 1138
1ac94400 1139 case mfhc_op:
e8f80cc1 1140 if (!cpu_has_mips_r2_r6)
1ac94400
LY		 1141 goto sigill;
1142
1143 /* copregister rd -> gpr[rt] */
1144 if (MIPSInst_RT(ir) != 0) {
1145 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1146 MIPSInst_RD(ir));
1147 }
1148 break;
1149
1150 case mthc_op:
e8f80cc1 1151 if (!cpu_has_mips_r2_r6)
1ac94400
LY		 1152 goto sigill;
1153
1154 /* copregister rd <- gpr[rt] */
1155 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1156 break;
1157
1da177e4
LT		 1158 case mfc_op:
1159 /* copregister rd -> gpr[rt] */
1da177e4
LT		 1160 if (MIPSInst_RT(ir) != 0) {
1161 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1162 MIPSInst_RD(ir));
1163 }
1164 break;
1165
1166 case mtc_op:
1167 /* copregister rd <- rt */
1da177e4
LT		 1168 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1169 break;
1170
3f7cac41 1171 case cfc_op:
1da177e4 1172 /* cop control register rd -> gpr[rt] */
d4f5b088 1173 cop1_cfc(xcp, ctx, ir);
1da177e4 1174 break;
1da177e4 1175
3f7cac41 1176 case ctc_op:
1da177e4 1177 /* copregister rd <- rt */
d4f5b088 1178 cop1_ctc(xcp, ctx, ir);
1da177e4
LT		 1179 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1180 return SIGFPE;
1181 }
1182 break;
1da177e4 1183
c909ca71
MC		 1184 case bc1eqz_op:
1185 case bc1nez_op:
1186 if (!cpu_has_mips_r6 || delay_slot(xcp))
1187 return SIGILL;
1188
1189 cond = likely = 0;
1190 switch (MIPSInst_RS(ir)) {
1191 case bc1eqz_op:
1192 if (get_fpr32(&current->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1)
1193 cond = 1;
1194 break;
1195 case bc1nez_op:
1196 if (!(get_fpr32(&current->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1))
1197 cond = 1;
1198 break;
1199 }
1200 goto branch_common;
1201
3f7cac41 1202 case bc_op:
e7e9cae5 1203 if (delay_slot(xcp))
1da177e4
LT		 1204 return SIGILL;
1205
08a07904
RB		 1206 if (cpu_has_mips_4_5_r)
1207 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1208 else
1209 cbit = FPU_CSR_COND;
1210 cond = ctx->fcr31 & cbit;
1211
3f7cac41 1212 likely = 0;
1da177e4
LT		 1213 switch (MIPSInst_RT(ir) & 3) {
1214 case bcfl_op:
2d83fea7
MR		 1215 if (cpu_has_mips_2_3_4_5_r)
1216 likely = 1;
1217 /* Fall through */
1da177e4
LT		 1218 case bcf_op:
1219 cond = !cond;
1220 break;
1221 case bctl_op:
2d83fea7
MR		 1222 if (cpu_has_mips_2_3_4_5_r)
1223 likely = 1;
1224 /* Fall through */
1da177e4
LT		 1225 case bct_op:
1226 break;
1da177e4 1227 }
c909ca71 1228branch_common:
e7e9cae5 1229 set_delay_slot(xcp);
1da177e4 1230 if (cond) {
3f7cac41
RB		 1231 /*
1232 * Branch taken: emulate dslot instruction
1da177e4 1233 */
9ab4471c
MR		 1234 unsigned long bcpc;
1235
1236 /*
1237 * Remember EPC at the branch to point back
1238 * at so that any delay-slot instruction
1239 * signal is not silently ignored.
1240 */
1241 bcpc = xcp->cp0_epc;
102cedc3
LY		 1242 xcp->cp0_epc += dec_insn.pc_inc;
1243
1244 contpc = MIPSInst_SIMM(ir);
1245 ir = dec_insn.next_insn;
1246 if (dec_insn.micro_mips_mode) {
1247 contpc = (xcp->cp0_epc + (contpc << 1));
1248
1249 /* If 16-bit instruction, not FPU. */
1250 if ((dec_insn.next_pc_inc == 2) ||
1251 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1252
1253 /*
1254 * Since this instruction will
1255 * be put on the stack with
1256 * 32-bit words, get around
1257 * this problem by putting a
1258 * NOP16 as the second one.
1259 */
1260 if (dec_insn.next_pc_inc == 2)
1261 ir = (ir & (~0xffff)) | MM_NOP16;
1262
1263 /*
1264 * Single step the non-CP1
1265 * instruction in the dslot.
1266 */
9ab4471c
MR		 1267 sig = mips_dsemul(xcp, ir,
1268 contpc);
1269 if (sig)
1270 xcp->cp0_epc = bcpc;
1271 /*
1272 * SIGILL forces out of
1273 * the emulation loop.
1274 */
1275 return sig ? sig : SIGILL;
102cedc3
LY		 1276 }
1277 } else
1278 contpc = (xcp->cp0_epc + (contpc << 2));
1da177e4
LT		 1279
1280 switch (MIPSInst_OPCODE(ir)) {
1281 case lwc1_op:
1282 case swc1_op:
08a07904 1283 goto emul;
3f7cac41 1284
1da177e4
LT		 1285 case ldc1_op:
1286 case sdc1_op:
2d83fea7 1287 if (cpu_has_mips_2_3_4_5_r)
08a07904
RB		 1288 goto emul;
1289
9ab4471c 1290 goto bc_sigill;
3f7cac41 1291
1da177e4 1292 case cop1_op:
1da177e4 1293 goto emul;
3f7cac41 1294
08a07904 1295 case cop1x_op:
2d83fea7 1296 if (cpu_has_mips_4_5_64_r2_r6)
08a07904
RB		 1297 /* its one of ours */
1298 goto emul;
1299
9ab4471c 1300 goto bc_sigill;
3f7cac41 1301
1da177e4 1302 case spec_op:
2d83fea7
MR		 1303 switch (MIPSInst_FUNC(ir)) {
1304 case movc_op:
1305 if (cpu_has_mips_4_5_r)
1306 goto emul;
08a07904 1307
9ab4471c 1308 goto bc_sigill;
2d83fea7 1309 }
1da177e4 1310 break;
9ab4471c
MR		 1311
1312 bc_sigill:
1313 xcp->cp0_epc = bcpc;
1314 return SIGILL;
1da177e4
LT		 1315 }
1316
1317 /*
1318 * Single step the non-cp1
1319 * instruction in the dslot
1320 */
9ab4471c
MR		 1321 sig = mips_dsemul(xcp, ir, contpc);
1322 if (sig)
1323 xcp->cp0_epc = bcpc;
1324 /* SIGILL forces out of the emulation loop. */
1325 return sig ? sig : SIGILL;
3f7cac41 1326 } else if (likely) { /* branch not taken */
5d77cf28
MR		 1327 /*
1328 * branch likely nullifies
1329 * dslot if not taken
1330 */
1331 xcp->cp0_epc += dec_insn.pc_inc;
1332 contpc += dec_insn.pc_inc;
1333 /*
1334 * else continue & execute
1335 * dslot as normal insn
1336 */
1337 }
1da177e4 1338 break;
1da177e4
LT		 1339
1340 default:
1341 if (!(MIPSInst_RS(ir) & 0x10))
1342 return SIGILL;
1da177e4 1343
3f7cac41
RB		 1344 /* a real fpu computation instruction */
1345 if ((sig = fpu_emu(xcp, ctx, ir)))
1346 return sig;
1da177e4
LT		 1347 }
1348 break;
1349
3f7cac41 1350 case cop1x_op:
2d83fea7 1351 if (!cpu_has_mips_4_5_64_r2_r6)
08a07904
RB		 1352 return SIGILL;
1353
1354 sig = fpux_emu(xcp, ctx, ir, fault_addr);
515b029d 1355 if (sig)
1da177e4
LT		 1356 return sig;
1357 break;
1da177e4 1358
1da177e4 1359 case spec_op:
08a07904
RB		 1360 if (!cpu_has_mips_4_5_r)
1361 return SIGILL;
1362
1da177e4
LT		 1363 if (MIPSInst_FUNC(ir) != movc_op)
1364 return SIGILL;
1365 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1366 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1367 xcp->regs[MIPSInst_RD(ir)] =
1368 xcp->regs[MIPSInst_RS(ir)];
1369 break;
1da177e4 1370 default:
1ac94400 1371sigill:
1da177e4
LT		 1372 return SIGILL;
1373 }
1374
1375 /* we did it !! */
e70dfc10 1376 xcp->cp0_epc = contpc;
e7e9cae5 1377 clear_delay_slot(xcp);
333d1f67 1378
1da177e4
LT		 1379 return 0;
1380}
1381
1382/*
1383 * Conversion table from MIPS compare ops 48-63
1384 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1385 */
1386static const unsigned char cmptab[8] = {
1387 0, /* cmp_0 (sig) cmp_sf */
1388 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1389 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1390 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1391 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1392 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1393 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1394 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1395};
1396
f8c3c671
MC		 1397static const unsigned char negative_cmptab[8] = {
1398 0, /* Reserved */
1399 IEEE754_CLT | IEEE754_CGT | IEEE754_CEQ,
1400 IEEE754_CLT | IEEE754_CGT | IEEE754_CUN,
1401 IEEE754_CLT | IEEE754_CGT,
1402 /* Reserved */
1403};
1404
1da177e4 1405
1da177e4
LT		 1406/*
1407 * Additional MIPS4 instructions
1408 */
1409
47fa0c02
RB		 1410#define DEF3OP(name, p, f1, f2, f3) \
1411static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1412 union ieee754##p s, union ieee754##p t) \
1413{ \
1414 struct _ieee754_csr ieee754_csr_save; \
1415 s = f1(s, t); \
1416 ieee754_csr_save = ieee754_csr; \
1417 s = f2(s, r); \
1418 ieee754_csr_save.cx |= ieee754_csr.cx; \
1419 ieee754_csr_save.sx |= ieee754_csr.sx; \
1420 s = f3(s); \
1421 ieee754_csr.cx |= ieee754_csr_save.cx; \
1422 ieee754_csr.sx |= ieee754_csr_save.sx; \
1423 return s; \
1da177e4
LT		 1424}
1425
2209bcb1 1426static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1da177e4
LT		 1427{
1428 return ieee754dp_div(ieee754dp_one(0), d);
1429}
1430
2209bcb1 1431static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1da177e4
LT		 1432{
1433 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1434}
1435
2209bcb1 1436static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1da177e4
LT		 1437{
1438 return ieee754sp_div(ieee754sp_one(0), s);
1439}
1440
2209bcb1 1441static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1da177e4
LT		 1442{
1443 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1444}
1445
21a151d8
RB		 1446DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1447DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1da177e4
LT		 1448DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1449DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
21a151d8
RB		 1450DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1451DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1da177e4
LT		 1452DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1453DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1454
eae89076 1455static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
515b029d 1456 mips_instruction ir, void *__user *fault_addr)
1da177e4
LT		 1457{
1458 unsigned rcsr = 0; /* resulting csr */
1459
b6ee75ed 1460 MIPS_FPU_EMU_INC_STATS(cp1xops);
1da177e4
LT		 1461
1462 switch (MIPSInst_FMA_FFMT(ir)) {
1463 case s_fmt:{ /* 0 */
1464
2209bcb1
RB		 1465 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1466 union ieee754sp fd, fr, fs, ft;
3fccc015 1467 u32 __user *va;
1da177e4
LT		 1468 u32 val;
1469
1470 switch (MIPSInst_FUNC(ir)) {
1471 case lwxc1_op:
3fccc015 1472 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1da177e4
LT		 1473 xcp->regs[MIPSInst_FT(ir)]);
1474
b6ee75ed 1475 MIPS_FPU_EMU_INC_STATS(loads);
515b029d 1476 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
b6ee75ed 1477 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1478 *fault_addr = va;
1da177e4
LT		 1479 return SIGBUS;
1480 }
515b029d
DD		 1481 if (__get_user(val, va)) {
1482 MIPS_FPU_EMU_INC_STATS(errors);
1483 *fault_addr = va;
1484 return SIGSEGV;
1485 }
1da177e4
LT		 1486 SITOREG(val, MIPSInst_FD(ir));
1487 break;
1488
1489 case swxc1_op:
3fccc015 1490 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1da177e4
LT		 1491 xcp->regs[MIPSInst_FT(ir)]);
1492
b6ee75ed 1493 MIPS_FPU_EMU_INC_STATS(stores);
1da177e4
LT		 1494
1495 SIFROMREG(val, MIPSInst_FS(ir));
515b029d 1496 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
b6ee75ed 1497 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1498 *fault_addr = va;
1da177e4
LT		 1499 return SIGBUS;
1500 }
515b029d
DD		 1501 if (put_user(val, va)) {
1502 MIPS_FPU_EMU_INC_STATS(errors);
1503 *fault_addr = va;
1504 return SIGSEGV;
1505 }
1da177e4
LT		 1506 break;
1507
1508 case madd_s_op:
1509 handler = fpemu_sp_madd;
1510 goto scoptop;
1511 case msub_s_op:
1512 handler = fpemu_sp_msub;
1513 goto scoptop;
1514 case nmadd_s_op:
1515 handler = fpemu_sp_nmadd;
1516 goto scoptop;
1517 case nmsub_s_op:
1518 handler = fpemu_sp_nmsub;
1519 goto scoptop;
1520
1521 scoptop:
1522 SPFROMREG(fr, MIPSInst_FR(ir));
1523 SPFROMREG(fs, MIPSInst_FS(ir));
1524 SPFROMREG(ft, MIPSInst_FT(ir));
1525 fd = (*handler) (fr, fs, ft);
1526 SPTOREG(fd, MIPSInst_FD(ir));
1527
1528 copcsr:
c4103526
DCZ		 1529 if (ieee754_cxtest(IEEE754_INEXACT)) {
1530 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1da177e4 1531 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
c4103526
DCZ		 1532 }
1533 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1534 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1da177e4 1535 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
c4103526
DCZ		 1536 }
1537 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1538 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1da177e4 1539 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
c4103526
DCZ		 1540 }
1541 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1542 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1da177e4 1543 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
c4103526 1544 }
1da177e4
LT		 1545
1546 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1da177e4 1547 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
3f7cac41 1548 /*printk ("SIGFPE: FPU csr = %08x\n",
1da177e4
LT		 1549 ctx->fcr31); */
1550 return SIGFPE;
1551 }
1552
1553 break;
1554
1555 default:
1556 return SIGILL;
1557 }
1558 break;
1559 }
1560
1da177e4 1561 case d_fmt:{ /* 1 */
2209bcb1
RB		 1562 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1563 union ieee754dp fd, fr, fs, ft;
3fccc015 1564 u64 __user *va;
1da177e4
LT		 1565 u64 val;
1566
1567 switch (MIPSInst_FUNC(ir)) {
1568 case ldxc1_op:
3fccc015 1569 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1da177e4
LT		 1570 xcp->regs[MIPSInst_FT(ir)]);
1571
b6ee75ed 1572 MIPS_FPU_EMU_INC_STATS(loads);
515b029d 1573 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
b6ee75ed 1574 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1575 *fault_addr = va;
1da177e4
LT		 1576 return SIGBUS;
1577 }
515b029d
DD		 1578 if (__get_user(val, va)) {
1579 MIPS_FPU_EMU_INC_STATS(errors);
1580 *fault_addr = va;
1581 return SIGSEGV;
1582 }
1da177e4
LT		 1583 DITOREG(val, MIPSInst_FD(ir));
1584 break;
1585
1586 case sdxc1_op:
3fccc015 1587 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1da177e4
LT		 1588 xcp->regs[MIPSInst_FT(ir)]);
1589
b6ee75ed 1590 MIPS_FPU_EMU_INC_STATS(stores);
1da177e4 1591 DIFROMREG(val, MIPSInst_FS(ir));
515b029d 1592 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
b6ee75ed 1593 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1594 *fault_addr = va;
1da177e4
LT		 1595 return SIGBUS;
1596 }
515b029d
DD		 1597 if (__put_user(val, va)) {
1598 MIPS_FPU_EMU_INC_STATS(errors);
1599 *fault_addr = va;
1600 return SIGSEGV;
1601 }
1da177e4
LT		 1602 break;
1603
1604 case madd_d_op:
1605 handler = fpemu_dp_madd;
1606 goto dcoptop;
1607 case msub_d_op:
1608 handler = fpemu_dp_msub;
1609 goto dcoptop;
1610 case nmadd_d_op:
1611 handler = fpemu_dp_nmadd;
1612 goto dcoptop;
1613 case nmsub_d_op:
1614 handler = fpemu_dp_nmsub;
1615 goto dcoptop;
1616
1617 dcoptop:
1618 DPFROMREG(fr, MIPSInst_FR(ir));
1619 DPFROMREG(fs, MIPSInst_FS(ir));
1620 DPFROMREG(ft, MIPSInst_FT(ir));
1621 fd = (*handler) (fr, fs, ft);
1622 DPTOREG(fd, MIPSInst_FD(ir));
1623 goto copcsr;
1624
1625 default:
1626 return SIGILL;
1627 }
1628 break;
1629 }
1da177e4 1630
51061b88
DCZ		 1631 case 0x3:
1632 if (MIPSInst_FUNC(ir) != pfetch_op)
1da177e4 1633 return SIGILL;
51061b88 1634
1da177e4
LT		 1635 /* ignore prefx operation */
1636 break;
1637
1638 default:
1639 return SIGILL;
1640 }
1641
1642 return 0;
1643}
1da177e4
LT		 1644
1645
1646
1647/*
1648 * Emulate a single COP1 arithmetic instruction.
1649 */
eae89076 1650static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1da177e4
LT		 1651 mips_instruction ir)
1652{
1653 int rfmt; /* resulting format */
1654 unsigned rcsr = 0; /* resulting csr */
3f7cac41
RB		 1655 unsigned int oldrm;
1656 unsigned int cbit;
1da177e4
LT		 1657 unsigned cond;
1658 union {
2209bcb1
RB		 1659 union ieee754dp d;
1660 union ieee754sp s;
1da177e4 1661 int w;
1da177e4 1662 s64 l;
1da177e4 1663 } rv; /* resulting value */
3f7cac41 1664 u64 bits;
1da177e4 1665
b6ee75ed 1666 MIPS_FPU_EMU_INC_STATS(cp1ops);
1da177e4 1667 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
3f7cac41 1668 case s_fmt: { /* 0 */
1da177e4 1669 union {
2209bcb1
RB		 1670 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1671 union ieee754sp(*u) (union ieee754sp);
1da177e4 1672 } handler;
3f7cac41 1673 union ieee754sp fs, ft;
1da177e4
LT		 1674
1675 switch (MIPSInst_FUNC(ir)) {
1676 /* binary ops */
1677 case fadd_op:
1678 handler.b = ieee754sp_add;
1679 goto scopbop;
1680 case fsub_op:
1681 handler.b = ieee754sp_sub;
1682 goto scopbop;
1683 case fmul_op:
1684 handler.b = ieee754sp_mul;
1685 goto scopbop;
1686 case fdiv_op:
1687 handler.b = ieee754sp_div;
1688 goto scopbop;
1689
1690 /* unary ops */
1da177e4 1691 case fsqrt_op:
2d83fea7 1692 if (!cpu_has_mips_2_3_4_5_r)
08a07904
RB		 1693 return SIGILL;
1694
1da177e4
LT		 1695 handler.u = ieee754sp_sqrt;
1696 goto scopuop;
3f7cac41 1697
08a07904
RB		 1698 /*
1699 * Note that on some MIPS IV implementations such as the
1700 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1701 * achieve full IEEE-754 accuracy - however this emulator does.
1702 */
1da177e4 1703 case frsqrt_op:
2d83fea7 1704 if (!cpu_has_mips_4_5_64_r2_r6)
08a07904
RB		 1705 return SIGILL;
1706
1da177e4
LT		 1707 handler.u = fpemu_sp_rsqrt;
1708 goto scopuop;
3f7cac41 1709
1da177e4 1710 case frecip_op:
2d83fea7 1711 if (!cpu_has_mips_4_5_64_r2_r6)
08a07904
RB		 1712 return SIGILL;
1713
1da177e4
LT		 1714 handler.u = fpemu_sp_recip;
1715 goto scopuop;
08a07904 1716
1da177e4 1717 case fmovc_op:
08a07904
RB		 1718 if (!cpu_has_mips_4_5_r)
1719 return SIGILL;
1720
1da177e4
LT		 1721 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1722 if (((ctx->fcr31 & cond) != 0) !=
1723 ((MIPSInst_FT(ir) & 1) != 0))
1724 return 0;
1725 SPFROMREG(rv.s, MIPSInst_FS(ir));
1726 break;
3f7cac41 1727
1da177e4 1728 case fmovz_op:
08a07904
RB		 1729 if (!cpu_has_mips_4_5_r)
1730 return SIGILL;
1731
1da177e4
LT		 1732 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1733 return 0;
1734 SPFROMREG(rv.s, MIPSInst_FS(ir));
1735 break;
3f7cac41 1736
1da177e4 1737 case fmovn_op:
08a07904
RB		 1738 if (!cpu_has_mips_4_5_r)
1739 return SIGILL;
1740
1da177e4
LT		 1741 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1742 return 0;
1743 SPFROMREG(rv.s, MIPSInst_FS(ir));
1744 break;
3f7cac41 1745
67613f02
MC		 1746 case fseleqz_op:
1747 if (!cpu_has_mips_r6)
1748 return SIGILL;
1749
1750 SPFROMREG(rv.s, MIPSInst_FT(ir));
1751 if (rv.w & 0x1)
1752 rv.w = 0;
1753 else
1754 SPFROMREG(rv.s, MIPSInst_FS(ir));
1755 break;
1756
130fe357
MC		 1757 case fselnez_op:
1758 if (!cpu_has_mips_r6)
1759 return SIGILL;
1760
1761 SPFROMREG(rv.s, MIPSInst_FT(ir));
1762 if (rv.w & 0x1)
1763 SPFROMREG(rv.s, MIPSInst_FS(ir));
1764 else
1765 rv.w = 0;
1766 break;
1767
e24c3bec
MC		 1768 case fmaddf_op: {
1769 union ieee754sp ft, fs, fd;
1770
1771 if (!cpu_has_mips_r6)
1772 return SIGILL;
1773
1774 SPFROMREG(ft, MIPSInst_FT(ir));
1775 SPFROMREG(fs, MIPSInst_FS(ir));
1776 SPFROMREG(fd, MIPSInst_FD(ir));
1777 rv.s = ieee754sp_maddf(fd, fs, ft);
1778 break;
1779 }
1780
83d43305
MC		 1781 case fmsubf_op: {
1782 union ieee754sp ft, fs, fd;
1783
1784 if (!cpu_has_mips_r6)
1785 return SIGILL;
1786
1787 SPFROMREG(ft, MIPSInst_FT(ir));
1788 SPFROMREG(fs, MIPSInst_FS(ir));
1789 SPFROMREG(fd, MIPSInst_FD(ir));
1790 rv.s = ieee754sp_msubf(fd, fs, ft);
1791 break;
1792 }
1793
400bd2e4
MC		 1794 case frint_op: {
1795 union ieee754sp fs;
1796
1797 if (!cpu_has_mips_r6)
1798 return SIGILL;
1799
1800 SPFROMREG(fs, MIPSInst_FS(ir));
1801 rv.l = ieee754sp_tlong(fs);
1802 rv.s = ieee754sp_flong(rv.l);
1803 goto copcsr;
1804 }
1805
1da177e4
LT		 1806 case fabs_op:
1807 handler.u = ieee754sp_abs;
1808 goto scopuop;
3f7cac41 1809
1da177e4
LT		 1810 case fneg_op:
1811 handler.u = ieee754sp_neg;
1812 goto scopuop;
3f7cac41 1813
1da177e4
LT		 1814 case fmov_op:
1815 /* an easy one */
1816 SPFROMREG(rv.s, MIPSInst_FS(ir));
1817 goto copcsr;
1818
1819 /* binary op on handler */
3f7cac41
RB		 1820scopbop:
1821 SPFROMREG(fs, MIPSInst_FS(ir));
1822 SPFROMREG(ft, MIPSInst_FT(ir));
1da177e4 1823
3f7cac41
RB		 1824 rv.s = (*handler.b) (fs, ft);
1825 goto copcsr;
1826scopuop:
1827 SPFROMREG(fs, MIPSInst_FS(ir));
1828 rv.s = (*handler.u) (fs);
1829 goto copcsr;
1830copcsr:
c4103526
DCZ		 1831 if (ieee754_cxtest(IEEE754_INEXACT)) {
1832 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1da177e4 1833 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
c4103526
DCZ		 1834 }
1835 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1836 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1da177e4 1837 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
c4103526
DCZ		 1838 }
1839 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1840 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1da177e4 1841 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
c4103526
DCZ		 1842 }
1843 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1844 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1da177e4 1845 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
c4103526
DCZ		 1846 }
1847 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1848 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1da177e4 1849 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
c4103526 1850 }
1da177e4
LT		 1851 break;
1852
1853 /* unary conv ops */
1854 case fcvts_op:
1855 return SIGILL; /* not defined */
1da177e4 1856
3f7cac41 1857 case fcvtd_op:
1da177e4
LT		 1858 SPFROMREG(fs, MIPSInst_FS(ir));
1859 rv.d = ieee754dp_fsp(fs);
1860 rfmt = d_fmt;
1861 goto copcsr;
1da177e4 1862
3f7cac41 1863 case fcvtw_op:
1da177e4
LT		 1864 SPFROMREG(fs, MIPSInst_FS(ir));
1865 rv.w = ieee754sp_tint(fs);
1866 rfmt = w_fmt;
1867 goto copcsr;
1da177e4 1868
1da177e4
LT		 1869 case fround_op:
1870 case ftrunc_op:
1871 case fceil_op:
3f7cac41 1872 case ffloor_op:
2d83fea7 1873 if (!cpu_has_mips_2_3_4_5_r)
08a07904
RB		 1874 return SIGILL;
1875
3f7cac41 1876 oldrm = ieee754_csr.rm;
1da177e4 1877 SPFROMREG(fs, MIPSInst_FS(ir));
2cfcf8a8 1878 ieee754_csr.rm = MIPSInst_FUNC(ir);
1da177e4
LT		 1879 rv.w = ieee754sp_tint(fs);
1880 ieee754_csr.rm = oldrm;
1881 rfmt = w_fmt;
1882 goto copcsr;
1da177e4 1883
3f7cac41 1884 case fcvtl_op:
2d83fea7 1885 if (!cpu_has_mips_3_4_5_64_r2_r6)
08a07904
RB		 1886 return SIGILL;
1887
1da177e4
LT		 1888 SPFROMREG(fs, MIPSInst_FS(ir));
1889 rv.l = ieee754sp_tlong(fs);
1890 rfmt = l_fmt;
1891 goto copcsr;
1da177e4
LT		 1892
1893 case froundl_op:
1894 case ftruncl_op:
1895 case fceill_op:
3f7cac41 1896 case ffloorl_op:
2d83fea7 1897 if (!cpu_has_mips_3_4_5_64_r2_r6)
08a07904
RB		 1898 return SIGILL;
1899
3f7cac41 1900 oldrm = ieee754_csr.rm;
1da177e4 1901 SPFROMREG(fs, MIPSInst_FS(ir));
2cfcf8a8 1902 ieee754_csr.rm = MIPSInst_FUNC(ir);
1da177e4
LT		 1903 rv.l = ieee754sp_tlong(fs);
1904 ieee754_csr.rm = oldrm;
1905 rfmt = l_fmt;
1906 goto copcsr;
1da177e4
LT		 1907
1908 default:
f8c3c671 1909 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
1da177e4 1910 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2209bcb1 1911 union ieee754sp fs, ft;
1da177e4
LT		 1912
1913 SPFROMREG(fs, MIPSInst_FS(ir));
1914 SPFROMREG(ft, MIPSInst_FT(ir));
1915 rv.w = ieee754sp_cmp(fs, ft,
1916 cmptab[cmpop & 0x7], cmpop & 0x8);
1917 rfmt = -1;
1918 if ((cmpop & 0x8) && ieee754_cxtest
1919 (IEEE754_INVALID_OPERATION))
1920 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1921 else
1922 goto copcsr;
1923
3f7cac41 1924 } else
1da177e4 1925 return SIGILL;
1da177e4
LT		 1926 break;
1927 }
1928 break;
1929 }
1930
3f7cac41
RB		 1931 case d_fmt: {
1932 union ieee754dp fs, ft;
1da177e4 1933 union {
2209bcb1
RB		 1934 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
1935 union ieee754dp(*u) (union ieee754dp);
1da177e4
LT		 1936 } handler;
1937
1938 switch (MIPSInst_FUNC(ir)) {
1939 /* binary ops */
1940 case fadd_op:
1941 handler.b = ieee754dp_add;
1942 goto dcopbop;
1943 case fsub_op:
1944 handler.b = ieee754dp_sub;
1945 goto dcopbop;
1946 case fmul_op:
1947 handler.b = ieee754dp_mul;
1948 goto dcopbop;
1949 case fdiv_op:
1950 handler.b = ieee754dp_div;
1951 goto dcopbop;
1952
1953 /* unary ops */
1da177e4 1954 case fsqrt_op:
08a07904
RB		 1955 if (!cpu_has_mips_2_3_4_5_r)
1956 return SIGILL;
1957
1da177e4
LT		 1958 handler.u = ieee754dp_sqrt;
1959 goto dcopuop;
08a07904
RB		 1960 /*
1961 * Note that on some MIPS IV implementations such as the
1962 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1963 * achieve full IEEE-754 accuracy - however this emulator does.
1964 */
1da177e4 1965 case frsqrt_op:
2d83fea7 1966 if (!cpu_has_mips_4_5_64_r2_r6)
08a07904
RB		 1967 return SIGILL;
1968
1da177e4
LT		 1969 handler.u = fpemu_dp_rsqrt;
1970 goto dcopuop;
1971 case frecip_op:
2d83fea7 1972 if (!cpu_has_mips_4_5_64_r2_r6)
08a07904
RB		 1973 return SIGILL;
1974
1da177e4
LT		 1975 handler.u = fpemu_dp_recip;
1976 goto dcopuop;
1da177e4 1977 case fmovc_op:
08a07904
RB		 1978 if (!cpu_has_mips_4_5_r)
1979 return SIGILL;
1980
1da177e4
LT		 1981 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1982 if (((ctx->fcr31 & cond) != 0) !=
1983 ((MIPSInst_FT(ir) & 1) != 0))
1984 return 0;
1985 DPFROMREG(rv.d, MIPSInst_FS(ir));
1986 break;
1987 case fmovz_op:
08a07904
RB		 1988 if (!cpu_has_mips_4_5_r)
1989 return SIGILL;
1990
1da177e4
LT		 1991 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1992 return 0;
1993 DPFROMREG(rv.d, MIPSInst_FS(ir));
1994 break;
1995 case fmovn_op:
08a07904
RB		 1996 if (!cpu_has_mips_4_5_r)
1997 return SIGILL;
1998
1da177e4
LT		 1999 if (xcp->regs[MIPSInst_FT(ir)] == 0)
2000 return 0;
2001 DPFROMREG(rv.d, MIPSInst_FS(ir));
2002 break;
67613f02
MC		 2003
2004 case fseleqz_op:
2005 if (!cpu_has_mips_r6)
2006 return SIGILL;
2007
2008 DPFROMREG(rv.d, MIPSInst_FT(ir));
2009 if (rv.l & 0x1)
2010 rv.l = 0;
2011 else
2012 DPFROMREG(rv.d, MIPSInst_FS(ir));
2013 break;
2014
130fe357
MC		 2015 case fselnez_op:
2016 if (!cpu_has_mips_r6)
2017 return SIGILL;
2018
2019 DPFROMREG(rv.d, MIPSInst_FT(ir));
2020 if (rv.l & 0x1)
2021 DPFROMREG(rv.d, MIPSInst_FS(ir));
2022 else
2023 rv.l = 0;
2024 break;
2025
e24c3bec
MC		 2026 case fmaddf_op: {
2027 union ieee754dp ft, fs, fd;
2028
2029 if (!cpu_has_mips_r6)
2030 return SIGILL;
2031
2032 DPFROMREG(ft, MIPSInst_FT(ir));
2033 DPFROMREG(fs, MIPSInst_FS(ir));
2034 DPFROMREG(fd, MIPSInst_FD(ir));
2035 rv.d = ieee754dp_maddf(fd, fs, ft);
2036 break;
2037 }
2038
83d43305
MC		 2039 case fmsubf_op: {
2040 union ieee754dp ft, fs, fd;
2041
2042 if (!cpu_has_mips_r6)
2043 return SIGILL;
2044
2045 DPFROMREG(ft, MIPSInst_FT(ir));
2046 DPFROMREG(fs, MIPSInst_FS(ir));
2047 DPFROMREG(fd, MIPSInst_FD(ir));
2048 rv.d = ieee754dp_msubf(fd, fs, ft);
2049 break;
2050 }
2051
400bd2e4
MC		 2052 case frint_op: {
2053 union ieee754dp fs;
2054
2055 if (!cpu_has_mips_r6)
2056 return SIGILL;
2057
2058 DPFROMREG(fs, MIPSInst_FS(ir));
2059 rv.l = ieee754dp_tlong(fs);
2060 rv.d = ieee754dp_flong(rv.l);
2061 goto copcsr;
2062 }
2063
1da177e4
LT		 2064 case fabs_op:
2065 handler.u = ieee754dp_abs;
2066 goto dcopuop;
2067
2068 case fneg_op:
2069 handler.u = ieee754dp_neg;
2070 goto dcopuop;
2071
2072 case fmov_op:
2073 /* an easy one */
2074 DPFROMREG(rv.d, MIPSInst_FS(ir));
2075 goto copcsr;
2076
2077 /* binary op on handler */
3f7cac41
RB		 2078dcopbop:
2079 DPFROMREG(fs, MIPSInst_FS(ir));
2080 DPFROMREG(ft, MIPSInst_FT(ir));
1da177e4 2081
3f7cac41
RB		 2082 rv.d = (*handler.b) (fs, ft);
2083 goto copcsr;
2084dcopuop:
2085 DPFROMREG(fs, MIPSInst_FS(ir));
2086 rv.d = (*handler.u) (fs);
2087 goto copcsr;
1da177e4 2088
3f7cac41
RB		 2089 /*
2090 * unary conv ops
2091 */
2092 case fcvts_op:
1da177e4
LT		 2093 DPFROMREG(fs, MIPSInst_FS(ir));
2094 rv.s = ieee754sp_fdp(fs);
2095 rfmt = s_fmt;
2096 goto copcsr;
3f7cac41 2097
1da177e4
LT		 2098 case fcvtd_op:
2099 return SIGILL; /* not defined */
2100
3f7cac41 2101 case fcvtw_op:
1da177e4
LT		 2102 DPFROMREG(fs, MIPSInst_FS(ir));
2103 rv.w = ieee754dp_tint(fs); /* wrong */
2104 rfmt = w_fmt;
2105 goto copcsr;
1da177e4 2106
1da177e4
LT		 2107 case fround_op:
2108 case ftrunc_op:
2109 case fceil_op:
3f7cac41 2110 case ffloor_op:
08a07904
RB		 2111 if (!cpu_has_mips_2_3_4_5_r)
2112 return SIGILL;
2113
3f7cac41 2114 oldrm = ieee754_csr.rm;
1da177e4 2115 DPFROMREG(fs, MIPSInst_FS(ir));
2cfcf8a8 2116 ieee754_csr.rm = MIPSInst_FUNC(ir);
1da177e4
LT		 2117 rv.w = ieee754dp_tint(fs);
2118 ieee754_csr.rm = oldrm;
2119 rfmt = w_fmt;
2120 goto copcsr;
1da177e4 2121
3f7cac41 2122 case fcvtl_op:
2d83fea7 2123 if (!cpu_has_mips_3_4_5_64_r2_r6)
08a07904
RB		 2124 return SIGILL;
2125
1da177e4
LT		 2126 DPFROMREG(fs, MIPSInst_FS(ir));
2127 rv.l = ieee754dp_tlong(fs);
2128 rfmt = l_fmt;
2129 goto copcsr;
1da177e4
LT		 2130
2131 case froundl_op:
2132 case ftruncl_op:
2133 case fceill_op:
3f7cac41 2134 case ffloorl_op:
2d83fea7 2135 if (!cpu_has_mips_3_4_5_64_r2_r6)
08a07904
RB		 2136 return SIGILL;
2137
3f7cac41 2138 oldrm = ieee754_csr.rm;
1da177e4 2139 DPFROMREG(fs, MIPSInst_FS(ir));
2cfcf8a8 2140 ieee754_csr.rm = MIPSInst_FUNC(ir);
1da177e4
LT		 2141 rv.l = ieee754dp_tlong(fs);
2142 ieee754_csr.rm = oldrm;
2143 rfmt = l_fmt;
2144 goto copcsr;
1da177e4
LT		 2145
2146 default:
f8c3c671 2147 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
1da177e4 2148 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2209bcb1 2149 union ieee754dp fs, ft;
1da177e4
LT		 2150
2151 DPFROMREG(fs, MIPSInst_FS(ir));
2152 DPFROMREG(ft, MIPSInst_FT(ir));
2153 rv.w = ieee754dp_cmp(fs, ft,
2154 cmptab[cmpop & 0x7], cmpop & 0x8);
2155 rfmt = -1;
2156 if ((cmpop & 0x8)
2157 &&
2158 ieee754_cxtest
2159 (IEEE754_INVALID_OPERATION))
2160 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2161 else
2162 goto copcsr;
2163
2164 }
2165 else {
2166 return SIGILL;
2167 }
2168 break;
2169 }
2170 break;
bbdd8147
MC		 2171 }
2172
2173 case w_fmt: {
2174 union ieee754dp fs;
1da177e4
LT		 2175
2176 switch (MIPSInst_FUNC(ir)) {
2177 case fcvts_op:
2178 /* convert word to single precision real */
2179 SPFROMREG(fs, MIPSInst_FS(ir));
2180 rv.s = ieee754sp_fint(fs.bits);
2181 rfmt = s_fmt;
2182 goto copcsr;
1da177e4
LT		 2183 case fcvtd_op:
2184 /* convert word to double precision real */
2185 SPFROMREG(fs, MIPSInst_FS(ir));
2186 rv.d = ieee754dp_fint(fs.bits);
2187 rfmt = d_fmt;
2188 goto copcsr;
f8c3c671
MC		 2189 default: {
2190 /* Emulating the new CMP.condn.fmt R6 instruction */
2191#define CMPOP_MASK 0x7
2192#define SIGN_BIT (0x1 << 3)
2193#define PREDICATE_BIT (0x1 << 4)
2194
2195 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2196 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2197 union ieee754sp fs, ft;
2198
2199 /* This is an R6 only instruction */
2200 if (!cpu_has_mips_r6 ||
2201 (MIPSInst_FUNC(ir) & 0x20))
2202 return SIGILL;
2203
2204 /* fmt is w_fmt for single precision so fix it */
2205 rfmt = s_fmt;
2206 /* default to false */
2207 rv.w = 0;
2208
2209 /* CMP.condn.S */
2210 SPFROMREG(fs, MIPSInst_FS(ir));
2211 SPFROMREG(ft, MIPSInst_FT(ir));
2212
2213 /* positive predicates */
2214 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2215 if (ieee754sp_cmp(fs, ft, cmptab[cmpop],
2216 sig))
2217 rv.w = -1; /* true, all 1s */
2218 if ((sig) &&
2219 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2220 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2221 else
2222 goto copcsr;
2223 } else {
2224 /* negative predicates */
2225 switch (cmpop) {
2226 case 1:
2227 case 2:
2228 case 3:
2229 if (ieee754sp_cmp(fs, ft,
2230 negative_cmptab[cmpop],
2231 sig))
2232 rv.w = -1; /* true, all 1s */
2233 if (sig &&
2234 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2235 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2236 else
2237 goto copcsr;
2238 break;
2239 default:
2240 /* Reserved R6 ops */
2241 pr_err("Reserved MIPS R6 CMP.condn.S operation\n");
2242 return SIGILL;
2243 }
2244 }
2245 break;
2246 }
1da177e4 2247 }
1da177e4
LT		 2248 }
2249
3f7cac41 2250 case l_fmt:
08a07904 2251
2d83fea7 2252 if (!cpu_has_mips_3_4_5_64_r2_r6)
08a07904
RB		 2253 return SIGILL;
2254
bbd426f5
PB		 2255 DIFROMREG(bits, MIPSInst_FS(ir));
2256
1da177e4
LT		 2257 switch (MIPSInst_FUNC(ir)) {
2258 case fcvts_op:
2259 /* convert long to single precision real */
bbd426f5 2260 rv.s = ieee754sp_flong(bits);
1da177e4
LT		 2261 rfmt = s_fmt;
2262 goto copcsr;
2263 case fcvtd_op:
2264 /* convert long to double precision real */
bbd426f5 2265 rv.d = ieee754dp_flong(bits);
1da177e4
LT		 2266 rfmt = d_fmt;
2267 goto copcsr;
f8c3c671
MC		 2268 default: {
2269 /* Emulating the new CMP.condn.fmt R6 instruction */
2270 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2271 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2272 union ieee754dp fs, ft;
2273
2274 if (!cpu_has_mips_r6 ||
2275 (MIPSInst_FUNC(ir) & 0x20))
2276 return SIGILL;
2277
2278 /* fmt is l_fmt for double precision so fix it */
2279 rfmt = d_fmt;
2280 /* default to false */
2281 rv.l = 0;
2282
2283 /* CMP.condn.D */
2284 DPFROMREG(fs, MIPSInst_FS(ir));
2285 DPFROMREG(ft, MIPSInst_FT(ir));
1da177e4 2286
f8c3c671
MC		 2287 /* positive predicates */
2288 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2289 if (ieee754dp_cmp(fs, ft,
2290 cmptab[cmpop], sig))
2291 rv.l = -1LL; /* true, all 1s */
2292 if (sig &&
2293 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2294 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2295 else
2296 goto copcsr;
2297 } else {
2298 /* negative predicates */
2299 switch (cmpop) {
2300 case 1:
2301 case 2:
2302 case 3:
2303 if (ieee754dp_cmp(fs, ft,
2304 negative_cmptab[cmpop],
2305 sig))
2306 rv.l = -1LL; /* true, all 1s */
2307 if (sig &&
2308 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2309 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2310 else
2311 goto copcsr;
2312 break;
2313 default:
2314 /* Reserved R6 ops */
2315 pr_err("Reserved MIPS R6 CMP.condn.D operation\n");
2316 return SIGILL;
2317 }
2318 }
2319 break;
2320 }
2321 }
1da177e4
LT		 2322 default:
2323 return SIGILL;
2324 }
2325
2326 /*
2327 * Update the fpu CSR register for this operation.
2328 * If an exception is required, generate a tidy SIGFPE exception,
2329 * without updating the result register.
2330 * Note: cause exception bits do not accumulate, they are rewritten
2331 * for each op; only the flag/sticky bits accumulate.
2332 */
2333 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2334 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
3f7cac41 2335 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
1da177e4
LT		 2336 return SIGFPE;
2337 }
2338
2339 /*
2340 * Now we can safely write the result back to the register file.
2341 */
2342 switch (rfmt) {
08a07904
RB		 2343 case -1:
2344
2345 if (cpu_has_mips_4_5_r)
c3b9b945 2346 cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
08a07904
RB		 2347 else
2348 cbit = FPU_CSR_COND;
1da177e4 2349 if (rv.w)
08a07904 2350 ctx->fcr31 |= cbit;
1da177e4 2351 else
08a07904 2352 ctx->fcr31 &= ~cbit;
1da177e4 2353 break;
08a07904 2354
1da177e4
LT		 2355 case d_fmt:
2356 DPTOREG(rv.d, MIPSInst_FD(ir));
2357 break;
1da177e4
LT		 2358 case s_fmt:
2359 SPTOREG(rv.s, MIPSInst_FD(ir));
2360 break;
2361 case w_fmt:
2362 SITOREG(rv.w, MIPSInst_FD(ir));
2363 break;
1da177e4 2364 case l_fmt:
2d83fea7 2365 if (!cpu_has_mips_3_4_5_64_r2_r6)
08a07904
RB		 2366 return SIGILL;
2367
1da177e4
LT		 2368 DITOREG(rv.l, MIPSInst_FD(ir));
2369 break;
1da177e4
LT		 2370 default:
2371 return SIGILL;
2372 }
2373
2374 return 0;
2375}
2376
e04582b7 2377int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
515b029d 2378 int has_fpu, void *__user *fault_addr)
1da177e4 2379{
333d1f67 2380 unsigned long oldepc, prevepc;
102cedc3
LY		 2381 struct mm_decoded_insn dec_insn;
2382 u16 instr[4];
2383 u16 *instr_ptr;
1da177e4
LT		 2384 int sig = 0;
2385
2386 oldepc = xcp->cp0_epc;
2387 do {
2388 prevepc = xcp->cp0_epc;
2389
102cedc3
LY		 2390 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2391 /*
2392 * Get next 2 microMIPS instructions and convert them
2393 * into 32-bit instructions.
2394 */
2395 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2396 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2397 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2398 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2399 MIPS_FPU_EMU_INC_STATS(errors);
2400 return SIGBUS;
2401 }
2402 instr_ptr = instr;
2403
2404 /* Get first instruction. */
2405 if (mm_insn_16bit(*instr_ptr)) {
2406 /* Duplicate the half-word. */
2407 dec_insn.insn = (*instr_ptr << 16) |
2408 (*instr_ptr);
2409 /* 16-bit instruction. */
2410 dec_insn.pc_inc = 2;
2411 instr_ptr += 1;
2412 } else {
2413 dec_insn.insn = (*instr_ptr << 16) |
2414 *(instr_ptr+1);
2415 /* 32-bit instruction. */
2416 dec_insn.pc_inc = 4;
2417 instr_ptr += 2;
2418 }
2419 /* Get second instruction. */
2420 if (mm_insn_16bit(*instr_ptr)) {
2421 /* Duplicate the half-word. */
2422 dec_insn.next_insn = (*instr_ptr << 16) |
2423 (*instr_ptr);
2424 /* 16-bit instruction. */
2425 dec_insn.next_pc_inc = 2;
2426 } else {
2427 dec_insn.next_insn = (*instr_ptr << 16) |
2428 *(instr_ptr+1);
2429 /* 32-bit instruction. */
2430 dec_insn.next_pc_inc = 4;
2431 }
2432 dec_insn.micro_mips_mode = 1;
2433 } else {
2434 if ((get_user(dec_insn.insn,
2435 (mips_instruction __user *) xcp->cp0_epc)) ||
2436 (get_user(dec_insn.next_insn,
2437 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2438 MIPS_FPU_EMU_INC_STATS(errors);
2439 return SIGBUS;
2440 }
2441 dec_insn.pc_inc = 4;
2442 dec_insn.next_pc_inc = 4;
2443 dec_insn.micro_mips_mode = 0;
515b029d 2444 }
102cedc3
LY		 2445
2446 if ((dec_insn.insn == 0) ||
2447 ((dec_insn.pc_inc == 2) &&
2448 ((dec_insn.insn & 0xffff) == MM_NOP16)))
2449 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
1da177e4 2450 else {
cd21dfcf 2451 /*
2cfcf8a8
MR		 2452 * The 'ieee754_csr' is an alias of ctx->fcr31.
2453 * No need to copy ctx->fcr31 to ieee754_csr.
cd21dfcf 2454 */
102cedc3 2455 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
1da177e4
LT		 2456 }
2457
e04582b7 2458 if (has_fpu)
1da177e4
LT		 2459 break;
2460 if (sig)
2461 break;
2462
2463 cond_resched();
2464 } while (xcp->cp0_epc > prevepc);
2465
2466 /* SIGILL indicates a non-fpu instruction */
2467 if (sig == SIGILL && xcp->cp0_epc != oldepc)
3f7cac41 2468 /* but if EPC has advanced, then ignore it */
1da177e4
LT		 2469 sig = 0;
2470
2471 return sig;
2472}
Linux kernel - Deliverables
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