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1da177e4 LT |
1 | /* |
2 | * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator | |
3 | * | |
4 | * MIPS floating point support | |
5 | * Copyright (C) 1994-2000 Algorithmics Ltd. | |
1da177e4 LT |
6 | * |
7 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
8 | * Copyright (C) 2000 MIPS Technologies, Inc. | |
9 | * | |
10 | * This program is free software; you can distribute it and/or modify it | |
11 | * under the terms of the GNU General Public License (Version 2) as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | * for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along | |
20 | * with this program; if not, write to the Free Software Foundation, Inc., | |
21 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
22 | * | |
23 | * A complete emulator for MIPS coprocessor 1 instructions. This is | |
24 | * required for #float(switch) or #float(trap), where it catches all | |
25 | * COP1 instructions via the "CoProcessor Unusable" exception. | |
26 | * | |
27 | * More surprisingly it is also required for #float(ieee), to help out | |
28 | * the hardware fpu at the boundaries of the IEEE-754 representation | |
29 | * (denormalised values, infinities, underflow, etc). It is made | |
30 | * quite nasty because emulation of some non-COP1 instructions is | |
31 | * required, e.g. in branch delay slots. | |
32 | * | |
33 | * Note if you know that you won't have an fpu, then you'll get much | |
34 | * better performance by compiling with -msoft-float! | |
35 | */ | |
36 | #include <linux/sched.h> | |
b6ee75ed | 37 | #include <linux/module.h> |
83fd38ca | 38 | #include <linux/debugfs.h> |
7f788d2d | 39 | #include <linux/perf_event.h> |
1da177e4 LT |
40 | |
41 | #include <asm/inst.h> | |
42 | #include <asm/bootinfo.h> | |
1da177e4 LT |
43 | #include <asm/processor.h> |
44 | #include <asm/ptrace.h> | |
45 | #include <asm/signal.h> | |
46 | #include <asm/mipsregs.h> | |
47 | #include <asm/fpu_emulator.h> | |
102cedc3 | 48 | #include <asm/fpu.h> |
1da177e4 LT |
49 | #include <asm/uaccess.h> |
50 | #include <asm/branch.h> | |
51 | ||
52 | #include "ieee754.h" | |
1da177e4 LT |
53 | |
54 | /* Strap kernel emulator for full MIPS IV emulation */ | |
55 | ||
56 | #ifdef __mips | |
57 | #undef __mips | |
58 | #endif | |
59 | #define __mips 4 | |
60 | ||
61 | /* Function which emulates a floating point instruction. */ | |
62 | ||
eae89076 | 63 | static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, |
1da177e4 LT |
64 | mips_instruction); |
65 | ||
66 | #if __mips >= 4 && __mips != 32 | |
67 | static int fpux_emu(struct pt_regs *, | |
515b029d | 68 | struct mips_fpu_struct *, mips_instruction, void *__user *); |
1da177e4 LT |
69 | #endif |
70 | ||
eae89076 | 71 | /* Further private data for which no space exists in mips_fpu_struct */ |
1da177e4 | 72 | |
b6ee75ed DD |
73 | #ifdef CONFIG_DEBUG_FS |
74 | DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats); | |
75 | #endif | |
1da177e4 LT |
76 | |
77 | /* Control registers */ | |
78 | ||
79 | #define FPCREG_RID 0 /* $0 = revision id */ | |
80 | #define FPCREG_CSR 31 /* $31 = csr */ | |
81 | ||
95e8f634 SM |
82 | /* Determine rounding mode from the RM bits of the FCSR */ |
83 | #define modeindex(v) ((v) & FPU_CSR_RM) | |
84 | ||
102cedc3 LY |
85 | /* microMIPS bitfields */ |
86 | #define MM_POOL32A_MINOR_MASK 0x3f | |
87 | #define MM_POOL32A_MINOR_SHIFT 0x6 | |
88 | #define MM_MIPS32_COND_FC 0x30 | |
89 | ||
1da177e4 LT |
90 | /* Convert Mips rounding mode (0..3) to IEEE library modes. */ |
91 | static const unsigned char ieee_rm[4] = { | |
cd21dfcf RB |
92 | [FPU_CSR_RN] = IEEE754_RN, |
93 | [FPU_CSR_RZ] = IEEE754_RZ, | |
94 | [FPU_CSR_RU] = IEEE754_RU, | |
95 | [FPU_CSR_RD] = IEEE754_RD, | |
96 | }; | |
97 | /* Convert IEEE library modes to Mips rounding mode (0..3). */ | |
98 | static const unsigned char mips_rm[4] = { | |
99 | [IEEE754_RN] = FPU_CSR_RN, | |
100 | [IEEE754_RZ] = FPU_CSR_RZ, | |
101 | [IEEE754_RD] = FPU_CSR_RD, | |
102 | [IEEE754_RU] = FPU_CSR_RU, | |
1da177e4 LT |
103 | }; |
104 | ||
105 | #if __mips >= 4 | |
106 | /* convert condition code register number to csr bit */ | |
107 | static const unsigned int fpucondbit[8] = { | |
108 | FPU_CSR_COND0, | |
109 | FPU_CSR_COND1, | |
110 | FPU_CSR_COND2, | |
111 | FPU_CSR_COND3, | |
112 | FPU_CSR_COND4, | |
113 | FPU_CSR_COND5, | |
114 | FPU_CSR_COND6, | |
115 | FPU_CSR_COND7 | |
116 | }; | |
117 | #endif | |
118 | ||
102cedc3 LY |
119 | /* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */ |
120 | static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7}; | |
121 | ||
122 | /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */ | |
123 | static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0}; | |
124 | static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0}; | |
125 | static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0}; | |
126 | static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0}; | |
127 | ||
128 | /* | |
129 | * This functions translates a 32-bit microMIPS instruction | |
130 | * into a 32-bit MIPS32 instruction. Returns 0 on success | |
131 | * and SIGILL otherwise. | |
132 | */ | |
133 | static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) | |
134 | { | |
135 | union mips_instruction insn = *insn_ptr; | |
136 | union mips_instruction mips32_insn = insn; | |
137 | int func, fmt, op; | |
138 | ||
139 | switch (insn.mm_i_format.opcode) { | |
140 | case mm_ldc132_op: | |
141 | mips32_insn.mm_i_format.opcode = ldc1_op; | |
142 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
143 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
144 | break; | |
145 | case mm_lwc132_op: | |
146 | mips32_insn.mm_i_format.opcode = lwc1_op; | |
147 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
148 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
149 | break; | |
150 | case mm_sdc132_op: | |
151 | mips32_insn.mm_i_format.opcode = sdc1_op; | |
152 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
153 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
154 | break; | |
155 | case mm_swc132_op: | |
156 | mips32_insn.mm_i_format.opcode = swc1_op; | |
157 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
158 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
159 | break; | |
160 | case mm_pool32i_op: | |
161 | /* NOTE: offset is << by 1 if in microMIPS mode. */ | |
162 | if ((insn.mm_i_format.rt == mm_bc1f_op) || | |
163 | (insn.mm_i_format.rt == mm_bc1t_op)) { | |
164 | mips32_insn.fb_format.opcode = cop1_op; | |
165 | mips32_insn.fb_format.bc = bc_op; | |
166 | mips32_insn.fb_format.flag = | |
167 | (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0; | |
168 | } else | |
169 | return SIGILL; | |
170 | break; | |
171 | case mm_pool32f_op: | |
172 | switch (insn.mm_fp0_format.func) { | |
173 | case mm_32f_01_op: | |
174 | case mm_32f_11_op: | |
175 | case mm_32f_02_op: | |
176 | case mm_32f_12_op: | |
177 | case mm_32f_41_op: | |
178 | case mm_32f_51_op: | |
179 | case mm_32f_42_op: | |
180 | case mm_32f_52_op: | |
181 | op = insn.mm_fp0_format.func; | |
182 | if (op == mm_32f_01_op) | |
183 | func = madd_s_op; | |
184 | else if (op == mm_32f_11_op) | |
185 | func = madd_d_op; | |
186 | else if (op == mm_32f_02_op) | |
187 | func = nmadd_s_op; | |
188 | else if (op == mm_32f_12_op) | |
189 | func = nmadd_d_op; | |
190 | else if (op == mm_32f_41_op) | |
191 | func = msub_s_op; | |
192 | else if (op == mm_32f_51_op) | |
193 | func = msub_d_op; | |
194 | else if (op == mm_32f_42_op) | |
195 | func = nmsub_s_op; | |
196 | else | |
197 | func = nmsub_d_op; | |
198 | mips32_insn.fp6_format.opcode = cop1x_op; | |
199 | mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr; | |
200 | mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft; | |
201 | mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs; | |
202 | mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd; | |
203 | mips32_insn.fp6_format.func = func; | |
204 | break; | |
205 | case mm_32f_10_op: | |
206 | func = -1; /* Invalid */ | |
207 | op = insn.mm_fp5_format.op & 0x7; | |
208 | if (op == mm_ldxc1_op) | |
209 | func = ldxc1_op; | |
210 | else if (op == mm_sdxc1_op) | |
211 | func = sdxc1_op; | |
212 | else if (op == mm_lwxc1_op) | |
213 | func = lwxc1_op; | |
214 | else if (op == mm_swxc1_op) | |
215 | func = swxc1_op; | |
216 | ||
217 | if (func != -1) { | |
218 | mips32_insn.r_format.opcode = cop1x_op; | |
219 | mips32_insn.r_format.rs = | |
220 | insn.mm_fp5_format.base; | |
221 | mips32_insn.r_format.rt = | |
222 | insn.mm_fp5_format.index; | |
223 | mips32_insn.r_format.rd = 0; | |
224 | mips32_insn.r_format.re = insn.mm_fp5_format.fd; | |
225 | mips32_insn.r_format.func = func; | |
226 | } else | |
227 | return SIGILL; | |
228 | break; | |
229 | case mm_32f_40_op: | |
230 | op = -1; /* Invalid */ | |
231 | if (insn.mm_fp2_format.op == mm_fmovt_op) | |
232 | op = 1; | |
233 | else if (insn.mm_fp2_format.op == mm_fmovf_op) | |
234 | op = 0; | |
235 | if (op != -1) { | |
236 | mips32_insn.fp0_format.opcode = cop1_op; | |
237 | mips32_insn.fp0_format.fmt = | |
238 | sdps_format[insn.mm_fp2_format.fmt]; | |
239 | mips32_insn.fp0_format.ft = | |
240 | (insn.mm_fp2_format.cc<<2) + op; | |
241 | mips32_insn.fp0_format.fs = | |
242 | insn.mm_fp2_format.fs; | |
243 | mips32_insn.fp0_format.fd = | |
244 | insn.mm_fp2_format.fd; | |
245 | mips32_insn.fp0_format.func = fmovc_op; | |
246 | } else | |
247 | return SIGILL; | |
248 | break; | |
249 | case mm_32f_60_op: | |
250 | func = -1; /* Invalid */ | |
251 | if (insn.mm_fp0_format.op == mm_fadd_op) | |
252 | func = fadd_op; | |
253 | else if (insn.mm_fp0_format.op == mm_fsub_op) | |
254 | func = fsub_op; | |
255 | else if (insn.mm_fp0_format.op == mm_fmul_op) | |
256 | func = fmul_op; | |
257 | else if (insn.mm_fp0_format.op == mm_fdiv_op) | |
258 | func = fdiv_op; | |
259 | if (func != -1) { | |
260 | mips32_insn.fp0_format.opcode = cop1_op; | |
261 | mips32_insn.fp0_format.fmt = | |
262 | sdps_format[insn.mm_fp0_format.fmt]; | |
263 | mips32_insn.fp0_format.ft = | |
264 | insn.mm_fp0_format.ft; | |
265 | mips32_insn.fp0_format.fs = | |
266 | insn.mm_fp0_format.fs; | |
267 | mips32_insn.fp0_format.fd = | |
268 | insn.mm_fp0_format.fd; | |
269 | mips32_insn.fp0_format.func = func; | |
270 | } else | |
271 | return SIGILL; | |
272 | break; | |
273 | case mm_32f_70_op: | |
274 | func = -1; /* Invalid */ | |
275 | if (insn.mm_fp0_format.op == mm_fmovn_op) | |
276 | func = fmovn_op; | |
277 | else if (insn.mm_fp0_format.op == mm_fmovz_op) | |
278 | func = fmovz_op; | |
279 | if (func != -1) { | |
280 | mips32_insn.fp0_format.opcode = cop1_op; | |
281 | mips32_insn.fp0_format.fmt = | |
282 | sdps_format[insn.mm_fp0_format.fmt]; | |
283 | mips32_insn.fp0_format.ft = | |
284 | insn.mm_fp0_format.ft; | |
285 | mips32_insn.fp0_format.fs = | |
286 | insn.mm_fp0_format.fs; | |
287 | mips32_insn.fp0_format.fd = | |
288 | insn.mm_fp0_format.fd; | |
289 | mips32_insn.fp0_format.func = func; | |
290 | } else | |
291 | return SIGILL; | |
292 | break; | |
293 | case mm_32f_73_op: /* POOL32FXF */ | |
294 | switch (insn.mm_fp1_format.op) { | |
295 | case mm_movf0_op: | |
296 | case mm_movf1_op: | |
297 | case mm_movt0_op: | |
298 | case mm_movt1_op: | |
299 | if ((insn.mm_fp1_format.op & 0x7f) == | |
300 | mm_movf0_op) | |
301 | op = 0; | |
302 | else | |
303 | op = 1; | |
304 | mips32_insn.r_format.opcode = spec_op; | |
305 | mips32_insn.r_format.rs = insn.mm_fp4_format.fs; | |
306 | mips32_insn.r_format.rt = | |
307 | (insn.mm_fp4_format.cc << 2) + op; | |
308 | mips32_insn.r_format.rd = insn.mm_fp4_format.rt; | |
309 | mips32_insn.r_format.re = 0; | |
310 | mips32_insn.r_format.func = movc_op; | |
311 | break; | |
312 | case mm_fcvtd0_op: | |
313 | case mm_fcvtd1_op: | |
314 | case mm_fcvts0_op: | |
315 | case mm_fcvts1_op: | |
316 | if ((insn.mm_fp1_format.op & 0x7f) == | |
317 | mm_fcvtd0_op) { | |
318 | func = fcvtd_op; | |
319 | fmt = swl_format[insn.mm_fp3_format.fmt]; | |
320 | } else { | |
321 | func = fcvts_op; | |
322 | fmt = dwl_format[insn.mm_fp3_format.fmt]; | |
323 | } | |
324 | mips32_insn.fp0_format.opcode = cop1_op; | |
325 | mips32_insn.fp0_format.fmt = fmt; | |
326 | mips32_insn.fp0_format.ft = 0; | |
327 | mips32_insn.fp0_format.fs = | |
328 | insn.mm_fp3_format.fs; | |
329 | mips32_insn.fp0_format.fd = | |
330 | insn.mm_fp3_format.rt; | |
331 | mips32_insn.fp0_format.func = func; | |
332 | break; | |
333 | case mm_fmov0_op: | |
334 | case mm_fmov1_op: | |
335 | case mm_fabs0_op: | |
336 | case mm_fabs1_op: | |
337 | case mm_fneg0_op: | |
338 | case mm_fneg1_op: | |
339 | if ((insn.mm_fp1_format.op & 0x7f) == | |
340 | mm_fmov0_op) | |
341 | func = fmov_op; | |
342 | else if ((insn.mm_fp1_format.op & 0x7f) == | |
343 | mm_fabs0_op) | |
344 | func = fabs_op; | |
345 | else | |
346 | func = fneg_op; | |
347 | mips32_insn.fp0_format.opcode = cop1_op; | |
348 | mips32_insn.fp0_format.fmt = | |
349 | sdps_format[insn.mm_fp3_format.fmt]; | |
350 | mips32_insn.fp0_format.ft = 0; | |
351 | mips32_insn.fp0_format.fs = | |
352 | insn.mm_fp3_format.fs; | |
353 | mips32_insn.fp0_format.fd = | |
354 | insn.mm_fp3_format.rt; | |
355 | mips32_insn.fp0_format.func = func; | |
356 | break; | |
357 | case mm_ffloorl_op: | |
358 | case mm_ffloorw_op: | |
359 | case mm_fceill_op: | |
360 | case mm_fceilw_op: | |
361 | case mm_ftruncl_op: | |
362 | case mm_ftruncw_op: | |
363 | case mm_froundl_op: | |
364 | case mm_froundw_op: | |
365 | case mm_fcvtl_op: | |
366 | case mm_fcvtw_op: | |
367 | if (insn.mm_fp1_format.op == mm_ffloorl_op) | |
368 | func = ffloorl_op; | |
369 | else if (insn.mm_fp1_format.op == mm_ffloorw_op) | |
370 | func = ffloor_op; | |
371 | else if (insn.mm_fp1_format.op == mm_fceill_op) | |
372 | func = fceill_op; | |
373 | else if (insn.mm_fp1_format.op == mm_fceilw_op) | |
374 | func = fceil_op; | |
375 | else if (insn.mm_fp1_format.op == mm_ftruncl_op) | |
376 | func = ftruncl_op; | |
377 | else if (insn.mm_fp1_format.op == mm_ftruncw_op) | |
378 | func = ftrunc_op; | |
379 | else if (insn.mm_fp1_format.op == mm_froundl_op) | |
380 | func = froundl_op; | |
381 | else if (insn.mm_fp1_format.op == mm_froundw_op) | |
382 | func = fround_op; | |
383 | else if (insn.mm_fp1_format.op == mm_fcvtl_op) | |
384 | func = fcvtl_op; | |
385 | else | |
386 | func = fcvtw_op; | |
387 | mips32_insn.fp0_format.opcode = cop1_op; | |
388 | mips32_insn.fp0_format.fmt = | |
389 | sd_format[insn.mm_fp1_format.fmt]; | |
390 | mips32_insn.fp0_format.ft = 0; | |
391 | mips32_insn.fp0_format.fs = | |
392 | insn.mm_fp1_format.fs; | |
393 | mips32_insn.fp0_format.fd = | |
394 | insn.mm_fp1_format.rt; | |
395 | mips32_insn.fp0_format.func = func; | |
396 | break; | |
397 | case mm_frsqrt_op: | |
398 | case mm_fsqrt_op: | |
399 | case mm_frecip_op: | |
400 | if (insn.mm_fp1_format.op == mm_frsqrt_op) | |
401 | func = frsqrt_op; | |
402 | else if (insn.mm_fp1_format.op == mm_fsqrt_op) | |
403 | func = fsqrt_op; | |
404 | else | |
405 | func = frecip_op; | |
406 | mips32_insn.fp0_format.opcode = cop1_op; | |
407 | mips32_insn.fp0_format.fmt = | |
408 | sdps_format[insn.mm_fp1_format.fmt]; | |
409 | mips32_insn.fp0_format.ft = 0; | |
410 | mips32_insn.fp0_format.fs = | |
411 | insn.mm_fp1_format.fs; | |
412 | mips32_insn.fp0_format.fd = | |
413 | insn.mm_fp1_format.rt; | |
414 | mips32_insn.fp0_format.func = func; | |
415 | break; | |
416 | case mm_mfc1_op: | |
417 | case mm_mtc1_op: | |
418 | case mm_cfc1_op: | |
419 | case mm_ctc1_op: | |
9355e59c SH |
420 | case mm_mfhc1_op: |
421 | case mm_mthc1_op: | |
102cedc3 LY |
422 | if (insn.mm_fp1_format.op == mm_mfc1_op) |
423 | op = mfc_op; | |
424 | else if (insn.mm_fp1_format.op == mm_mtc1_op) | |
425 | op = mtc_op; | |
426 | else if (insn.mm_fp1_format.op == mm_cfc1_op) | |
427 | op = cfc_op; | |
9355e59c | 428 | else if (insn.mm_fp1_format.op == mm_ctc1_op) |
102cedc3 | 429 | op = ctc_op; |
9355e59c SH |
430 | else if (insn.mm_fp1_format.op == mm_mfhc1_op) |
431 | op = mfhc_op; | |
432 | else | |
433 | op = mthc_op; | |
102cedc3 LY |
434 | mips32_insn.fp1_format.opcode = cop1_op; |
435 | mips32_insn.fp1_format.op = op; | |
436 | mips32_insn.fp1_format.rt = | |
437 | insn.mm_fp1_format.rt; | |
438 | mips32_insn.fp1_format.fs = | |
439 | insn.mm_fp1_format.fs; | |
440 | mips32_insn.fp1_format.fd = 0; | |
441 | mips32_insn.fp1_format.func = 0; | |
442 | break; | |
443 | default: | |
444 | return SIGILL; | |
102cedc3 LY |
445 | } |
446 | break; | |
447 | case mm_32f_74_op: /* c.cond.fmt */ | |
448 | mips32_insn.fp0_format.opcode = cop1_op; | |
449 | mips32_insn.fp0_format.fmt = | |
450 | sdps_format[insn.mm_fp4_format.fmt]; | |
451 | mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt; | |
452 | mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs; | |
453 | mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2; | |
454 | mips32_insn.fp0_format.func = | |
455 | insn.mm_fp4_format.cond | MM_MIPS32_COND_FC; | |
456 | break; | |
457 | default: | |
458 | return SIGILL; | |
102cedc3 LY |
459 | } |
460 | break; | |
461 | default: | |
462 | return SIGILL; | |
102cedc3 LY |
463 | } |
464 | ||
465 | *insn_ptr = mips32_insn; | |
466 | return 0; | |
467 | } | |
468 | ||
469 | int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, | |
470 | unsigned long *contpc) | |
471 | { | |
472 | union mips_instruction insn = (union mips_instruction)dec_insn.insn; | |
473 | int bc_false = 0; | |
474 | unsigned int fcr31; | |
475 | unsigned int bit; | |
476 | ||
fe6d2909 DD |
477 | if (!cpu_has_mmips) |
478 | return 0; | |
479 | ||
102cedc3 LY |
480 | switch (insn.mm_i_format.opcode) { |
481 | case mm_pool32a_op: | |
482 | if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) == | |
483 | mm_pool32axf_op) { | |
484 | switch (insn.mm_i_format.simmediate >> | |
485 | MM_POOL32A_MINOR_SHIFT) { | |
486 | case mm_jalr_op: | |
487 | case mm_jalrhb_op: | |
488 | case mm_jalrs_op: | |
489 | case mm_jalrshb_op: | |
490 | if (insn.mm_i_format.rt != 0) /* Not mm_jr */ | |
491 | regs->regs[insn.mm_i_format.rt] = | |
492 | regs->cp0_epc + | |
493 | dec_insn.pc_inc + | |
494 | dec_insn.next_pc_inc; | |
495 | *contpc = regs->regs[insn.mm_i_format.rs]; | |
496 | return 1; | |
102cedc3 LY |
497 | } |
498 | } | |
499 | break; | |
500 | case mm_pool32i_op: | |
501 | switch (insn.mm_i_format.rt) { | |
502 | case mm_bltzals_op: | |
503 | case mm_bltzal_op: | |
504 | regs->regs[31] = regs->cp0_epc + | |
505 | dec_insn.pc_inc + | |
506 | dec_insn.next_pc_inc; | |
507 | /* Fall through */ | |
508 | case mm_bltz_op: | |
509 | if ((long)regs->regs[insn.mm_i_format.rs] < 0) | |
510 | *contpc = regs->cp0_epc + | |
511 | dec_insn.pc_inc + | |
512 | (insn.mm_i_format.simmediate << 1); | |
513 | else | |
514 | *contpc = regs->cp0_epc + | |
515 | dec_insn.pc_inc + | |
516 | dec_insn.next_pc_inc; | |
517 | return 1; | |
102cedc3 LY |
518 | case mm_bgezals_op: |
519 | case mm_bgezal_op: | |
520 | regs->regs[31] = regs->cp0_epc + | |
521 | dec_insn.pc_inc + | |
522 | dec_insn.next_pc_inc; | |
523 | /* Fall through */ | |
524 | case mm_bgez_op: | |
525 | if ((long)regs->regs[insn.mm_i_format.rs] >= 0) | |
526 | *contpc = regs->cp0_epc + | |
527 | dec_insn.pc_inc + | |
528 | (insn.mm_i_format.simmediate << 1); | |
529 | else | |
530 | *contpc = regs->cp0_epc + | |
531 | dec_insn.pc_inc + | |
532 | dec_insn.next_pc_inc; | |
533 | return 1; | |
102cedc3 LY |
534 | case mm_blez_op: |
535 | if ((long)regs->regs[insn.mm_i_format.rs] <= 0) | |
536 | *contpc = regs->cp0_epc + | |
537 | dec_insn.pc_inc + | |
538 | (insn.mm_i_format.simmediate << 1); | |
539 | else | |
540 | *contpc = regs->cp0_epc + | |
541 | dec_insn.pc_inc + | |
542 | dec_insn.next_pc_inc; | |
543 | return 1; | |
102cedc3 LY |
544 | case mm_bgtz_op: |
545 | if ((long)regs->regs[insn.mm_i_format.rs] <= 0) | |
546 | *contpc = regs->cp0_epc + | |
547 | dec_insn.pc_inc + | |
548 | (insn.mm_i_format.simmediate << 1); | |
549 | else | |
550 | *contpc = regs->cp0_epc + | |
551 | dec_insn.pc_inc + | |
552 | dec_insn.next_pc_inc; | |
553 | return 1; | |
102cedc3 LY |
554 | case mm_bc2f_op: |
555 | case mm_bc1f_op: | |
556 | bc_false = 1; | |
557 | /* Fall through */ | |
558 | case mm_bc2t_op: | |
559 | case mm_bc1t_op: | |
560 | preempt_disable(); | |
561 | if (is_fpu_owner()) | |
562 | asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); | |
563 | else | |
564 | fcr31 = current->thread.fpu.fcr31; | |
565 | preempt_enable(); | |
566 | ||
567 | if (bc_false) | |
568 | fcr31 = ~fcr31; | |
569 | ||
570 | bit = (insn.mm_i_format.rs >> 2); | |
571 | bit += (bit != 0); | |
572 | bit += 23; | |
573 | if (fcr31 & (1 << bit)) | |
574 | *contpc = regs->cp0_epc + | |
575 | dec_insn.pc_inc + | |
576 | (insn.mm_i_format.simmediate << 1); | |
577 | else | |
578 | *contpc = regs->cp0_epc + | |
579 | dec_insn.pc_inc + dec_insn.next_pc_inc; | |
580 | return 1; | |
102cedc3 LY |
581 | } |
582 | break; | |
583 | case mm_pool16c_op: | |
584 | switch (insn.mm_i_format.rt) { | |
585 | case mm_jalr16_op: | |
586 | case mm_jalrs16_op: | |
587 | regs->regs[31] = regs->cp0_epc + | |
588 | dec_insn.pc_inc + dec_insn.next_pc_inc; | |
589 | /* Fall through */ | |
590 | case mm_jr16_op: | |
591 | *contpc = regs->regs[insn.mm_i_format.rs]; | |
592 | return 1; | |
102cedc3 LY |
593 | } |
594 | break; | |
595 | case mm_beqz16_op: | |
596 | if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0) | |
597 | *contpc = regs->cp0_epc + | |
598 | dec_insn.pc_inc + | |
599 | (insn.mm_b1_format.simmediate << 1); | |
600 | else | |
601 | *contpc = regs->cp0_epc + | |
602 | dec_insn.pc_inc + dec_insn.next_pc_inc; | |
603 | return 1; | |
102cedc3 LY |
604 | case mm_bnez16_op: |
605 | if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0) | |
606 | *contpc = regs->cp0_epc + | |
607 | dec_insn.pc_inc + | |
608 | (insn.mm_b1_format.simmediate << 1); | |
609 | else | |
610 | *contpc = regs->cp0_epc + | |
611 | dec_insn.pc_inc + dec_insn.next_pc_inc; | |
612 | return 1; | |
102cedc3 LY |
613 | case mm_b16_op: |
614 | *contpc = regs->cp0_epc + dec_insn.pc_inc + | |
615 | (insn.mm_b0_format.simmediate << 1); | |
616 | return 1; | |
102cedc3 LY |
617 | case mm_beq32_op: |
618 | if (regs->regs[insn.mm_i_format.rs] == | |
619 | regs->regs[insn.mm_i_format.rt]) | |
620 | *contpc = regs->cp0_epc + | |
621 | dec_insn.pc_inc + | |
622 | (insn.mm_i_format.simmediate << 1); | |
623 | else | |
624 | *contpc = regs->cp0_epc + | |
625 | dec_insn.pc_inc + | |
626 | dec_insn.next_pc_inc; | |
627 | return 1; | |
102cedc3 LY |
628 | case mm_bne32_op: |
629 | if (regs->regs[insn.mm_i_format.rs] != | |
630 | regs->regs[insn.mm_i_format.rt]) | |
631 | *contpc = regs->cp0_epc + | |
632 | dec_insn.pc_inc + | |
633 | (insn.mm_i_format.simmediate << 1); | |
634 | else | |
635 | *contpc = regs->cp0_epc + | |
636 | dec_insn.pc_inc + dec_insn.next_pc_inc; | |
637 | return 1; | |
102cedc3 LY |
638 | case mm_jalx32_op: |
639 | regs->regs[31] = regs->cp0_epc + | |
640 | dec_insn.pc_inc + dec_insn.next_pc_inc; | |
641 | *contpc = regs->cp0_epc + dec_insn.pc_inc; | |
642 | *contpc >>= 28; | |
643 | *contpc <<= 28; | |
644 | *contpc |= (insn.j_format.target << 2); | |
645 | return 1; | |
102cedc3 LY |
646 | case mm_jals32_op: |
647 | case mm_jal32_op: | |
648 | regs->regs[31] = regs->cp0_epc + | |
649 | dec_insn.pc_inc + dec_insn.next_pc_inc; | |
650 | /* Fall through */ | |
651 | case mm_j32_op: | |
652 | *contpc = regs->cp0_epc + dec_insn.pc_inc; | |
653 | *contpc >>= 27; | |
654 | *contpc <<= 27; | |
655 | *contpc |= (insn.j_format.target << 1); | |
656 | set_isa16_mode(*contpc); | |
657 | return 1; | |
102cedc3 LY |
658 | } |
659 | return 0; | |
660 | } | |
1da177e4 LT |
661 | |
662 | /* | |
663 | * Redundant with logic already in kernel/branch.c, | |
664 | * embedded in compute_return_epc. At some point, | |
665 | * a single subroutine should be used across both | |
666 | * modules. | |
667 | */ | |
102cedc3 LY |
668 | static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, |
669 | unsigned long *contpc) | |
1da177e4 | 670 | { |
102cedc3 LY |
671 | union mips_instruction insn = (union mips_instruction)dec_insn.insn; |
672 | unsigned int fcr31; | |
673 | unsigned int bit = 0; | |
674 | ||
675 | switch (insn.i_format.opcode) { | |
1da177e4 | 676 | case spec_op: |
102cedc3 | 677 | switch (insn.r_format.func) { |
1da177e4 | 678 | case jalr_op: |
102cedc3 LY |
679 | regs->regs[insn.r_format.rd] = |
680 | regs->cp0_epc + dec_insn.pc_inc + | |
681 | dec_insn.next_pc_inc; | |
682 | /* Fall through */ | |
1da177e4 | 683 | case jr_op: |
102cedc3 | 684 | *contpc = regs->regs[insn.r_format.rs]; |
1da177e4 LT |
685 | return 1; |
686 | } | |
687 | break; | |
1da177e4 | 688 | case bcond_op: |
102cedc3 LY |
689 | switch (insn.i_format.rt) { |
690 | case bltzal_op: | |
691 | case bltzall_op: | |
692 | regs->regs[31] = regs->cp0_epc + | |
693 | dec_insn.pc_inc + | |
694 | dec_insn.next_pc_inc; | |
695 | /* Fall through */ | |
1da177e4 | 696 | case bltz_op: |
1da177e4 | 697 | case bltzl_op: |
102cedc3 LY |
698 | if ((long)regs->regs[insn.i_format.rs] < 0) |
699 | *contpc = regs->cp0_epc + | |
700 | dec_insn.pc_inc + | |
701 | (insn.i_format.simmediate << 2); | |
702 | else | |
703 | *contpc = regs->cp0_epc + | |
704 | dec_insn.pc_inc + | |
705 | dec_insn.next_pc_inc; | |
706 | return 1; | |
1da177e4 | 707 | case bgezal_op: |
1da177e4 | 708 | case bgezall_op: |
102cedc3 LY |
709 | regs->regs[31] = regs->cp0_epc + |
710 | dec_insn.pc_inc + | |
711 | dec_insn.next_pc_inc; | |
712 | /* Fall through */ | |
713 | case bgez_op: | |
714 | case bgezl_op: | |
715 | if ((long)regs->regs[insn.i_format.rs] >= 0) | |
716 | *contpc = regs->cp0_epc + | |
717 | dec_insn.pc_inc + | |
718 | (insn.i_format.simmediate << 2); | |
719 | else | |
720 | *contpc = regs->cp0_epc + | |
721 | dec_insn.pc_inc + | |
722 | dec_insn.next_pc_inc; | |
1da177e4 LT |
723 | return 1; |
724 | } | |
725 | break; | |
1da177e4 | 726 | case jalx_op: |
102cedc3 LY |
727 | set_isa16_mode(bit); |
728 | case jal_op: | |
729 | regs->regs[31] = regs->cp0_epc + | |
730 | dec_insn.pc_inc + | |
731 | dec_insn.next_pc_inc; | |
732 | /* Fall through */ | |
733 | case j_op: | |
734 | *contpc = regs->cp0_epc + dec_insn.pc_inc; | |
735 | *contpc >>= 28; | |
736 | *contpc <<= 28; | |
737 | *contpc |= (insn.j_format.target << 2); | |
738 | /* Set microMIPS mode bit: XOR for jalx. */ | |
739 | *contpc ^= bit; | |
740 | return 1; | |
1da177e4 | 741 | case beq_op: |
1da177e4 | 742 | case beql_op: |
102cedc3 LY |
743 | if (regs->regs[insn.i_format.rs] == |
744 | regs->regs[insn.i_format.rt]) | |
745 | *contpc = regs->cp0_epc + | |
746 | dec_insn.pc_inc + | |
747 | (insn.i_format.simmediate << 2); | |
748 | else | |
749 | *contpc = regs->cp0_epc + | |
750 | dec_insn.pc_inc + | |
751 | dec_insn.next_pc_inc; | |
752 | return 1; | |
102cedc3 | 753 | case bne_op: |
1da177e4 | 754 | case bnel_op: |
102cedc3 LY |
755 | if (regs->regs[insn.i_format.rs] != |
756 | regs->regs[insn.i_format.rt]) | |
757 | *contpc = regs->cp0_epc + | |
758 | dec_insn.pc_inc + | |
759 | (insn.i_format.simmediate << 2); | |
760 | else | |
761 | *contpc = regs->cp0_epc + | |
762 | dec_insn.pc_inc + | |
763 | dec_insn.next_pc_inc; | |
764 | return 1; | |
102cedc3 | 765 | case blez_op: |
1da177e4 | 766 | case blezl_op: |
102cedc3 LY |
767 | if ((long)regs->regs[insn.i_format.rs] <= 0) |
768 | *contpc = regs->cp0_epc + | |
769 | dec_insn.pc_inc + | |
770 | (insn.i_format.simmediate << 2); | |
771 | else | |
772 | *contpc = regs->cp0_epc + | |
773 | dec_insn.pc_inc + | |
774 | dec_insn.next_pc_inc; | |
775 | return 1; | |
102cedc3 | 776 | case bgtz_op: |
1da177e4 | 777 | case bgtzl_op: |
102cedc3 LY |
778 | if ((long)regs->regs[insn.i_format.rs] > 0) |
779 | *contpc = regs->cp0_epc + | |
780 | dec_insn.pc_inc + | |
781 | (insn.i_format.simmediate << 2); | |
782 | else | |
783 | *contpc = regs->cp0_epc + | |
784 | dec_insn.pc_inc + | |
785 | dec_insn.next_pc_inc; | |
1da177e4 | 786 | return 1; |
c26d4219 DD |
787 | #ifdef CONFIG_CPU_CAVIUM_OCTEON |
788 | case lwc2_op: /* This is bbit0 on Octeon */ | |
789 | if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0) | |
790 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
791 | else | |
792 | *contpc = regs->cp0_epc + 8; | |
793 | return 1; | |
794 | case ldc2_op: /* This is bbit032 on Octeon */ | |
795 | if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0) | |
796 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
797 | else | |
798 | *contpc = regs->cp0_epc + 8; | |
799 | return 1; | |
800 | case swc2_op: /* This is bbit1 on Octeon */ | |
801 | if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) | |
802 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
803 | else | |
804 | *contpc = regs->cp0_epc + 8; | |
805 | return 1; | |
806 | case sdc2_op: /* This is bbit132 on Octeon */ | |
807 | if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) | |
808 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
809 | else | |
810 | *contpc = regs->cp0_epc + 8; | |
811 | return 1; | |
812 | #endif | |
1da177e4 LT |
813 | case cop0_op: |
814 | case cop1_op: | |
815 | case cop2_op: | |
816 | case cop1x_op: | |
102cedc3 LY |
817 | if (insn.i_format.rs == bc_op) { |
818 | preempt_disable(); | |
819 | if (is_fpu_owner()) | |
820 | asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); | |
821 | else | |
822 | fcr31 = current->thread.fpu.fcr31; | |
823 | preempt_enable(); | |
824 | ||
825 | bit = (insn.i_format.rt >> 2); | |
826 | bit += (bit != 0); | |
827 | bit += 23; | |
828 | switch (insn.i_format.rt & 3) { | |
829 | case 0: /* bc1f */ | |
830 | case 2: /* bc1fl */ | |
831 | if (~fcr31 & (1 << bit)) | |
832 | *contpc = regs->cp0_epc + | |
833 | dec_insn.pc_inc + | |
834 | (insn.i_format.simmediate << 2); | |
835 | else | |
836 | *contpc = regs->cp0_epc + | |
837 | dec_insn.pc_inc + | |
838 | dec_insn.next_pc_inc; | |
839 | return 1; | |
102cedc3 LY |
840 | case 1: /* bc1t */ |
841 | case 3: /* bc1tl */ | |
842 | if (fcr31 & (1 << bit)) | |
843 | *contpc = regs->cp0_epc + | |
844 | dec_insn.pc_inc + | |
845 | (insn.i_format.simmediate << 2); | |
846 | else | |
847 | *contpc = regs->cp0_epc + | |
848 | dec_insn.pc_inc + | |
849 | dec_insn.next_pc_inc; | |
850 | return 1; | |
102cedc3 LY |
851 | } |
852 | } | |
1da177e4 LT |
853 | break; |
854 | } | |
1da177e4 LT |
855 | return 0; |
856 | } | |
857 | ||
858 | /* | |
859 | * In the Linux kernel, we support selection of FPR format on the | |
70342287 | 860 | * basis of the Status.FR bit. If an FPU is not present, the FR bit |
da0bac33 | 861 | * is hardwired to zero, which would imply a 32-bit FPU even for |
597ce172 | 862 | * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS. |
51d943f0 RB |
863 | * FPU emu is slow and bulky and optimizing this function offers fairly |
864 | * sizeable benefits so we try to be clever and make this function return | |
865 | * a constant whenever possible, that is on 64-bit kernels without O32 | |
597ce172 | 866 | * compatibility enabled and on 32-bit without 64-bit FPU support. |
1da177e4 | 867 | */ |
da0bac33 DD |
868 | static inline int cop1_64bit(struct pt_regs *xcp) |
869 | { | |
51d943f0 RB |
870 | #if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32) |
871 | return 1; | |
597ce172 | 872 | #elif defined(CONFIG_32BIT) && !defined(CONFIG_MIPS_O32_FP64_SUPPORT) |
da0bac33 | 873 | return 0; |
597ce172 PB |
874 | #else |
875 | return !test_thread_flag(TIF_32BIT_FPREGS); | |
1da177e4 | 876 | #endif |
da0bac33 DD |
877 | } |
878 | ||
bbd426f5 PB |
879 | #define SIFROMREG(si, x) do { \ |
880 | if (cop1_64bit(xcp)) \ | |
881 | (si) = get_fpr32(&ctx->fpr[x], 0); \ | |
882 | else \ | |
883 | (si) = get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \ | |
884 | } while (0) | |
1da177e4 | 885 | |
bbd426f5 PB |
886 | #define SITOREG(si, x) do { \ |
887 | if (cop1_64bit(xcp)) \ | |
888 | set_fpr32(&ctx->fpr[x], 0, si); \ | |
889 | else \ | |
890 | set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \ | |
891 | } while (0) | |
1da177e4 | 892 | |
bbd426f5 PB |
893 | #define SIFROMHREG(si, x) ((si) = get_fpr32(&ctx->fpr[x], 1)) |
894 | #define SITOHREG(si, x) set_fpr32(&ctx->fpr[x], 1, si) | |
1ac94400 | 895 | |
bbd426f5 PB |
896 | #define DIFROMREG(di, x) \ |
897 | ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0)) | |
898 | ||
899 | #define DITOREG(di, x) \ | |
900 | set_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0, di) | |
1da177e4 | 901 | |
21a151d8 RB |
902 | #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x) |
903 | #define SPTOREG(sp, x) SITOREG((sp).bits, x) | |
904 | #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x) | |
905 | #define DPTOREG(dp, x) DITOREG((dp).bits, x) | |
1da177e4 LT |
906 | |
907 | /* | |
908 | * Emulate the single floating point instruction pointed at by EPC. | |
909 | * Two instructions if the instruction is in a branch delay slot. | |
910 | */ | |
911 | ||
515b029d | 912 | static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
102cedc3 | 913 | struct mm_decoded_insn dec_insn, void *__user *fault_addr) |
1da177e4 LT |
914 | { |
915 | mips_instruction ir; | |
102cedc3 | 916 | unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; |
1da177e4 | 917 | unsigned int cond; |
102cedc3 | 918 | int pc_inc; |
1da177e4 LT |
919 | |
920 | /* XXX NEC Vr54xx bug workaround */ | |
102cedc3 LY |
921 | if (xcp->cp0_cause & CAUSEF_BD) { |
922 | if (dec_insn.micro_mips_mode) { | |
923 | if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) | |
924 | xcp->cp0_cause &= ~CAUSEF_BD; | |
925 | } else { | |
926 | if (!isBranchInstr(xcp, dec_insn, &contpc)) | |
927 | xcp->cp0_cause &= ~CAUSEF_BD; | |
928 | } | |
929 | } | |
1da177e4 LT |
930 | |
931 | if (xcp->cp0_cause & CAUSEF_BD) { | |
932 | /* | |
933 | * The instruction to be emulated is in a branch delay slot | |
70342287 | 934 | * which means that we have to emulate the branch instruction |
1da177e4 LT |
935 | * BEFORE we do the cop1 instruction. |
936 | * | |
937 | * This branch could be a COP1 branch, but in that case we | |
938 | * would have had a trap for that instruction, and would not | |
939 | * come through this route. | |
940 | * | |
941 | * Linux MIPS branch emulator operates on context, updating the | |
942 | * cp0_epc. | |
943 | */ | |
102cedc3 LY |
944 | ir = dec_insn.next_insn; /* process delay slot instr */ |
945 | pc_inc = dec_insn.next_pc_inc; | |
946 | } else { | |
947 | ir = dec_insn.insn; /* process current instr */ | |
948 | pc_inc = dec_insn.pc_inc; | |
949 | } | |
1da177e4 | 950 | |
102cedc3 LY |
951 | /* |
952 | * Since microMIPS FPU instructios are a subset of MIPS32 FPU | |
953 | * instructions, we want to convert microMIPS FPU instructions | |
954 | * into MIPS32 instructions so that we could reuse all of the | |
955 | * FPU emulation code. | |
956 | * | |
957 | * NOTE: We cannot do this for branch instructions since they | |
958 | * are not a subset. Example: Cannot emulate a 16-bit | |
959 | * aligned target address with a MIPS32 instruction. | |
960 | */ | |
961 | if (dec_insn.micro_mips_mode) { | |
962 | /* | |
963 | * If next instruction is a 16-bit instruction, then it | |
964 | * it cannot be a FPU instruction. This could happen | |
965 | * since we can be called for non-FPU instructions. | |
966 | */ | |
967 | if ((pc_inc == 2) || | |
968 | (microMIPS32_to_MIPS32((union mips_instruction *)&ir) | |
969 | == SIGILL)) | |
1da177e4 | 970 | return SIGILL; |
1da177e4 LT |
971 | } |
972 | ||
973 | emul: | |
a8b0ca17 | 974 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0); |
b6ee75ed | 975 | MIPS_FPU_EMU_INC_STATS(emulated); |
1da177e4 | 976 | switch (MIPSInst_OPCODE(ir)) { |
1da177e4 | 977 | case ldc1_op:{ |
3fccc015 | 978 | u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + |
1da177e4 LT |
979 | MIPSInst_SIMM(ir)); |
980 | u64 val; | |
981 | ||
b6ee75ed | 982 | MIPS_FPU_EMU_INC_STATS(loads); |
515b029d DD |
983 | |
984 | if (!access_ok(VERIFY_READ, va, sizeof(u64))) { | |
b6ee75ed | 985 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 986 | *fault_addr = va; |
1da177e4 LT |
987 | return SIGBUS; |
988 | } | |
515b029d DD |
989 | if (__get_user(val, va)) { |
990 | MIPS_FPU_EMU_INC_STATS(errors); | |
991 | *fault_addr = va; | |
992 | return SIGSEGV; | |
993 | } | |
1da177e4 LT |
994 | DITOREG(val, MIPSInst_RT(ir)); |
995 | break; | |
996 | } | |
997 | ||
998 | case sdc1_op:{ | |
3fccc015 | 999 | u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + |
1da177e4 LT |
1000 | MIPSInst_SIMM(ir)); |
1001 | u64 val; | |
1002 | ||
b6ee75ed | 1003 | MIPS_FPU_EMU_INC_STATS(stores); |
1da177e4 | 1004 | DIFROMREG(val, MIPSInst_RT(ir)); |
515b029d | 1005 | if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { |
b6ee75ed | 1006 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1007 | *fault_addr = va; |
1da177e4 LT |
1008 | return SIGBUS; |
1009 | } | |
515b029d DD |
1010 | if (__put_user(val, va)) { |
1011 | MIPS_FPU_EMU_INC_STATS(errors); | |
1012 | *fault_addr = va; | |
1013 | return SIGSEGV; | |
1014 | } | |
1da177e4 LT |
1015 | break; |
1016 | } | |
1da177e4 LT |
1017 | |
1018 | case lwc1_op:{ | |
3fccc015 | 1019 | u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + |
1da177e4 LT |
1020 | MIPSInst_SIMM(ir)); |
1021 | u32 val; | |
1022 | ||
b6ee75ed | 1023 | MIPS_FPU_EMU_INC_STATS(loads); |
515b029d | 1024 | if (!access_ok(VERIFY_READ, va, sizeof(u32))) { |
b6ee75ed | 1025 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1026 | *fault_addr = va; |
1da177e4 LT |
1027 | return SIGBUS; |
1028 | } | |
515b029d DD |
1029 | if (__get_user(val, va)) { |
1030 | MIPS_FPU_EMU_INC_STATS(errors); | |
1031 | *fault_addr = va; | |
1032 | return SIGSEGV; | |
1033 | } | |
1da177e4 LT |
1034 | SITOREG(val, MIPSInst_RT(ir)); |
1035 | break; | |
1036 | } | |
1037 | ||
1038 | case swc1_op:{ | |
3fccc015 | 1039 | u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + |
1da177e4 LT |
1040 | MIPSInst_SIMM(ir)); |
1041 | u32 val; | |
1042 | ||
b6ee75ed | 1043 | MIPS_FPU_EMU_INC_STATS(stores); |
1da177e4 | 1044 | SIFROMREG(val, MIPSInst_RT(ir)); |
515b029d | 1045 | if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { |
b6ee75ed | 1046 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1047 | *fault_addr = va; |
1da177e4 LT |
1048 | return SIGBUS; |
1049 | } | |
515b029d DD |
1050 | if (__put_user(val, va)) { |
1051 | MIPS_FPU_EMU_INC_STATS(errors); | |
1052 | *fault_addr = va; | |
1053 | return SIGSEGV; | |
1054 | } | |
1da177e4 LT |
1055 | break; |
1056 | } | |
1057 | ||
1058 | case cop1_op: | |
1059 | switch (MIPSInst_RS(ir)) { | |
1060 | ||
4b724efd | 1061 | #if defined(__mips64) |
1da177e4 LT |
1062 | case dmfc_op: |
1063 | /* copregister fs -> gpr[rt] */ | |
1064 | if (MIPSInst_RT(ir) != 0) { | |
1065 | DIFROMREG(xcp->regs[MIPSInst_RT(ir)], | |
1066 | MIPSInst_RD(ir)); | |
1067 | } | |
1068 | break; | |
1069 | ||
1070 | case dmtc_op: | |
1071 | /* copregister fs <- rt */ | |
1072 | DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); | |
1073 | break; | |
1074 | #endif | |
1075 | ||
1ac94400 LY |
1076 | case mfhc_op: |
1077 | if (!cpu_has_mips_r2) | |
1078 | goto sigill; | |
1079 | ||
1080 | /* copregister rd -> gpr[rt] */ | |
1081 | if (MIPSInst_RT(ir) != 0) { | |
1082 | SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], | |
1083 | MIPSInst_RD(ir)); | |
1084 | } | |
1085 | break; | |
1086 | ||
1087 | case mthc_op: | |
1088 | if (!cpu_has_mips_r2) | |
1089 | goto sigill; | |
1090 | ||
1091 | /* copregister rd <- gpr[rt] */ | |
1092 | SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); | |
1093 | break; | |
1094 | ||
1da177e4 LT |
1095 | case mfc_op: |
1096 | /* copregister rd -> gpr[rt] */ | |
1da177e4 LT |
1097 | if (MIPSInst_RT(ir) != 0) { |
1098 | SIFROMREG(xcp->regs[MIPSInst_RT(ir)], | |
1099 | MIPSInst_RD(ir)); | |
1100 | } | |
1101 | break; | |
1102 | ||
1103 | case mtc_op: | |
1104 | /* copregister rd <- rt */ | |
1da177e4 LT |
1105 | SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); |
1106 | break; | |
1107 | ||
1108 | case cfc_op:{ | |
1109 | /* cop control register rd -> gpr[rt] */ | |
1110 | u32 value; | |
1111 | ||
1da177e4 LT |
1112 | if (MIPSInst_RD(ir) == FPCREG_CSR) { |
1113 | value = ctx->fcr31; | |
3f135530 SM |
1114 | value = (value & ~FPU_CSR_RM) | |
1115 | mips_rm[modeindex(value)]; | |
1da177e4 LT |
1116 | #ifdef CSRTRACE |
1117 | printk("%p gpr[%d]<-csr=%08x\n", | |
333d1f67 | 1118 | (void *) (xcp->cp0_epc), |
1da177e4 LT |
1119 | MIPSInst_RT(ir), value); |
1120 | #endif | |
1121 | } | |
1122 | else if (MIPSInst_RD(ir) == FPCREG_RID) | |
1123 | value = 0; | |
1124 | else | |
1125 | value = 0; | |
1126 | if (MIPSInst_RT(ir)) | |
1127 | xcp->regs[MIPSInst_RT(ir)] = value; | |
1128 | break; | |
1129 | } | |
1130 | ||
1131 | case ctc_op:{ | |
1132 | /* copregister rd <- rt */ | |
1133 | u32 value; | |
1134 | ||
1135 | if (MIPSInst_RT(ir) == 0) | |
1136 | value = 0; | |
1137 | else | |
1138 | value = xcp->regs[MIPSInst_RT(ir)]; | |
1139 | ||
1140 | /* we only have one writable control reg | |
1141 | */ | |
1142 | if (MIPSInst_RD(ir) == FPCREG_CSR) { | |
1143 | #ifdef CSRTRACE | |
1144 | printk("%p gpr[%d]->csr=%08x\n", | |
333d1f67 | 1145 | (void *) (xcp->cp0_epc), |
1da177e4 LT |
1146 | MIPSInst_RT(ir), value); |
1147 | #endif | |
95e8f634 SM |
1148 | |
1149 | /* | |
1150 | * Don't write reserved bits, | |
1151 | * and convert to ieee library modes | |
1152 | */ | |
1153 | ctx->fcr31 = (value & | |
1154 | ~(FPU_CSR_RSVD | FPU_CSR_RM)) | | |
1155 | ieee_rm[modeindex(value)]; | |
1da177e4 LT |
1156 | } |
1157 | if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { | |
1158 | return SIGFPE; | |
1159 | } | |
1160 | break; | |
1161 | } | |
1162 | ||
1163 | case bc_op:{ | |
1164 | int likely = 0; | |
1165 | ||
1166 | if (xcp->cp0_cause & CAUSEF_BD) | |
1167 | return SIGILL; | |
1168 | ||
1169 | #if __mips >= 4 | |
1170 | cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2]; | |
1171 | #else | |
1172 | cond = ctx->fcr31 & FPU_CSR_COND; | |
1173 | #endif | |
1174 | switch (MIPSInst_RT(ir) & 3) { | |
1175 | case bcfl_op: | |
1176 | likely = 1; | |
1177 | case bcf_op: | |
1178 | cond = !cond; | |
1179 | break; | |
1180 | case bctl_op: | |
1181 | likely = 1; | |
1182 | case bct_op: | |
1183 | break; | |
1184 | default: | |
1185 | /* thats an illegal instruction */ | |
1186 | return SIGILL; | |
1187 | } | |
1188 | ||
1189 | xcp->cp0_cause |= CAUSEF_BD; | |
1190 | if (cond) { | |
1191 | /* branch taken: emulate dslot | |
1192 | * instruction | |
1193 | */ | |
102cedc3 LY |
1194 | xcp->cp0_epc += dec_insn.pc_inc; |
1195 | ||
1196 | contpc = MIPSInst_SIMM(ir); | |
1197 | ir = dec_insn.next_insn; | |
1198 | if (dec_insn.micro_mips_mode) { | |
1199 | contpc = (xcp->cp0_epc + (contpc << 1)); | |
1200 | ||
1201 | /* If 16-bit instruction, not FPU. */ | |
1202 | if ((dec_insn.next_pc_inc == 2) || | |
1203 | (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) { | |
1204 | ||
1205 | /* | |
1206 | * Since this instruction will | |
1207 | * be put on the stack with | |
1208 | * 32-bit words, get around | |
1209 | * this problem by putting a | |
1210 | * NOP16 as the second one. | |
1211 | */ | |
1212 | if (dec_insn.next_pc_inc == 2) | |
1213 | ir = (ir & (~0xffff)) | MM_NOP16; | |
1214 | ||
1215 | /* | |
1216 | * Single step the non-CP1 | |
1217 | * instruction in the dslot. | |
1218 | */ | |
1219 | return mips_dsemul(xcp, ir, contpc); | |
1220 | } | |
1221 | } else | |
1222 | contpc = (xcp->cp0_epc + (contpc << 2)); | |
1da177e4 LT |
1223 | |
1224 | switch (MIPSInst_OPCODE(ir)) { | |
1225 | case lwc1_op: | |
1226 | case swc1_op: | |
4b724efd | 1227 | #if (__mips >= 2 || defined(__mips64)) |
1da177e4 LT |
1228 | case ldc1_op: |
1229 | case sdc1_op: | |
1230 | #endif | |
1231 | case cop1_op: | |
1232 | #if __mips >= 4 && __mips != 32 | |
1233 | case cop1x_op: | |
1234 | #endif | |
1235 | /* its one of ours */ | |
1236 | goto emul; | |
1237 | #if __mips >= 4 | |
1238 | case spec_op: | |
1239 | if (MIPSInst_FUNC(ir) == movc_op) | |
1240 | goto emul; | |
1241 | break; | |
1242 | #endif | |
1243 | } | |
1244 | ||
1245 | /* | |
1246 | * Single step the non-cp1 | |
1247 | * instruction in the dslot | |
1248 | */ | |
e70dfc10 | 1249 | return mips_dsemul(xcp, ir, contpc); |
1da177e4 LT |
1250 | } |
1251 | else { | |
1252 | /* branch not taken */ | |
1253 | if (likely) { | |
1254 | /* | |
1255 | * branch likely nullifies | |
1256 | * dslot if not taken | |
1257 | */ | |
102cedc3 LY |
1258 | xcp->cp0_epc += dec_insn.pc_inc; |
1259 | contpc += dec_insn.pc_inc; | |
1da177e4 LT |
1260 | /* |
1261 | * else continue & execute | |
1262 | * dslot as normal insn | |
1263 | */ | |
1264 | } | |
1265 | } | |
1266 | break; | |
1267 | } | |
1268 | ||
1269 | default: | |
1270 | if (!(MIPSInst_RS(ir) & 0x10)) | |
1271 | return SIGILL; | |
1272 | { | |
1273 | int sig; | |
1274 | ||
1275 | /* a real fpu computation instruction */ | |
1276 | if ((sig = fpu_emu(xcp, ctx, ir))) | |
1277 | return sig; | |
1278 | } | |
1279 | } | |
1280 | break; | |
1281 | ||
1282 | #if __mips >= 4 && __mips != 32 | |
1283 | case cop1x_op:{ | |
515b029d DD |
1284 | int sig = fpux_emu(xcp, ctx, ir, fault_addr); |
1285 | if (sig) | |
1da177e4 LT |
1286 | return sig; |
1287 | break; | |
1288 | } | |
1289 | #endif | |
1290 | ||
1291 | #if __mips >= 4 | |
1292 | case spec_op: | |
1293 | if (MIPSInst_FUNC(ir) != movc_op) | |
1294 | return SIGILL; | |
1295 | cond = fpucondbit[MIPSInst_RT(ir) >> 2]; | |
1296 | if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) | |
1297 | xcp->regs[MIPSInst_RD(ir)] = | |
1298 | xcp->regs[MIPSInst_RS(ir)]; | |
1299 | break; | |
1300 | #endif | |
1301 | ||
1302 | default: | |
1ac94400 | 1303 | sigill: |
1da177e4 LT |
1304 | return SIGILL; |
1305 | } | |
1306 | ||
1307 | /* we did it !! */ | |
e70dfc10 | 1308 | xcp->cp0_epc = contpc; |
1da177e4 | 1309 | xcp->cp0_cause &= ~CAUSEF_BD; |
333d1f67 | 1310 | |
1da177e4 LT |
1311 | return 0; |
1312 | } | |
1313 | ||
1314 | /* | |
1315 | * Conversion table from MIPS compare ops 48-63 | |
1316 | * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig); | |
1317 | */ | |
1318 | static const unsigned char cmptab[8] = { | |
1319 | 0, /* cmp_0 (sig) cmp_sf */ | |
1320 | IEEE754_CUN, /* cmp_un (sig) cmp_ngle */ | |
1321 | IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */ | |
1322 | IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */ | |
1323 | IEEE754_CLT, /* cmp_olt (sig) cmp_lt */ | |
1324 | IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */ | |
1325 | IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */ | |
1326 | IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */ | |
1327 | }; | |
1328 | ||
1329 | ||
1330 | #if __mips >= 4 && __mips != 32 | |
1331 | ||
1332 | /* | |
1333 | * Additional MIPS4 instructions | |
1334 | */ | |
1335 | ||
1336 | #define DEF3OP(name, p, f1, f2, f3) \ | |
49a89efb | 1337 | static ieee754##p fpemu_##p##_##name(ieee754##p r, ieee754##p s, \ |
1da177e4 LT |
1338 | ieee754##p t) \ |
1339 | { \ | |
cd21dfcf | 1340 | struct _ieee754_csr ieee754_csr_save; \ |
49a89efb | 1341 | s = f1(s, t); \ |
1da177e4 | 1342 | ieee754_csr_save = ieee754_csr; \ |
49a89efb | 1343 | s = f2(s, r); \ |
1da177e4 LT |
1344 | ieee754_csr_save.cx |= ieee754_csr.cx; \ |
1345 | ieee754_csr_save.sx |= ieee754_csr.sx; \ | |
49a89efb | 1346 | s = f3(s); \ |
1da177e4 LT |
1347 | ieee754_csr.cx |= ieee754_csr_save.cx; \ |
1348 | ieee754_csr.sx |= ieee754_csr_save.sx; \ | |
1349 | return s; \ | |
1350 | } | |
1351 | ||
1352 | static ieee754dp fpemu_dp_recip(ieee754dp d) | |
1353 | { | |
1354 | return ieee754dp_div(ieee754dp_one(0), d); | |
1355 | } | |
1356 | ||
1357 | static ieee754dp fpemu_dp_rsqrt(ieee754dp d) | |
1358 | { | |
1359 | return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d)); | |
1360 | } | |
1361 | ||
1362 | static ieee754sp fpemu_sp_recip(ieee754sp s) | |
1363 | { | |
1364 | return ieee754sp_div(ieee754sp_one(0), s); | |
1365 | } | |
1366 | ||
1367 | static ieee754sp fpemu_sp_rsqrt(ieee754sp s) | |
1368 | { | |
1369 | return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); | |
1370 | } | |
1371 | ||
21a151d8 RB |
1372 | DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, ); |
1373 | DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, ); | |
1da177e4 LT |
1374 | DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); |
1375 | DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); | |
21a151d8 RB |
1376 | DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, ); |
1377 | DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, ); | |
1da177e4 LT |
1378 | DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); |
1379 | DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); | |
1380 | ||
eae89076 | 1381 | static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
515b029d | 1382 | mips_instruction ir, void *__user *fault_addr) |
1da177e4 LT |
1383 | { |
1384 | unsigned rcsr = 0; /* resulting csr */ | |
1385 | ||
b6ee75ed | 1386 | MIPS_FPU_EMU_INC_STATS(cp1xops); |
1da177e4 LT |
1387 | |
1388 | switch (MIPSInst_FMA_FFMT(ir)) { | |
1389 | case s_fmt:{ /* 0 */ | |
1390 | ||
1391 | ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp); | |
1392 | ieee754sp fd, fr, fs, ft; | |
3fccc015 | 1393 | u32 __user *va; |
1da177e4 LT |
1394 | u32 val; |
1395 | ||
1396 | switch (MIPSInst_FUNC(ir)) { | |
1397 | case lwxc1_op: | |
3fccc015 | 1398 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1399 | xcp->regs[MIPSInst_FT(ir)]); |
1400 | ||
b6ee75ed | 1401 | MIPS_FPU_EMU_INC_STATS(loads); |
515b029d | 1402 | if (!access_ok(VERIFY_READ, va, sizeof(u32))) { |
b6ee75ed | 1403 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1404 | *fault_addr = va; |
1da177e4 LT |
1405 | return SIGBUS; |
1406 | } | |
515b029d DD |
1407 | if (__get_user(val, va)) { |
1408 | MIPS_FPU_EMU_INC_STATS(errors); | |
1409 | *fault_addr = va; | |
1410 | return SIGSEGV; | |
1411 | } | |
1da177e4 LT |
1412 | SITOREG(val, MIPSInst_FD(ir)); |
1413 | break; | |
1414 | ||
1415 | case swxc1_op: | |
3fccc015 | 1416 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1417 | xcp->regs[MIPSInst_FT(ir)]); |
1418 | ||
b6ee75ed | 1419 | MIPS_FPU_EMU_INC_STATS(stores); |
1da177e4 LT |
1420 | |
1421 | SIFROMREG(val, MIPSInst_FS(ir)); | |
515b029d | 1422 | if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { |
b6ee75ed | 1423 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1424 | *fault_addr = va; |
1da177e4 LT |
1425 | return SIGBUS; |
1426 | } | |
515b029d DD |
1427 | if (put_user(val, va)) { |
1428 | MIPS_FPU_EMU_INC_STATS(errors); | |
1429 | *fault_addr = va; | |
1430 | return SIGSEGV; | |
1431 | } | |
1da177e4 LT |
1432 | break; |
1433 | ||
1434 | case madd_s_op: | |
1435 | handler = fpemu_sp_madd; | |
1436 | goto scoptop; | |
1437 | case msub_s_op: | |
1438 | handler = fpemu_sp_msub; | |
1439 | goto scoptop; | |
1440 | case nmadd_s_op: | |
1441 | handler = fpemu_sp_nmadd; | |
1442 | goto scoptop; | |
1443 | case nmsub_s_op: | |
1444 | handler = fpemu_sp_nmsub; | |
1445 | goto scoptop; | |
1446 | ||
1447 | scoptop: | |
1448 | SPFROMREG(fr, MIPSInst_FR(ir)); | |
1449 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1450 | SPFROMREG(ft, MIPSInst_FT(ir)); | |
1451 | fd = (*handler) (fr, fs, ft); | |
1452 | SPTOREG(fd, MIPSInst_FD(ir)); | |
1453 | ||
1454 | copcsr: | |
1455 | if (ieee754_cxtest(IEEE754_INEXACT)) | |
1456 | rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; | |
1457 | if (ieee754_cxtest(IEEE754_UNDERFLOW)) | |
1458 | rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; | |
1459 | if (ieee754_cxtest(IEEE754_OVERFLOW)) | |
1460 | rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; | |
1461 | if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) | |
1462 | rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; | |
1463 | ||
1464 | ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; | |
1da177e4 LT |
1465 | if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { |
1466 | /*printk ("SIGFPE: fpu csr = %08x\n", | |
1467 | ctx->fcr31); */ | |
1468 | return SIGFPE; | |
1469 | } | |
1470 | ||
1471 | break; | |
1472 | ||
1473 | default: | |
1474 | return SIGILL; | |
1475 | } | |
1476 | break; | |
1477 | } | |
1478 | ||
1da177e4 LT |
1479 | case d_fmt:{ /* 1 */ |
1480 | ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp); | |
1481 | ieee754dp fd, fr, fs, ft; | |
3fccc015 | 1482 | u64 __user *va; |
1da177e4 LT |
1483 | u64 val; |
1484 | ||
1485 | switch (MIPSInst_FUNC(ir)) { | |
1486 | case ldxc1_op: | |
3fccc015 | 1487 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1488 | xcp->regs[MIPSInst_FT(ir)]); |
1489 | ||
b6ee75ed | 1490 | MIPS_FPU_EMU_INC_STATS(loads); |
515b029d | 1491 | if (!access_ok(VERIFY_READ, va, sizeof(u64))) { |
b6ee75ed | 1492 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1493 | *fault_addr = va; |
1da177e4 LT |
1494 | return SIGBUS; |
1495 | } | |
515b029d DD |
1496 | if (__get_user(val, va)) { |
1497 | MIPS_FPU_EMU_INC_STATS(errors); | |
1498 | *fault_addr = va; | |
1499 | return SIGSEGV; | |
1500 | } | |
1da177e4 LT |
1501 | DITOREG(val, MIPSInst_FD(ir)); |
1502 | break; | |
1503 | ||
1504 | case sdxc1_op: | |
3fccc015 | 1505 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1506 | xcp->regs[MIPSInst_FT(ir)]); |
1507 | ||
b6ee75ed | 1508 | MIPS_FPU_EMU_INC_STATS(stores); |
1da177e4 | 1509 | DIFROMREG(val, MIPSInst_FS(ir)); |
515b029d | 1510 | if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { |
b6ee75ed | 1511 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1512 | *fault_addr = va; |
1da177e4 LT |
1513 | return SIGBUS; |
1514 | } | |
515b029d DD |
1515 | if (__put_user(val, va)) { |
1516 | MIPS_FPU_EMU_INC_STATS(errors); | |
1517 | *fault_addr = va; | |
1518 | return SIGSEGV; | |
1519 | } | |
1da177e4 LT |
1520 | break; |
1521 | ||
1522 | case madd_d_op: | |
1523 | handler = fpemu_dp_madd; | |
1524 | goto dcoptop; | |
1525 | case msub_d_op: | |
1526 | handler = fpemu_dp_msub; | |
1527 | goto dcoptop; | |
1528 | case nmadd_d_op: | |
1529 | handler = fpemu_dp_nmadd; | |
1530 | goto dcoptop; | |
1531 | case nmsub_d_op: | |
1532 | handler = fpemu_dp_nmsub; | |
1533 | goto dcoptop; | |
1534 | ||
1535 | dcoptop: | |
1536 | DPFROMREG(fr, MIPSInst_FR(ir)); | |
1537 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1538 | DPFROMREG(ft, MIPSInst_FT(ir)); | |
1539 | fd = (*handler) (fr, fs, ft); | |
1540 | DPTOREG(fd, MIPSInst_FD(ir)); | |
1541 | goto copcsr; | |
1542 | ||
1543 | default: | |
1544 | return SIGILL; | |
1545 | } | |
1546 | break; | |
1547 | } | |
1da177e4 LT |
1548 | |
1549 | case 0x7: /* 7 */ | |
1550 | if (MIPSInst_FUNC(ir) != pfetch_op) { | |
1551 | return SIGILL; | |
1552 | } | |
1553 | /* ignore prefx operation */ | |
1554 | break; | |
1555 | ||
1556 | default: | |
1557 | return SIGILL; | |
1558 | } | |
1559 | ||
1560 | return 0; | |
1561 | } | |
1562 | #endif | |
1563 | ||
1564 | ||
1565 | ||
1566 | /* | |
1567 | * Emulate a single COP1 arithmetic instruction. | |
1568 | */ | |
eae89076 | 1569 | static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
1da177e4 LT |
1570 | mips_instruction ir) |
1571 | { | |
1572 | int rfmt; /* resulting format */ | |
1573 | unsigned rcsr = 0; /* resulting csr */ | |
1574 | unsigned cond; | |
1575 | union { | |
1576 | ieee754dp d; | |
1577 | ieee754sp s; | |
1578 | int w; | |
766160c2 | 1579 | #ifdef __mips64 |
1da177e4 LT |
1580 | s64 l; |
1581 | #endif | |
1582 | } rv; /* resulting value */ | |
1583 | ||
b6ee75ed | 1584 | MIPS_FPU_EMU_INC_STATS(cp1ops); |
1da177e4 LT |
1585 | switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { |
1586 | case s_fmt:{ /* 0 */ | |
1587 | union { | |
1588 | ieee754sp(*b) (ieee754sp, ieee754sp); | |
1589 | ieee754sp(*u) (ieee754sp); | |
1590 | } handler; | |
1591 | ||
1592 | switch (MIPSInst_FUNC(ir)) { | |
1593 | /* binary ops */ | |
1594 | case fadd_op: | |
1595 | handler.b = ieee754sp_add; | |
1596 | goto scopbop; | |
1597 | case fsub_op: | |
1598 | handler.b = ieee754sp_sub; | |
1599 | goto scopbop; | |
1600 | case fmul_op: | |
1601 | handler.b = ieee754sp_mul; | |
1602 | goto scopbop; | |
1603 | case fdiv_op: | |
1604 | handler.b = ieee754sp_div; | |
1605 | goto scopbop; | |
1606 | ||
1607 | /* unary ops */ | |
587cb98f | 1608 | #if __mips >= 2 || defined(__mips64) |
1da177e4 LT |
1609 | case fsqrt_op: |
1610 | handler.u = ieee754sp_sqrt; | |
1611 | goto scopuop; | |
1612 | #endif | |
1613 | #if __mips >= 4 && __mips != 32 | |
1614 | case frsqrt_op: | |
1615 | handler.u = fpemu_sp_rsqrt; | |
1616 | goto scopuop; | |
1617 | case frecip_op: | |
1618 | handler.u = fpemu_sp_recip; | |
1619 | goto scopuop; | |
1620 | #endif | |
1621 | #if __mips >= 4 | |
1622 | case fmovc_op: | |
1623 | cond = fpucondbit[MIPSInst_FT(ir) >> 2]; | |
1624 | if (((ctx->fcr31 & cond) != 0) != | |
1625 | ((MIPSInst_FT(ir) & 1) != 0)) | |
1626 | return 0; | |
1627 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1628 | break; | |
1629 | case fmovz_op: | |
1630 | if (xcp->regs[MIPSInst_FT(ir)] != 0) | |
1631 | return 0; | |
1632 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1633 | break; | |
1634 | case fmovn_op: | |
1635 | if (xcp->regs[MIPSInst_FT(ir)] == 0) | |
1636 | return 0; | |
1637 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1638 | break; | |
1639 | #endif | |
1640 | case fabs_op: | |
1641 | handler.u = ieee754sp_abs; | |
1642 | goto scopuop; | |
1643 | case fneg_op: | |
1644 | handler.u = ieee754sp_neg; | |
1645 | goto scopuop; | |
1646 | case fmov_op: | |
1647 | /* an easy one */ | |
1648 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1649 | goto copcsr; | |
1650 | ||
1651 | /* binary op on handler */ | |
1652 | scopbop: | |
1653 | { | |
1654 | ieee754sp fs, ft; | |
1655 | ||
1656 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1657 | SPFROMREG(ft, MIPSInst_FT(ir)); | |
1658 | ||
1659 | rv.s = (*handler.b) (fs, ft); | |
1660 | goto copcsr; | |
1661 | } | |
1662 | scopuop: | |
1663 | { | |
1664 | ieee754sp fs; | |
1665 | ||
1666 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1667 | rv.s = (*handler.u) (fs); | |
1668 | goto copcsr; | |
1669 | } | |
1670 | copcsr: | |
1671 | if (ieee754_cxtest(IEEE754_INEXACT)) | |
1672 | rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; | |
1673 | if (ieee754_cxtest(IEEE754_UNDERFLOW)) | |
1674 | rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; | |
1675 | if (ieee754_cxtest(IEEE754_OVERFLOW)) | |
1676 | rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; | |
1677 | if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) | |
1678 | rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S; | |
1679 | if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) | |
1680 | rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; | |
1681 | break; | |
1682 | ||
1683 | /* unary conv ops */ | |
1684 | case fcvts_op: | |
1685 | return SIGILL; /* not defined */ | |
1686 | case fcvtd_op:{ | |
1da177e4 LT |
1687 | ieee754sp fs; |
1688 | ||
1689 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1690 | rv.d = ieee754dp_fsp(fs); | |
1691 | rfmt = d_fmt; | |
1692 | goto copcsr; | |
1693 | } | |
1da177e4 LT |
1694 | case fcvtw_op:{ |
1695 | ieee754sp fs; | |
1696 | ||
1697 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1698 | rv.w = ieee754sp_tint(fs); | |
1699 | rfmt = w_fmt; | |
1700 | goto copcsr; | |
1701 | } | |
1702 | ||
587cb98f | 1703 | #if __mips >= 2 || defined(__mips64) |
1da177e4 LT |
1704 | case fround_op: |
1705 | case ftrunc_op: | |
1706 | case fceil_op: | |
1707 | case ffloor_op:{ | |
1708 | unsigned int oldrm = ieee754_csr.rm; | |
1709 | ieee754sp fs; | |
1710 | ||
1711 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
3f135530 | 1712 | ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; |
1da177e4 LT |
1713 | rv.w = ieee754sp_tint(fs); |
1714 | ieee754_csr.rm = oldrm; | |
1715 | rfmt = w_fmt; | |
1716 | goto copcsr; | |
1717 | } | |
1718 | #endif /* __mips >= 2 */ | |
1719 | ||
4b724efd | 1720 | #if defined(__mips64) |
1da177e4 LT |
1721 | case fcvtl_op:{ |
1722 | ieee754sp fs; | |
1723 | ||
1724 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1725 | rv.l = ieee754sp_tlong(fs); | |
1726 | rfmt = l_fmt; | |
1727 | goto copcsr; | |
1728 | } | |
1729 | ||
1730 | case froundl_op: | |
1731 | case ftruncl_op: | |
1732 | case fceill_op: | |
1733 | case ffloorl_op:{ | |
1734 | unsigned int oldrm = ieee754_csr.rm; | |
1735 | ieee754sp fs; | |
1736 | ||
1737 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
3f135530 | 1738 | ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; |
1da177e4 LT |
1739 | rv.l = ieee754sp_tlong(fs); |
1740 | ieee754_csr.rm = oldrm; | |
1741 | rfmt = l_fmt; | |
1742 | goto copcsr; | |
1743 | } | |
4b724efd | 1744 | #endif /* defined(__mips64) */ |
1da177e4 LT |
1745 | |
1746 | default: | |
1747 | if (MIPSInst_FUNC(ir) >= fcmp_op) { | |
1748 | unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; | |
1749 | ieee754sp fs, ft; | |
1750 | ||
1751 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1752 | SPFROMREG(ft, MIPSInst_FT(ir)); | |
1753 | rv.w = ieee754sp_cmp(fs, ft, | |
1754 | cmptab[cmpop & 0x7], cmpop & 0x8); | |
1755 | rfmt = -1; | |
1756 | if ((cmpop & 0x8) && ieee754_cxtest | |
1757 | (IEEE754_INVALID_OPERATION)) | |
1758 | rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; | |
1759 | else | |
1760 | goto copcsr; | |
1761 | ||
1762 | } | |
1763 | else { | |
1764 | return SIGILL; | |
1765 | } | |
1766 | break; | |
1767 | } | |
1768 | break; | |
1769 | } | |
1770 | ||
1da177e4 LT |
1771 | case d_fmt:{ |
1772 | union { | |
1773 | ieee754dp(*b) (ieee754dp, ieee754dp); | |
1774 | ieee754dp(*u) (ieee754dp); | |
1775 | } handler; | |
1776 | ||
1777 | switch (MIPSInst_FUNC(ir)) { | |
1778 | /* binary ops */ | |
1779 | case fadd_op: | |
1780 | handler.b = ieee754dp_add; | |
1781 | goto dcopbop; | |
1782 | case fsub_op: | |
1783 | handler.b = ieee754dp_sub; | |
1784 | goto dcopbop; | |
1785 | case fmul_op: | |
1786 | handler.b = ieee754dp_mul; | |
1787 | goto dcopbop; | |
1788 | case fdiv_op: | |
1789 | handler.b = ieee754dp_div; | |
1790 | goto dcopbop; | |
1791 | ||
1792 | /* unary ops */ | |
587cb98f | 1793 | #if __mips >= 2 || defined(__mips64) |
1da177e4 LT |
1794 | case fsqrt_op: |
1795 | handler.u = ieee754dp_sqrt; | |
1796 | goto dcopuop; | |
1797 | #endif | |
1798 | #if __mips >= 4 && __mips != 32 | |
1799 | case frsqrt_op: | |
1800 | handler.u = fpemu_dp_rsqrt; | |
1801 | goto dcopuop; | |
1802 | case frecip_op: | |
1803 | handler.u = fpemu_dp_recip; | |
1804 | goto dcopuop; | |
1805 | #endif | |
1806 | #if __mips >= 4 | |
1807 | case fmovc_op: | |
1808 | cond = fpucondbit[MIPSInst_FT(ir) >> 2]; | |
1809 | if (((ctx->fcr31 & cond) != 0) != | |
1810 | ((MIPSInst_FT(ir) & 1) != 0)) | |
1811 | return 0; | |
1812 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1813 | break; | |
1814 | case fmovz_op: | |
1815 | if (xcp->regs[MIPSInst_FT(ir)] != 0) | |
1816 | return 0; | |
1817 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1818 | break; | |
1819 | case fmovn_op: | |
1820 | if (xcp->regs[MIPSInst_FT(ir)] == 0) | |
1821 | return 0; | |
1822 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1823 | break; | |
1824 | #endif | |
1825 | case fabs_op: | |
1826 | handler.u = ieee754dp_abs; | |
1827 | goto dcopuop; | |
1828 | ||
1829 | case fneg_op: | |
1830 | handler.u = ieee754dp_neg; | |
1831 | goto dcopuop; | |
1832 | ||
1833 | case fmov_op: | |
1834 | /* an easy one */ | |
1835 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1836 | goto copcsr; | |
1837 | ||
1838 | /* binary op on handler */ | |
1839 | dcopbop:{ | |
1840 | ieee754dp fs, ft; | |
1841 | ||
1842 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1843 | DPFROMREG(ft, MIPSInst_FT(ir)); | |
1844 | ||
1845 | rv.d = (*handler.b) (fs, ft); | |
1846 | goto copcsr; | |
1847 | } | |
1848 | dcopuop:{ | |
1849 | ieee754dp fs; | |
1850 | ||
1851 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1852 | rv.d = (*handler.u) (fs); | |
1853 | goto copcsr; | |
1854 | } | |
1855 | ||
1856 | /* unary conv ops */ | |
1857 | case fcvts_op:{ | |
1858 | ieee754dp fs; | |
1859 | ||
1860 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1861 | rv.s = ieee754sp_fdp(fs); | |
1862 | rfmt = s_fmt; | |
1863 | goto copcsr; | |
1864 | } | |
1865 | case fcvtd_op: | |
1866 | return SIGILL; /* not defined */ | |
1867 | ||
1868 | case fcvtw_op:{ | |
1869 | ieee754dp fs; | |
1870 | ||
1871 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1872 | rv.w = ieee754dp_tint(fs); /* wrong */ | |
1873 | rfmt = w_fmt; | |
1874 | goto copcsr; | |
1875 | } | |
1876 | ||
587cb98f | 1877 | #if __mips >= 2 || defined(__mips64) |
1da177e4 LT |
1878 | case fround_op: |
1879 | case ftrunc_op: | |
1880 | case fceil_op: | |
1881 | case ffloor_op:{ | |
1882 | unsigned int oldrm = ieee754_csr.rm; | |
1883 | ieee754dp fs; | |
1884 | ||
1885 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
3f135530 | 1886 | ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; |
1da177e4 LT |
1887 | rv.w = ieee754dp_tint(fs); |
1888 | ieee754_csr.rm = oldrm; | |
1889 | rfmt = w_fmt; | |
1890 | goto copcsr; | |
1891 | } | |
1892 | #endif | |
1893 | ||
4b724efd | 1894 | #if defined(__mips64) |
1da177e4 LT |
1895 | case fcvtl_op:{ |
1896 | ieee754dp fs; | |
1897 | ||
1898 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1899 | rv.l = ieee754dp_tlong(fs); | |
1900 | rfmt = l_fmt; | |
1901 | goto copcsr; | |
1902 | } | |
1903 | ||
1904 | case froundl_op: | |
1905 | case ftruncl_op: | |
1906 | case fceill_op: | |
1907 | case ffloorl_op:{ | |
1908 | unsigned int oldrm = ieee754_csr.rm; | |
1909 | ieee754dp fs; | |
1910 | ||
1911 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
3f135530 | 1912 | ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; |
1da177e4 LT |
1913 | rv.l = ieee754dp_tlong(fs); |
1914 | ieee754_csr.rm = oldrm; | |
1915 | rfmt = l_fmt; | |
1916 | goto copcsr; | |
1917 | } | |
4b724efd | 1918 | #endif /* __mips >= 3 */ |
1da177e4 LT |
1919 | |
1920 | default: | |
1921 | if (MIPSInst_FUNC(ir) >= fcmp_op) { | |
1922 | unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; | |
1923 | ieee754dp fs, ft; | |
1924 | ||
1925 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1926 | DPFROMREG(ft, MIPSInst_FT(ir)); | |
1927 | rv.w = ieee754dp_cmp(fs, ft, | |
1928 | cmptab[cmpop & 0x7], cmpop & 0x8); | |
1929 | rfmt = -1; | |
1930 | if ((cmpop & 0x8) | |
1931 | && | |
1932 | ieee754_cxtest | |
1933 | (IEEE754_INVALID_OPERATION)) | |
1934 | rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; | |
1935 | else | |
1936 | goto copcsr; | |
1937 | ||
1938 | } | |
1939 | else { | |
1940 | return SIGILL; | |
1941 | } | |
1942 | break; | |
1943 | } | |
1944 | break; | |
1945 | } | |
1da177e4 LT |
1946 | |
1947 | case w_fmt:{ | |
1948 | ieee754sp fs; | |
1949 | ||
1950 | switch (MIPSInst_FUNC(ir)) { | |
1951 | case fcvts_op: | |
1952 | /* convert word to single precision real */ | |
1953 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1954 | rv.s = ieee754sp_fint(fs.bits); | |
1955 | rfmt = s_fmt; | |
1956 | goto copcsr; | |
1da177e4 LT |
1957 | case fcvtd_op: |
1958 | /* convert word to double precision real */ | |
1959 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1960 | rv.d = ieee754dp_fint(fs.bits); | |
1961 | rfmt = d_fmt; | |
1962 | goto copcsr; | |
1da177e4 LT |
1963 | default: |
1964 | return SIGILL; | |
1965 | } | |
1966 | break; | |
1967 | } | |
1968 | ||
4b724efd | 1969 | #if defined(__mips64) |
1da177e4 | 1970 | case l_fmt:{ |
bbd426f5 PB |
1971 | u64 bits; |
1972 | DIFROMREG(bits, MIPSInst_FS(ir)); | |
1973 | ||
1da177e4 LT |
1974 | switch (MIPSInst_FUNC(ir)) { |
1975 | case fcvts_op: | |
1976 | /* convert long to single precision real */ | |
bbd426f5 | 1977 | rv.s = ieee754sp_flong(bits); |
1da177e4 LT |
1978 | rfmt = s_fmt; |
1979 | goto copcsr; | |
1980 | case fcvtd_op: | |
1981 | /* convert long to double precision real */ | |
bbd426f5 | 1982 | rv.d = ieee754dp_flong(bits); |
1da177e4 LT |
1983 | rfmt = d_fmt; |
1984 | goto copcsr; | |
1985 | default: | |
1986 | return SIGILL; | |
1987 | } | |
1988 | break; | |
1989 | } | |
1990 | #endif | |
1991 | ||
1992 | default: | |
1993 | return SIGILL; | |
1994 | } | |
1995 | ||
1996 | /* | |
1997 | * Update the fpu CSR register for this operation. | |
1998 | * If an exception is required, generate a tidy SIGFPE exception, | |
1999 | * without updating the result register. | |
2000 | * Note: cause exception bits do not accumulate, they are rewritten | |
2001 | * for each op; only the flag/sticky bits accumulate. | |
2002 | */ | |
2003 | ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; | |
2004 | if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { | |
2005 | /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */ | |
2006 | return SIGFPE; | |
2007 | } | |
2008 | ||
2009 | /* | |
2010 | * Now we can safely write the result back to the register file. | |
2011 | */ | |
2012 | switch (rfmt) { | |
2013 | case -1:{ | |
2014 | #if __mips >= 4 | |
2015 | cond = fpucondbit[MIPSInst_FD(ir) >> 2]; | |
2016 | #else | |
2017 | cond = FPU_CSR_COND; | |
2018 | #endif | |
2019 | if (rv.w) | |
2020 | ctx->fcr31 |= cond; | |
2021 | else | |
2022 | ctx->fcr31 &= ~cond; | |
2023 | break; | |
2024 | } | |
1da177e4 LT |
2025 | case d_fmt: |
2026 | DPTOREG(rv.d, MIPSInst_FD(ir)); | |
2027 | break; | |
1da177e4 LT |
2028 | case s_fmt: |
2029 | SPTOREG(rv.s, MIPSInst_FD(ir)); | |
2030 | break; | |
2031 | case w_fmt: | |
2032 | SITOREG(rv.w, MIPSInst_FD(ir)); | |
2033 | break; | |
4b724efd | 2034 | #if defined(__mips64) |
1da177e4 LT |
2035 | case l_fmt: |
2036 | DITOREG(rv.l, MIPSInst_FD(ir)); | |
2037 | break; | |
2038 | #endif | |
2039 | default: | |
2040 | return SIGILL; | |
2041 | } | |
2042 | ||
2043 | return 0; | |
2044 | } | |
2045 | ||
e04582b7 | 2046 | int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
515b029d | 2047 | int has_fpu, void *__user *fault_addr) |
1da177e4 | 2048 | { |
333d1f67 | 2049 | unsigned long oldepc, prevepc; |
102cedc3 LY |
2050 | struct mm_decoded_insn dec_insn; |
2051 | u16 instr[4]; | |
2052 | u16 *instr_ptr; | |
1da177e4 LT |
2053 | int sig = 0; |
2054 | ||
2055 | oldepc = xcp->cp0_epc; | |
2056 | do { | |
2057 | prevepc = xcp->cp0_epc; | |
2058 | ||
102cedc3 LY |
2059 | if (get_isa16_mode(prevepc) && cpu_has_mmips) { |
2060 | /* | |
2061 | * Get next 2 microMIPS instructions and convert them | |
2062 | * into 32-bit instructions. | |
2063 | */ | |
2064 | if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) || | |
2065 | (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) || | |
2066 | (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) || | |
2067 | (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) { | |
2068 | MIPS_FPU_EMU_INC_STATS(errors); | |
2069 | return SIGBUS; | |
2070 | } | |
2071 | instr_ptr = instr; | |
2072 | ||
2073 | /* Get first instruction. */ | |
2074 | if (mm_insn_16bit(*instr_ptr)) { | |
2075 | /* Duplicate the half-word. */ | |
2076 | dec_insn.insn = (*instr_ptr << 16) | | |
2077 | (*instr_ptr); | |
2078 | /* 16-bit instruction. */ | |
2079 | dec_insn.pc_inc = 2; | |
2080 | instr_ptr += 1; | |
2081 | } else { | |
2082 | dec_insn.insn = (*instr_ptr << 16) | | |
2083 | *(instr_ptr+1); | |
2084 | /* 32-bit instruction. */ | |
2085 | dec_insn.pc_inc = 4; | |
2086 | instr_ptr += 2; | |
2087 | } | |
2088 | /* Get second instruction. */ | |
2089 | if (mm_insn_16bit(*instr_ptr)) { | |
2090 | /* Duplicate the half-word. */ | |
2091 | dec_insn.next_insn = (*instr_ptr << 16) | | |
2092 | (*instr_ptr); | |
2093 | /* 16-bit instruction. */ | |
2094 | dec_insn.next_pc_inc = 2; | |
2095 | } else { | |
2096 | dec_insn.next_insn = (*instr_ptr << 16) | | |
2097 | *(instr_ptr+1); | |
2098 | /* 32-bit instruction. */ | |
2099 | dec_insn.next_pc_inc = 4; | |
2100 | } | |
2101 | dec_insn.micro_mips_mode = 1; | |
2102 | } else { | |
2103 | if ((get_user(dec_insn.insn, | |
2104 | (mips_instruction __user *) xcp->cp0_epc)) || | |
2105 | (get_user(dec_insn.next_insn, | |
2106 | (mips_instruction __user *)(xcp->cp0_epc+4)))) { | |
2107 | MIPS_FPU_EMU_INC_STATS(errors); | |
2108 | return SIGBUS; | |
2109 | } | |
2110 | dec_insn.pc_inc = 4; | |
2111 | dec_insn.next_pc_inc = 4; | |
2112 | dec_insn.micro_mips_mode = 0; | |
515b029d | 2113 | } |
102cedc3 LY |
2114 | |
2115 | if ((dec_insn.insn == 0) || | |
2116 | ((dec_insn.pc_inc == 2) && | |
2117 | ((dec_insn.insn & 0xffff) == MM_NOP16))) | |
2118 | xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ | |
1da177e4 | 2119 | else { |
cd21dfcf RB |
2120 | /* |
2121 | * The 'ieee754_csr' is an alias of | |
70342287 RB |
2122 | * ctx->fcr31. No need to copy ctx->fcr31 to |
2123 | * ieee754_csr. But ieee754_csr.rm is ieee | |
cd21dfcf RB |
2124 | * library modes. (not mips rounding mode) |
2125 | */ | |
2126 | /* convert to ieee library modes */ | |
2127 | ieee754_csr.rm = ieee_rm[ieee754_csr.rm]; | |
102cedc3 | 2128 | sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); |
cd21dfcf RB |
2129 | /* revert to mips rounding mode */ |
2130 | ieee754_csr.rm = mips_rm[ieee754_csr.rm]; | |
1da177e4 LT |
2131 | } |
2132 | ||
e04582b7 | 2133 | if (has_fpu) |
1da177e4 LT |
2134 | break; |
2135 | if (sig) | |
2136 | break; | |
2137 | ||
2138 | cond_resched(); | |
2139 | } while (xcp->cp0_epc > prevepc); | |
2140 | ||
2141 | /* SIGILL indicates a non-fpu instruction */ | |
2142 | if (sig == SIGILL && xcp->cp0_epc != oldepc) | |
2143 | /* but if epc has advanced, then ignore it */ | |
2144 | sig = 0; | |
2145 | ||
2146 | return sig; | |
2147 | } | |
83fd38ca AN |
2148 | |
2149 | #ifdef CONFIG_DEBUG_FS | |
b6ee75ed DD |
2150 | |
2151 | static int fpuemu_stat_get(void *data, u64 *val) | |
2152 | { | |
2153 | int cpu; | |
2154 | unsigned long sum = 0; | |
2155 | for_each_online_cpu(cpu) { | |
2156 | struct mips_fpu_emulator_stats *ps; | |
2157 | local_t *pv; | |
2158 | ps = &per_cpu(fpuemustats, cpu); | |
2159 | pv = (void *)ps + (unsigned long)data; | |
2160 | sum += local_read(pv); | |
2161 | } | |
2162 | *val = sum; | |
2163 | return 0; | |
2164 | } | |
2165 | DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat, fpuemu_stat_get, NULL, "%llu\n"); | |
2166 | ||
83fd38ca AN |
2167 | extern struct dentry *mips_debugfs_dir; |
2168 | static int __init debugfs_fpuemu(void) | |
2169 | { | |
2170 | struct dentry *d, *dir; | |
83fd38ca AN |
2171 | |
2172 | if (!mips_debugfs_dir) | |
2173 | return -ENODEV; | |
2174 | dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir); | |
ecab1f44 Z |
2175 | if (!dir) |
2176 | return -ENOMEM; | |
b6ee75ed DD |
2177 | |
2178 | #define FPU_STAT_CREATE(M) \ | |
2179 | do { \ | |
2180 | d = debugfs_create_file(#M , S_IRUGO, dir, \ | |
2181 | (void *)offsetof(struct mips_fpu_emulator_stats, M), \ | |
2182 | &fops_fpuemu_stat); \ | |
2183 | if (!d) \ | |
2184 | return -ENOMEM; \ | |
2185 | } while (0) | |
2186 | ||
2187 | FPU_STAT_CREATE(emulated); | |
2188 | FPU_STAT_CREATE(loads); | |
2189 | FPU_STAT_CREATE(stores); | |
2190 | FPU_STAT_CREATE(cp1ops); | |
2191 | FPU_STAT_CREATE(cp1xops); | |
2192 | FPU_STAT_CREATE(errors); | |
2193 | ||
83fd38ca AN |
2194 | return 0; |
2195 | } | |
2196 | __initcall(debugfs_fpuemu); | |
2197 | #endif |