Commit | Line | Data |
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1da177e4 | 1 | /* |
3f7cac41 | 2 | * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator |
1da177e4 LT |
3 | * |
4 | * MIPS floating point support | |
5 | * Copyright (C) 1994-2000 Algorithmics Ltd. | |
1da177e4 LT |
6 | * |
7 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
8 | * Copyright (C) 2000 MIPS Technologies, Inc. | |
9 | * | |
10 | * This program is free software; you can distribute it and/or modify it | |
11 | * under the terms of the GNU General Public License (Version 2) as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | * for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along | |
20 | * with this program; if not, write to the Free Software Foundation, Inc., | |
3f7cac41 | 21 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
1da177e4 LT |
22 | * |
23 | * A complete emulator for MIPS coprocessor 1 instructions. This is | |
24 | * required for #float(switch) or #float(trap), where it catches all | |
25 | * COP1 instructions via the "CoProcessor Unusable" exception. | |
26 | * | |
27 | * More surprisingly it is also required for #float(ieee), to help out | |
3f7cac41 | 28 | * the hardware FPU at the boundaries of the IEEE-754 representation |
1da177e4 LT |
29 | * (denormalised values, infinities, underflow, etc). It is made |
30 | * quite nasty because emulation of some non-COP1 instructions is | |
31 | * required, e.g. in branch delay slots. | |
32 | * | |
3f7cac41 | 33 | * Note if you know that you won't have an FPU, then you'll get much |
1da177e4 LT |
34 | * better performance by compiling with -msoft-float! |
35 | */ | |
36 | #include <linux/sched.h> | |
83fd38ca | 37 | #include <linux/debugfs.h> |
08a07904 | 38 | #include <linux/kconfig.h> |
85c51c51 | 39 | #include <linux/percpu-defs.h> |
7f788d2d | 40 | #include <linux/perf_event.h> |
1da177e4 | 41 | |
cd8ee345 | 42 | #include <asm/branch.h> |
1da177e4 | 43 | #include <asm/inst.h> |
1da177e4 LT |
44 | #include <asm/ptrace.h> |
45 | #include <asm/signal.h> | |
cd8ee345 RB |
46 | #include <asm/uaccess.h> |
47 | ||
48 | #include <asm/processor.h> | |
1da177e4 | 49 | #include <asm/fpu_emulator.h> |
102cedc3 | 50 | #include <asm/fpu.h> |
1da177e4 LT |
51 | |
52 | #include "ieee754.h" | |
1da177e4 | 53 | |
1da177e4 LT |
54 | /* Function which emulates a floating point instruction. */ |
55 | ||
eae89076 | 56 | static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, |
1da177e4 LT |
57 | mips_instruction); |
58 | ||
1da177e4 | 59 | static int fpux_emu(struct pt_regs *, |
515b029d | 60 | struct mips_fpu_struct *, mips_instruction, void *__user *); |
1da177e4 | 61 | |
1da177e4 LT |
62 | /* Control registers */ |
63 | ||
64 | #define FPCREG_RID 0 /* $0 = revision id */ | |
65 | #define FPCREG_CSR 31 /* $31 = csr */ | |
66 | ||
95e8f634 SM |
67 | /* Determine rounding mode from the RM bits of the FCSR */ |
68 | #define modeindex(v) ((v) & FPU_CSR_RM) | |
69 | ||
1da177e4 LT |
70 | /* convert condition code register number to csr bit */ |
71 | static const unsigned int fpucondbit[8] = { | |
72 | FPU_CSR_COND0, | |
73 | FPU_CSR_COND1, | |
74 | FPU_CSR_COND2, | |
75 | FPU_CSR_COND3, | |
76 | FPU_CSR_COND4, | |
77 | FPU_CSR_COND5, | |
78 | FPU_CSR_COND6, | |
79 | FPU_CSR_COND7 | |
80 | }; | |
1da177e4 | 81 | |
102cedc3 LY |
82 | /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */ |
83 | static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0}; | |
84 | static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0}; | |
85 | static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0}; | |
86 | static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0}; | |
87 | ||
88 | /* | |
89 | * This functions translates a 32-bit microMIPS instruction | |
90 | * into a 32-bit MIPS32 instruction. Returns 0 on success | |
91 | * and SIGILL otherwise. | |
92 | */ | |
93 | static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) | |
94 | { | |
95 | union mips_instruction insn = *insn_ptr; | |
96 | union mips_instruction mips32_insn = insn; | |
97 | int func, fmt, op; | |
98 | ||
99 | switch (insn.mm_i_format.opcode) { | |
100 | case mm_ldc132_op: | |
101 | mips32_insn.mm_i_format.opcode = ldc1_op; | |
102 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
103 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
104 | break; | |
105 | case mm_lwc132_op: | |
106 | mips32_insn.mm_i_format.opcode = lwc1_op; | |
107 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
108 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
109 | break; | |
110 | case mm_sdc132_op: | |
111 | mips32_insn.mm_i_format.opcode = sdc1_op; | |
112 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
113 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
114 | break; | |
115 | case mm_swc132_op: | |
116 | mips32_insn.mm_i_format.opcode = swc1_op; | |
117 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
118 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
119 | break; | |
120 | case mm_pool32i_op: | |
121 | /* NOTE: offset is << by 1 if in microMIPS mode. */ | |
122 | if ((insn.mm_i_format.rt == mm_bc1f_op) || | |
123 | (insn.mm_i_format.rt == mm_bc1t_op)) { | |
124 | mips32_insn.fb_format.opcode = cop1_op; | |
125 | mips32_insn.fb_format.bc = bc_op; | |
126 | mips32_insn.fb_format.flag = | |
127 | (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0; | |
128 | } else | |
129 | return SIGILL; | |
130 | break; | |
131 | case mm_pool32f_op: | |
132 | switch (insn.mm_fp0_format.func) { | |
133 | case mm_32f_01_op: | |
134 | case mm_32f_11_op: | |
135 | case mm_32f_02_op: | |
136 | case mm_32f_12_op: | |
137 | case mm_32f_41_op: | |
138 | case mm_32f_51_op: | |
139 | case mm_32f_42_op: | |
140 | case mm_32f_52_op: | |
141 | op = insn.mm_fp0_format.func; | |
142 | if (op == mm_32f_01_op) | |
143 | func = madd_s_op; | |
144 | else if (op == mm_32f_11_op) | |
145 | func = madd_d_op; | |
146 | else if (op == mm_32f_02_op) | |
147 | func = nmadd_s_op; | |
148 | else if (op == mm_32f_12_op) | |
149 | func = nmadd_d_op; | |
150 | else if (op == mm_32f_41_op) | |
151 | func = msub_s_op; | |
152 | else if (op == mm_32f_51_op) | |
153 | func = msub_d_op; | |
154 | else if (op == mm_32f_42_op) | |
155 | func = nmsub_s_op; | |
156 | else | |
157 | func = nmsub_d_op; | |
158 | mips32_insn.fp6_format.opcode = cop1x_op; | |
159 | mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr; | |
160 | mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft; | |
161 | mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs; | |
162 | mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd; | |
163 | mips32_insn.fp6_format.func = func; | |
164 | break; | |
165 | case mm_32f_10_op: | |
166 | func = -1; /* Invalid */ | |
167 | op = insn.mm_fp5_format.op & 0x7; | |
168 | if (op == mm_ldxc1_op) | |
169 | func = ldxc1_op; | |
170 | else if (op == mm_sdxc1_op) | |
171 | func = sdxc1_op; | |
172 | else if (op == mm_lwxc1_op) | |
173 | func = lwxc1_op; | |
174 | else if (op == mm_swxc1_op) | |
175 | func = swxc1_op; | |
176 | ||
177 | if (func != -1) { | |
178 | mips32_insn.r_format.opcode = cop1x_op; | |
179 | mips32_insn.r_format.rs = | |
180 | insn.mm_fp5_format.base; | |
181 | mips32_insn.r_format.rt = | |
182 | insn.mm_fp5_format.index; | |
183 | mips32_insn.r_format.rd = 0; | |
184 | mips32_insn.r_format.re = insn.mm_fp5_format.fd; | |
185 | mips32_insn.r_format.func = func; | |
186 | } else | |
187 | return SIGILL; | |
188 | break; | |
189 | case mm_32f_40_op: | |
190 | op = -1; /* Invalid */ | |
191 | if (insn.mm_fp2_format.op == mm_fmovt_op) | |
192 | op = 1; | |
193 | else if (insn.mm_fp2_format.op == mm_fmovf_op) | |
194 | op = 0; | |
195 | if (op != -1) { | |
196 | mips32_insn.fp0_format.opcode = cop1_op; | |
197 | mips32_insn.fp0_format.fmt = | |
198 | sdps_format[insn.mm_fp2_format.fmt]; | |
199 | mips32_insn.fp0_format.ft = | |
200 | (insn.mm_fp2_format.cc<<2) + op; | |
201 | mips32_insn.fp0_format.fs = | |
202 | insn.mm_fp2_format.fs; | |
203 | mips32_insn.fp0_format.fd = | |
204 | insn.mm_fp2_format.fd; | |
205 | mips32_insn.fp0_format.func = fmovc_op; | |
206 | } else | |
207 | return SIGILL; | |
208 | break; | |
209 | case mm_32f_60_op: | |
210 | func = -1; /* Invalid */ | |
211 | if (insn.mm_fp0_format.op == mm_fadd_op) | |
212 | func = fadd_op; | |
213 | else if (insn.mm_fp0_format.op == mm_fsub_op) | |
214 | func = fsub_op; | |
215 | else if (insn.mm_fp0_format.op == mm_fmul_op) | |
216 | func = fmul_op; | |
217 | else if (insn.mm_fp0_format.op == mm_fdiv_op) | |
218 | func = fdiv_op; | |
219 | if (func != -1) { | |
220 | mips32_insn.fp0_format.opcode = cop1_op; | |
221 | mips32_insn.fp0_format.fmt = | |
222 | sdps_format[insn.mm_fp0_format.fmt]; | |
223 | mips32_insn.fp0_format.ft = | |
224 | insn.mm_fp0_format.ft; | |
225 | mips32_insn.fp0_format.fs = | |
226 | insn.mm_fp0_format.fs; | |
227 | mips32_insn.fp0_format.fd = | |
228 | insn.mm_fp0_format.fd; | |
229 | mips32_insn.fp0_format.func = func; | |
230 | } else | |
231 | return SIGILL; | |
232 | break; | |
233 | case mm_32f_70_op: | |
234 | func = -1; /* Invalid */ | |
235 | if (insn.mm_fp0_format.op == mm_fmovn_op) | |
236 | func = fmovn_op; | |
237 | else if (insn.mm_fp0_format.op == mm_fmovz_op) | |
238 | func = fmovz_op; | |
239 | if (func != -1) { | |
240 | mips32_insn.fp0_format.opcode = cop1_op; | |
241 | mips32_insn.fp0_format.fmt = | |
242 | sdps_format[insn.mm_fp0_format.fmt]; | |
243 | mips32_insn.fp0_format.ft = | |
244 | insn.mm_fp0_format.ft; | |
245 | mips32_insn.fp0_format.fs = | |
246 | insn.mm_fp0_format.fs; | |
247 | mips32_insn.fp0_format.fd = | |
248 | insn.mm_fp0_format.fd; | |
249 | mips32_insn.fp0_format.func = func; | |
250 | } else | |
251 | return SIGILL; | |
252 | break; | |
253 | case mm_32f_73_op: /* POOL32FXF */ | |
254 | switch (insn.mm_fp1_format.op) { | |
255 | case mm_movf0_op: | |
256 | case mm_movf1_op: | |
257 | case mm_movt0_op: | |
258 | case mm_movt1_op: | |
259 | if ((insn.mm_fp1_format.op & 0x7f) == | |
260 | mm_movf0_op) | |
261 | op = 0; | |
262 | else | |
263 | op = 1; | |
264 | mips32_insn.r_format.opcode = spec_op; | |
265 | mips32_insn.r_format.rs = insn.mm_fp4_format.fs; | |
266 | mips32_insn.r_format.rt = | |
267 | (insn.mm_fp4_format.cc << 2) + op; | |
268 | mips32_insn.r_format.rd = insn.mm_fp4_format.rt; | |
269 | mips32_insn.r_format.re = 0; | |
270 | mips32_insn.r_format.func = movc_op; | |
271 | break; | |
272 | case mm_fcvtd0_op: | |
273 | case mm_fcvtd1_op: | |
274 | case mm_fcvts0_op: | |
275 | case mm_fcvts1_op: | |
276 | if ((insn.mm_fp1_format.op & 0x7f) == | |
277 | mm_fcvtd0_op) { | |
278 | func = fcvtd_op; | |
279 | fmt = swl_format[insn.mm_fp3_format.fmt]; | |
280 | } else { | |
281 | func = fcvts_op; | |
282 | fmt = dwl_format[insn.mm_fp3_format.fmt]; | |
283 | } | |
284 | mips32_insn.fp0_format.opcode = cop1_op; | |
285 | mips32_insn.fp0_format.fmt = fmt; | |
286 | mips32_insn.fp0_format.ft = 0; | |
287 | mips32_insn.fp0_format.fs = | |
288 | insn.mm_fp3_format.fs; | |
289 | mips32_insn.fp0_format.fd = | |
290 | insn.mm_fp3_format.rt; | |
291 | mips32_insn.fp0_format.func = func; | |
292 | break; | |
293 | case mm_fmov0_op: | |
294 | case mm_fmov1_op: | |
295 | case mm_fabs0_op: | |
296 | case mm_fabs1_op: | |
297 | case mm_fneg0_op: | |
298 | case mm_fneg1_op: | |
299 | if ((insn.mm_fp1_format.op & 0x7f) == | |
300 | mm_fmov0_op) | |
301 | func = fmov_op; | |
302 | else if ((insn.mm_fp1_format.op & 0x7f) == | |
303 | mm_fabs0_op) | |
304 | func = fabs_op; | |
305 | else | |
306 | func = fneg_op; | |
307 | mips32_insn.fp0_format.opcode = cop1_op; | |
308 | mips32_insn.fp0_format.fmt = | |
309 | sdps_format[insn.mm_fp3_format.fmt]; | |
310 | mips32_insn.fp0_format.ft = 0; | |
311 | mips32_insn.fp0_format.fs = | |
312 | insn.mm_fp3_format.fs; | |
313 | mips32_insn.fp0_format.fd = | |
314 | insn.mm_fp3_format.rt; | |
315 | mips32_insn.fp0_format.func = func; | |
316 | break; | |
317 | case mm_ffloorl_op: | |
318 | case mm_ffloorw_op: | |
319 | case mm_fceill_op: | |
320 | case mm_fceilw_op: | |
321 | case mm_ftruncl_op: | |
322 | case mm_ftruncw_op: | |
323 | case mm_froundl_op: | |
324 | case mm_froundw_op: | |
325 | case mm_fcvtl_op: | |
326 | case mm_fcvtw_op: | |
327 | if (insn.mm_fp1_format.op == mm_ffloorl_op) | |
328 | func = ffloorl_op; | |
329 | else if (insn.mm_fp1_format.op == mm_ffloorw_op) | |
330 | func = ffloor_op; | |
331 | else if (insn.mm_fp1_format.op == mm_fceill_op) | |
332 | func = fceill_op; | |
333 | else if (insn.mm_fp1_format.op == mm_fceilw_op) | |
334 | func = fceil_op; | |
335 | else if (insn.mm_fp1_format.op == mm_ftruncl_op) | |
336 | func = ftruncl_op; | |
337 | else if (insn.mm_fp1_format.op == mm_ftruncw_op) | |
338 | func = ftrunc_op; | |
339 | else if (insn.mm_fp1_format.op == mm_froundl_op) | |
340 | func = froundl_op; | |
341 | else if (insn.mm_fp1_format.op == mm_froundw_op) | |
342 | func = fround_op; | |
343 | else if (insn.mm_fp1_format.op == mm_fcvtl_op) | |
344 | func = fcvtl_op; | |
345 | else | |
346 | func = fcvtw_op; | |
347 | mips32_insn.fp0_format.opcode = cop1_op; | |
348 | mips32_insn.fp0_format.fmt = | |
349 | sd_format[insn.mm_fp1_format.fmt]; | |
350 | mips32_insn.fp0_format.ft = 0; | |
351 | mips32_insn.fp0_format.fs = | |
352 | insn.mm_fp1_format.fs; | |
353 | mips32_insn.fp0_format.fd = | |
354 | insn.mm_fp1_format.rt; | |
355 | mips32_insn.fp0_format.func = func; | |
356 | break; | |
357 | case mm_frsqrt_op: | |
358 | case mm_fsqrt_op: | |
359 | case mm_frecip_op: | |
360 | if (insn.mm_fp1_format.op == mm_frsqrt_op) | |
361 | func = frsqrt_op; | |
362 | else if (insn.mm_fp1_format.op == mm_fsqrt_op) | |
363 | func = fsqrt_op; | |
364 | else | |
365 | func = frecip_op; | |
366 | mips32_insn.fp0_format.opcode = cop1_op; | |
367 | mips32_insn.fp0_format.fmt = | |
368 | sdps_format[insn.mm_fp1_format.fmt]; | |
369 | mips32_insn.fp0_format.ft = 0; | |
370 | mips32_insn.fp0_format.fs = | |
371 | insn.mm_fp1_format.fs; | |
372 | mips32_insn.fp0_format.fd = | |
373 | insn.mm_fp1_format.rt; | |
374 | mips32_insn.fp0_format.func = func; | |
375 | break; | |
376 | case mm_mfc1_op: | |
377 | case mm_mtc1_op: | |
378 | case mm_cfc1_op: | |
379 | case mm_ctc1_op: | |
9355e59c SH |
380 | case mm_mfhc1_op: |
381 | case mm_mthc1_op: | |
102cedc3 LY |
382 | if (insn.mm_fp1_format.op == mm_mfc1_op) |
383 | op = mfc_op; | |
384 | else if (insn.mm_fp1_format.op == mm_mtc1_op) | |
385 | op = mtc_op; | |
386 | else if (insn.mm_fp1_format.op == mm_cfc1_op) | |
387 | op = cfc_op; | |
9355e59c | 388 | else if (insn.mm_fp1_format.op == mm_ctc1_op) |
102cedc3 | 389 | op = ctc_op; |
9355e59c SH |
390 | else if (insn.mm_fp1_format.op == mm_mfhc1_op) |
391 | op = mfhc_op; | |
392 | else | |
393 | op = mthc_op; | |
102cedc3 LY |
394 | mips32_insn.fp1_format.opcode = cop1_op; |
395 | mips32_insn.fp1_format.op = op; | |
396 | mips32_insn.fp1_format.rt = | |
397 | insn.mm_fp1_format.rt; | |
398 | mips32_insn.fp1_format.fs = | |
399 | insn.mm_fp1_format.fs; | |
400 | mips32_insn.fp1_format.fd = 0; | |
401 | mips32_insn.fp1_format.func = 0; | |
402 | break; | |
403 | default: | |
404 | return SIGILL; | |
102cedc3 LY |
405 | } |
406 | break; | |
407 | case mm_32f_74_op: /* c.cond.fmt */ | |
408 | mips32_insn.fp0_format.opcode = cop1_op; | |
409 | mips32_insn.fp0_format.fmt = | |
410 | sdps_format[insn.mm_fp4_format.fmt]; | |
411 | mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt; | |
412 | mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs; | |
413 | mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2; | |
414 | mips32_insn.fp0_format.func = | |
415 | insn.mm_fp4_format.cond | MM_MIPS32_COND_FC; | |
416 | break; | |
417 | default: | |
418 | return SIGILL; | |
102cedc3 LY |
419 | } |
420 | break; | |
421 | default: | |
422 | return SIGILL; | |
102cedc3 LY |
423 | } |
424 | ||
425 | *insn_ptr = mips32_insn; | |
426 | return 0; | |
427 | } | |
428 | ||
1da177e4 LT |
429 | /* |
430 | * Redundant with logic already in kernel/branch.c, | |
431 | * embedded in compute_return_epc. At some point, | |
432 | * a single subroutine should be used across both | |
433 | * modules. | |
434 | */ | |
102cedc3 LY |
435 | static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, |
436 | unsigned long *contpc) | |
1da177e4 | 437 | { |
102cedc3 LY |
438 | union mips_instruction insn = (union mips_instruction)dec_insn.insn; |
439 | unsigned int fcr31; | |
440 | unsigned int bit = 0; | |
441 | ||
442 | switch (insn.i_format.opcode) { | |
1da177e4 | 443 | case spec_op: |
102cedc3 | 444 | switch (insn.r_format.func) { |
1da177e4 | 445 | case jalr_op: |
102cedc3 LY |
446 | regs->regs[insn.r_format.rd] = |
447 | regs->cp0_epc + dec_insn.pc_inc + | |
448 | dec_insn.next_pc_inc; | |
449 | /* Fall through */ | |
1da177e4 | 450 | case jr_op: |
5f9f41c4 MC |
451 | /* For R6, JR already emulated in jalr_op */ |
452 | if (NO_R6EMU && insn.r_format.opcode == jr_op) | |
453 | break; | |
102cedc3 | 454 | *contpc = regs->regs[insn.r_format.rs]; |
1da177e4 LT |
455 | return 1; |
456 | } | |
457 | break; | |
1da177e4 | 458 | case bcond_op: |
102cedc3 LY |
459 | switch (insn.i_format.rt) { |
460 | case bltzal_op: | |
461 | case bltzall_op: | |
319824ea MC |
462 | if (NO_R6EMU && (insn.i_format.rs || |
463 | insn.i_format.rt == bltzall_op)) | |
464 | break; | |
465 | ||
102cedc3 LY |
466 | regs->regs[31] = regs->cp0_epc + |
467 | dec_insn.pc_inc + | |
468 | dec_insn.next_pc_inc; | |
469 | /* Fall through */ | |
1da177e4 | 470 | case bltzl_op: |
319824ea MC |
471 | if (NO_R6EMU) |
472 | break; | |
473 | case bltz_op: | |
102cedc3 LY |
474 | if ((long)regs->regs[insn.i_format.rs] < 0) |
475 | *contpc = regs->cp0_epc + | |
476 | dec_insn.pc_inc + | |
477 | (insn.i_format.simmediate << 2); | |
478 | else | |
479 | *contpc = regs->cp0_epc + | |
480 | dec_insn.pc_inc + | |
481 | dec_insn.next_pc_inc; | |
482 | return 1; | |
1da177e4 | 483 | case bgezal_op: |
1da177e4 | 484 | case bgezall_op: |
319824ea MC |
485 | if (NO_R6EMU && (insn.i_format.rs || |
486 | insn.i_format.rt == bgezall_op)) | |
487 | break; | |
488 | ||
102cedc3 LY |
489 | regs->regs[31] = regs->cp0_epc + |
490 | dec_insn.pc_inc + | |
491 | dec_insn.next_pc_inc; | |
492 | /* Fall through */ | |
102cedc3 | 493 | case bgezl_op: |
319824ea MC |
494 | if (NO_R6EMU) |
495 | break; | |
496 | case bgez_op: | |
102cedc3 LY |
497 | if ((long)regs->regs[insn.i_format.rs] >= 0) |
498 | *contpc = regs->cp0_epc + | |
499 | dec_insn.pc_inc + | |
500 | (insn.i_format.simmediate << 2); | |
501 | else | |
502 | *contpc = regs->cp0_epc + | |
503 | dec_insn.pc_inc + | |
504 | dec_insn.next_pc_inc; | |
1da177e4 LT |
505 | return 1; |
506 | } | |
507 | break; | |
1da177e4 | 508 | case jalx_op: |
102cedc3 LY |
509 | set_isa16_mode(bit); |
510 | case jal_op: | |
511 | regs->regs[31] = regs->cp0_epc + | |
512 | dec_insn.pc_inc + | |
513 | dec_insn.next_pc_inc; | |
514 | /* Fall through */ | |
515 | case j_op: | |
516 | *contpc = regs->cp0_epc + dec_insn.pc_inc; | |
517 | *contpc >>= 28; | |
518 | *contpc <<= 28; | |
519 | *contpc |= (insn.j_format.target << 2); | |
520 | /* Set microMIPS mode bit: XOR for jalx. */ | |
521 | *contpc ^= bit; | |
522 | return 1; | |
1da177e4 | 523 | case beql_op: |
319824ea MC |
524 | if (NO_R6EMU) |
525 | break; | |
526 | case beq_op: | |
102cedc3 LY |
527 | if (regs->regs[insn.i_format.rs] == |
528 | regs->regs[insn.i_format.rt]) | |
529 | *contpc = regs->cp0_epc + | |
530 | dec_insn.pc_inc + | |
531 | (insn.i_format.simmediate << 2); | |
532 | else | |
533 | *contpc = regs->cp0_epc + | |
534 | dec_insn.pc_inc + | |
535 | dec_insn.next_pc_inc; | |
536 | return 1; | |
1da177e4 | 537 | case bnel_op: |
319824ea MC |
538 | if (NO_R6EMU) |
539 | break; | |
540 | case bne_op: | |
102cedc3 LY |
541 | if (regs->regs[insn.i_format.rs] != |
542 | regs->regs[insn.i_format.rt]) | |
543 | *contpc = regs->cp0_epc + | |
544 | dec_insn.pc_inc + | |
545 | (insn.i_format.simmediate << 2); | |
546 | else | |
547 | *contpc = regs->cp0_epc + | |
548 | dec_insn.pc_inc + | |
549 | dec_insn.next_pc_inc; | |
550 | return 1; | |
1da177e4 | 551 | case blezl_op: |
319824ea MC |
552 | if (NO_R6EMU) |
553 | break; | |
554 | case blez_op: | |
a8ff66f5 MC |
555 | |
556 | /* | |
557 | * Compact branches for R6 for the | |
558 | * blez and blezl opcodes. | |
559 | * BLEZ | rs = 0 | rt != 0 == BLEZALC | |
560 | * BLEZ | rs = rt != 0 == BGEZALC | |
561 | * BLEZ | rs != 0 | rt != 0 == BGEUC | |
562 | * BLEZL | rs = 0 | rt != 0 == BLEZC | |
563 | * BLEZL | rs = rt != 0 == BGEZC | |
564 | * BLEZL | rs != 0 | rt != 0 == BGEC | |
565 | * | |
566 | * For real BLEZ{,L}, rt is always 0. | |
567 | */ | |
568 | if (cpu_has_mips_r6 && insn.i_format.rt) { | |
569 | if ((insn.i_format.opcode == blez_op) && | |
570 | ((!insn.i_format.rs && insn.i_format.rt) || | |
571 | (insn.i_format.rs == insn.i_format.rt))) | |
572 | regs->regs[31] = regs->cp0_epc + | |
573 | dec_insn.pc_inc; | |
574 | *contpc = regs->cp0_epc + dec_insn.pc_inc + | |
575 | dec_insn.next_pc_inc; | |
576 | ||
577 | return 1; | |
578 | } | |
102cedc3 LY |
579 | if ((long)regs->regs[insn.i_format.rs] <= 0) |
580 | *contpc = regs->cp0_epc + | |
581 | dec_insn.pc_inc + | |
582 | (insn.i_format.simmediate << 2); | |
583 | else | |
584 | *contpc = regs->cp0_epc + | |
585 | dec_insn.pc_inc + | |
586 | dec_insn.next_pc_inc; | |
587 | return 1; | |
1da177e4 | 588 | case bgtzl_op: |
319824ea MC |
589 | if (NO_R6EMU) |
590 | break; | |
591 | case bgtz_op: | |
f1b44067 MC |
592 | /* |
593 | * Compact branches for R6 for the | |
594 | * bgtz and bgtzl opcodes. | |
595 | * BGTZ | rs = 0 | rt != 0 == BGTZALC | |
596 | * BGTZ | rs = rt != 0 == BLTZALC | |
597 | * BGTZ | rs != 0 | rt != 0 == BLTUC | |
598 | * BGTZL | rs = 0 | rt != 0 == BGTZC | |
599 | * BGTZL | rs = rt != 0 == BLTZC | |
600 | * BGTZL | rs != 0 | rt != 0 == BLTC | |
601 | * | |
602 | * *ZALC varint for BGTZ &&& rt != 0 | |
603 | * For real GTZ{,L}, rt is always 0. | |
604 | */ | |
605 | if (cpu_has_mips_r6 && insn.i_format.rt) { | |
606 | if ((insn.i_format.opcode == blez_op) && | |
607 | ((!insn.i_format.rs && insn.i_format.rt) || | |
608 | (insn.i_format.rs == insn.i_format.rt))) | |
609 | regs->regs[31] = regs->cp0_epc + | |
610 | dec_insn.pc_inc; | |
611 | *contpc = regs->cp0_epc + dec_insn.pc_inc + | |
612 | dec_insn.next_pc_inc; | |
613 | ||
614 | return 1; | |
615 | } | |
616 | ||
102cedc3 LY |
617 | if ((long)regs->regs[insn.i_format.rs] > 0) |
618 | *contpc = regs->cp0_epc + | |
619 | dec_insn.pc_inc + | |
620 | (insn.i_format.simmediate << 2); | |
621 | else | |
622 | *contpc = regs->cp0_epc + | |
623 | dec_insn.pc_inc + | |
624 | dec_insn.next_pc_inc; | |
1da177e4 | 625 | return 1; |
c893ce38 | 626 | case cbcond0_op: |
10d962d5 | 627 | case cbcond1_op: |
c893ce38 MC |
628 | if (!cpu_has_mips_r6) |
629 | break; | |
630 | if (insn.i_format.rt && !insn.i_format.rs) | |
631 | regs->regs[31] = regs->cp0_epc + 4; | |
632 | *contpc = regs->cp0_epc + dec_insn.pc_inc + | |
633 | dec_insn.next_pc_inc; | |
634 | ||
635 | return 1; | |
c26d4219 DD |
636 | #ifdef CONFIG_CPU_CAVIUM_OCTEON |
637 | case lwc2_op: /* This is bbit0 on Octeon */ | |
638 | if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0) | |
639 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
640 | else | |
641 | *contpc = regs->cp0_epc + 8; | |
642 | return 1; | |
643 | case ldc2_op: /* This is bbit032 on Octeon */ | |
644 | if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0) | |
645 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
646 | else | |
647 | *contpc = regs->cp0_epc + 8; | |
648 | return 1; | |
649 | case swc2_op: /* This is bbit1 on Octeon */ | |
650 | if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) | |
651 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
652 | else | |
653 | *contpc = regs->cp0_epc + 8; | |
654 | return 1; | |
655 | case sdc2_op: /* This is bbit132 on Octeon */ | |
656 | if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) | |
657 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
658 | else | |
659 | *contpc = regs->cp0_epc + 8; | |
660 | return 1; | |
8467ca01 MC |
661 | #else |
662 | case bc6_op: | |
663 | /* | |
664 | * Only valid for MIPS R6 but we can still end up | |
665 | * here from a broken userland so just tell emulator | |
666 | * this is not a branch and let it break later on. | |
667 | */ | |
668 | if (!cpu_has_mips_r6) | |
669 | break; | |
670 | *contpc = regs->cp0_epc + dec_insn.pc_inc + | |
671 | dec_insn.next_pc_inc; | |
672 | ||
84fef630 MC |
673 | return 1; |
674 | case balc6_op: | |
675 | if (!cpu_has_mips_r6) | |
676 | break; | |
677 | regs->regs[31] = regs->cp0_epc + 4; | |
678 | *contpc = regs->cp0_epc + dec_insn.pc_inc + | |
679 | dec_insn.next_pc_inc; | |
680 | ||
8467ca01 | 681 | return 1; |
c26d4219 | 682 | #endif |
1da177e4 LT |
683 | case cop0_op: |
684 | case cop1_op: | |
c8a34581 MC |
685 | /* Need to check for R6 bc1nez and bc1eqz branches */ |
686 | if (cpu_has_mips_r6 && | |
687 | ((insn.i_format.rs == bc1eqz_op) || | |
688 | (insn.i_format.rs == bc1nez_op))) { | |
689 | bit = 0; | |
690 | switch (insn.i_format.rs) { | |
691 | case bc1eqz_op: | |
692 | if (get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1) | |
693 | bit = 1; | |
694 | break; | |
695 | case bc1nez_op: | |
696 | if (!(get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)) | |
697 | bit = 1; | |
698 | break; | |
699 | } | |
700 | if (bit) | |
701 | *contpc = regs->cp0_epc + | |
702 | dec_insn.pc_inc + | |
703 | (insn.i_format.simmediate << 2); | |
704 | else | |
705 | *contpc = regs->cp0_epc + | |
706 | dec_insn.pc_inc + | |
707 | dec_insn.next_pc_inc; | |
708 | ||
709 | return 1; | |
710 | } | |
711 | /* R2/R6 compatible cop1 instruction. Fall through */ | |
1da177e4 LT |
712 | case cop2_op: |
713 | case cop1x_op: | |
102cedc3 LY |
714 | if (insn.i_format.rs == bc_op) { |
715 | preempt_disable(); | |
716 | if (is_fpu_owner()) | |
842dfc11 | 717 | fcr31 = read_32bit_cp1_register(CP1_STATUS); |
102cedc3 LY |
718 | else |
719 | fcr31 = current->thread.fpu.fcr31; | |
720 | preempt_enable(); | |
721 | ||
722 | bit = (insn.i_format.rt >> 2); | |
723 | bit += (bit != 0); | |
724 | bit += 23; | |
725 | switch (insn.i_format.rt & 3) { | |
726 | case 0: /* bc1f */ | |
727 | case 2: /* bc1fl */ | |
728 | if (~fcr31 & (1 << bit)) | |
729 | *contpc = regs->cp0_epc + | |
730 | dec_insn.pc_inc + | |
731 | (insn.i_format.simmediate << 2); | |
732 | else | |
733 | *contpc = regs->cp0_epc + | |
734 | dec_insn.pc_inc + | |
735 | dec_insn.next_pc_inc; | |
736 | return 1; | |
102cedc3 LY |
737 | case 1: /* bc1t */ |
738 | case 3: /* bc1tl */ | |
739 | if (fcr31 & (1 << bit)) | |
740 | *contpc = regs->cp0_epc + | |
741 | dec_insn.pc_inc + | |
742 | (insn.i_format.simmediate << 2); | |
743 | else | |
744 | *contpc = regs->cp0_epc + | |
745 | dec_insn.pc_inc + | |
746 | dec_insn.next_pc_inc; | |
747 | return 1; | |
102cedc3 LY |
748 | } |
749 | } | |
1da177e4 LT |
750 | break; |
751 | } | |
1da177e4 LT |
752 | return 0; |
753 | } | |
754 | ||
755 | /* | |
756 | * In the Linux kernel, we support selection of FPR format on the | |
70342287 | 757 | * basis of the Status.FR bit. If an FPU is not present, the FR bit |
da0bac33 | 758 | * is hardwired to zero, which would imply a 32-bit FPU even for |
597ce172 | 759 | * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS. |
51d943f0 RB |
760 | * FPU emu is slow and bulky and optimizing this function offers fairly |
761 | * sizeable benefits so we try to be clever and make this function return | |
762 | * a constant whenever possible, that is on 64-bit kernels without O32 | |
597ce172 | 763 | * compatibility enabled and on 32-bit without 64-bit FPU support. |
1da177e4 | 764 | */ |
da0bac33 DD |
765 | static inline int cop1_64bit(struct pt_regs *xcp) |
766 | { | |
08a07904 RB |
767 | if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32)) |
768 | return 1; | |
769 | else if (config_enabled(CONFIG_32BIT) && | |
770 | !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT)) | |
771 | return 0; | |
772 | ||
597ce172 | 773 | return !test_thread_flag(TIF_32BIT_FPREGS); |
da0bac33 DD |
774 | } |
775 | ||
4227a2d4 PB |
776 | static inline bool hybrid_fprs(void) |
777 | { | |
778 | return test_thread_flag(TIF_HYBRID_FPREGS); | |
779 | } | |
780 | ||
47fa0c02 RB |
781 | #define SIFROMREG(si, x) \ |
782 | do { \ | |
4227a2d4 | 783 | if (cop1_64bit(xcp) && !hybrid_fprs()) \ |
c8c0da6b | 784 | (si) = (int)get_fpr32(&ctx->fpr[x], 0); \ |
bbd426f5 | 785 | else \ |
c8c0da6b | 786 | (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \ |
bbd426f5 | 787 | } while (0) |
1da177e4 | 788 | |
47fa0c02 RB |
789 | #define SITOREG(si, x) \ |
790 | do { \ | |
4227a2d4 | 791 | if (cop1_64bit(xcp) && !hybrid_fprs()) { \ |
ef1c47af | 792 | unsigned i; \ |
bbd426f5 | 793 | set_fpr32(&ctx->fpr[x], 0, si); \ |
ef1c47af PB |
794 | for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ |
795 | set_fpr32(&ctx->fpr[x], i, 0); \ | |
796 | } else { \ | |
bbd426f5 | 797 | set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \ |
ef1c47af | 798 | } \ |
bbd426f5 | 799 | } while (0) |
1da177e4 | 800 | |
c8c0da6b | 801 | #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1)) |
ef1c47af | 802 | |
47fa0c02 RB |
803 | #define SITOHREG(si, x) \ |
804 | do { \ | |
ef1c47af PB |
805 | unsigned i; \ |
806 | set_fpr32(&ctx->fpr[x], 1, si); \ | |
807 | for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ | |
808 | set_fpr32(&ctx->fpr[x], i, 0); \ | |
809 | } while (0) | |
1ac94400 | 810 | |
47fa0c02 | 811 | #define DIFROMREG(di, x) \ |
bbd426f5 PB |
812 | ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0)) |
813 | ||
47fa0c02 RB |
814 | #define DITOREG(di, x) \ |
815 | do { \ | |
ef1c47af PB |
816 | unsigned fpr, i; \ |
817 | fpr = (x) & ~(cop1_64bit(xcp) == 0); \ | |
818 | set_fpr64(&ctx->fpr[fpr], 0, di); \ | |
819 | for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \ | |
820 | set_fpr64(&ctx->fpr[fpr], i, 0); \ | |
821 | } while (0) | |
1da177e4 | 822 | |
21a151d8 RB |
823 | #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x) |
824 | #define SPTOREG(sp, x) SITOREG((sp).bits, x) | |
825 | #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x) | |
826 | #define DPTOREG(dp, x) DITOREG((dp).bits, x) | |
1da177e4 LT |
827 | |
828 | /* | |
829 | * Emulate the single floating point instruction pointed at by EPC. | |
830 | * Two instructions if the instruction is in a branch delay slot. | |
831 | */ | |
832 | ||
515b029d | 833 | static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
102cedc3 | 834 | struct mm_decoded_insn dec_insn, void *__user *fault_addr) |
1da177e4 | 835 | { |
102cedc3 | 836 | unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; |
3f7cac41 RB |
837 | unsigned int cond, cbit; |
838 | mips_instruction ir; | |
839 | int likely, pc_inc; | |
840 | u32 __user *wva; | |
841 | u64 __user *dva; | |
842 | u32 value; | |
843 | u32 wval; | |
844 | u64 dval; | |
845 | int sig; | |
1da177e4 | 846 | |
70e4c234 RB |
847 | /* |
848 | * These are giving gcc a gentle hint about what to expect in | |
849 | * dec_inst in order to do better optimization. | |
850 | */ | |
851 | if (!cpu_has_mmips && dec_insn.micro_mips_mode) | |
852 | unreachable(); | |
853 | ||
1da177e4 | 854 | /* XXX NEC Vr54xx bug workaround */ |
e7e9cae5 | 855 | if (delay_slot(xcp)) { |
102cedc3 LY |
856 | if (dec_insn.micro_mips_mode) { |
857 | if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) | |
e7e9cae5 | 858 | clear_delay_slot(xcp); |
102cedc3 LY |
859 | } else { |
860 | if (!isBranchInstr(xcp, dec_insn, &contpc)) | |
e7e9cae5 | 861 | clear_delay_slot(xcp); |
102cedc3 LY |
862 | } |
863 | } | |
1da177e4 | 864 | |
e7e9cae5 | 865 | if (delay_slot(xcp)) { |
1da177e4 LT |
866 | /* |
867 | * The instruction to be emulated is in a branch delay slot | |
70342287 | 868 | * which means that we have to emulate the branch instruction |
1da177e4 LT |
869 | * BEFORE we do the cop1 instruction. |
870 | * | |
871 | * This branch could be a COP1 branch, but in that case we | |
872 | * would have had a trap for that instruction, and would not | |
873 | * come through this route. | |
874 | * | |
875 | * Linux MIPS branch emulator operates on context, updating the | |
876 | * cp0_epc. | |
877 | */ | |
102cedc3 LY |
878 | ir = dec_insn.next_insn; /* process delay slot instr */ |
879 | pc_inc = dec_insn.next_pc_inc; | |
880 | } else { | |
881 | ir = dec_insn.insn; /* process current instr */ | |
882 | pc_inc = dec_insn.pc_inc; | |
883 | } | |
1da177e4 | 884 | |
102cedc3 LY |
885 | /* |
886 | * Since microMIPS FPU instructios are a subset of MIPS32 FPU | |
887 | * instructions, we want to convert microMIPS FPU instructions | |
888 | * into MIPS32 instructions so that we could reuse all of the | |
889 | * FPU emulation code. | |
890 | * | |
891 | * NOTE: We cannot do this for branch instructions since they | |
892 | * are not a subset. Example: Cannot emulate a 16-bit | |
893 | * aligned target address with a MIPS32 instruction. | |
894 | */ | |
895 | if (dec_insn.micro_mips_mode) { | |
896 | /* | |
897 | * If next instruction is a 16-bit instruction, then it | |
898 | * it cannot be a FPU instruction. This could happen | |
899 | * since we can be called for non-FPU instructions. | |
900 | */ | |
901 | if ((pc_inc == 2) || | |
902 | (microMIPS32_to_MIPS32((union mips_instruction *)&ir) | |
903 | == SIGILL)) | |
1da177e4 | 904 | return SIGILL; |
1da177e4 LT |
905 | } |
906 | ||
3f7cac41 | 907 | emul: |
a8b0ca17 | 908 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0); |
b6ee75ed | 909 | MIPS_FPU_EMU_INC_STATS(emulated); |
1da177e4 | 910 | switch (MIPSInst_OPCODE(ir)) { |
3f7cac41 RB |
911 | case ldc1_op: |
912 | dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + | |
913 | MIPSInst_SIMM(ir)); | |
b6ee75ed | 914 | MIPS_FPU_EMU_INC_STATS(loads); |
515b029d | 915 | |
3f7cac41 | 916 | if (!access_ok(VERIFY_READ, dva, sizeof(u64))) { |
b6ee75ed | 917 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 918 | *fault_addr = dva; |
1da177e4 LT |
919 | return SIGBUS; |
920 | } | |
3f7cac41 | 921 | if (__get_user(dval, dva)) { |
515b029d | 922 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 923 | *fault_addr = dva; |
515b029d DD |
924 | return SIGSEGV; |
925 | } | |
3f7cac41 | 926 | DITOREG(dval, MIPSInst_RT(ir)); |
1da177e4 | 927 | break; |
1da177e4 | 928 | |
3f7cac41 RB |
929 | case sdc1_op: |
930 | dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + | |
931 | MIPSInst_SIMM(ir)); | |
b6ee75ed | 932 | MIPS_FPU_EMU_INC_STATS(stores); |
3f7cac41 RB |
933 | DIFROMREG(dval, MIPSInst_RT(ir)); |
934 | if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) { | |
b6ee75ed | 935 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 936 | *fault_addr = dva; |
1da177e4 LT |
937 | return SIGBUS; |
938 | } | |
3f7cac41 | 939 | if (__put_user(dval, dva)) { |
515b029d | 940 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 941 | *fault_addr = dva; |
515b029d DD |
942 | return SIGSEGV; |
943 | } | |
1da177e4 | 944 | break; |
1da177e4 | 945 | |
3f7cac41 RB |
946 | case lwc1_op: |
947 | wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + | |
948 | MIPSInst_SIMM(ir)); | |
b6ee75ed | 949 | MIPS_FPU_EMU_INC_STATS(loads); |
3f7cac41 | 950 | if (!access_ok(VERIFY_READ, wva, sizeof(u32))) { |
b6ee75ed | 951 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 952 | *fault_addr = wva; |
1da177e4 LT |
953 | return SIGBUS; |
954 | } | |
3f7cac41 | 955 | if (__get_user(wval, wva)) { |
515b029d | 956 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 957 | *fault_addr = wva; |
515b029d DD |
958 | return SIGSEGV; |
959 | } | |
3f7cac41 | 960 | SITOREG(wval, MIPSInst_RT(ir)); |
1da177e4 | 961 | break; |
1da177e4 | 962 | |
3f7cac41 RB |
963 | case swc1_op: |
964 | wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + | |
965 | MIPSInst_SIMM(ir)); | |
b6ee75ed | 966 | MIPS_FPU_EMU_INC_STATS(stores); |
3f7cac41 RB |
967 | SIFROMREG(wval, MIPSInst_RT(ir)); |
968 | if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) { | |
b6ee75ed | 969 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 970 | *fault_addr = wva; |
1da177e4 LT |
971 | return SIGBUS; |
972 | } | |
3f7cac41 | 973 | if (__put_user(wval, wva)) { |
515b029d | 974 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 975 | *fault_addr = wva; |
515b029d DD |
976 | return SIGSEGV; |
977 | } | |
1da177e4 | 978 | break; |
1da177e4 LT |
979 | |
980 | case cop1_op: | |
981 | switch (MIPSInst_RS(ir)) { | |
1da177e4 | 982 | case dmfc_op: |
08a07904 RB |
983 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
984 | return SIGILL; | |
985 | ||
1da177e4 LT |
986 | /* copregister fs -> gpr[rt] */ |
987 | if (MIPSInst_RT(ir) != 0) { | |
988 | DIFROMREG(xcp->regs[MIPSInst_RT(ir)], | |
989 | MIPSInst_RD(ir)); | |
990 | } | |
991 | break; | |
992 | ||
993 | case dmtc_op: | |
08a07904 RB |
994 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
995 | return SIGILL; | |
996 | ||
1da177e4 LT |
997 | /* copregister fs <- rt */ |
998 | DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); | |
999 | break; | |
1da177e4 | 1000 | |
1ac94400 LY |
1001 | case mfhc_op: |
1002 | if (!cpu_has_mips_r2) | |
1003 | goto sigill; | |
1004 | ||
1005 | /* copregister rd -> gpr[rt] */ | |
1006 | if (MIPSInst_RT(ir) != 0) { | |
1007 | SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], | |
1008 | MIPSInst_RD(ir)); | |
1009 | } | |
1010 | break; | |
1011 | ||
1012 | case mthc_op: | |
1013 | if (!cpu_has_mips_r2) | |
1014 | goto sigill; | |
1015 | ||
1016 | /* copregister rd <- gpr[rt] */ | |
1017 | SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); | |
1018 | break; | |
1019 | ||
1da177e4 LT |
1020 | case mfc_op: |
1021 | /* copregister rd -> gpr[rt] */ | |
1da177e4 LT |
1022 | if (MIPSInst_RT(ir) != 0) { |
1023 | SIFROMREG(xcp->regs[MIPSInst_RT(ir)], | |
1024 | MIPSInst_RD(ir)); | |
1025 | } | |
1026 | break; | |
1027 | ||
1028 | case mtc_op: | |
1029 | /* copregister rd <- rt */ | |
1da177e4 LT |
1030 | SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); |
1031 | break; | |
1032 | ||
3f7cac41 | 1033 | case cfc_op: |
1da177e4 | 1034 | /* cop control register rd -> gpr[rt] */ |
1da177e4 LT |
1035 | if (MIPSInst_RD(ir) == FPCREG_CSR) { |
1036 | value = ctx->fcr31; | |
56a64733 | 1037 | value = (value & ~FPU_CSR_RM) | modeindex(value); |
92df0f8b RB |
1038 | pr_debug("%p gpr[%d]<-csr=%08x\n", |
1039 | (void *) (xcp->cp0_epc), | |
1040 | MIPSInst_RT(ir), value); | |
1da177e4 LT |
1041 | } |
1042 | else if (MIPSInst_RD(ir) == FPCREG_RID) | |
1043 | value = 0; | |
1044 | else | |
1045 | value = 0; | |
1046 | if (MIPSInst_RT(ir)) | |
1047 | xcp->regs[MIPSInst_RT(ir)] = value; | |
1048 | break; | |
1da177e4 | 1049 | |
3f7cac41 | 1050 | case ctc_op: |
1da177e4 | 1051 | /* copregister rd <- rt */ |
1da177e4 LT |
1052 | if (MIPSInst_RT(ir) == 0) |
1053 | value = 0; | |
1054 | else | |
1055 | value = xcp->regs[MIPSInst_RT(ir)]; | |
1056 | ||
1057 | /* we only have one writable control reg | |
1058 | */ | |
1059 | if (MIPSInst_RD(ir) == FPCREG_CSR) { | |
92df0f8b RB |
1060 | pr_debug("%p gpr[%d]->csr=%08x\n", |
1061 | (void *) (xcp->cp0_epc), | |
1062 | MIPSInst_RT(ir), value); | |
95e8f634 SM |
1063 | |
1064 | /* | |
1065 | * Don't write reserved bits, | |
1066 | * and convert to ieee library modes | |
1067 | */ | |
56a64733 RB |
1068 | ctx->fcr31 = (value & ~(FPU_CSR_RSVD | FPU_CSR_RM)) | |
1069 | modeindex(value); | |
1da177e4 LT |
1070 | } |
1071 | if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { | |
1072 | return SIGFPE; | |
1073 | } | |
1074 | break; | |
1da177e4 | 1075 | |
3f7cac41 | 1076 | case bc_op: |
e7e9cae5 | 1077 | if (delay_slot(xcp)) |
1da177e4 LT |
1078 | return SIGILL; |
1079 | ||
08a07904 RB |
1080 | if (cpu_has_mips_4_5_r) |
1081 | cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; | |
1082 | else | |
1083 | cbit = FPU_CSR_COND; | |
1084 | cond = ctx->fcr31 & cbit; | |
1085 | ||
3f7cac41 | 1086 | likely = 0; |
1da177e4 LT |
1087 | switch (MIPSInst_RT(ir) & 3) { |
1088 | case bcfl_op: | |
1089 | likely = 1; | |
1090 | case bcf_op: | |
1091 | cond = !cond; | |
1092 | break; | |
1093 | case bctl_op: | |
1094 | likely = 1; | |
1095 | case bct_op: | |
1096 | break; | |
1097 | default: | |
1098 | /* thats an illegal instruction */ | |
1099 | return SIGILL; | |
1100 | } | |
1101 | ||
e7e9cae5 | 1102 | set_delay_slot(xcp); |
1da177e4 | 1103 | if (cond) { |
3f7cac41 RB |
1104 | /* |
1105 | * Branch taken: emulate dslot instruction | |
1da177e4 | 1106 | */ |
102cedc3 LY |
1107 | xcp->cp0_epc += dec_insn.pc_inc; |
1108 | ||
1109 | contpc = MIPSInst_SIMM(ir); | |
1110 | ir = dec_insn.next_insn; | |
1111 | if (dec_insn.micro_mips_mode) { | |
1112 | contpc = (xcp->cp0_epc + (contpc << 1)); | |
1113 | ||
1114 | /* If 16-bit instruction, not FPU. */ | |
1115 | if ((dec_insn.next_pc_inc == 2) || | |
1116 | (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) { | |
1117 | ||
1118 | /* | |
1119 | * Since this instruction will | |
1120 | * be put on the stack with | |
1121 | * 32-bit words, get around | |
1122 | * this problem by putting a | |
1123 | * NOP16 as the second one. | |
1124 | */ | |
1125 | if (dec_insn.next_pc_inc == 2) | |
1126 | ir = (ir & (~0xffff)) | MM_NOP16; | |
1127 | ||
1128 | /* | |
1129 | * Single step the non-CP1 | |
1130 | * instruction in the dslot. | |
1131 | */ | |
1132 | return mips_dsemul(xcp, ir, contpc); | |
1133 | } | |
1134 | } else | |
1135 | contpc = (xcp->cp0_epc + (contpc << 2)); | |
1da177e4 LT |
1136 | |
1137 | switch (MIPSInst_OPCODE(ir)) { | |
1138 | case lwc1_op: | |
08a07904 | 1139 | goto emul; |
3f7cac41 | 1140 | |
1da177e4 | 1141 | case swc1_op: |
08a07904 | 1142 | goto emul; |
3f7cac41 | 1143 | |
1da177e4 LT |
1144 | case ldc1_op: |
1145 | case sdc1_op: | |
08a07904 RB |
1146 | if (cpu_has_mips_2_3_4_5 || |
1147 | cpu_has_mips64) | |
1148 | goto emul; | |
1149 | ||
1150 | return SIGILL; | |
1151 | goto emul; | |
3f7cac41 | 1152 | |
1da177e4 | 1153 | case cop1_op: |
1da177e4 | 1154 | goto emul; |
3f7cac41 | 1155 | |
08a07904 | 1156 | case cop1x_op: |
a5466d7b | 1157 | if (cpu_has_mips_4_5 || cpu_has_mips64 || cpu_has_mips32r2) |
08a07904 RB |
1158 | /* its one of ours */ |
1159 | goto emul; | |
1160 | ||
1161 | return SIGILL; | |
3f7cac41 | 1162 | |
1da177e4 | 1163 | case spec_op: |
08a07904 RB |
1164 | if (!cpu_has_mips_4_5_r) |
1165 | return SIGILL; | |
1166 | ||
1da177e4 LT |
1167 | if (MIPSInst_FUNC(ir) == movc_op) |
1168 | goto emul; | |
1169 | break; | |
1da177e4 LT |
1170 | } |
1171 | ||
1172 | /* | |
1173 | * Single step the non-cp1 | |
1174 | * instruction in the dslot | |
1175 | */ | |
e70dfc10 | 1176 | return mips_dsemul(xcp, ir, contpc); |
3f7cac41 | 1177 | } else if (likely) { /* branch not taken */ |
1da177e4 LT |
1178 | /* |
1179 | * branch likely nullifies | |
1180 | * dslot if not taken | |
1181 | */ | |
102cedc3 LY |
1182 | xcp->cp0_epc += dec_insn.pc_inc; |
1183 | contpc += dec_insn.pc_inc; | |
1da177e4 LT |
1184 | /* |
1185 | * else continue & execute | |
1186 | * dslot as normal insn | |
1187 | */ | |
1188 | } | |
1da177e4 | 1189 | break; |
1da177e4 LT |
1190 | |
1191 | default: | |
1192 | if (!(MIPSInst_RS(ir) & 0x10)) | |
1193 | return SIGILL; | |
1da177e4 | 1194 | |
3f7cac41 RB |
1195 | /* a real fpu computation instruction */ |
1196 | if ((sig = fpu_emu(xcp, ctx, ir))) | |
1197 | return sig; | |
1da177e4 LT |
1198 | } |
1199 | break; | |
1200 | ||
3f7cac41 | 1201 | case cop1x_op: |
a5466d7b | 1202 | if (!cpu_has_mips_4_5 && !cpu_has_mips64 && !cpu_has_mips32r2) |
08a07904 RB |
1203 | return SIGILL; |
1204 | ||
1205 | sig = fpux_emu(xcp, ctx, ir, fault_addr); | |
515b029d | 1206 | if (sig) |
1da177e4 LT |
1207 | return sig; |
1208 | break; | |
1da177e4 | 1209 | |
1da177e4 | 1210 | case spec_op: |
08a07904 RB |
1211 | if (!cpu_has_mips_4_5_r) |
1212 | return SIGILL; | |
1213 | ||
1da177e4 LT |
1214 | if (MIPSInst_FUNC(ir) != movc_op) |
1215 | return SIGILL; | |
1216 | cond = fpucondbit[MIPSInst_RT(ir) >> 2]; | |
1217 | if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) | |
1218 | xcp->regs[MIPSInst_RD(ir)] = | |
1219 | xcp->regs[MIPSInst_RS(ir)]; | |
1220 | break; | |
1da177e4 | 1221 | default: |
1ac94400 | 1222 | sigill: |
1da177e4 LT |
1223 | return SIGILL; |
1224 | } | |
1225 | ||
1226 | /* we did it !! */ | |
e70dfc10 | 1227 | xcp->cp0_epc = contpc; |
e7e9cae5 | 1228 | clear_delay_slot(xcp); |
333d1f67 | 1229 | |
1da177e4 LT |
1230 | return 0; |
1231 | } | |
1232 | ||
1233 | /* | |
1234 | * Conversion table from MIPS compare ops 48-63 | |
1235 | * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig); | |
1236 | */ | |
1237 | static const unsigned char cmptab[8] = { | |
1238 | 0, /* cmp_0 (sig) cmp_sf */ | |
1239 | IEEE754_CUN, /* cmp_un (sig) cmp_ngle */ | |
1240 | IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */ | |
1241 | IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */ | |
1242 | IEEE754_CLT, /* cmp_olt (sig) cmp_lt */ | |
1243 | IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */ | |
1244 | IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */ | |
1245 | IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */ | |
1246 | }; | |
1247 | ||
1248 | ||
1da177e4 LT |
1249 | /* |
1250 | * Additional MIPS4 instructions | |
1251 | */ | |
1252 | ||
47fa0c02 RB |
1253 | #define DEF3OP(name, p, f1, f2, f3) \ |
1254 | static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \ | |
1255 | union ieee754##p s, union ieee754##p t) \ | |
1256 | { \ | |
1257 | struct _ieee754_csr ieee754_csr_save; \ | |
1258 | s = f1(s, t); \ | |
1259 | ieee754_csr_save = ieee754_csr; \ | |
1260 | s = f2(s, r); \ | |
1261 | ieee754_csr_save.cx |= ieee754_csr.cx; \ | |
1262 | ieee754_csr_save.sx |= ieee754_csr.sx; \ | |
1263 | s = f3(s); \ | |
1264 | ieee754_csr.cx |= ieee754_csr_save.cx; \ | |
1265 | ieee754_csr.sx |= ieee754_csr_save.sx; \ | |
1266 | return s; \ | |
1da177e4 LT |
1267 | } |
1268 | ||
2209bcb1 | 1269 | static union ieee754dp fpemu_dp_recip(union ieee754dp d) |
1da177e4 LT |
1270 | { |
1271 | return ieee754dp_div(ieee754dp_one(0), d); | |
1272 | } | |
1273 | ||
2209bcb1 | 1274 | static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d) |
1da177e4 LT |
1275 | { |
1276 | return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d)); | |
1277 | } | |
1278 | ||
2209bcb1 | 1279 | static union ieee754sp fpemu_sp_recip(union ieee754sp s) |
1da177e4 LT |
1280 | { |
1281 | return ieee754sp_div(ieee754sp_one(0), s); | |
1282 | } | |
1283 | ||
2209bcb1 | 1284 | static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s) |
1da177e4 LT |
1285 | { |
1286 | return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); | |
1287 | } | |
1288 | ||
21a151d8 RB |
1289 | DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, ); |
1290 | DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, ); | |
1da177e4 LT |
1291 | DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); |
1292 | DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); | |
21a151d8 RB |
1293 | DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, ); |
1294 | DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, ); | |
1da177e4 LT |
1295 | DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); |
1296 | DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); | |
1297 | ||
eae89076 | 1298 | static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
515b029d | 1299 | mips_instruction ir, void *__user *fault_addr) |
1da177e4 LT |
1300 | { |
1301 | unsigned rcsr = 0; /* resulting csr */ | |
1302 | ||
b6ee75ed | 1303 | MIPS_FPU_EMU_INC_STATS(cp1xops); |
1da177e4 LT |
1304 | |
1305 | switch (MIPSInst_FMA_FFMT(ir)) { | |
1306 | case s_fmt:{ /* 0 */ | |
1307 | ||
2209bcb1 RB |
1308 | union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp); |
1309 | union ieee754sp fd, fr, fs, ft; | |
3fccc015 | 1310 | u32 __user *va; |
1da177e4 LT |
1311 | u32 val; |
1312 | ||
1313 | switch (MIPSInst_FUNC(ir)) { | |
1314 | case lwxc1_op: | |
3fccc015 | 1315 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1316 | xcp->regs[MIPSInst_FT(ir)]); |
1317 | ||
b6ee75ed | 1318 | MIPS_FPU_EMU_INC_STATS(loads); |
515b029d | 1319 | if (!access_ok(VERIFY_READ, va, sizeof(u32))) { |
b6ee75ed | 1320 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1321 | *fault_addr = va; |
1da177e4 LT |
1322 | return SIGBUS; |
1323 | } | |
515b029d DD |
1324 | if (__get_user(val, va)) { |
1325 | MIPS_FPU_EMU_INC_STATS(errors); | |
1326 | *fault_addr = va; | |
1327 | return SIGSEGV; | |
1328 | } | |
1da177e4 LT |
1329 | SITOREG(val, MIPSInst_FD(ir)); |
1330 | break; | |
1331 | ||
1332 | case swxc1_op: | |
3fccc015 | 1333 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1334 | xcp->regs[MIPSInst_FT(ir)]); |
1335 | ||
b6ee75ed | 1336 | MIPS_FPU_EMU_INC_STATS(stores); |
1da177e4 LT |
1337 | |
1338 | SIFROMREG(val, MIPSInst_FS(ir)); | |
515b029d | 1339 | if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { |
b6ee75ed | 1340 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1341 | *fault_addr = va; |
1da177e4 LT |
1342 | return SIGBUS; |
1343 | } | |
515b029d DD |
1344 | if (put_user(val, va)) { |
1345 | MIPS_FPU_EMU_INC_STATS(errors); | |
1346 | *fault_addr = va; | |
1347 | return SIGSEGV; | |
1348 | } | |
1da177e4 LT |
1349 | break; |
1350 | ||
1351 | case madd_s_op: | |
1352 | handler = fpemu_sp_madd; | |
1353 | goto scoptop; | |
1354 | case msub_s_op: | |
1355 | handler = fpemu_sp_msub; | |
1356 | goto scoptop; | |
1357 | case nmadd_s_op: | |
1358 | handler = fpemu_sp_nmadd; | |
1359 | goto scoptop; | |
1360 | case nmsub_s_op: | |
1361 | handler = fpemu_sp_nmsub; | |
1362 | goto scoptop; | |
1363 | ||
1364 | scoptop: | |
1365 | SPFROMREG(fr, MIPSInst_FR(ir)); | |
1366 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1367 | SPFROMREG(ft, MIPSInst_FT(ir)); | |
1368 | fd = (*handler) (fr, fs, ft); | |
1369 | SPTOREG(fd, MIPSInst_FD(ir)); | |
1370 | ||
1371 | copcsr: | |
c4103526 DCZ |
1372 | if (ieee754_cxtest(IEEE754_INEXACT)) { |
1373 | MIPS_FPU_EMU_INC_STATS(ieee754_inexact); | |
1da177e4 | 1374 | rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; |
c4103526 DCZ |
1375 | } |
1376 | if (ieee754_cxtest(IEEE754_UNDERFLOW)) { | |
1377 | MIPS_FPU_EMU_INC_STATS(ieee754_underflow); | |
1da177e4 | 1378 | rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; |
c4103526 DCZ |
1379 | } |
1380 | if (ieee754_cxtest(IEEE754_OVERFLOW)) { | |
1381 | MIPS_FPU_EMU_INC_STATS(ieee754_overflow); | |
1da177e4 | 1382 | rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; |
c4103526 DCZ |
1383 | } |
1384 | if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { | |
1385 | MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); | |
1da177e4 | 1386 | rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; |
c4103526 | 1387 | } |
1da177e4 LT |
1388 | |
1389 | ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; | |
1da177e4 | 1390 | if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { |
3f7cac41 | 1391 | /*printk ("SIGFPE: FPU csr = %08x\n", |
1da177e4 LT |
1392 | ctx->fcr31); */ |
1393 | return SIGFPE; | |
1394 | } | |
1395 | ||
1396 | break; | |
1397 | ||
1398 | default: | |
1399 | return SIGILL; | |
1400 | } | |
1401 | break; | |
1402 | } | |
1403 | ||
1da177e4 | 1404 | case d_fmt:{ /* 1 */ |
2209bcb1 RB |
1405 | union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp); |
1406 | union ieee754dp fd, fr, fs, ft; | |
3fccc015 | 1407 | u64 __user *va; |
1da177e4 LT |
1408 | u64 val; |
1409 | ||
1410 | switch (MIPSInst_FUNC(ir)) { | |
1411 | case ldxc1_op: | |
3fccc015 | 1412 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1413 | xcp->regs[MIPSInst_FT(ir)]); |
1414 | ||
b6ee75ed | 1415 | MIPS_FPU_EMU_INC_STATS(loads); |
515b029d | 1416 | if (!access_ok(VERIFY_READ, va, sizeof(u64))) { |
b6ee75ed | 1417 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1418 | *fault_addr = va; |
1da177e4 LT |
1419 | return SIGBUS; |
1420 | } | |
515b029d DD |
1421 | if (__get_user(val, va)) { |
1422 | MIPS_FPU_EMU_INC_STATS(errors); | |
1423 | *fault_addr = va; | |
1424 | return SIGSEGV; | |
1425 | } | |
1da177e4 LT |
1426 | DITOREG(val, MIPSInst_FD(ir)); |
1427 | break; | |
1428 | ||
1429 | case sdxc1_op: | |
3fccc015 | 1430 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1431 | xcp->regs[MIPSInst_FT(ir)]); |
1432 | ||
b6ee75ed | 1433 | MIPS_FPU_EMU_INC_STATS(stores); |
1da177e4 | 1434 | DIFROMREG(val, MIPSInst_FS(ir)); |
515b029d | 1435 | if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { |
b6ee75ed | 1436 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1437 | *fault_addr = va; |
1da177e4 LT |
1438 | return SIGBUS; |
1439 | } | |
515b029d DD |
1440 | if (__put_user(val, va)) { |
1441 | MIPS_FPU_EMU_INC_STATS(errors); | |
1442 | *fault_addr = va; | |
1443 | return SIGSEGV; | |
1444 | } | |
1da177e4 LT |
1445 | break; |
1446 | ||
1447 | case madd_d_op: | |
1448 | handler = fpemu_dp_madd; | |
1449 | goto dcoptop; | |
1450 | case msub_d_op: | |
1451 | handler = fpemu_dp_msub; | |
1452 | goto dcoptop; | |
1453 | case nmadd_d_op: | |
1454 | handler = fpemu_dp_nmadd; | |
1455 | goto dcoptop; | |
1456 | case nmsub_d_op: | |
1457 | handler = fpemu_dp_nmsub; | |
1458 | goto dcoptop; | |
1459 | ||
1460 | dcoptop: | |
1461 | DPFROMREG(fr, MIPSInst_FR(ir)); | |
1462 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1463 | DPFROMREG(ft, MIPSInst_FT(ir)); | |
1464 | fd = (*handler) (fr, fs, ft); | |
1465 | DPTOREG(fd, MIPSInst_FD(ir)); | |
1466 | goto copcsr; | |
1467 | ||
1468 | default: | |
1469 | return SIGILL; | |
1470 | } | |
1471 | break; | |
1472 | } | |
1da177e4 | 1473 | |
51061b88 DCZ |
1474 | case 0x3: |
1475 | if (MIPSInst_FUNC(ir) != pfetch_op) | |
1da177e4 | 1476 | return SIGILL; |
51061b88 | 1477 | |
1da177e4 LT |
1478 | /* ignore prefx operation */ |
1479 | break; | |
1480 | ||
1481 | default: | |
1482 | return SIGILL; | |
1483 | } | |
1484 | ||
1485 | return 0; | |
1486 | } | |
1da177e4 LT |
1487 | |
1488 | ||
1489 | ||
1490 | /* | |
1491 | * Emulate a single COP1 arithmetic instruction. | |
1492 | */ | |
eae89076 | 1493 | static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
1da177e4 LT |
1494 | mips_instruction ir) |
1495 | { | |
1496 | int rfmt; /* resulting format */ | |
1497 | unsigned rcsr = 0; /* resulting csr */ | |
3f7cac41 RB |
1498 | unsigned int oldrm; |
1499 | unsigned int cbit; | |
1da177e4 LT |
1500 | unsigned cond; |
1501 | union { | |
2209bcb1 RB |
1502 | union ieee754dp d; |
1503 | union ieee754sp s; | |
1da177e4 | 1504 | int w; |
1da177e4 | 1505 | s64 l; |
1da177e4 | 1506 | } rv; /* resulting value */ |
3f7cac41 | 1507 | u64 bits; |
1da177e4 | 1508 | |
b6ee75ed | 1509 | MIPS_FPU_EMU_INC_STATS(cp1ops); |
1da177e4 | 1510 | switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { |
3f7cac41 | 1511 | case s_fmt: { /* 0 */ |
1da177e4 | 1512 | union { |
2209bcb1 RB |
1513 | union ieee754sp(*b) (union ieee754sp, union ieee754sp); |
1514 | union ieee754sp(*u) (union ieee754sp); | |
1da177e4 | 1515 | } handler; |
3f7cac41 | 1516 | union ieee754sp fs, ft; |
1da177e4 LT |
1517 | |
1518 | switch (MIPSInst_FUNC(ir)) { | |
1519 | /* binary ops */ | |
1520 | case fadd_op: | |
1521 | handler.b = ieee754sp_add; | |
1522 | goto scopbop; | |
1523 | case fsub_op: | |
1524 | handler.b = ieee754sp_sub; | |
1525 | goto scopbop; | |
1526 | case fmul_op: | |
1527 | handler.b = ieee754sp_mul; | |
1528 | goto scopbop; | |
1529 | case fdiv_op: | |
1530 | handler.b = ieee754sp_div; | |
1531 | goto scopbop; | |
1532 | ||
1533 | /* unary ops */ | |
1da177e4 | 1534 | case fsqrt_op: |
08a07904 RB |
1535 | if (!cpu_has_mips_4_5_r) |
1536 | return SIGILL; | |
1537 | ||
1da177e4 LT |
1538 | handler.u = ieee754sp_sqrt; |
1539 | goto scopuop; | |
3f7cac41 | 1540 | |
08a07904 RB |
1541 | /* |
1542 | * Note that on some MIPS IV implementations such as the | |
1543 | * R5000 and R8000 the FSQRT and FRECIP instructions do not | |
1544 | * achieve full IEEE-754 accuracy - however this emulator does. | |
1545 | */ | |
1da177e4 | 1546 | case frsqrt_op: |
08a07904 RB |
1547 | if (!cpu_has_mips_4_5_r2) |
1548 | return SIGILL; | |
1549 | ||
1da177e4 LT |
1550 | handler.u = fpemu_sp_rsqrt; |
1551 | goto scopuop; | |
3f7cac41 | 1552 | |
1da177e4 | 1553 | case frecip_op: |
08a07904 RB |
1554 | if (!cpu_has_mips_4_5_r2) |
1555 | return SIGILL; | |
1556 | ||
1da177e4 LT |
1557 | handler.u = fpemu_sp_recip; |
1558 | goto scopuop; | |
08a07904 | 1559 | |
1da177e4 | 1560 | case fmovc_op: |
08a07904 RB |
1561 | if (!cpu_has_mips_4_5_r) |
1562 | return SIGILL; | |
1563 | ||
1da177e4 LT |
1564 | cond = fpucondbit[MIPSInst_FT(ir) >> 2]; |
1565 | if (((ctx->fcr31 & cond) != 0) != | |
1566 | ((MIPSInst_FT(ir) & 1) != 0)) | |
1567 | return 0; | |
1568 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1569 | break; | |
3f7cac41 | 1570 | |
1da177e4 | 1571 | case fmovz_op: |
08a07904 RB |
1572 | if (!cpu_has_mips_4_5_r) |
1573 | return SIGILL; | |
1574 | ||
1da177e4 LT |
1575 | if (xcp->regs[MIPSInst_FT(ir)] != 0) |
1576 | return 0; | |
1577 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1578 | break; | |
3f7cac41 | 1579 | |
1da177e4 | 1580 | case fmovn_op: |
08a07904 RB |
1581 | if (!cpu_has_mips_4_5_r) |
1582 | return SIGILL; | |
1583 | ||
1da177e4 LT |
1584 | if (xcp->regs[MIPSInst_FT(ir)] == 0) |
1585 | return 0; | |
1586 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1587 | break; | |
3f7cac41 | 1588 | |
1da177e4 LT |
1589 | case fabs_op: |
1590 | handler.u = ieee754sp_abs; | |
1591 | goto scopuop; | |
3f7cac41 | 1592 | |
1da177e4 LT |
1593 | case fneg_op: |
1594 | handler.u = ieee754sp_neg; | |
1595 | goto scopuop; | |
3f7cac41 | 1596 | |
1da177e4 LT |
1597 | case fmov_op: |
1598 | /* an easy one */ | |
1599 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1600 | goto copcsr; | |
1601 | ||
1602 | /* binary op on handler */ | |
3f7cac41 RB |
1603 | scopbop: |
1604 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1605 | SPFROMREG(ft, MIPSInst_FT(ir)); | |
1da177e4 | 1606 | |
3f7cac41 RB |
1607 | rv.s = (*handler.b) (fs, ft); |
1608 | goto copcsr; | |
1609 | scopuop: | |
1610 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1611 | rv.s = (*handler.u) (fs); | |
1612 | goto copcsr; | |
1613 | copcsr: | |
c4103526 DCZ |
1614 | if (ieee754_cxtest(IEEE754_INEXACT)) { |
1615 | MIPS_FPU_EMU_INC_STATS(ieee754_inexact); | |
1da177e4 | 1616 | rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; |
c4103526 DCZ |
1617 | } |
1618 | if (ieee754_cxtest(IEEE754_UNDERFLOW)) { | |
1619 | MIPS_FPU_EMU_INC_STATS(ieee754_underflow); | |
1da177e4 | 1620 | rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; |
c4103526 DCZ |
1621 | } |
1622 | if (ieee754_cxtest(IEEE754_OVERFLOW)) { | |
1623 | MIPS_FPU_EMU_INC_STATS(ieee754_overflow); | |
1da177e4 | 1624 | rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; |
c4103526 DCZ |
1625 | } |
1626 | if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) { | |
1627 | MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv); | |
1da177e4 | 1628 | rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S; |
c4103526 DCZ |
1629 | } |
1630 | if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { | |
1631 | MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); | |
1da177e4 | 1632 | rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; |
c4103526 | 1633 | } |
1da177e4 LT |
1634 | break; |
1635 | ||
1636 | /* unary conv ops */ | |
1637 | case fcvts_op: | |
1638 | return SIGILL; /* not defined */ | |
1da177e4 | 1639 | |
3f7cac41 | 1640 | case fcvtd_op: |
1da177e4 LT |
1641 | SPFROMREG(fs, MIPSInst_FS(ir)); |
1642 | rv.d = ieee754dp_fsp(fs); | |
1643 | rfmt = d_fmt; | |
1644 | goto copcsr; | |
1da177e4 | 1645 | |
3f7cac41 | 1646 | case fcvtw_op: |
1da177e4 LT |
1647 | SPFROMREG(fs, MIPSInst_FS(ir)); |
1648 | rv.w = ieee754sp_tint(fs); | |
1649 | rfmt = w_fmt; | |
1650 | goto copcsr; | |
1da177e4 | 1651 | |
1da177e4 LT |
1652 | case fround_op: |
1653 | case ftrunc_op: | |
1654 | case fceil_op: | |
3f7cac41 | 1655 | case ffloor_op: |
08a07904 RB |
1656 | if (!cpu_has_mips_2_3_4_5 && !cpu_has_mips64) |
1657 | return SIGILL; | |
1658 | ||
3f7cac41 | 1659 | oldrm = ieee754_csr.rm; |
1da177e4 | 1660 | SPFROMREG(fs, MIPSInst_FS(ir)); |
56a64733 | 1661 | ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); |
1da177e4 LT |
1662 | rv.w = ieee754sp_tint(fs); |
1663 | ieee754_csr.rm = oldrm; | |
1664 | rfmt = w_fmt; | |
1665 | goto copcsr; | |
1da177e4 | 1666 | |
3f7cac41 | 1667 | case fcvtl_op: |
08a07904 RB |
1668 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1669 | return SIGILL; | |
1670 | ||
1da177e4 LT |
1671 | SPFROMREG(fs, MIPSInst_FS(ir)); |
1672 | rv.l = ieee754sp_tlong(fs); | |
1673 | rfmt = l_fmt; | |
1674 | goto copcsr; | |
1da177e4 LT |
1675 | |
1676 | case froundl_op: | |
1677 | case ftruncl_op: | |
1678 | case fceill_op: | |
3f7cac41 | 1679 | case ffloorl_op: |
08a07904 RB |
1680 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1681 | return SIGILL; | |
1682 | ||
3f7cac41 | 1683 | oldrm = ieee754_csr.rm; |
1da177e4 | 1684 | SPFROMREG(fs, MIPSInst_FS(ir)); |
56a64733 | 1685 | ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); |
1da177e4 LT |
1686 | rv.l = ieee754sp_tlong(fs); |
1687 | ieee754_csr.rm = oldrm; | |
1688 | rfmt = l_fmt; | |
1689 | goto copcsr; | |
1da177e4 LT |
1690 | |
1691 | default: | |
1692 | if (MIPSInst_FUNC(ir) >= fcmp_op) { | |
1693 | unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; | |
2209bcb1 | 1694 | union ieee754sp fs, ft; |
1da177e4 LT |
1695 | |
1696 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1697 | SPFROMREG(ft, MIPSInst_FT(ir)); | |
1698 | rv.w = ieee754sp_cmp(fs, ft, | |
1699 | cmptab[cmpop & 0x7], cmpop & 0x8); | |
1700 | rfmt = -1; | |
1701 | if ((cmpop & 0x8) && ieee754_cxtest | |
1702 | (IEEE754_INVALID_OPERATION)) | |
1703 | rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; | |
1704 | else | |
1705 | goto copcsr; | |
1706 | ||
3f7cac41 | 1707 | } else |
1da177e4 | 1708 | return SIGILL; |
1da177e4 LT |
1709 | break; |
1710 | } | |
1711 | break; | |
1712 | } | |
1713 | ||
3f7cac41 RB |
1714 | case d_fmt: { |
1715 | union ieee754dp fs, ft; | |
1da177e4 | 1716 | union { |
2209bcb1 RB |
1717 | union ieee754dp(*b) (union ieee754dp, union ieee754dp); |
1718 | union ieee754dp(*u) (union ieee754dp); | |
1da177e4 LT |
1719 | } handler; |
1720 | ||
1721 | switch (MIPSInst_FUNC(ir)) { | |
1722 | /* binary ops */ | |
1723 | case fadd_op: | |
1724 | handler.b = ieee754dp_add; | |
1725 | goto dcopbop; | |
1726 | case fsub_op: | |
1727 | handler.b = ieee754dp_sub; | |
1728 | goto dcopbop; | |
1729 | case fmul_op: | |
1730 | handler.b = ieee754dp_mul; | |
1731 | goto dcopbop; | |
1732 | case fdiv_op: | |
1733 | handler.b = ieee754dp_div; | |
1734 | goto dcopbop; | |
1735 | ||
1736 | /* unary ops */ | |
1da177e4 | 1737 | case fsqrt_op: |
08a07904 RB |
1738 | if (!cpu_has_mips_2_3_4_5_r) |
1739 | return SIGILL; | |
1740 | ||
1da177e4 LT |
1741 | handler.u = ieee754dp_sqrt; |
1742 | goto dcopuop; | |
08a07904 RB |
1743 | /* |
1744 | * Note that on some MIPS IV implementations such as the | |
1745 | * R5000 and R8000 the FSQRT and FRECIP instructions do not | |
1746 | * achieve full IEEE-754 accuracy - however this emulator does. | |
1747 | */ | |
1da177e4 | 1748 | case frsqrt_op: |
08a07904 RB |
1749 | if (!cpu_has_mips_4_5_r2) |
1750 | return SIGILL; | |
1751 | ||
1da177e4 LT |
1752 | handler.u = fpemu_dp_rsqrt; |
1753 | goto dcopuop; | |
1754 | case frecip_op: | |
08a07904 RB |
1755 | if (!cpu_has_mips_4_5_r2) |
1756 | return SIGILL; | |
1757 | ||
1da177e4 LT |
1758 | handler.u = fpemu_dp_recip; |
1759 | goto dcopuop; | |
1da177e4 | 1760 | case fmovc_op: |
08a07904 RB |
1761 | if (!cpu_has_mips_4_5_r) |
1762 | return SIGILL; | |
1763 | ||
1da177e4 LT |
1764 | cond = fpucondbit[MIPSInst_FT(ir) >> 2]; |
1765 | if (((ctx->fcr31 & cond) != 0) != | |
1766 | ((MIPSInst_FT(ir) & 1) != 0)) | |
1767 | return 0; | |
1768 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1769 | break; | |
1770 | case fmovz_op: | |
08a07904 RB |
1771 | if (!cpu_has_mips_4_5_r) |
1772 | return SIGILL; | |
1773 | ||
1da177e4 LT |
1774 | if (xcp->regs[MIPSInst_FT(ir)] != 0) |
1775 | return 0; | |
1776 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1777 | break; | |
1778 | case fmovn_op: | |
08a07904 RB |
1779 | if (!cpu_has_mips_4_5_r) |
1780 | return SIGILL; | |
1781 | ||
1da177e4 LT |
1782 | if (xcp->regs[MIPSInst_FT(ir)] == 0) |
1783 | return 0; | |
1784 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1785 | break; | |
1da177e4 LT |
1786 | case fabs_op: |
1787 | handler.u = ieee754dp_abs; | |
1788 | goto dcopuop; | |
1789 | ||
1790 | case fneg_op: | |
1791 | handler.u = ieee754dp_neg; | |
1792 | goto dcopuop; | |
1793 | ||
1794 | case fmov_op: | |
1795 | /* an easy one */ | |
1796 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1797 | goto copcsr; | |
1798 | ||
1799 | /* binary op on handler */ | |
3f7cac41 RB |
1800 | dcopbop: |
1801 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1802 | DPFROMREG(ft, MIPSInst_FT(ir)); | |
1da177e4 | 1803 | |
3f7cac41 RB |
1804 | rv.d = (*handler.b) (fs, ft); |
1805 | goto copcsr; | |
1806 | dcopuop: | |
1807 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1808 | rv.d = (*handler.u) (fs); | |
1809 | goto copcsr; | |
1da177e4 | 1810 | |
3f7cac41 RB |
1811 | /* |
1812 | * unary conv ops | |
1813 | */ | |
1814 | case fcvts_op: | |
1da177e4 LT |
1815 | DPFROMREG(fs, MIPSInst_FS(ir)); |
1816 | rv.s = ieee754sp_fdp(fs); | |
1817 | rfmt = s_fmt; | |
1818 | goto copcsr; | |
3f7cac41 | 1819 | |
1da177e4 LT |
1820 | case fcvtd_op: |
1821 | return SIGILL; /* not defined */ | |
1822 | ||
3f7cac41 | 1823 | case fcvtw_op: |
1da177e4 LT |
1824 | DPFROMREG(fs, MIPSInst_FS(ir)); |
1825 | rv.w = ieee754dp_tint(fs); /* wrong */ | |
1826 | rfmt = w_fmt; | |
1827 | goto copcsr; | |
1da177e4 | 1828 | |
1da177e4 LT |
1829 | case fround_op: |
1830 | case ftrunc_op: | |
1831 | case fceil_op: | |
3f7cac41 | 1832 | case ffloor_op: |
08a07904 RB |
1833 | if (!cpu_has_mips_2_3_4_5_r) |
1834 | return SIGILL; | |
1835 | ||
3f7cac41 | 1836 | oldrm = ieee754_csr.rm; |
1da177e4 | 1837 | DPFROMREG(fs, MIPSInst_FS(ir)); |
56a64733 | 1838 | ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); |
1da177e4 LT |
1839 | rv.w = ieee754dp_tint(fs); |
1840 | ieee754_csr.rm = oldrm; | |
1841 | rfmt = w_fmt; | |
1842 | goto copcsr; | |
1da177e4 | 1843 | |
3f7cac41 | 1844 | case fcvtl_op: |
08a07904 RB |
1845 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1846 | return SIGILL; | |
1847 | ||
1da177e4 LT |
1848 | DPFROMREG(fs, MIPSInst_FS(ir)); |
1849 | rv.l = ieee754dp_tlong(fs); | |
1850 | rfmt = l_fmt; | |
1851 | goto copcsr; | |
1da177e4 LT |
1852 | |
1853 | case froundl_op: | |
1854 | case ftruncl_op: | |
1855 | case fceill_op: | |
3f7cac41 | 1856 | case ffloorl_op: |
08a07904 RB |
1857 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1858 | return SIGILL; | |
1859 | ||
3f7cac41 | 1860 | oldrm = ieee754_csr.rm; |
1da177e4 | 1861 | DPFROMREG(fs, MIPSInst_FS(ir)); |
56a64733 | 1862 | ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); |
1da177e4 LT |
1863 | rv.l = ieee754dp_tlong(fs); |
1864 | ieee754_csr.rm = oldrm; | |
1865 | rfmt = l_fmt; | |
1866 | goto copcsr; | |
1da177e4 LT |
1867 | |
1868 | default: | |
1869 | if (MIPSInst_FUNC(ir) >= fcmp_op) { | |
1870 | unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; | |
2209bcb1 | 1871 | union ieee754dp fs, ft; |
1da177e4 LT |
1872 | |
1873 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1874 | DPFROMREG(ft, MIPSInst_FT(ir)); | |
1875 | rv.w = ieee754dp_cmp(fs, ft, | |
1876 | cmptab[cmpop & 0x7], cmpop & 0x8); | |
1877 | rfmt = -1; | |
1878 | if ((cmpop & 0x8) | |
1879 | && | |
1880 | ieee754_cxtest | |
1881 | (IEEE754_INVALID_OPERATION)) | |
1882 | rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; | |
1883 | else | |
1884 | goto copcsr; | |
1885 | ||
1886 | } | |
1887 | else { | |
1888 | return SIGILL; | |
1889 | } | |
1890 | break; | |
1891 | } | |
1892 | break; | |
1da177e4 | 1893 | |
3f7cac41 | 1894 | case w_fmt: |
1da177e4 LT |
1895 | switch (MIPSInst_FUNC(ir)) { |
1896 | case fcvts_op: | |
1897 | /* convert word to single precision real */ | |
1898 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1899 | rv.s = ieee754sp_fint(fs.bits); | |
1900 | rfmt = s_fmt; | |
1901 | goto copcsr; | |
1da177e4 LT |
1902 | case fcvtd_op: |
1903 | /* convert word to double precision real */ | |
1904 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1905 | rv.d = ieee754dp_fint(fs.bits); | |
1906 | rfmt = d_fmt; | |
1907 | goto copcsr; | |
1da177e4 LT |
1908 | default: |
1909 | return SIGILL; | |
1910 | } | |
1911 | break; | |
1912 | } | |
1913 | ||
3f7cac41 | 1914 | case l_fmt: |
08a07904 RB |
1915 | |
1916 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) | |
1917 | return SIGILL; | |
1918 | ||
bbd426f5 PB |
1919 | DIFROMREG(bits, MIPSInst_FS(ir)); |
1920 | ||
1da177e4 LT |
1921 | switch (MIPSInst_FUNC(ir)) { |
1922 | case fcvts_op: | |
1923 | /* convert long to single precision real */ | |
bbd426f5 | 1924 | rv.s = ieee754sp_flong(bits); |
1da177e4 LT |
1925 | rfmt = s_fmt; |
1926 | goto copcsr; | |
1927 | case fcvtd_op: | |
1928 | /* convert long to double precision real */ | |
bbd426f5 | 1929 | rv.d = ieee754dp_flong(bits); |
1da177e4 LT |
1930 | rfmt = d_fmt; |
1931 | goto copcsr; | |
1932 | default: | |
1933 | return SIGILL; | |
1934 | } | |
1935 | break; | |
1da177e4 LT |
1936 | |
1937 | default: | |
1938 | return SIGILL; | |
1939 | } | |
1940 | ||
1941 | /* | |
1942 | * Update the fpu CSR register for this operation. | |
1943 | * If an exception is required, generate a tidy SIGFPE exception, | |
1944 | * without updating the result register. | |
1945 | * Note: cause exception bits do not accumulate, they are rewritten | |
1946 | * for each op; only the flag/sticky bits accumulate. | |
1947 | */ | |
1948 | ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; | |
1949 | if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { | |
3f7cac41 | 1950 | /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */ |
1da177e4 LT |
1951 | return SIGFPE; |
1952 | } | |
1953 | ||
1954 | /* | |
1955 | * Now we can safely write the result back to the register file. | |
1956 | */ | |
1957 | switch (rfmt) { | |
08a07904 RB |
1958 | case -1: |
1959 | ||
1960 | if (cpu_has_mips_4_5_r) | |
c3b9b945 | 1961 | cbit = fpucondbit[MIPSInst_FD(ir) >> 2]; |
08a07904 RB |
1962 | else |
1963 | cbit = FPU_CSR_COND; | |
1da177e4 | 1964 | if (rv.w) |
08a07904 | 1965 | ctx->fcr31 |= cbit; |
1da177e4 | 1966 | else |
08a07904 | 1967 | ctx->fcr31 &= ~cbit; |
1da177e4 | 1968 | break; |
08a07904 | 1969 | |
1da177e4 LT |
1970 | case d_fmt: |
1971 | DPTOREG(rv.d, MIPSInst_FD(ir)); | |
1972 | break; | |
1da177e4 LT |
1973 | case s_fmt: |
1974 | SPTOREG(rv.s, MIPSInst_FD(ir)); | |
1975 | break; | |
1976 | case w_fmt: | |
1977 | SITOREG(rv.w, MIPSInst_FD(ir)); | |
1978 | break; | |
1da177e4 | 1979 | case l_fmt: |
08a07904 RB |
1980 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1981 | return SIGILL; | |
1982 | ||
1da177e4 LT |
1983 | DITOREG(rv.l, MIPSInst_FD(ir)); |
1984 | break; | |
1da177e4 LT |
1985 | default: |
1986 | return SIGILL; | |
1987 | } | |
1988 | ||
1989 | return 0; | |
1990 | } | |
1991 | ||
e04582b7 | 1992 | int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
515b029d | 1993 | int has_fpu, void *__user *fault_addr) |
1da177e4 | 1994 | { |
333d1f67 | 1995 | unsigned long oldepc, prevepc; |
102cedc3 LY |
1996 | struct mm_decoded_insn dec_insn; |
1997 | u16 instr[4]; | |
1998 | u16 *instr_ptr; | |
1da177e4 LT |
1999 | int sig = 0; |
2000 | ||
2001 | oldepc = xcp->cp0_epc; | |
2002 | do { | |
2003 | prevepc = xcp->cp0_epc; | |
2004 | ||
102cedc3 LY |
2005 | if (get_isa16_mode(prevepc) && cpu_has_mmips) { |
2006 | /* | |
2007 | * Get next 2 microMIPS instructions and convert them | |
2008 | * into 32-bit instructions. | |
2009 | */ | |
2010 | if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) || | |
2011 | (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) || | |
2012 | (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) || | |
2013 | (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) { | |
2014 | MIPS_FPU_EMU_INC_STATS(errors); | |
2015 | return SIGBUS; | |
2016 | } | |
2017 | instr_ptr = instr; | |
2018 | ||
2019 | /* Get first instruction. */ | |
2020 | if (mm_insn_16bit(*instr_ptr)) { | |
2021 | /* Duplicate the half-word. */ | |
2022 | dec_insn.insn = (*instr_ptr << 16) | | |
2023 | (*instr_ptr); | |
2024 | /* 16-bit instruction. */ | |
2025 | dec_insn.pc_inc = 2; | |
2026 | instr_ptr += 1; | |
2027 | } else { | |
2028 | dec_insn.insn = (*instr_ptr << 16) | | |
2029 | *(instr_ptr+1); | |
2030 | /* 32-bit instruction. */ | |
2031 | dec_insn.pc_inc = 4; | |
2032 | instr_ptr += 2; | |
2033 | } | |
2034 | /* Get second instruction. */ | |
2035 | if (mm_insn_16bit(*instr_ptr)) { | |
2036 | /* Duplicate the half-word. */ | |
2037 | dec_insn.next_insn = (*instr_ptr << 16) | | |
2038 | (*instr_ptr); | |
2039 | /* 16-bit instruction. */ | |
2040 | dec_insn.next_pc_inc = 2; | |
2041 | } else { | |
2042 | dec_insn.next_insn = (*instr_ptr << 16) | | |
2043 | *(instr_ptr+1); | |
2044 | /* 32-bit instruction. */ | |
2045 | dec_insn.next_pc_inc = 4; | |
2046 | } | |
2047 | dec_insn.micro_mips_mode = 1; | |
2048 | } else { | |
2049 | if ((get_user(dec_insn.insn, | |
2050 | (mips_instruction __user *) xcp->cp0_epc)) || | |
2051 | (get_user(dec_insn.next_insn, | |
2052 | (mips_instruction __user *)(xcp->cp0_epc+4)))) { | |
2053 | MIPS_FPU_EMU_INC_STATS(errors); | |
2054 | return SIGBUS; | |
2055 | } | |
2056 | dec_insn.pc_inc = 4; | |
2057 | dec_insn.next_pc_inc = 4; | |
2058 | dec_insn.micro_mips_mode = 0; | |
515b029d | 2059 | } |
102cedc3 LY |
2060 | |
2061 | if ((dec_insn.insn == 0) || | |
2062 | ((dec_insn.pc_inc == 2) && | |
2063 | ((dec_insn.insn & 0xffff) == MM_NOP16))) | |
2064 | xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ | |
1da177e4 | 2065 | else { |
cd21dfcf RB |
2066 | /* |
2067 | * The 'ieee754_csr' is an alias of | |
70342287 RB |
2068 | * ctx->fcr31. No need to copy ctx->fcr31 to |
2069 | * ieee754_csr. But ieee754_csr.rm is ieee | |
cd21dfcf RB |
2070 | * library modes. (not mips rounding mode) |
2071 | */ | |
102cedc3 | 2072 | sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); |
1da177e4 LT |
2073 | } |
2074 | ||
e04582b7 | 2075 | if (has_fpu) |
1da177e4 LT |
2076 | break; |
2077 | if (sig) | |
2078 | break; | |
2079 | ||
2080 | cond_resched(); | |
2081 | } while (xcp->cp0_epc > prevepc); | |
2082 | ||
2083 | /* SIGILL indicates a non-fpu instruction */ | |
2084 | if (sig == SIGILL && xcp->cp0_epc != oldepc) | |
3f7cac41 | 2085 | /* but if EPC has advanced, then ignore it */ |
1da177e4 LT |
2086 | sig = 0; |
2087 | ||
2088 | return sig; | |
2089 | } |