Commit | Line | Data |
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1da177e4 | 1 | /* |
3f7cac41 | 2 | * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator |
1da177e4 LT |
3 | * |
4 | * MIPS floating point support | |
5 | * Copyright (C) 1994-2000 Algorithmics Ltd. | |
1da177e4 LT |
6 | * |
7 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
8 | * Copyright (C) 2000 MIPS Technologies, Inc. | |
9 | * | |
10 | * This program is free software; you can distribute it and/or modify it | |
11 | * under the terms of the GNU General Public License (Version 2) as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | * for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along | |
20 | * with this program; if not, write to the Free Software Foundation, Inc., | |
3f7cac41 | 21 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
1da177e4 LT |
22 | * |
23 | * A complete emulator for MIPS coprocessor 1 instructions. This is | |
24 | * required for #float(switch) or #float(trap), where it catches all | |
25 | * COP1 instructions via the "CoProcessor Unusable" exception. | |
26 | * | |
27 | * More surprisingly it is also required for #float(ieee), to help out | |
3f7cac41 | 28 | * the hardware FPU at the boundaries of the IEEE-754 representation |
1da177e4 LT |
29 | * (denormalised values, infinities, underflow, etc). It is made |
30 | * quite nasty because emulation of some non-COP1 instructions is | |
31 | * required, e.g. in branch delay slots. | |
32 | * | |
3f7cac41 | 33 | * Note if you know that you won't have an FPU, then you'll get much |
1da177e4 LT |
34 | * better performance by compiling with -msoft-float! |
35 | */ | |
36 | #include <linux/sched.h> | |
83fd38ca | 37 | #include <linux/debugfs.h> |
08a07904 | 38 | #include <linux/kconfig.h> |
85c51c51 | 39 | #include <linux/percpu-defs.h> |
7f788d2d | 40 | #include <linux/perf_event.h> |
1da177e4 | 41 | |
cd8ee345 | 42 | #include <asm/branch.h> |
1da177e4 | 43 | #include <asm/inst.h> |
1da177e4 LT |
44 | #include <asm/ptrace.h> |
45 | #include <asm/signal.h> | |
cd8ee345 RB |
46 | #include <asm/uaccess.h> |
47 | ||
48 | #include <asm/processor.h> | |
1da177e4 | 49 | #include <asm/fpu_emulator.h> |
102cedc3 | 50 | #include <asm/fpu.h> |
1da177e4 LT |
51 | |
52 | #include "ieee754.h" | |
1da177e4 | 53 | |
1da177e4 LT |
54 | /* Function which emulates a floating point instruction. */ |
55 | ||
eae89076 | 56 | static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, |
1da177e4 LT |
57 | mips_instruction); |
58 | ||
1da177e4 | 59 | static int fpux_emu(struct pt_regs *, |
515b029d | 60 | struct mips_fpu_struct *, mips_instruction, void *__user *); |
1da177e4 | 61 | |
1da177e4 LT |
62 | /* Control registers */ |
63 | ||
64 | #define FPCREG_RID 0 /* $0 = revision id */ | |
65 | #define FPCREG_CSR 31 /* $31 = csr */ | |
66 | ||
95e8f634 SM |
67 | /* Determine rounding mode from the RM bits of the FCSR */ |
68 | #define modeindex(v) ((v) & FPU_CSR_RM) | |
69 | ||
1da177e4 LT |
70 | /* convert condition code register number to csr bit */ |
71 | static const unsigned int fpucondbit[8] = { | |
72 | FPU_CSR_COND0, | |
73 | FPU_CSR_COND1, | |
74 | FPU_CSR_COND2, | |
75 | FPU_CSR_COND3, | |
76 | FPU_CSR_COND4, | |
77 | FPU_CSR_COND5, | |
78 | FPU_CSR_COND6, | |
79 | FPU_CSR_COND7 | |
80 | }; | |
1da177e4 | 81 | |
102cedc3 LY |
82 | /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */ |
83 | static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0}; | |
84 | static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0}; | |
85 | static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0}; | |
86 | static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0}; | |
87 | ||
88 | /* | |
89 | * This functions translates a 32-bit microMIPS instruction | |
90 | * into a 32-bit MIPS32 instruction. Returns 0 on success | |
91 | * and SIGILL otherwise. | |
92 | */ | |
93 | static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) | |
94 | { | |
95 | union mips_instruction insn = *insn_ptr; | |
96 | union mips_instruction mips32_insn = insn; | |
97 | int func, fmt, op; | |
98 | ||
99 | switch (insn.mm_i_format.opcode) { | |
100 | case mm_ldc132_op: | |
101 | mips32_insn.mm_i_format.opcode = ldc1_op; | |
102 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
103 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
104 | break; | |
105 | case mm_lwc132_op: | |
106 | mips32_insn.mm_i_format.opcode = lwc1_op; | |
107 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
108 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
109 | break; | |
110 | case mm_sdc132_op: | |
111 | mips32_insn.mm_i_format.opcode = sdc1_op; | |
112 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
113 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
114 | break; | |
115 | case mm_swc132_op: | |
116 | mips32_insn.mm_i_format.opcode = swc1_op; | |
117 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
118 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
119 | break; | |
120 | case mm_pool32i_op: | |
121 | /* NOTE: offset is << by 1 if in microMIPS mode. */ | |
122 | if ((insn.mm_i_format.rt == mm_bc1f_op) || | |
123 | (insn.mm_i_format.rt == mm_bc1t_op)) { | |
124 | mips32_insn.fb_format.opcode = cop1_op; | |
125 | mips32_insn.fb_format.bc = bc_op; | |
126 | mips32_insn.fb_format.flag = | |
127 | (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0; | |
128 | } else | |
129 | return SIGILL; | |
130 | break; | |
131 | case mm_pool32f_op: | |
132 | switch (insn.mm_fp0_format.func) { | |
133 | case mm_32f_01_op: | |
134 | case mm_32f_11_op: | |
135 | case mm_32f_02_op: | |
136 | case mm_32f_12_op: | |
137 | case mm_32f_41_op: | |
138 | case mm_32f_51_op: | |
139 | case mm_32f_42_op: | |
140 | case mm_32f_52_op: | |
141 | op = insn.mm_fp0_format.func; | |
142 | if (op == mm_32f_01_op) | |
143 | func = madd_s_op; | |
144 | else if (op == mm_32f_11_op) | |
145 | func = madd_d_op; | |
146 | else if (op == mm_32f_02_op) | |
147 | func = nmadd_s_op; | |
148 | else if (op == mm_32f_12_op) | |
149 | func = nmadd_d_op; | |
150 | else if (op == mm_32f_41_op) | |
151 | func = msub_s_op; | |
152 | else if (op == mm_32f_51_op) | |
153 | func = msub_d_op; | |
154 | else if (op == mm_32f_42_op) | |
155 | func = nmsub_s_op; | |
156 | else | |
157 | func = nmsub_d_op; | |
158 | mips32_insn.fp6_format.opcode = cop1x_op; | |
159 | mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr; | |
160 | mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft; | |
161 | mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs; | |
162 | mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd; | |
163 | mips32_insn.fp6_format.func = func; | |
164 | break; | |
165 | case mm_32f_10_op: | |
166 | func = -1; /* Invalid */ | |
167 | op = insn.mm_fp5_format.op & 0x7; | |
168 | if (op == mm_ldxc1_op) | |
169 | func = ldxc1_op; | |
170 | else if (op == mm_sdxc1_op) | |
171 | func = sdxc1_op; | |
172 | else if (op == mm_lwxc1_op) | |
173 | func = lwxc1_op; | |
174 | else if (op == mm_swxc1_op) | |
175 | func = swxc1_op; | |
176 | ||
177 | if (func != -1) { | |
178 | mips32_insn.r_format.opcode = cop1x_op; | |
179 | mips32_insn.r_format.rs = | |
180 | insn.mm_fp5_format.base; | |
181 | mips32_insn.r_format.rt = | |
182 | insn.mm_fp5_format.index; | |
183 | mips32_insn.r_format.rd = 0; | |
184 | mips32_insn.r_format.re = insn.mm_fp5_format.fd; | |
185 | mips32_insn.r_format.func = func; | |
186 | } else | |
187 | return SIGILL; | |
188 | break; | |
189 | case mm_32f_40_op: | |
190 | op = -1; /* Invalid */ | |
191 | if (insn.mm_fp2_format.op == mm_fmovt_op) | |
192 | op = 1; | |
193 | else if (insn.mm_fp2_format.op == mm_fmovf_op) | |
194 | op = 0; | |
195 | if (op != -1) { | |
196 | mips32_insn.fp0_format.opcode = cop1_op; | |
197 | mips32_insn.fp0_format.fmt = | |
198 | sdps_format[insn.mm_fp2_format.fmt]; | |
199 | mips32_insn.fp0_format.ft = | |
200 | (insn.mm_fp2_format.cc<<2) + op; | |
201 | mips32_insn.fp0_format.fs = | |
202 | insn.mm_fp2_format.fs; | |
203 | mips32_insn.fp0_format.fd = | |
204 | insn.mm_fp2_format.fd; | |
205 | mips32_insn.fp0_format.func = fmovc_op; | |
206 | } else | |
207 | return SIGILL; | |
208 | break; | |
209 | case mm_32f_60_op: | |
210 | func = -1; /* Invalid */ | |
211 | if (insn.mm_fp0_format.op == mm_fadd_op) | |
212 | func = fadd_op; | |
213 | else if (insn.mm_fp0_format.op == mm_fsub_op) | |
214 | func = fsub_op; | |
215 | else if (insn.mm_fp0_format.op == mm_fmul_op) | |
216 | func = fmul_op; | |
217 | else if (insn.mm_fp0_format.op == mm_fdiv_op) | |
218 | func = fdiv_op; | |
219 | if (func != -1) { | |
220 | mips32_insn.fp0_format.opcode = cop1_op; | |
221 | mips32_insn.fp0_format.fmt = | |
222 | sdps_format[insn.mm_fp0_format.fmt]; | |
223 | mips32_insn.fp0_format.ft = | |
224 | insn.mm_fp0_format.ft; | |
225 | mips32_insn.fp0_format.fs = | |
226 | insn.mm_fp0_format.fs; | |
227 | mips32_insn.fp0_format.fd = | |
228 | insn.mm_fp0_format.fd; | |
229 | mips32_insn.fp0_format.func = func; | |
230 | } else | |
231 | return SIGILL; | |
232 | break; | |
233 | case mm_32f_70_op: | |
234 | func = -1; /* Invalid */ | |
235 | if (insn.mm_fp0_format.op == mm_fmovn_op) | |
236 | func = fmovn_op; | |
237 | else if (insn.mm_fp0_format.op == mm_fmovz_op) | |
238 | func = fmovz_op; | |
239 | if (func != -1) { | |
240 | mips32_insn.fp0_format.opcode = cop1_op; | |
241 | mips32_insn.fp0_format.fmt = | |
242 | sdps_format[insn.mm_fp0_format.fmt]; | |
243 | mips32_insn.fp0_format.ft = | |
244 | insn.mm_fp0_format.ft; | |
245 | mips32_insn.fp0_format.fs = | |
246 | insn.mm_fp0_format.fs; | |
247 | mips32_insn.fp0_format.fd = | |
248 | insn.mm_fp0_format.fd; | |
249 | mips32_insn.fp0_format.func = func; | |
250 | } else | |
251 | return SIGILL; | |
252 | break; | |
253 | case mm_32f_73_op: /* POOL32FXF */ | |
254 | switch (insn.mm_fp1_format.op) { | |
255 | case mm_movf0_op: | |
256 | case mm_movf1_op: | |
257 | case mm_movt0_op: | |
258 | case mm_movt1_op: | |
259 | if ((insn.mm_fp1_format.op & 0x7f) == | |
260 | mm_movf0_op) | |
261 | op = 0; | |
262 | else | |
263 | op = 1; | |
264 | mips32_insn.r_format.opcode = spec_op; | |
265 | mips32_insn.r_format.rs = insn.mm_fp4_format.fs; | |
266 | mips32_insn.r_format.rt = | |
267 | (insn.mm_fp4_format.cc << 2) + op; | |
268 | mips32_insn.r_format.rd = insn.mm_fp4_format.rt; | |
269 | mips32_insn.r_format.re = 0; | |
270 | mips32_insn.r_format.func = movc_op; | |
271 | break; | |
272 | case mm_fcvtd0_op: | |
273 | case mm_fcvtd1_op: | |
274 | case mm_fcvts0_op: | |
275 | case mm_fcvts1_op: | |
276 | if ((insn.mm_fp1_format.op & 0x7f) == | |
277 | mm_fcvtd0_op) { | |
278 | func = fcvtd_op; | |
279 | fmt = swl_format[insn.mm_fp3_format.fmt]; | |
280 | } else { | |
281 | func = fcvts_op; | |
282 | fmt = dwl_format[insn.mm_fp3_format.fmt]; | |
283 | } | |
284 | mips32_insn.fp0_format.opcode = cop1_op; | |
285 | mips32_insn.fp0_format.fmt = fmt; | |
286 | mips32_insn.fp0_format.ft = 0; | |
287 | mips32_insn.fp0_format.fs = | |
288 | insn.mm_fp3_format.fs; | |
289 | mips32_insn.fp0_format.fd = | |
290 | insn.mm_fp3_format.rt; | |
291 | mips32_insn.fp0_format.func = func; | |
292 | break; | |
293 | case mm_fmov0_op: | |
294 | case mm_fmov1_op: | |
295 | case mm_fabs0_op: | |
296 | case mm_fabs1_op: | |
297 | case mm_fneg0_op: | |
298 | case mm_fneg1_op: | |
299 | if ((insn.mm_fp1_format.op & 0x7f) == | |
300 | mm_fmov0_op) | |
301 | func = fmov_op; | |
302 | else if ((insn.mm_fp1_format.op & 0x7f) == | |
303 | mm_fabs0_op) | |
304 | func = fabs_op; | |
305 | else | |
306 | func = fneg_op; | |
307 | mips32_insn.fp0_format.opcode = cop1_op; | |
308 | mips32_insn.fp0_format.fmt = | |
309 | sdps_format[insn.mm_fp3_format.fmt]; | |
310 | mips32_insn.fp0_format.ft = 0; | |
311 | mips32_insn.fp0_format.fs = | |
312 | insn.mm_fp3_format.fs; | |
313 | mips32_insn.fp0_format.fd = | |
314 | insn.mm_fp3_format.rt; | |
315 | mips32_insn.fp0_format.func = func; | |
316 | break; | |
317 | case mm_ffloorl_op: | |
318 | case mm_ffloorw_op: | |
319 | case mm_fceill_op: | |
320 | case mm_fceilw_op: | |
321 | case mm_ftruncl_op: | |
322 | case mm_ftruncw_op: | |
323 | case mm_froundl_op: | |
324 | case mm_froundw_op: | |
325 | case mm_fcvtl_op: | |
326 | case mm_fcvtw_op: | |
327 | if (insn.mm_fp1_format.op == mm_ffloorl_op) | |
328 | func = ffloorl_op; | |
329 | else if (insn.mm_fp1_format.op == mm_ffloorw_op) | |
330 | func = ffloor_op; | |
331 | else if (insn.mm_fp1_format.op == mm_fceill_op) | |
332 | func = fceill_op; | |
333 | else if (insn.mm_fp1_format.op == mm_fceilw_op) | |
334 | func = fceil_op; | |
335 | else if (insn.mm_fp1_format.op == mm_ftruncl_op) | |
336 | func = ftruncl_op; | |
337 | else if (insn.mm_fp1_format.op == mm_ftruncw_op) | |
338 | func = ftrunc_op; | |
339 | else if (insn.mm_fp1_format.op == mm_froundl_op) | |
340 | func = froundl_op; | |
341 | else if (insn.mm_fp1_format.op == mm_froundw_op) | |
342 | func = fround_op; | |
343 | else if (insn.mm_fp1_format.op == mm_fcvtl_op) | |
344 | func = fcvtl_op; | |
345 | else | |
346 | func = fcvtw_op; | |
347 | mips32_insn.fp0_format.opcode = cop1_op; | |
348 | mips32_insn.fp0_format.fmt = | |
349 | sd_format[insn.mm_fp1_format.fmt]; | |
350 | mips32_insn.fp0_format.ft = 0; | |
351 | mips32_insn.fp0_format.fs = | |
352 | insn.mm_fp1_format.fs; | |
353 | mips32_insn.fp0_format.fd = | |
354 | insn.mm_fp1_format.rt; | |
355 | mips32_insn.fp0_format.func = func; | |
356 | break; | |
357 | case mm_frsqrt_op: | |
358 | case mm_fsqrt_op: | |
359 | case mm_frecip_op: | |
360 | if (insn.mm_fp1_format.op == mm_frsqrt_op) | |
361 | func = frsqrt_op; | |
362 | else if (insn.mm_fp1_format.op == mm_fsqrt_op) | |
363 | func = fsqrt_op; | |
364 | else | |
365 | func = frecip_op; | |
366 | mips32_insn.fp0_format.opcode = cop1_op; | |
367 | mips32_insn.fp0_format.fmt = | |
368 | sdps_format[insn.mm_fp1_format.fmt]; | |
369 | mips32_insn.fp0_format.ft = 0; | |
370 | mips32_insn.fp0_format.fs = | |
371 | insn.mm_fp1_format.fs; | |
372 | mips32_insn.fp0_format.fd = | |
373 | insn.mm_fp1_format.rt; | |
374 | mips32_insn.fp0_format.func = func; | |
375 | break; | |
376 | case mm_mfc1_op: | |
377 | case mm_mtc1_op: | |
378 | case mm_cfc1_op: | |
379 | case mm_ctc1_op: | |
9355e59c SH |
380 | case mm_mfhc1_op: |
381 | case mm_mthc1_op: | |
102cedc3 LY |
382 | if (insn.mm_fp1_format.op == mm_mfc1_op) |
383 | op = mfc_op; | |
384 | else if (insn.mm_fp1_format.op == mm_mtc1_op) | |
385 | op = mtc_op; | |
386 | else if (insn.mm_fp1_format.op == mm_cfc1_op) | |
387 | op = cfc_op; | |
9355e59c | 388 | else if (insn.mm_fp1_format.op == mm_ctc1_op) |
102cedc3 | 389 | op = ctc_op; |
9355e59c SH |
390 | else if (insn.mm_fp1_format.op == mm_mfhc1_op) |
391 | op = mfhc_op; | |
392 | else | |
393 | op = mthc_op; | |
102cedc3 LY |
394 | mips32_insn.fp1_format.opcode = cop1_op; |
395 | mips32_insn.fp1_format.op = op; | |
396 | mips32_insn.fp1_format.rt = | |
397 | insn.mm_fp1_format.rt; | |
398 | mips32_insn.fp1_format.fs = | |
399 | insn.mm_fp1_format.fs; | |
400 | mips32_insn.fp1_format.fd = 0; | |
401 | mips32_insn.fp1_format.func = 0; | |
402 | break; | |
403 | default: | |
404 | return SIGILL; | |
102cedc3 LY |
405 | } |
406 | break; | |
407 | case mm_32f_74_op: /* c.cond.fmt */ | |
408 | mips32_insn.fp0_format.opcode = cop1_op; | |
409 | mips32_insn.fp0_format.fmt = | |
410 | sdps_format[insn.mm_fp4_format.fmt]; | |
411 | mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt; | |
412 | mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs; | |
413 | mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2; | |
414 | mips32_insn.fp0_format.func = | |
415 | insn.mm_fp4_format.cond | MM_MIPS32_COND_FC; | |
416 | break; | |
417 | default: | |
418 | return SIGILL; | |
102cedc3 LY |
419 | } |
420 | break; | |
421 | default: | |
422 | return SIGILL; | |
102cedc3 LY |
423 | } |
424 | ||
425 | *insn_ptr = mips32_insn; | |
426 | return 0; | |
427 | } | |
428 | ||
1da177e4 LT |
429 | /* |
430 | * Redundant with logic already in kernel/branch.c, | |
431 | * embedded in compute_return_epc. At some point, | |
432 | * a single subroutine should be used across both | |
433 | * modules. | |
434 | */ | |
102cedc3 LY |
435 | static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, |
436 | unsigned long *contpc) | |
1da177e4 | 437 | { |
102cedc3 LY |
438 | union mips_instruction insn = (union mips_instruction)dec_insn.insn; |
439 | unsigned int fcr31; | |
440 | unsigned int bit = 0; | |
441 | ||
442 | switch (insn.i_format.opcode) { | |
1da177e4 | 443 | case spec_op: |
102cedc3 | 444 | switch (insn.r_format.func) { |
1da177e4 | 445 | case jalr_op: |
102cedc3 LY |
446 | regs->regs[insn.r_format.rd] = |
447 | regs->cp0_epc + dec_insn.pc_inc + | |
448 | dec_insn.next_pc_inc; | |
449 | /* Fall through */ | |
1da177e4 | 450 | case jr_op: |
5f9f41c4 MC |
451 | /* For R6, JR already emulated in jalr_op */ |
452 | if (NO_R6EMU && insn.r_format.opcode == jr_op) | |
453 | break; | |
102cedc3 | 454 | *contpc = regs->regs[insn.r_format.rs]; |
1da177e4 LT |
455 | return 1; |
456 | } | |
457 | break; | |
1da177e4 | 458 | case bcond_op: |
102cedc3 LY |
459 | switch (insn.i_format.rt) { |
460 | case bltzal_op: | |
461 | case bltzall_op: | |
319824ea MC |
462 | if (NO_R6EMU && (insn.i_format.rs || |
463 | insn.i_format.rt == bltzall_op)) | |
464 | break; | |
465 | ||
102cedc3 LY |
466 | regs->regs[31] = regs->cp0_epc + |
467 | dec_insn.pc_inc + | |
468 | dec_insn.next_pc_inc; | |
469 | /* Fall through */ | |
1da177e4 | 470 | case bltzl_op: |
319824ea MC |
471 | if (NO_R6EMU) |
472 | break; | |
473 | case bltz_op: | |
102cedc3 LY |
474 | if ((long)regs->regs[insn.i_format.rs] < 0) |
475 | *contpc = regs->cp0_epc + | |
476 | dec_insn.pc_inc + | |
477 | (insn.i_format.simmediate << 2); | |
478 | else | |
479 | *contpc = regs->cp0_epc + | |
480 | dec_insn.pc_inc + | |
481 | dec_insn.next_pc_inc; | |
482 | return 1; | |
1da177e4 | 483 | case bgezal_op: |
1da177e4 | 484 | case bgezall_op: |
319824ea MC |
485 | if (NO_R6EMU && (insn.i_format.rs || |
486 | insn.i_format.rt == bgezall_op)) | |
487 | break; | |
488 | ||
102cedc3 LY |
489 | regs->regs[31] = regs->cp0_epc + |
490 | dec_insn.pc_inc + | |
491 | dec_insn.next_pc_inc; | |
492 | /* Fall through */ | |
102cedc3 | 493 | case bgezl_op: |
319824ea MC |
494 | if (NO_R6EMU) |
495 | break; | |
496 | case bgez_op: | |
102cedc3 LY |
497 | if ((long)regs->regs[insn.i_format.rs] >= 0) |
498 | *contpc = regs->cp0_epc + | |
499 | dec_insn.pc_inc + | |
500 | (insn.i_format.simmediate << 2); | |
501 | else | |
502 | *contpc = regs->cp0_epc + | |
503 | dec_insn.pc_inc + | |
504 | dec_insn.next_pc_inc; | |
1da177e4 LT |
505 | return 1; |
506 | } | |
507 | break; | |
1da177e4 | 508 | case jalx_op: |
102cedc3 LY |
509 | set_isa16_mode(bit); |
510 | case jal_op: | |
511 | regs->regs[31] = regs->cp0_epc + | |
512 | dec_insn.pc_inc + | |
513 | dec_insn.next_pc_inc; | |
514 | /* Fall through */ | |
515 | case j_op: | |
516 | *contpc = regs->cp0_epc + dec_insn.pc_inc; | |
517 | *contpc >>= 28; | |
518 | *contpc <<= 28; | |
519 | *contpc |= (insn.j_format.target << 2); | |
520 | /* Set microMIPS mode bit: XOR for jalx. */ | |
521 | *contpc ^= bit; | |
522 | return 1; | |
1da177e4 | 523 | case beql_op: |
319824ea MC |
524 | if (NO_R6EMU) |
525 | break; | |
526 | case beq_op: | |
102cedc3 LY |
527 | if (regs->regs[insn.i_format.rs] == |
528 | regs->regs[insn.i_format.rt]) | |
529 | *contpc = regs->cp0_epc + | |
530 | dec_insn.pc_inc + | |
531 | (insn.i_format.simmediate << 2); | |
532 | else | |
533 | *contpc = regs->cp0_epc + | |
534 | dec_insn.pc_inc + | |
535 | dec_insn.next_pc_inc; | |
536 | return 1; | |
1da177e4 | 537 | case bnel_op: |
319824ea MC |
538 | if (NO_R6EMU) |
539 | break; | |
540 | case bne_op: | |
102cedc3 LY |
541 | if (regs->regs[insn.i_format.rs] != |
542 | regs->regs[insn.i_format.rt]) | |
543 | *contpc = regs->cp0_epc + | |
544 | dec_insn.pc_inc + | |
545 | (insn.i_format.simmediate << 2); | |
546 | else | |
547 | *contpc = regs->cp0_epc + | |
548 | dec_insn.pc_inc + | |
549 | dec_insn.next_pc_inc; | |
550 | return 1; | |
1da177e4 | 551 | case blezl_op: |
319824ea MC |
552 | if (NO_R6EMU) |
553 | break; | |
554 | case blez_op: | |
a8ff66f5 MC |
555 | |
556 | /* | |
557 | * Compact branches for R6 for the | |
558 | * blez and blezl opcodes. | |
559 | * BLEZ | rs = 0 | rt != 0 == BLEZALC | |
560 | * BLEZ | rs = rt != 0 == BGEZALC | |
561 | * BLEZ | rs != 0 | rt != 0 == BGEUC | |
562 | * BLEZL | rs = 0 | rt != 0 == BLEZC | |
563 | * BLEZL | rs = rt != 0 == BGEZC | |
564 | * BLEZL | rs != 0 | rt != 0 == BGEC | |
565 | * | |
566 | * For real BLEZ{,L}, rt is always 0. | |
567 | */ | |
568 | if (cpu_has_mips_r6 && insn.i_format.rt) { | |
569 | if ((insn.i_format.opcode == blez_op) && | |
570 | ((!insn.i_format.rs && insn.i_format.rt) || | |
571 | (insn.i_format.rs == insn.i_format.rt))) | |
572 | regs->regs[31] = regs->cp0_epc + | |
573 | dec_insn.pc_inc; | |
574 | *contpc = regs->cp0_epc + dec_insn.pc_inc + | |
575 | dec_insn.next_pc_inc; | |
576 | ||
577 | return 1; | |
578 | } | |
102cedc3 LY |
579 | if ((long)regs->regs[insn.i_format.rs] <= 0) |
580 | *contpc = regs->cp0_epc + | |
581 | dec_insn.pc_inc + | |
582 | (insn.i_format.simmediate << 2); | |
583 | else | |
584 | *contpc = regs->cp0_epc + | |
585 | dec_insn.pc_inc + | |
586 | dec_insn.next_pc_inc; | |
587 | return 1; | |
1da177e4 | 588 | case bgtzl_op: |
319824ea MC |
589 | if (NO_R6EMU) |
590 | break; | |
591 | case bgtz_op: | |
102cedc3 LY |
592 | if ((long)regs->regs[insn.i_format.rs] > 0) |
593 | *contpc = regs->cp0_epc + | |
594 | dec_insn.pc_inc + | |
595 | (insn.i_format.simmediate << 2); | |
596 | else | |
597 | *contpc = regs->cp0_epc + | |
598 | dec_insn.pc_inc + | |
599 | dec_insn.next_pc_inc; | |
1da177e4 | 600 | return 1; |
c26d4219 DD |
601 | #ifdef CONFIG_CPU_CAVIUM_OCTEON |
602 | case lwc2_op: /* This is bbit0 on Octeon */ | |
603 | if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0) | |
604 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
605 | else | |
606 | *contpc = regs->cp0_epc + 8; | |
607 | return 1; | |
608 | case ldc2_op: /* This is bbit032 on Octeon */ | |
609 | if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0) | |
610 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
611 | else | |
612 | *contpc = regs->cp0_epc + 8; | |
613 | return 1; | |
614 | case swc2_op: /* This is bbit1 on Octeon */ | |
615 | if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) | |
616 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
617 | else | |
618 | *contpc = regs->cp0_epc + 8; | |
619 | return 1; | |
620 | case sdc2_op: /* This is bbit132 on Octeon */ | |
621 | if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) | |
622 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
623 | else | |
624 | *contpc = regs->cp0_epc + 8; | |
625 | return 1; | |
626 | #endif | |
1da177e4 LT |
627 | case cop0_op: |
628 | case cop1_op: | |
c8a34581 MC |
629 | /* Need to check for R6 bc1nez and bc1eqz branches */ |
630 | if (cpu_has_mips_r6 && | |
631 | ((insn.i_format.rs == bc1eqz_op) || | |
632 | (insn.i_format.rs == bc1nez_op))) { | |
633 | bit = 0; | |
634 | switch (insn.i_format.rs) { | |
635 | case bc1eqz_op: | |
636 | if (get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1) | |
637 | bit = 1; | |
638 | break; | |
639 | case bc1nez_op: | |
640 | if (!(get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)) | |
641 | bit = 1; | |
642 | break; | |
643 | } | |
644 | if (bit) | |
645 | *contpc = regs->cp0_epc + | |
646 | dec_insn.pc_inc + | |
647 | (insn.i_format.simmediate << 2); | |
648 | else | |
649 | *contpc = regs->cp0_epc + | |
650 | dec_insn.pc_inc + | |
651 | dec_insn.next_pc_inc; | |
652 | ||
653 | return 1; | |
654 | } | |
655 | /* R2/R6 compatible cop1 instruction. Fall through */ | |
1da177e4 LT |
656 | case cop2_op: |
657 | case cop1x_op: | |
102cedc3 LY |
658 | if (insn.i_format.rs == bc_op) { |
659 | preempt_disable(); | |
660 | if (is_fpu_owner()) | |
842dfc11 | 661 | fcr31 = read_32bit_cp1_register(CP1_STATUS); |
102cedc3 LY |
662 | else |
663 | fcr31 = current->thread.fpu.fcr31; | |
664 | preempt_enable(); | |
665 | ||
666 | bit = (insn.i_format.rt >> 2); | |
667 | bit += (bit != 0); | |
668 | bit += 23; | |
669 | switch (insn.i_format.rt & 3) { | |
670 | case 0: /* bc1f */ | |
671 | case 2: /* bc1fl */ | |
672 | if (~fcr31 & (1 << bit)) | |
673 | *contpc = regs->cp0_epc + | |
674 | dec_insn.pc_inc + | |
675 | (insn.i_format.simmediate << 2); | |
676 | else | |
677 | *contpc = regs->cp0_epc + | |
678 | dec_insn.pc_inc + | |
679 | dec_insn.next_pc_inc; | |
680 | return 1; | |
102cedc3 LY |
681 | case 1: /* bc1t */ |
682 | case 3: /* bc1tl */ | |
683 | if (fcr31 & (1 << bit)) | |
684 | *contpc = regs->cp0_epc + | |
685 | dec_insn.pc_inc + | |
686 | (insn.i_format.simmediate << 2); | |
687 | else | |
688 | *contpc = regs->cp0_epc + | |
689 | dec_insn.pc_inc + | |
690 | dec_insn.next_pc_inc; | |
691 | return 1; | |
102cedc3 LY |
692 | } |
693 | } | |
1da177e4 LT |
694 | break; |
695 | } | |
1da177e4 LT |
696 | return 0; |
697 | } | |
698 | ||
699 | /* | |
700 | * In the Linux kernel, we support selection of FPR format on the | |
70342287 | 701 | * basis of the Status.FR bit. If an FPU is not present, the FR bit |
da0bac33 | 702 | * is hardwired to zero, which would imply a 32-bit FPU even for |
597ce172 | 703 | * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS. |
51d943f0 RB |
704 | * FPU emu is slow and bulky and optimizing this function offers fairly |
705 | * sizeable benefits so we try to be clever and make this function return | |
706 | * a constant whenever possible, that is on 64-bit kernels without O32 | |
597ce172 | 707 | * compatibility enabled and on 32-bit without 64-bit FPU support. |
1da177e4 | 708 | */ |
da0bac33 DD |
709 | static inline int cop1_64bit(struct pt_regs *xcp) |
710 | { | |
08a07904 RB |
711 | if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32)) |
712 | return 1; | |
713 | else if (config_enabled(CONFIG_32BIT) && | |
714 | !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT)) | |
715 | return 0; | |
716 | ||
597ce172 | 717 | return !test_thread_flag(TIF_32BIT_FPREGS); |
da0bac33 DD |
718 | } |
719 | ||
4227a2d4 PB |
720 | static inline bool hybrid_fprs(void) |
721 | { | |
722 | return test_thread_flag(TIF_HYBRID_FPREGS); | |
723 | } | |
724 | ||
47fa0c02 RB |
725 | #define SIFROMREG(si, x) \ |
726 | do { \ | |
4227a2d4 | 727 | if (cop1_64bit(xcp) && !hybrid_fprs()) \ |
c8c0da6b | 728 | (si) = (int)get_fpr32(&ctx->fpr[x], 0); \ |
bbd426f5 | 729 | else \ |
c8c0da6b | 730 | (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \ |
bbd426f5 | 731 | } while (0) |
1da177e4 | 732 | |
47fa0c02 RB |
733 | #define SITOREG(si, x) \ |
734 | do { \ | |
4227a2d4 | 735 | if (cop1_64bit(xcp) && !hybrid_fprs()) { \ |
ef1c47af | 736 | unsigned i; \ |
bbd426f5 | 737 | set_fpr32(&ctx->fpr[x], 0, si); \ |
ef1c47af PB |
738 | for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ |
739 | set_fpr32(&ctx->fpr[x], i, 0); \ | |
740 | } else { \ | |
bbd426f5 | 741 | set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \ |
ef1c47af | 742 | } \ |
bbd426f5 | 743 | } while (0) |
1da177e4 | 744 | |
c8c0da6b | 745 | #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1)) |
ef1c47af | 746 | |
47fa0c02 RB |
747 | #define SITOHREG(si, x) \ |
748 | do { \ | |
ef1c47af PB |
749 | unsigned i; \ |
750 | set_fpr32(&ctx->fpr[x], 1, si); \ | |
751 | for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ | |
752 | set_fpr32(&ctx->fpr[x], i, 0); \ | |
753 | } while (0) | |
1ac94400 | 754 | |
47fa0c02 | 755 | #define DIFROMREG(di, x) \ |
bbd426f5 PB |
756 | ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0)) |
757 | ||
47fa0c02 RB |
758 | #define DITOREG(di, x) \ |
759 | do { \ | |
ef1c47af PB |
760 | unsigned fpr, i; \ |
761 | fpr = (x) & ~(cop1_64bit(xcp) == 0); \ | |
762 | set_fpr64(&ctx->fpr[fpr], 0, di); \ | |
763 | for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \ | |
764 | set_fpr64(&ctx->fpr[fpr], i, 0); \ | |
765 | } while (0) | |
1da177e4 | 766 | |
21a151d8 RB |
767 | #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x) |
768 | #define SPTOREG(sp, x) SITOREG((sp).bits, x) | |
769 | #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x) | |
770 | #define DPTOREG(dp, x) DITOREG((dp).bits, x) | |
1da177e4 LT |
771 | |
772 | /* | |
773 | * Emulate the single floating point instruction pointed at by EPC. | |
774 | * Two instructions if the instruction is in a branch delay slot. | |
775 | */ | |
776 | ||
515b029d | 777 | static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
102cedc3 | 778 | struct mm_decoded_insn dec_insn, void *__user *fault_addr) |
1da177e4 | 779 | { |
102cedc3 | 780 | unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; |
3f7cac41 RB |
781 | unsigned int cond, cbit; |
782 | mips_instruction ir; | |
783 | int likely, pc_inc; | |
784 | u32 __user *wva; | |
785 | u64 __user *dva; | |
786 | u32 value; | |
787 | u32 wval; | |
788 | u64 dval; | |
789 | int sig; | |
1da177e4 | 790 | |
70e4c234 RB |
791 | /* |
792 | * These are giving gcc a gentle hint about what to expect in | |
793 | * dec_inst in order to do better optimization. | |
794 | */ | |
795 | if (!cpu_has_mmips && dec_insn.micro_mips_mode) | |
796 | unreachable(); | |
797 | ||
1da177e4 | 798 | /* XXX NEC Vr54xx bug workaround */ |
e7e9cae5 | 799 | if (delay_slot(xcp)) { |
102cedc3 LY |
800 | if (dec_insn.micro_mips_mode) { |
801 | if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) | |
e7e9cae5 | 802 | clear_delay_slot(xcp); |
102cedc3 LY |
803 | } else { |
804 | if (!isBranchInstr(xcp, dec_insn, &contpc)) | |
e7e9cae5 | 805 | clear_delay_slot(xcp); |
102cedc3 LY |
806 | } |
807 | } | |
1da177e4 | 808 | |
e7e9cae5 | 809 | if (delay_slot(xcp)) { |
1da177e4 LT |
810 | /* |
811 | * The instruction to be emulated is in a branch delay slot | |
70342287 | 812 | * which means that we have to emulate the branch instruction |
1da177e4 LT |
813 | * BEFORE we do the cop1 instruction. |
814 | * | |
815 | * This branch could be a COP1 branch, but in that case we | |
816 | * would have had a trap for that instruction, and would not | |
817 | * come through this route. | |
818 | * | |
819 | * Linux MIPS branch emulator operates on context, updating the | |
820 | * cp0_epc. | |
821 | */ | |
102cedc3 LY |
822 | ir = dec_insn.next_insn; /* process delay slot instr */ |
823 | pc_inc = dec_insn.next_pc_inc; | |
824 | } else { | |
825 | ir = dec_insn.insn; /* process current instr */ | |
826 | pc_inc = dec_insn.pc_inc; | |
827 | } | |
1da177e4 | 828 | |
102cedc3 LY |
829 | /* |
830 | * Since microMIPS FPU instructios are a subset of MIPS32 FPU | |
831 | * instructions, we want to convert microMIPS FPU instructions | |
832 | * into MIPS32 instructions so that we could reuse all of the | |
833 | * FPU emulation code. | |
834 | * | |
835 | * NOTE: We cannot do this for branch instructions since they | |
836 | * are not a subset. Example: Cannot emulate a 16-bit | |
837 | * aligned target address with a MIPS32 instruction. | |
838 | */ | |
839 | if (dec_insn.micro_mips_mode) { | |
840 | /* | |
841 | * If next instruction is a 16-bit instruction, then it | |
842 | * it cannot be a FPU instruction. This could happen | |
843 | * since we can be called for non-FPU instructions. | |
844 | */ | |
845 | if ((pc_inc == 2) || | |
846 | (microMIPS32_to_MIPS32((union mips_instruction *)&ir) | |
847 | == SIGILL)) | |
1da177e4 | 848 | return SIGILL; |
1da177e4 LT |
849 | } |
850 | ||
3f7cac41 | 851 | emul: |
a8b0ca17 | 852 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0); |
b6ee75ed | 853 | MIPS_FPU_EMU_INC_STATS(emulated); |
1da177e4 | 854 | switch (MIPSInst_OPCODE(ir)) { |
3f7cac41 RB |
855 | case ldc1_op: |
856 | dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + | |
857 | MIPSInst_SIMM(ir)); | |
b6ee75ed | 858 | MIPS_FPU_EMU_INC_STATS(loads); |
515b029d | 859 | |
3f7cac41 | 860 | if (!access_ok(VERIFY_READ, dva, sizeof(u64))) { |
b6ee75ed | 861 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 862 | *fault_addr = dva; |
1da177e4 LT |
863 | return SIGBUS; |
864 | } | |
3f7cac41 | 865 | if (__get_user(dval, dva)) { |
515b029d | 866 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 867 | *fault_addr = dva; |
515b029d DD |
868 | return SIGSEGV; |
869 | } | |
3f7cac41 | 870 | DITOREG(dval, MIPSInst_RT(ir)); |
1da177e4 | 871 | break; |
1da177e4 | 872 | |
3f7cac41 RB |
873 | case sdc1_op: |
874 | dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + | |
875 | MIPSInst_SIMM(ir)); | |
b6ee75ed | 876 | MIPS_FPU_EMU_INC_STATS(stores); |
3f7cac41 RB |
877 | DIFROMREG(dval, MIPSInst_RT(ir)); |
878 | if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) { | |
b6ee75ed | 879 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 880 | *fault_addr = dva; |
1da177e4 LT |
881 | return SIGBUS; |
882 | } | |
3f7cac41 | 883 | if (__put_user(dval, dva)) { |
515b029d | 884 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 885 | *fault_addr = dva; |
515b029d DD |
886 | return SIGSEGV; |
887 | } | |
1da177e4 | 888 | break; |
1da177e4 | 889 | |
3f7cac41 RB |
890 | case lwc1_op: |
891 | wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + | |
892 | MIPSInst_SIMM(ir)); | |
b6ee75ed | 893 | MIPS_FPU_EMU_INC_STATS(loads); |
3f7cac41 | 894 | if (!access_ok(VERIFY_READ, wva, sizeof(u32))) { |
b6ee75ed | 895 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 896 | *fault_addr = wva; |
1da177e4 LT |
897 | return SIGBUS; |
898 | } | |
3f7cac41 | 899 | if (__get_user(wval, wva)) { |
515b029d | 900 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 901 | *fault_addr = wva; |
515b029d DD |
902 | return SIGSEGV; |
903 | } | |
3f7cac41 | 904 | SITOREG(wval, MIPSInst_RT(ir)); |
1da177e4 | 905 | break; |
1da177e4 | 906 | |
3f7cac41 RB |
907 | case swc1_op: |
908 | wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + | |
909 | MIPSInst_SIMM(ir)); | |
b6ee75ed | 910 | MIPS_FPU_EMU_INC_STATS(stores); |
3f7cac41 RB |
911 | SIFROMREG(wval, MIPSInst_RT(ir)); |
912 | if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) { | |
b6ee75ed | 913 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 914 | *fault_addr = wva; |
1da177e4 LT |
915 | return SIGBUS; |
916 | } | |
3f7cac41 | 917 | if (__put_user(wval, wva)) { |
515b029d | 918 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 919 | *fault_addr = wva; |
515b029d DD |
920 | return SIGSEGV; |
921 | } | |
1da177e4 | 922 | break; |
1da177e4 LT |
923 | |
924 | case cop1_op: | |
925 | switch (MIPSInst_RS(ir)) { | |
1da177e4 | 926 | case dmfc_op: |
08a07904 RB |
927 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
928 | return SIGILL; | |
929 | ||
1da177e4 LT |
930 | /* copregister fs -> gpr[rt] */ |
931 | if (MIPSInst_RT(ir) != 0) { | |
932 | DIFROMREG(xcp->regs[MIPSInst_RT(ir)], | |
933 | MIPSInst_RD(ir)); | |
934 | } | |
935 | break; | |
936 | ||
937 | case dmtc_op: | |
08a07904 RB |
938 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
939 | return SIGILL; | |
940 | ||
1da177e4 LT |
941 | /* copregister fs <- rt */ |
942 | DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); | |
943 | break; | |
1da177e4 | 944 | |
1ac94400 LY |
945 | case mfhc_op: |
946 | if (!cpu_has_mips_r2) | |
947 | goto sigill; | |
948 | ||
949 | /* copregister rd -> gpr[rt] */ | |
950 | if (MIPSInst_RT(ir) != 0) { | |
951 | SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], | |
952 | MIPSInst_RD(ir)); | |
953 | } | |
954 | break; | |
955 | ||
956 | case mthc_op: | |
957 | if (!cpu_has_mips_r2) | |
958 | goto sigill; | |
959 | ||
960 | /* copregister rd <- gpr[rt] */ | |
961 | SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); | |
962 | break; | |
963 | ||
1da177e4 LT |
964 | case mfc_op: |
965 | /* copregister rd -> gpr[rt] */ | |
1da177e4 LT |
966 | if (MIPSInst_RT(ir) != 0) { |
967 | SIFROMREG(xcp->regs[MIPSInst_RT(ir)], | |
968 | MIPSInst_RD(ir)); | |
969 | } | |
970 | break; | |
971 | ||
972 | case mtc_op: | |
973 | /* copregister rd <- rt */ | |
1da177e4 LT |
974 | SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); |
975 | break; | |
976 | ||
3f7cac41 | 977 | case cfc_op: |
1da177e4 | 978 | /* cop control register rd -> gpr[rt] */ |
1da177e4 LT |
979 | if (MIPSInst_RD(ir) == FPCREG_CSR) { |
980 | value = ctx->fcr31; | |
56a64733 | 981 | value = (value & ~FPU_CSR_RM) | modeindex(value); |
92df0f8b RB |
982 | pr_debug("%p gpr[%d]<-csr=%08x\n", |
983 | (void *) (xcp->cp0_epc), | |
984 | MIPSInst_RT(ir), value); | |
1da177e4 LT |
985 | } |
986 | else if (MIPSInst_RD(ir) == FPCREG_RID) | |
987 | value = 0; | |
988 | else | |
989 | value = 0; | |
990 | if (MIPSInst_RT(ir)) | |
991 | xcp->regs[MIPSInst_RT(ir)] = value; | |
992 | break; | |
1da177e4 | 993 | |
3f7cac41 | 994 | case ctc_op: |
1da177e4 | 995 | /* copregister rd <- rt */ |
1da177e4 LT |
996 | if (MIPSInst_RT(ir) == 0) |
997 | value = 0; | |
998 | else | |
999 | value = xcp->regs[MIPSInst_RT(ir)]; | |
1000 | ||
1001 | /* we only have one writable control reg | |
1002 | */ | |
1003 | if (MIPSInst_RD(ir) == FPCREG_CSR) { | |
92df0f8b RB |
1004 | pr_debug("%p gpr[%d]->csr=%08x\n", |
1005 | (void *) (xcp->cp0_epc), | |
1006 | MIPSInst_RT(ir), value); | |
95e8f634 SM |
1007 | |
1008 | /* | |
1009 | * Don't write reserved bits, | |
1010 | * and convert to ieee library modes | |
1011 | */ | |
56a64733 RB |
1012 | ctx->fcr31 = (value & ~(FPU_CSR_RSVD | FPU_CSR_RM)) | |
1013 | modeindex(value); | |
1da177e4 LT |
1014 | } |
1015 | if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { | |
1016 | return SIGFPE; | |
1017 | } | |
1018 | break; | |
1da177e4 | 1019 | |
3f7cac41 | 1020 | case bc_op: |
e7e9cae5 | 1021 | if (delay_slot(xcp)) |
1da177e4 LT |
1022 | return SIGILL; |
1023 | ||
08a07904 RB |
1024 | if (cpu_has_mips_4_5_r) |
1025 | cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; | |
1026 | else | |
1027 | cbit = FPU_CSR_COND; | |
1028 | cond = ctx->fcr31 & cbit; | |
1029 | ||
3f7cac41 | 1030 | likely = 0; |
1da177e4 LT |
1031 | switch (MIPSInst_RT(ir) & 3) { |
1032 | case bcfl_op: | |
1033 | likely = 1; | |
1034 | case bcf_op: | |
1035 | cond = !cond; | |
1036 | break; | |
1037 | case bctl_op: | |
1038 | likely = 1; | |
1039 | case bct_op: | |
1040 | break; | |
1041 | default: | |
1042 | /* thats an illegal instruction */ | |
1043 | return SIGILL; | |
1044 | } | |
1045 | ||
e7e9cae5 | 1046 | set_delay_slot(xcp); |
1da177e4 | 1047 | if (cond) { |
3f7cac41 RB |
1048 | /* |
1049 | * Branch taken: emulate dslot instruction | |
1da177e4 | 1050 | */ |
102cedc3 LY |
1051 | xcp->cp0_epc += dec_insn.pc_inc; |
1052 | ||
1053 | contpc = MIPSInst_SIMM(ir); | |
1054 | ir = dec_insn.next_insn; | |
1055 | if (dec_insn.micro_mips_mode) { | |
1056 | contpc = (xcp->cp0_epc + (contpc << 1)); | |
1057 | ||
1058 | /* If 16-bit instruction, not FPU. */ | |
1059 | if ((dec_insn.next_pc_inc == 2) || | |
1060 | (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) { | |
1061 | ||
1062 | /* | |
1063 | * Since this instruction will | |
1064 | * be put on the stack with | |
1065 | * 32-bit words, get around | |
1066 | * this problem by putting a | |
1067 | * NOP16 as the second one. | |
1068 | */ | |
1069 | if (dec_insn.next_pc_inc == 2) | |
1070 | ir = (ir & (~0xffff)) | MM_NOP16; | |
1071 | ||
1072 | /* | |
1073 | * Single step the non-CP1 | |
1074 | * instruction in the dslot. | |
1075 | */ | |
1076 | return mips_dsemul(xcp, ir, contpc); | |
1077 | } | |
1078 | } else | |
1079 | contpc = (xcp->cp0_epc + (contpc << 2)); | |
1da177e4 LT |
1080 | |
1081 | switch (MIPSInst_OPCODE(ir)) { | |
1082 | case lwc1_op: | |
08a07904 | 1083 | goto emul; |
3f7cac41 | 1084 | |
1da177e4 | 1085 | case swc1_op: |
08a07904 | 1086 | goto emul; |
3f7cac41 | 1087 | |
1da177e4 LT |
1088 | case ldc1_op: |
1089 | case sdc1_op: | |
08a07904 RB |
1090 | if (cpu_has_mips_2_3_4_5 || |
1091 | cpu_has_mips64) | |
1092 | goto emul; | |
1093 | ||
1094 | return SIGILL; | |
1095 | goto emul; | |
3f7cac41 | 1096 | |
1da177e4 | 1097 | case cop1_op: |
1da177e4 | 1098 | goto emul; |
3f7cac41 | 1099 | |
08a07904 | 1100 | case cop1x_op: |
a5466d7b | 1101 | if (cpu_has_mips_4_5 || cpu_has_mips64 || cpu_has_mips32r2) |
08a07904 RB |
1102 | /* its one of ours */ |
1103 | goto emul; | |
1104 | ||
1105 | return SIGILL; | |
3f7cac41 | 1106 | |
1da177e4 | 1107 | case spec_op: |
08a07904 RB |
1108 | if (!cpu_has_mips_4_5_r) |
1109 | return SIGILL; | |
1110 | ||
1da177e4 LT |
1111 | if (MIPSInst_FUNC(ir) == movc_op) |
1112 | goto emul; | |
1113 | break; | |
1da177e4 LT |
1114 | } |
1115 | ||
1116 | /* | |
1117 | * Single step the non-cp1 | |
1118 | * instruction in the dslot | |
1119 | */ | |
e70dfc10 | 1120 | return mips_dsemul(xcp, ir, contpc); |
3f7cac41 | 1121 | } else if (likely) { /* branch not taken */ |
1da177e4 LT |
1122 | /* |
1123 | * branch likely nullifies | |
1124 | * dslot if not taken | |
1125 | */ | |
102cedc3 LY |
1126 | xcp->cp0_epc += dec_insn.pc_inc; |
1127 | contpc += dec_insn.pc_inc; | |
1da177e4 LT |
1128 | /* |
1129 | * else continue & execute | |
1130 | * dslot as normal insn | |
1131 | */ | |
1132 | } | |
1da177e4 | 1133 | break; |
1da177e4 LT |
1134 | |
1135 | default: | |
1136 | if (!(MIPSInst_RS(ir) & 0x10)) | |
1137 | return SIGILL; | |
1da177e4 | 1138 | |
3f7cac41 RB |
1139 | /* a real fpu computation instruction */ |
1140 | if ((sig = fpu_emu(xcp, ctx, ir))) | |
1141 | return sig; | |
1da177e4 LT |
1142 | } |
1143 | break; | |
1144 | ||
3f7cac41 | 1145 | case cop1x_op: |
a5466d7b | 1146 | if (!cpu_has_mips_4_5 && !cpu_has_mips64 && !cpu_has_mips32r2) |
08a07904 RB |
1147 | return SIGILL; |
1148 | ||
1149 | sig = fpux_emu(xcp, ctx, ir, fault_addr); | |
515b029d | 1150 | if (sig) |
1da177e4 LT |
1151 | return sig; |
1152 | break; | |
1da177e4 | 1153 | |
1da177e4 | 1154 | case spec_op: |
08a07904 RB |
1155 | if (!cpu_has_mips_4_5_r) |
1156 | return SIGILL; | |
1157 | ||
1da177e4 LT |
1158 | if (MIPSInst_FUNC(ir) != movc_op) |
1159 | return SIGILL; | |
1160 | cond = fpucondbit[MIPSInst_RT(ir) >> 2]; | |
1161 | if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) | |
1162 | xcp->regs[MIPSInst_RD(ir)] = | |
1163 | xcp->regs[MIPSInst_RS(ir)]; | |
1164 | break; | |
1da177e4 | 1165 | default: |
1ac94400 | 1166 | sigill: |
1da177e4 LT |
1167 | return SIGILL; |
1168 | } | |
1169 | ||
1170 | /* we did it !! */ | |
e70dfc10 | 1171 | xcp->cp0_epc = contpc; |
e7e9cae5 | 1172 | clear_delay_slot(xcp); |
333d1f67 | 1173 | |
1da177e4 LT |
1174 | return 0; |
1175 | } | |
1176 | ||
1177 | /* | |
1178 | * Conversion table from MIPS compare ops 48-63 | |
1179 | * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig); | |
1180 | */ | |
1181 | static const unsigned char cmptab[8] = { | |
1182 | 0, /* cmp_0 (sig) cmp_sf */ | |
1183 | IEEE754_CUN, /* cmp_un (sig) cmp_ngle */ | |
1184 | IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */ | |
1185 | IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */ | |
1186 | IEEE754_CLT, /* cmp_olt (sig) cmp_lt */ | |
1187 | IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */ | |
1188 | IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */ | |
1189 | IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */ | |
1190 | }; | |
1191 | ||
1192 | ||
1da177e4 LT |
1193 | /* |
1194 | * Additional MIPS4 instructions | |
1195 | */ | |
1196 | ||
47fa0c02 RB |
1197 | #define DEF3OP(name, p, f1, f2, f3) \ |
1198 | static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \ | |
1199 | union ieee754##p s, union ieee754##p t) \ | |
1200 | { \ | |
1201 | struct _ieee754_csr ieee754_csr_save; \ | |
1202 | s = f1(s, t); \ | |
1203 | ieee754_csr_save = ieee754_csr; \ | |
1204 | s = f2(s, r); \ | |
1205 | ieee754_csr_save.cx |= ieee754_csr.cx; \ | |
1206 | ieee754_csr_save.sx |= ieee754_csr.sx; \ | |
1207 | s = f3(s); \ | |
1208 | ieee754_csr.cx |= ieee754_csr_save.cx; \ | |
1209 | ieee754_csr.sx |= ieee754_csr_save.sx; \ | |
1210 | return s; \ | |
1da177e4 LT |
1211 | } |
1212 | ||
2209bcb1 | 1213 | static union ieee754dp fpemu_dp_recip(union ieee754dp d) |
1da177e4 LT |
1214 | { |
1215 | return ieee754dp_div(ieee754dp_one(0), d); | |
1216 | } | |
1217 | ||
2209bcb1 | 1218 | static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d) |
1da177e4 LT |
1219 | { |
1220 | return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d)); | |
1221 | } | |
1222 | ||
2209bcb1 | 1223 | static union ieee754sp fpemu_sp_recip(union ieee754sp s) |
1da177e4 LT |
1224 | { |
1225 | return ieee754sp_div(ieee754sp_one(0), s); | |
1226 | } | |
1227 | ||
2209bcb1 | 1228 | static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s) |
1da177e4 LT |
1229 | { |
1230 | return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); | |
1231 | } | |
1232 | ||
21a151d8 RB |
1233 | DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, ); |
1234 | DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, ); | |
1da177e4 LT |
1235 | DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); |
1236 | DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); | |
21a151d8 RB |
1237 | DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, ); |
1238 | DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, ); | |
1da177e4 LT |
1239 | DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); |
1240 | DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); | |
1241 | ||
eae89076 | 1242 | static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
515b029d | 1243 | mips_instruction ir, void *__user *fault_addr) |
1da177e4 LT |
1244 | { |
1245 | unsigned rcsr = 0; /* resulting csr */ | |
1246 | ||
b6ee75ed | 1247 | MIPS_FPU_EMU_INC_STATS(cp1xops); |
1da177e4 LT |
1248 | |
1249 | switch (MIPSInst_FMA_FFMT(ir)) { | |
1250 | case s_fmt:{ /* 0 */ | |
1251 | ||
2209bcb1 RB |
1252 | union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp); |
1253 | union ieee754sp fd, fr, fs, ft; | |
3fccc015 | 1254 | u32 __user *va; |
1da177e4 LT |
1255 | u32 val; |
1256 | ||
1257 | switch (MIPSInst_FUNC(ir)) { | |
1258 | case lwxc1_op: | |
3fccc015 | 1259 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1260 | xcp->regs[MIPSInst_FT(ir)]); |
1261 | ||
b6ee75ed | 1262 | MIPS_FPU_EMU_INC_STATS(loads); |
515b029d | 1263 | if (!access_ok(VERIFY_READ, va, sizeof(u32))) { |
b6ee75ed | 1264 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1265 | *fault_addr = va; |
1da177e4 LT |
1266 | return SIGBUS; |
1267 | } | |
515b029d DD |
1268 | if (__get_user(val, va)) { |
1269 | MIPS_FPU_EMU_INC_STATS(errors); | |
1270 | *fault_addr = va; | |
1271 | return SIGSEGV; | |
1272 | } | |
1da177e4 LT |
1273 | SITOREG(val, MIPSInst_FD(ir)); |
1274 | break; | |
1275 | ||
1276 | case swxc1_op: | |
3fccc015 | 1277 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1278 | xcp->regs[MIPSInst_FT(ir)]); |
1279 | ||
b6ee75ed | 1280 | MIPS_FPU_EMU_INC_STATS(stores); |
1da177e4 LT |
1281 | |
1282 | SIFROMREG(val, MIPSInst_FS(ir)); | |
515b029d | 1283 | if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { |
b6ee75ed | 1284 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1285 | *fault_addr = va; |
1da177e4 LT |
1286 | return SIGBUS; |
1287 | } | |
515b029d DD |
1288 | if (put_user(val, va)) { |
1289 | MIPS_FPU_EMU_INC_STATS(errors); | |
1290 | *fault_addr = va; | |
1291 | return SIGSEGV; | |
1292 | } | |
1da177e4 LT |
1293 | break; |
1294 | ||
1295 | case madd_s_op: | |
1296 | handler = fpemu_sp_madd; | |
1297 | goto scoptop; | |
1298 | case msub_s_op: | |
1299 | handler = fpemu_sp_msub; | |
1300 | goto scoptop; | |
1301 | case nmadd_s_op: | |
1302 | handler = fpemu_sp_nmadd; | |
1303 | goto scoptop; | |
1304 | case nmsub_s_op: | |
1305 | handler = fpemu_sp_nmsub; | |
1306 | goto scoptop; | |
1307 | ||
1308 | scoptop: | |
1309 | SPFROMREG(fr, MIPSInst_FR(ir)); | |
1310 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1311 | SPFROMREG(ft, MIPSInst_FT(ir)); | |
1312 | fd = (*handler) (fr, fs, ft); | |
1313 | SPTOREG(fd, MIPSInst_FD(ir)); | |
1314 | ||
1315 | copcsr: | |
c4103526 DCZ |
1316 | if (ieee754_cxtest(IEEE754_INEXACT)) { |
1317 | MIPS_FPU_EMU_INC_STATS(ieee754_inexact); | |
1da177e4 | 1318 | rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; |
c4103526 DCZ |
1319 | } |
1320 | if (ieee754_cxtest(IEEE754_UNDERFLOW)) { | |
1321 | MIPS_FPU_EMU_INC_STATS(ieee754_underflow); | |
1da177e4 | 1322 | rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; |
c4103526 DCZ |
1323 | } |
1324 | if (ieee754_cxtest(IEEE754_OVERFLOW)) { | |
1325 | MIPS_FPU_EMU_INC_STATS(ieee754_overflow); | |
1da177e4 | 1326 | rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; |
c4103526 DCZ |
1327 | } |
1328 | if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { | |
1329 | MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); | |
1da177e4 | 1330 | rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; |
c4103526 | 1331 | } |
1da177e4 LT |
1332 | |
1333 | ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; | |
1da177e4 | 1334 | if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { |
3f7cac41 | 1335 | /*printk ("SIGFPE: FPU csr = %08x\n", |
1da177e4 LT |
1336 | ctx->fcr31); */ |
1337 | return SIGFPE; | |
1338 | } | |
1339 | ||
1340 | break; | |
1341 | ||
1342 | default: | |
1343 | return SIGILL; | |
1344 | } | |
1345 | break; | |
1346 | } | |
1347 | ||
1da177e4 | 1348 | case d_fmt:{ /* 1 */ |
2209bcb1 RB |
1349 | union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp); |
1350 | union ieee754dp fd, fr, fs, ft; | |
3fccc015 | 1351 | u64 __user *va; |
1da177e4 LT |
1352 | u64 val; |
1353 | ||
1354 | switch (MIPSInst_FUNC(ir)) { | |
1355 | case ldxc1_op: | |
3fccc015 | 1356 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1357 | xcp->regs[MIPSInst_FT(ir)]); |
1358 | ||
b6ee75ed | 1359 | MIPS_FPU_EMU_INC_STATS(loads); |
515b029d | 1360 | if (!access_ok(VERIFY_READ, va, sizeof(u64))) { |
b6ee75ed | 1361 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1362 | *fault_addr = va; |
1da177e4 LT |
1363 | return SIGBUS; |
1364 | } | |
515b029d DD |
1365 | if (__get_user(val, va)) { |
1366 | MIPS_FPU_EMU_INC_STATS(errors); | |
1367 | *fault_addr = va; | |
1368 | return SIGSEGV; | |
1369 | } | |
1da177e4 LT |
1370 | DITOREG(val, MIPSInst_FD(ir)); |
1371 | break; | |
1372 | ||
1373 | case sdxc1_op: | |
3fccc015 | 1374 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1375 | xcp->regs[MIPSInst_FT(ir)]); |
1376 | ||
b6ee75ed | 1377 | MIPS_FPU_EMU_INC_STATS(stores); |
1da177e4 | 1378 | DIFROMREG(val, MIPSInst_FS(ir)); |
515b029d | 1379 | if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { |
b6ee75ed | 1380 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1381 | *fault_addr = va; |
1da177e4 LT |
1382 | return SIGBUS; |
1383 | } | |
515b029d DD |
1384 | if (__put_user(val, va)) { |
1385 | MIPS_FPU_EMU_INC_STATS(errors); | |
1386 | *fault_addr = va; | |
1387 | return SIGSEGV; | |
1388 | } | |
1da177e4 LT |
1389 | break; |
1390 | ||
1391 | case madd_d_op: | |
1392 | handler = fpemu_dp_madd; | |
1393 | goto dcoptop; | |
1394 | case msub_d_op: | |
1395 | handler = fpemu_dp_msub; | |
1396 | goto dcoptop; | |
1397 | case nmadd_d_op: | |
1398 | handler = fpemu_dp_nmadd; | |
1399 | goto dcoptop; | |
1400 | case nmsub_d_op: | |
1401 | handler = fpemu_dp_nmsub; | |
1402 | goto dcoptop; | |
1403 | ||
1404 | dcoptop: | |
1405 | DPFROMREG(fr, MIPSInst_FR(ir)); | |
1406 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1407 | DPFROMREG(ft, MIPSInst_FT(ir)); | |
1408 | fd = (*handler) (fr, fs, ft); | |
1409 | DPTOREG(fd, MIPSInst_FD(ir)); | |
1410 | goto copcsr; | |
1411 | ||
1412 | default: | |
1413 | return SIGILL; | |
1414 | } | |
1415 | break; | |
1416 | } | |
1da177e4 | 1417 | |
51061b88 DCZ |
1418 | case 0x3: |
1419 | if (MIPSInst_FUNC(ir) != pfetch_op) | |
1da177e4 | 1420 | return SIGILL; |
51061b88 | 1421 | |
1da177e4 LT |
1422 | /* ignore prefx operation */ |
1423 | break; | |
1424 | ||
1425 | default: | |
1426 | return SIGILL; | |
1427 | } | |
1428 | ||
1429 | return 0; | |
1430 | } | |
1da177e4 LT |
1431 | |
1432 | ||
1433 | ||
1434 | /* | |
1435 | * Emulate a single COP1 arithmetic instruction. | |
1436 | */ | |
eae89076 | 1437 | static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
1da177e4 LT |
1438 | mips_instruction ir) |
1439 | { | |
1440 | int rfmt; /* resulting format */ | |
1441 | unsigned rcsr = 0; /* resulting csr */ | |
3f7cac41 RB |
1442 | unsigned int oldrm; |
1443 | unsigned int cbit; | |
1da177e4 LT |
1444 | unsigned cond; |
1445 | union { | |
2209bcb1 RB |
1446 | union ieee754dp d; |
1447 | union ieee754sp s; | |
1da177e4 | 1448 | int w; |
1da177e4 | 1449 | s64 l; |
1da177e4 | 1450 | } rv; /* resulting value */ |
3f7cac41 | 1451 | u64 bits; |
1da177e4 | 1452 | |
b6ee75ed | 1453 | MIPS_FPU_EMU_INC_STATS(cp1ops); |
1da177e4 | 1454 | switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { |
3f7cac41 | 1455 | case s_fmt: { /* 0 */ |
1da177e4 | 1456 | union { |
2209bcb1 RB |
1457 | union ieee754sp(*b) (union ieee754sp, union ieee754sp); |
1458 | union ieee754sp(*u) (union ieee754sp); | |
1da177e4 | 1459 | } handler; |
3f7cac41 | 1460 | union ieee754sp fs, ft; |
1da177e4 LT |
1461 | |
1462 | switch (MIPSInst_FUNC(ir)) { | |
1463 | /* binary ops */ | |
1464 | case fadd_op: | |
1465 | handler.b = ieee754sp_add; | |
1466 | goto scopbop; | |
1467 | case fsub_op: | |
1468 | handler.b = ieee754sp_sub; | |
1469 | goto scopbop; | |
1470 | case fmul_op: | |
1471 | handler.b = ieee754sp_mul; | |
1472 | goto scopbop; | |
1473 | case fdiv_op: | |
1474 | handler.b = ieee754sp_div; | |
1475 | goto scopbop; | |
1476 | ||
1477 | /* unary ops */ | |
1da177e4 | 1478 | case fsqrt_op: |
08a07904 RB |
1479 | if (!cpu_has_mips_4_5_r) |
1480 | return SIGILL; | |
1481 | ||
1da177e4 LT |
1482 | handler.u = ieee754sp_sqrt; |
1483 | goto scopuop; | |
3f7cac41 | 1484 | |
08a07904 RB |
1485 | /* |
1486 | * Note that on some MIPS IV implementations such as the | |
1487 | * R5000 and R8000 the FSQRT and FRECIP instructions do not | |
1488 | * achieve full IEEE-754 accuracy - however this emulator does. | |
1489 | */ | |
1da177e4 | 1490 | case frsqrt_op: |
08a07904 RB |
1491 | if (!cpu_has_mips_4_5_r2) |
1492 | return SIGILL; | |
1493 | ||
1da177e4 LT |
1494 | handler.u = fpemu_sp_rsqrt; |
1495 | goto scopuop; | |
3f7cac41 | 1496 | |
1da177e4 | 1497 | case frecip_op: |
08a07904 RB |
1498 | if (!cpu_has_mips_4_5_r2) |
1499 | return SIGILL; | |
1500 | ||
1da177e4 LT |
1501 | handler.u = fpemu_sp_recip; |
1502 | goto scopuop; | |
08a07904 | 1503 | |
1da177e4 | 1504 | case fmovc_op: |
08a07904 RB |
1505 | if (!cpu_has_mips_4_5_r) |
1506 | return SIGILL; | |
1507 | ||
1da177e4 LT |
1508 | cond = fpucondbit[MIPSInst_FT(ir) >> 2]; |
1509 | if (((ctx->fcr31 & cond) != 0) != | |
1510 | ((MIPSInst_FT(ir) & 1) != 0)) | |
1511 | return 0; | |
1512 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1513 | break; | |
3f7cac41 | 1514 | |
1da177e4 | 1515 | case fmovz_op: |
08a07904 RB |
1516 | if (!cpu_has_mips_4_5_r) |
1517 | return SIGILL; | |
1518 | ||
1da177e4 LT |
1519 | if (xcp->regs[MIPSInst_FT(ir)] != 0) |
1520 | return 0; | |
1521 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1522 | break; | |
3f7cac41 | 1523 | |
1da177e4 | 1524 | case fmovn_op: |
08a07904 RB |
1525 | if (!cpu_has_mips_4_5_r) |
1526 | return SIGILL; | |
1527 | ||
1da177e4 LT |
1528 | if (xcp->regs[MIPSInst_FT(ir)] == 0) |
1529 | return 0; | |
1530 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1531 | break; | |
3f7cac41 | 1532 | |
1da177e4 LT |
1533 | case fabs_op: |
1534 | handler.u = ieee754sp_abs; | |
1535 | goto scopuop; | |
3f7cac41 | 1536 | |
1da177e4 LT |
1537 | case fneg_op: |
1538 | handler.u = ieee754sp_neg; | |
1539 | goto scopuop; | |
3f7cac41 | 1540 | |
1da177e4 LT |
1541 | case fmov_op: |
1542 | /* an easy one */ | |
1543 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1544 | goto copcsr; | |
1545 | ||
1546 | /* binary op on handler */ | |
3f7cac41 RB |
1547 | scopbop: |
1548 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1549 | SPFROMREG(ft, MIPSInst_FT(ir)); | |
1da177e4 | 1550 | |
3f7cac41 RB |
1551 | rv.s = (*handler.b) (fs, ft); |
1552 | goto copcsr; | |
1553 | scopuop: | |
1554 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1555 | rv.s = (*handler.u) (fs); | |
1556 | goto copcsr; | |
1557 | copcsr: | |
c4103526 DCZ |
1558 | if (ieee754_cxtest(IEEE754_INEXACT)) { |
1559 | MIPS_FPU_EMU_INC_STATS(ieee754_inexact); | |
1da177e4 | 1560 | rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; |
c4103526 DCZ |
1561 | } |
1562 | if (ieee754_cxtest(IEEE754_UNDERFLOW)) { | |
1563 | MIPS_FPU_EMU_INC_STATS(ieee754_underflow); | |
1da177e4 | 1564 | rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; |
c4103526 DCZ |
1565 | } |
1566 | if (ieee754_cxtest(IEEE754_OVERFLOW)) { | |
1567 | MIPS_FPU_EMU_INC_STATS(ieee754_overflow); | |
1da177e4 | 1568 | rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; |
c4103526 DCZ |
1569 | } |
1570 | if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) { | |
1571 | MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv); | |
1da177e4 | 1572 | rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S; |
c4103526 DCZ |
1573 | } |
1574 | if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { | |
1575 | MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); | |
1da177e4 | 1576 | rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; |
c4103526 | 1577 | } |
1da177e4 LT |
1578 | break; |
1579 | ||
1580 | /* unary conv ops */ | |
1581 | case fcvts_op: | |
1582 | return SIGILL; /* not defined */ | |
1da177e4 | 1583 | |
3f7cac41 | 1584 | case fcvtd_op: |
1da177e4 LT |
1585 | SPFROMREG(fs, MIPSInst_FS(ir)); |
1586 | rv.d = ieee754dp_fsp(fs); | |
1587 | rfmt = d_fmt; | |
1588 | goto copcsr; | |
1da177e4 | 1589 | |
3f7cac41 | 1590 | case fcvtw_op: |
1da177e4 LT |
1591 | SPFROMREG(fs, MIPSInst_FS(ir)); |
1592 | rv.w = ieee754sp_tint(fs); | |
1593 | rfmt = w_fmt; | |
1594 | goto copcsr; | |
1da177e4 | 1595 | |
1da177e4 LT |
1596 | case fround_op: |
1597 | case ftrunc_op: | |
1598 | case fceil_op: | |
3f7cac41 | 1599 | case ffloor_op: |
08a07904 RB |
1600 | if (!cpu_has_mips_2_3_4_5 && !cpu_has_mips64) |
1601 | return SIGILL; | |
1602 | ||
3f7cac41 | 1603 | oldrm = ieee754_csr.rm; |
1da177e4 | 1604 | SPFROMREG(fs, MIPSInst_FS(ir)); |
56a64733 | 1605 | ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); |
1da177e4 LT |
1606 | rv.w = ieee754sp_tint(fs); |
1607 | ieee754_csr.rm = oldrm; | |
1608 | rfmt = w_fmt; | |
1609 | goto copcsr; | |
1da177e4 | 1610 | |
3f7cac41 | 1611 | case fcvtl_op: |
08a07904 RB |
1612 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1613 | return SIGILL; | |
1614 | ||
1da177e4 LT |
1615 | SPFROMREG(fs, MIPSInst_FS(ir)); |
1616 | rv.l = ieee754sp_tlong(fs); | |
1617 | rfmt = l_fmt; | |
1618 | goto copcsr; | |
1da177e4 LT |
1619 | |
1620 | case froundl_op: | |
1621 | case ftruncl_op: | |
1622 | case fceill_op: | |
3f7cac41 | 1623 | case ffloorl_op: |
08a07904 RB |
1624 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1625 | return SIGILL; | |
1626 | ||
3f7cac41 | 1627 | oldrm = ieee754_csr.rm; |
1da177e4 | 1628 | SPFROMREG(fs, MIPSInst_FS(ir)); |
56a64733 | 1629 | ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); |
1da177e4 LT |
1630 | rv.l = ieee754sp_tlong(fs); |
1631 | ieee754_csr.rm = oldrm; | |
1632 | rfmt = l_fmt; | |
1633 | goto copcsr; | |
1da177e4 LT |
1634 | |
1635 | default: | |
1636 | if (MIPSInst_FUNC(ir) >= fcmp_op) { | |
1637 | unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; | |
2209bcb1 | 1638 | union ieee754sp fs, ft; |
1da177e4 LT |
1639 | |
1640 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1641 | SPFROMREG(ft, MIPSInst_FT(ir)); | |
1642 | rv.w = ieee754sp_cmp(fs, ft, | |
1643 | cmptab[cmpop & 0x7], cmpop & 0x8); | |
1644 | rfmt = -1; | |
1645 | if ((cmpop & 0x8) && ieee754_cxtest | |
1646 | (IEEE754_INVALID_OPERATION)) | |
1647 | rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; | |
1648 | else | |
1649 | goto copcsr; | |
1650 | ||
3f7cac41 | 1651 | } else |
1da177e4 | 1652 | return SIGILL; |
1da177e4 LT |
1653 | break; |
1654 | } | |
1655 | break; | |
1656 | } | |
1657 | ||
3f7cac41 RB |
1658 | case d_fmt: { |
1659 | union ieee754dp fs, ft; | |
1da177e4 | 1660 | union { |
2209bcb1 RB |
1661 | union ieee754dp(*b) (union ieee754dp, union ieee754dp); |
1662 | union ieee754dp(*u) (union ieee754dp); | |
1da177e4 LT |
1663 | } handler; |
1664 | ||
1665 | switch (MIPSInst_FUNC(ir)) { | |
1666 | /* binary ops */ | |
1667 | case fadd_op: | |
1668 | handler.b = ieee754dp_add; | |
1669 | goto dcopbop; | |
1670 | case fsub_op: | |
1671 | handler.b = ieee754dp_sub; | |
1672 | goto dcopbop; | |
1673 | case fmul_op: | |
1674 | handler.b = ieee754dp_mul; | |
1675 | goto dcopbop; | |
1676 | case fdiv_op: | |
1677 | handler.b = ieee754dp_div; | |
1678 | goto dcopbop; | |
1679 | ||
1680 | /* unary ops */ | |
1da177e4 | 1681 | case fsqrt_op: |
08a07904 RB |
1682 | if (!cpu_has_mips_2_3_4_5_r) |
1683 | return SIGILL; | |
1684 | ||
1da177e4 LT |
1685 | handler.u = ieee754dp_sqrt; |
1686 | goto dcopuop; | |
08a07904 RB |
1687 | /* |
1688 | * Note that on some MIPS IV implementations such as the | |
1689 | * R5000 and R8000 the FSQRT and FRECIP instructions do not | |
1690 | * achieve full IEEE-754 accuracy - however this emulator does. | |
1691 | */ | |
1da177e4 | 1692 | case frsqrt_op: |
08a07904 RB |
1693 | if (!cpu_has_mips_4_5_r2) |
1694 | return SIGILL; | |
1695 | ||
1da177e4 LT |
1696 | handler.u = fpemu_dp_rsqrt; |
1697 | goto dcopuop; | |
1698 | case frecip_op: | |
08a07904 RB |
1699 | if (!cpu_has_mips_4_5_r2) |
1700 | return SIGILL; | |
1701 | ||
1da177e4 LT |
1702 | handler.u = fpemu_dp_recip; |
1703 | goto dcopuop; | |
1da177e4 | 1704 | case fmovc_op: |
08a07904 RB |
1705 | if (!cpu_has_mips_4_5_r) |
1706 | return SIGILL; | |
1707 | ||
1da177e4 LT |
1708 | cond = fpucondbit[MIPSInst_FT(ir) >> 2]; |
1709 | if (((ctx->fcr31 & cond) != 0) != | |
1710 | ((MIPSInst_FT(ir) & 1) != 0)) | |
1711 | return 0; | |
1712 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1713 | break; | |
1714 | case fmovz_op: | |
08a07904 RB |
1715 | if (!cpu_has_mips_4_5_r) |
1716 | return SIGILL; | |
1717 | ||
1da177e4 LT |
1718 | if (xcp->regs[MIPSInst_FT(ir)] != 0) |
1719 | return 0; | |
1720 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1721 | break; | |
1722 | case fmovn_op: | |
08a07904 RB |
1723 | if (!cpu_has_mips_4_5_r) |
1724 | return SIGILL; | |
1725 | ||
1da177e4 LT |
1726 | if (xcp->regs[MIPSInst_FT(ir)] == 0) |
1727 | return 0; | |
1728 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1729 | break; | |
1da177e4 LT |
1730 | case fabs_op: |
1731 | handler.u = ieee754dp_abs; | |
1732 | goto dcopuop; | |
1733 | ||
1734 | case fneg_op: | |
1735 | handler.u = ieee754dp_neg; | |
1736 | goto dcopuop; | |
1737 | ||
1738 | case fmov_op: | |
1739 | /* an easy one */ | |
1740 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1741 | goto copcsr; | |
1742 | ||
1743 | /* binary op on handler */ | |
3f7cac41 RB |
1744 | dcopbop: |
1745 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1746 | DPFROMREG(ft, MIPSInst_FT(ir)); | |
1da177e4 | 1747 | |
3f7cac41 RB |
1748 | rv.d = (*handler.b) (fs, ft); |
1749 | goto copcsr; | |
1750 | dcopuop: | |
1751 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1752 | rv.d = (*handler.u) (fs); | |
1753 | goto copcsr; | |
1da177e4 | 1754 | |
3f7cac41 RB |
1755 | /* |
1756 | * unary conv ops | |
1757 | */ | |
1758 | case fcvts_op: | |
1da177e4 LT |
1759 | DPFROMREG(fs, MIPSInst_FS(ir)); |
1760 | rv.s = ieee754sp_fdp(fs); | |
1761 | rfmt = s_fmt; | |
1762 | goto copcsr; | |
3f7cac41 | 1763 | |
1da177e4 LT |
1764 | case fcvtd_op: |
1765 | return SIGILL; /* not defined */ | |
1766 | ||
3f7cac41 | 1767 | case fcvtw_op: |
1da177e4 LT |
1768 | DPFROMREG(fs, MIPSInst_FS(ir)); |
1769 | rv.w = ieee754dp_tint(fs); /* wrong */ | |
1770 | rfmt = w_fmt; | |
1771 | goto copcsr; | |
1da177e4 | 1772 | |
1da177e4 LT |
1773 | case fround_op: |
1774 | case ftrunc_op: | |
1775 | case fceil_op: | |
3f7cac41 | 1776 | case ffloor_op: |
08a07904 RB |
1777 | if (!cpu_has_mips_2_3_4_5_r) |
1778 | return SIGILL; | |
1779 | ||
3f7cac41 | 1780 | oldrm = ieee754_csr.rm; |
1da177e4 | 1781 | DPFROMREG(fs, MIPSInst_FS(ir)); |
56a64733 | 1782 | ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); |
1da177e4 LT |
1783 | rv.w = ieee754dp_tint(fs); |
1784 | ieee754_csr.rm = oldrm; | |
1785 | rfmt = w_fmt; | |
1786 | goto copcsr; | |
1da177e4 | 1787 | |
3f7cac41 | 1788 | case fcvtl_op: |
08a07904 RB |
1789 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1790 | return SIGILL; | |
1791 | ||
1da177e4 LT |
1792 | DPFROMREG(fs, MIPSInst_FS(ir)); |
1793 | rv.l = ieee754dp_tlong(fs); | |
1794 | rfmt = l_fmt; | |
1795 | goto copcsr; | |
1da177e4 LT |
1796 | |
1797 | case froundl_op: | |
1798 | case ftruncl_op: | |
1799 | case fceill_op: | |
3f7cac41 | 1800 | case ffloorl_op: |
08a07904 RB |
1801 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1802 | return SIGILL; | |
1803 | ||
3f7cac41 | 1804 | oldrm = ieee754_csr.rm; |
1da177e4 | 1805 | DPFROMREG(fs, MIPSInst_FS(ir)); |
56a64733 | 1806 | ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); |
1da177e4 LT |
1807 | rv.l = ieee754dp_tlong(fs); |
1808 | ieee754_csr.rm = oldrm; | |
1809 | rfmt = l_fmt; | |
1810 | goto copcsr; | |
1da177e4 LT |
1811 | |
1812 | default: | |
1813 | if (MIPSInst_FUNC(ir) >= fcmp_op) { | |
1814 | unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; | |
2209bcb1 | 1815 | union ieee754dp fs, ft; |
1da177e4 LT |
1816 | |
1817 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1818 | DPFROMREG(ft, MIPSInst_FT(ir)); | |
1819 | rv.w = ieee754dp_cmp(fs, ft, | |
1820 | cmptab[cmpop & 0x7], cmpop & 0x8); | |
1821 | rfmt = -1; | |
1822 | if ((cmpop & 0x8) | |
1823 | && | |
1824 | ieee754_cxtest | |
1825 | (IEEE754_INVALID_OPERATION)) | |
1826 | rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; | |
1827 | else | |
1828 | goto copcsr; | |
1829 | ||
1830 | } | |
1831 | else { | |
1832 | return SIGILL; | |
1833 | } | |
1834 | break; | |
1835 | } | |
1836 | break; | |
1da177e4 | 1837 | |
3f7cac41 | 1838 | case w_fmt: |
1da177e4 LT |
1839 | switch (MIPSInst_FUNC(ir)) { |
1840 | case fcvts_op: | |
1841 | /* convert word to single precision real */ | |
1842 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1843 | rv.s = ieee754sp_fint(fs.bits); | |
1844 | rfmt = s_fmt; | |
1845 | goto copcsr; | |
1da177e4 LT |
1846 | case fcvtd_op: |
1847 | /* convert word to double precision real */ | |
1848 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1849 | rv.d = ieee754dp_fint(fs.bits); | |
1850 | rfmt = d_fmt; | |
1851 | goto copcsr; | |
1da177e4 LT |
1852 | default: |
1853 | return SIGILL; | |
1854 | } | |
1855 | break; | |
1856 | } | |
1857 | ||
3f7cac41 | 1858 | case l_fmt: |
08a07904 RB |
1859 | |
1860 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) | |
1861 | return SIGILL; | |
1862 | ||
bbd426f5 PB |
1863 | DIFROMREG(bits, MIPSInst_FS(ir)); |
1864 | ||
1da177e4 LT |
1865 | switch (MIPSInst_FUNC(ir)) { |
1866 | case fcvts_op: | |
1867 | /* convert long to single precision real */ | |
bbd426f5 | 1868 | rv.s = ieee754sp_flong(bits); |
1da177e4 LT |
1869 | rfmt = s_fmt; |
1870 | goto copcsr; | |
1871 | case fcvtd_op: | |
1872 | /* convert long to double precision real */ | |
bbd426f5 | 1873 | rv.d = ieee754dp_flong(bits); |
1da177e4 LT |
1874 | rfmt = d_fmt; |
1875 | goto copcsr; | |
1876 | default: | |
1877 | return SIGILL; | |
1878 | } | |
1879 | break; | |
1da177e4 LT |
1880 | |
1881 | default: | |
1882 | return SIGILL; | |
1883 | } | |
1884 | ||
1885 | /* | |
1886 | * Update the fpu CSR register for this operation. | |
1887 | * If an exception is required, generate a tidy SIGFPE exception, | |
1888 | * without updating the result register. | |
1889 | * Note: cause exception bits do not accumulate, they are rewritten | |
1890 | * for each op; only the flag/sticky bits accumulate. | |
1891 | */ | |
1892 | ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; | |
1893 | if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { | |
3f7cac41 | 1894 | /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */ |
1da177e4 LT |
1895 | return SIGFPE; |
1896 | } | |
1897 | ||
1898 | /* | |
1899 | * Now we can safely write the result back to the register file. | |
1900 | */ | |
1901 | switch (rfmt) { | |
08a07904 RB |
1902 | case -1: |
1903 | ||
1904 | if (cpu_has_mips_4_5_r) | |
c3b9b945 | 1905 | cbit = fpucondbit[MIPSInst_FD(ir) >> 2]; |
08a07904 RB |
1906 | else |
1907 | cbit = FPU_CSR_COND; | |
1da177e4 | 1908 | if (rv.w) |
08a07904 | 1909 | ctx->fcr31 |= cbit; |
1da177e4 | 1910 | else |
08a07904 | 1911 | ctx->fcr31 &= ~cbit; |
1da177e4 | 1912 | break; |
08a07904 | 1913 | |
1da177e4 LT |
1914 | case d_fmt: |
1915 | DPTOREG(rv.d, MIPSInst_FD(ir)); | |
1916 | break; | |
1da177e4 LT |
1917 | case s_fmt: |
1918 | SPTOREG(rv.s, MIPSInst_FD(ir)); | |
1919 | break; | |
1920 | case w_fmt: | |
1921 | SITOREG(rv.w, MIPSInst_FD(ir)); | |
1922 | break; | |
1da177e4 | 1923 | case l_fmt: |
08a07904 RB |
1924 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1925 | return SIGILL; | |
1926 | ||
1da177e4 LT |
1927 | DITOREG(rv.l, MIPSInst_FD(ir)); |
1928 | break; | |
1da177e4 LT |
1929 | default: |
1930 | return SIGILL; | |
1931 | } | |
1932 | ||
1933 | return 0; | |
1934 | } | |
1935 | ||
e04582b7 | 1936 | int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
515b029d | 1937 | int has_fpu, void *__user *fault_addr) |
1da177e4 | 1938 | { |
333d1f67 | 1939 | unsigned long oldepc, prevepc; |
102cedc3 LY |
1940 | struct mm_decoded_insn dec_insn; |
1941 | u16 instr[4]; | |
1942 | u16 *instr_ptr; | |
1da177e4 LT |
1943 | int sig = 0; |
1944 | ||
1945 | oldepc = xcp->cp0_epc; | |
1946 | do { | |
1947 | prevepc = xcp->cp0_epc; | |
1948 | ||
102cedc3 LY |
1949 | if (get_isa16_mode(prevepc) && cpu_has_mmips) { |
1950 | /* | |
1951 | * Get next 2 microMIPS instructions and convert them | |
1952 | * into 32-bit instructions. | |
1953 | */ | |
1954 | if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) || | |
1955 | (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) || | |
1956 | (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) || | |
1957 | (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) { | |
1958 | MIPS_FPU_EMU_INC_STATS(errors); | |
1959 | return SIGBUS; | |
1960 | } | |
1961 | instr_ptr = instr; | |
1962 | ||
1963 | /* Get first instruction. */ | |
1964 | if (mm_insn_16bit(*instr_ptr)) { | |
1965 | /* Duplicate the half-word. */ | |
1966 | dec_insn.insn = (*instr_ptr << 16) | | |
1967 | (*instr_ptr); | |
1968 | /* 16-bit instruction. */ | |
1969 | dec_insn.pc_inc = 2; | |
1970 | instr_ptr += 1; | |
1971 | } else { | |
1972 | dec_insn.insn = (*instr_ptr << 16) | | |
1973 | *(instr_ptr+1); | |
1974 | /* 32-bit instruction. */ | |
1975 | dec_insn.pc_inc = 4; | |
1976 | instr_ptr += 2; | |
1977 | } | |
1978 | /* Get second instruction. */ | |
1979 | if (mm_insn_16bit(*instr_ptr)) { | |
1980 | /* Duplicate the half-word. */ | |
1981 | dec_insn.next_insn = (*instr_ptr << 16) | | |
1982 | (*instr_ptr); | |
1983 | /* 16-bit instruction. */ | |
1984 | dec_insn.next_pc_inc = 2; | |
1985 | } else { | |
1986 | dec_insn.next_insn = (*instr_ptr << 16) | | |
1987 | *(instr_ptr+1); | |
1988 | /* 32-bit instruction. */ | |
1989 | dec_insn.next_pc_inc = 4; | |
1990 | } | |
1991 | dec_insn.micro_mips_mode = 1; | |
1992 | } else { | |
1993 | if ((get_user(dec_insn.insn, | |
1994 | (mips_instruction __user *) xcp->cp0_epc)) || | |
1995 | (get_user(dec_insn.next_insn, | |
1996 | (mips_instruction __user *)(xcp->cp0_epc+4)))) { | |
1997 | MIPS_FPU_EMU_INC_STATS(errors); | |
1998 | return SIGBUS; | |
1999 | } | |
2000 | dec_insn.pc_inc = 4; | |
2001 | dec_insn.next_pc_inc = 4; | |
2002 | dec_insn.micro_mips_mode = 0; | |
515b029d | 2003 | } |
102cedc3 LY |
2004 | |
2005 | if ((dec_insn.insn == 0) || | |
2006 | ((dec_insn.pc_inc == 2) && | |
2007 | ((dec_insn.insn & 0xffff) == MM_NOP16))) | |
2008 | xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ | |
1da177e4 | 2009 | else { |
cd21dfcf RB |
2010 | /* |
2011 | * The 'ieee754_csr' is an alias of | |
70342287 RB |
2012 | * ctx->fcr31. No need to copy ctx->fcr31 to |
2013 | * ieee754_csr. But ieee754_csr.rm is ieee | |
cd21dfcf RB |
2014 | * library modes. (not mips rounding mode) |
2015 | */ | |
102cedc3 | 2016 | sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); |
1da177e4 LT |
2017 | } |
2018 | ||
e04582b7 | 2019 | if (has_fpu) |
1da177e4 LT |
2020 | break; |
2021 | if (sig) | |
2022 | break; | |
2023 | ||
2024 | cond_resched(); | |
2025 | } while (xcp->cp0_epc > prevepc); | |
2026 | ||
2027 | /* SIGILL indicates a non-fpu instruction */ | |
2028 | if (sig == SIGILL && xcp->cp0_epc != oldepc) | |
3f7cac41 | 2029 | /* but if EPC has advanced, then ignore it */ |
1da177e4 LT |
2030 | sig = 0; |
2031 | ||
2032 | return sig; | |
2033 | } |