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1da177e4 LT |
1 | #include <linux/compiler.h> |
2 | #include <linux/mm.h> | |
3 | #include <linux/signal.h> | |
4 | #include <linux/smp.h> | |
1da177e4 LT |
5 | |
6 | #include <asm/asm.h> | |
7 | #include <asm/bootinfo.h> | |
8 | #include <asm/byteorder.h> | |
9 | #include <asm/cpu.h> | |
10 | #include <asm/inst.h> | |
11 | #include <asm/processor.h> | |
12 | #include <asm/uaccess.h> | |
13 | #include <asm/branch.h> | |
14 | #include <asm/mipsregs.h> | |
1da177e4 LT |
15 | #include <asm/cacheflush.h> |
16 | ||
17 | #include <asm/fpu_emulator.h> | |
18 | ||
19 | #include "ieee754.h" | |
1da177e4 LT |
20 | |
21 | /* Strap kernel emulator for full MIPS IV emulation */ | |
22 | ||
23 | #ifdef __mips | |
24 | #undef __mips | |
25 | #endif | |
26 | #define __mips 4 | |
27 | ||
1da177e4 LT |
28 | /* |
29 | * Emulate the arbritrary instruction ir at xcp->cp0_epc. Required when | |
30 | * we have to emulate the instruction in a COP1 branch delay slot. Do | |
31 | * not change cp0_epc due to the instruction | |
32 | * | |
33 | * According to the spec: | |
25985edc | 34 | * 1) it shouldn't be a branch :-) |
1da177e4 LT |
35 | * 2) it can be a COP instruction :-( |
36 | * 3) if we are tring to run a protected memory space we must take | |
37 | * special care on memory access instructions :-( | |
38 | */ | |
39 | ||
40 | /* | |
41 | * "Trampoline" return routine to catch exception following | |
42 | * execution of delay-slot instruction execution. | |
43 | */ | |
44 | ||
45 | struct emuframe { | |
46 | mips_instruction emul; | |
47 | mips_instruction badinst; | |
48 | mips_instruction cookie; | |
333d1f67 | 49 | unsigned long epc; |
1da177e4 LT |
50 | }; |
51 | ||
333d1f67 | 52 | int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) |
1da177e4 LT |
53 | { |
54 | extern asmlinkage void handle_dsemulret(void); | |
5e0373b8 | 55 | struct emuframe __user *fr; |
1da177e4 LT |
56 | int err; |
57 | ||
102cedc3 LY |
58 | if ((get_isa16_mode(regs->cp0_epc) && ((ir >> 16) == MM_NOP16)) || |
59 | (ir == 0)) { | |
60 | /* NOP is easy */ | |
1da177e4 | 61 | regs->cp0_epc = cpc; |
e7e9cae5 | 62 | clear_delay_slot(regs); |
1da177e4 LT |
63 | return 0; |
64 | } | |
65 | #ifdef DSEMUL_TRACE | |
66 | printk("dsemul %lx %lx\n", regs->cp0_epc, cpc); | |
67 | ||
68 | #endif | |
69 | ||
70 | /* | |
71 | * The strategy is to push the instruction onto the user stack | |
72 | * and put a trap after it which we can catch and jump to | |
73 | * the required address any alternative apart from full | |
74 | * instruction emulation!!. | |
75 | * | |
76 | * Algorithmics used a system call instruction, and | |
77 | * borrowed that vector. MIPS/Linux version is a bit | |
78 | * more heavyweight in the interests of portability and | |
79 | * multiprocessor support. For Linux we generate a | |
80 | * an unaligned access and force an address error exception. | |
81 | * | |
82 | * For embedded systems (stand-alone) we prefer to use a | |
83 | * non-existing CP1 instruction. This prevents us from emulating | |
84 | * branches, but gives us a cleaner interface to the exception | |
85 | * handler (single entry point). | |
86 | */ | |
87 | ||
88 | /* Ensure that the two instructions are in the same cache line */ | |
5e0373b8 AN |
89 | fr = (struct emuframe __user *) |
90 | ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7); | |
1da177e4 LT |
91 | |
92 | /* Verify that the stack pointer is not competely insane */ | |
93 | if (unlikely(!access_ok(VERIFY_WRITE, fr, sizeof(struct emuframe)))) | |
94 | return SIGBUS; | |
95 | ||
102cedc3 LY |
96 | if (get_isa16_mode(regs->cp0_epc)) { |
97 | err = __put_user(ir >> 16, (u16 __user *)(&fr->emul)); | |
98 | err |= __put_user(ir & 0xffff, (u16 __user *)((long)(&fr->emul) + 2)); | |
99 | err |= __put_user(BREAK_MATH >> 16, (u16 __user *)(&fr->badinst)); | |
100 | err |= __put_user(BREAK_MATH & 0xffff, (u16 __user *)((long)(&fr->badinst) + 2)); | |
101 | } else { | |
102 | err = __put_user(ir, &fr->emul); | |
103 | err |= __put_user((mips_instruction)BREAK_MATH, &fr->badinst); | |
104 | } | |
105 | ||
1da177e4 LT |
106 | err |= __put_user((mips_instruction)BD_COOKIE, &fr->cookie); |
107 | err |= __put_user(cpc, &fr->epc); | |
108 | ||
109 | if (unlikely(err)) { | |
b6ee75ed | 110 | MIPS_FPU_EMU_INC_STATS(errors); |
1da177e4 LT |
111 | return SIGBUS; |
112 | } | |
113 | ||
102cedc3 LY |
114 | regs->cp0_epc = ((unsigned long) &fr->emul) | |
115 | get_isa16_mode(regs->cp0_epc); | |
1da177e4 LT |
116 | |
117 | flush_cache_sigtramp((unsigned long)&fr->badinst); | |
118 | ||
119 | return SIGILL; /* force out of emulation loop */ | |
120 | } | |
121 | ||
122 | int do_dsemulret(struct pt_regs *xcp) | |
123 | { | |
5e0373b8 | 124 | struct emuframe __user *fr; |
333d1f67 | 125 | unsigned long epc; |
1da177e4 LT |
126 | u32 insn, cookie; |
127 | int err = 0; | |
102cedc3 | 128 | u16 instr[2]; |
1da177e4 | 129 | |
5e0373b8 | 130 | fr = (struct emuframe __user *) |
102cedc3 | 131 | (msk_isa16_mode(xcp->cp0_epc) - sizeof(mips_instruction)); |
1da177e4 LT |
132 | |
133 | /* | |
134 | * If we can't even access the area, something is very wrong, but we'll | |
135 | * leave that to the default handling | |
136 | */ | |
137 | if (!access_ok(VERIFY_READ, fr, sizeof(struct emuframe))) | |
138 | return 0; | |
139 | ||
140 | /* | |
141 | * Do some sanity checking on the stackframe: | |
142 | * | |
ba3049ed | 143 | * - Is the instruction pointed to by the EPC an BREAK_MATH? |
1da177e4 LT |
144 | * - Is the following memory word the BD_COOKIE? |
145 | */ | |
102cedc3 LY |
146 | if (get_isa16_mode(xcp->cp0_epc)) { |
147 | err = __get_user(instr[0], (u16 __user *)(&fr->badinst)); | |
148 | err |= __get_user(instr[1], (u16 __user *)((long)(&fr->badinst) + 2)); | |
149 | insn = (instr[0] << 16) | instr[1]; | |
150 | } else { | |
151 | err = __get_user(insn, &fr->badinst); | |
152 | } | |
1da177e4 LT |
153 | err |= __get_user(cookie, &fr->cookie); |
154 | ||
ba3049ed | 155 | if (unlikely(err || (insn != BREAK_MATH) || (cookie != BD_COOKIE))) { |
b6ee75ed | 156 | MIPS_FPU_EMU_INC_STATS(errors); |
1da177e4 LT |
157 | return 0; |
158 | } | |
159 | ||
160 | /* | |
161 | * At this point, we are satisfied that it's a BD emulation trap. Yes, | |
162 | * a user might have deliberately put two malformed and useless | |
163 | * instructions in a row in his program, in which case he's in for a | |
164 | * nasty surprise - the next instruction will be treated as a | |
165 | * continuation address! Alas, this seems to be the only way that we | |
166 | * can handle signals, recursion, and longjmps() in the context of | |
167 | * emulating the branch delay instruction. | |
168 | */ | |
169 | ||
170 | #ifdef DSEMUL_TRACE | |
171 | printk("dsemulret\n"); | |
172 | #endif | |
173 | if (__get_user(epc, &fr->epc)) { /* Saved EPC */ | |
174 | /* This is not a good situation to be in */ | |
175 | force_sig(SIGBUS, current); | |
176 | ||
177 | return 0; | |
178 | } | |
179 | ||
180 | /* Set EPC to return to post-branch instruction */ | |
181 | xcp->cp0_epc = epc; | |
182 | ||
183 | return 1; | |
184 | } |