Commit | Line | Data |
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1da177e4 LT |
1 | /* IEEE754 floating point arithmetic |
2 | * double precision: common utilities | |
3 | */ | |
4 | /* | |
5 | * MIPS floating point support | |
6 | * Copyright (C) 1994-2000 Algorithmics Ltd. | |
1da177e4 | 7 | * |
1da177e4 LT |
8 | * This program is free software; you can distribute it and/or modify it |
9 | * under the terms of the GNU General Public License (Version 2) as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | * for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along | |
18 | * with this program; if not, write to the Free Software Foundation, Inc., | |
3f7cac41 | 19 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
1da177e4 LT |
20 | */ |
21 | ||
cae55066 | 22 | #include <linux/compiler.h> |
1da177e4 LT |
23 | |
24 | #include "ieee754dp.h" | |
25 | ||
2209bcb1 | 26 | int ieee754dp_class(union ieee754dp x) |
1da177e4 LT |
27 | { |
28 | COMPXDP; | |
29 | EXPLODEXDP; | |
30 | return xc; | |
31 | } | |
32 | ||
2209bcb1 | 33 | int ieee754dp_isnan(union ieee754dp x) |
1da177e4 LT |
34 | { |
35 | return ieee754dp_class(x) >= IEEE754_CLASS_SNAN; | |
36 | } | |
37 | ||
f71baa11 | 38 | static inline int ieee754dp_issnan(union ieee754dp x) |
1da177e4 LT |
39 | { |
40 | assert(ieee754dp_isnan(x)); | |
635c9907 | 41 | return (DPMANT(x) & DP_MBIT(DP_FBITS - 1)) == DP_MBIT(DP_FBITS - 1); |
1da177e4 LT |
42 | } |
43 | ||
44 | ||
90efba36 | 45 | union ieee754dp __cold ieee754dp_nanxcpt(union ieee754dp r) |
1da177e4 | 46 | { |
1da177e4 LT |
47 | assert(ieee754dp_isnan(r)); |
48 | ||
49 | if (!ieee754dp_issnan(r)) /* QNAN does not cause invalid op !! */ | |
50 | return r; | |
51 | ||
ec98f9a0 MR |
52 | /* If not enabled convert to a quiet NaN. */ |
53 | if (!ieee754_setandtestcx(IEEE754_INVALID_OPERATION)) | |
54 | return ieee754dp_indef(); | |
1da177e4 | 55 | |
90efba36 | 56 | return r; |
1da177e4 LT |
57 | } |
58 | ||
de2fc342 | 59 | static u64 ieee754dp_get_rounding(int sn, u64 xm) |
1da177e4 LT |
60 | { |
61 | /* inexact must round of 3 bits | |
62 | */ | |
63 | if (xm & (DP_MBIT(3) - 1)) { | |
64 | switch (ieee754_csr.rm) { | |
56a64733 | 65 | case FPU_CSR_RZ: |
1da177e4 | 66 | break; |
56a64733 | 67 | case FPU_CSR_RN: |
1da177e4 LT |
68 | xm += 0x3 + ((xm >> 3) & 1); |
69 | /* xm += (xm&0x8)?0x4:0x3 */ | |
70 | break; | |
56a64733 | 71 | case FPU_CSR_RU: /* toward +Infinity */ |
1da177e4 LT |
72 | if (!sn) /* ?? */ |
73 | xm += 0x8; | |
74 | break; | |
56a64733 | 75 | case FPU_CSR_RD: /* toward -Infinity */ |
70342287 | 76 | if (sn) /* ?? */ |
1da177e4 LT |
77 | xm += 0x8; |
78 | break; | |
79 | } | |
80 | } | |
81 | return xm; | |
82 | } | |
83 | ||
84 | ||
85 | /* generate a normal/denormal number with over,under handling | |
86 | * sn is sign | |
87 | * xe is an unbiased exponent | |
88 | * xm is 3bit extended precision value. | |
89 | */ | |
2209bcb1 | 90 | union ieee754dp ieee754dp_format(int sn, int xe, u64 xm) |
1da177e4 LT |
91 | { |
92 | assert(xm); /* we don't gen exact zeros (probably should) */ | |
93 | ||
ad8fb553 | 94 | assert((xm >> (DP_FBITS + 1 + 3)) == 0); /* no execess */ |
1da177e4 LT |
95 | assert(xm & (DP_HIDDEN_BIT << 3)); |
96 | ||
97 | if (xe < DP_EMIN) { | |
98 | /* strip lower bits */ | |
99 | int es = DP_EMIN - xe; | |
100 | ||
101 | if (ieee754_csr.nod) { | |
9e8bad1f RB |
102 | ieee754_setcx(IEEE754_UNDERFLOW); |
103 | ieee754_setcx(IEEE754_INEXACT); | |
1da177e4 LT |
104 | |
105 | switch(ieee754_csr.rm) { | |
56a64733 RB |
106 | case FPU_CSR_RN: |
107 | case FPU_CSR_RZ: | |
1da177e4 | 108 | return ieee754dp_zero(sn); |
56a64733 | 109 | case FPU_CSR_RU: /* toward +Infinity */ |
47fa0c02 | 110 | if (sn == 0) |
1da177e4 LT |
111 | return ieee754dp_min(0); |
112 | else | |
113 | return ieee754dp_zero(1); | |
56a64733 | 114 | case FPU_CSR_RD: /* toward -Infinity */ |
47fa0c02 | 115 | if (sn == 0) |
1da177e4 LT |
116 | return ieee754dp_zero(0); |
117 | else | |
118 | return ieee754dp_min(1); | |
119 | } | |
120 | } | |
121 | ||
de2fc342 RB |
122 | if (xe == DP_EMIN - 1 && |
123 | ieee754dp_get_rounding(sn, xm) >> (DP_FBITS + 1 + 3)) | |
1da177e4 LT |
124 | { |
125 | /* Not tiny after rounding */ | |
9e8bad1f | 126 | ieee754_setcx(IEEE754_INEXACT); |
de2fc342 | 127 | xm = ieee754dp_get_rounding(sn, xm); |
1da177e4 LT |
128 | xm >>= 1; |
129 | /* Clear grs bits */ | |
130 | xm &= ~(DP_MBIT(3) - 1); | |
131 | xe++; | |
132 | } | |
133 | else { | |
134 | /* sticky right shift es bits | |
135 | */ | |
136 | xm = XDPSRS(xm, es); | |
137 | xe += es; | |
138 | assert((xm & (DP_HIDDEN_BIT << 3)) == 0); | |
139 | assert(xe == DP_EMIN); | |
140 | } | |
141 | } | |
142 | if (xm & (DP_MBIT(3) - 1)) { | |
9e8bad1f | 143 | ieee754_setcx(IEEE754_INEXACT); |
1da177e4 | 144 | if ((xm & (DP_HIDDEN_BIT << 3)) == 0) { |
9e8bad1f | 145 | ieee754_setcx(IEEE754_UNDERFLOW); |
1da177e4 LT |
146 | } |
147 | ||
148 | /* inexact must round of 3 bits | |
149 | */ | |
de2fc342 | 150 | xm = ieee754dp_get_rounding(sn, xm); |
1da177e4 LT |
151 | /* adjust exponent for rounding add overflowing |
152 | */ | |
ad8fb553 | 153 | if (xm >> (DP_FBITS + 3 + 1)) { |
1da177e4 LT |
154 | /* add causes mantissa overflow */ |
155 | xm >>= 1; | |
156 | xe++; | |
157 | } | |
158 | } | |
159 | /* strip grs bits */ | |
160 | xm >>= 3; | |
161 | ||
ad8fb553 | 162 | assert((xm >> (DP_FBITS + 1)) == 0); /* no execess */ |
1da177e4 LT |
163 | assert(xe >= DP_EMIN); |
164 | ||
165 | if (xe > DP_EMAX) { | |
9e8bad1f RB |
166 | ieee754_setcx(IEEE754_OVERFLOW); |
167 | ieee754_setcx(IEEE754_INEXACT); | |
1da177e4 LT |
168 | /* -O can be table indexed by (rm,sn) */ |
169 | switch (ieee754_csr.rm) { | |
56a64733 | 170 | case FPU_CSR_RN: |
1da177e4 | 171 | return ieee754dp_inf(sn); |
56a64733 | 172 | case FPU_CSR_RZ: |
1da177e4 | 173 | return ieee754dp_max(sn); |
56a64733 | 174 | case FPU_CSR_RU: /* toward +Infinity */ |
1da177e4 LT |
175 | if (sn == 0) |
176 | return ieee754dp_inf(0); | |
177 | else | |
178 | return ieee754dp_max(1); | |
56a64733 | 179 | case FPU_CSR_RD: /* toward -Infinity */ |
1da177e4 LT |
180 | if (sn == 0) |
181 | return ieee754dp_max(0); | |
182 | else | |
183 | return ieee754dp_inf(1); | |
184 | } | |
185 | } | |
186 | /* gen norm/denorm/zero */ | |
187 | ||
188 | if ((xm & DP_HIDDEN_BIT) == 0) { | |
189 | /* we underflow (tiny/zero) */ | |
190 | assert(xe == DP_EMIN); | |
191 | if (ieee754_csr.mx & IEEE754_UNDERFLOW) | |
9e8bad1f | 192 | ieee754_setcx(IEEE754_UNDERFLOW); |
1da177e4 LT |
193 | return builddp(sn, DP_EMIN - 1 + DP_EBIAS, xm); |
194 | } else { | |
ad8fb553 | 195 | assert((xm >> (DP_FBITS + 1)) == 0); /* no execess */ |
1da177e4 LT |
196 | assert(xm & DP_HIDDEN_BIT); |
197 | ||
198 | return builddp(sn, xe + DP_EBIAS, xm & ~DP_HIDDEN_BIT); | |
199 | } | |
200 | } |