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1da177e4 LT |
1 | /* |
2 | * Carsten Langgaard, carstenl@mips.com | |
3 | * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can distribute it and/or modify it | |
6 | * under the terms of the GNU General Public License (Version 2) as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | * for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along | |
15 | * with this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
17 | * | |
18 | * Setting up the clock on the MIPS boards. | |
19 | */ | |
20 | ||
21 | #include <linux/types.h> | |
1da177e4 LT |
22 | #include <linux/init.h> |
23 | #include <linux/kernel_stat.h> | |
24 | #include <linux/sched.h> | |
25 | #include <linux/spinlock.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/time.h> | |
28 | #include <linux/timex.h> | |
29 | #include <linux/mc146818rtc.h> | |
30 | ||
31 | #include <asm/mipsregs.h> | |
41c594ab | 32 | #include <asm/mipsmtregs.h> |
e01402b1 | 33 | #include <asm/hardirq.h> |
d865bea4 | 34 | #include <asm/i8253.h> |
e01402b1 | 35 | #include <asm/irq.h> |
1da177e4 LT |
36 | #include <asm/div64.h> |
37 | #include <asm/cpu.h> | |
38 | #include <asm/time.h> | |
39 | #include <asm/mc146818-time.h> | |
e01402b1 | 40 | #include <asm/msc01_ic.h> |
1da177e4 LT |
41 | |
42 | #include <asm/mips-boards/generic.h> | |
43 | #include <asm/mips-boards/prom.h> | |
fc095a90 | 44 | |
fc095a90 | 45 | #ifdef CONFIG_MIPS_MALTA |
e01402b1 | 46 | #include <asm/mips-boards/maltaint.h> |
fc095a90 | 47 | #endif |
f75f369f AN |
48 | #ifdef CONFIG_MIPS_SEAD |
49 | #include <asm/mips-boards/seadint.h> | |
50 | #endif | |
1da177e4 LT |
51 | |
52 | unsigned long cpu_khz; | |
53 | ||
e01402b1 | 54 | static int mips_cpu_timer_irq; |
39b8d525 | 55 | static int mips_cpu_perf_irq; |
3b1d4ed5 | 56 | extern int cp0_perfcount_irq; |
1da177e4 | 57 | |
937a8015 | 58 | static void mips_timer_dispatch(void) |
1da177e4 | 59 | { |
937a8015 | 60 | do_IRQ(mips_cpu_timer_irq); |
e01402b1 RB |
61 | } |
62 | ||
ffe9ee47 CD |
63 | static void mips_perf_dispatch(void) |
64 | { | |
39b8d525 | 65 | do_IRQ(mips_cpu_perf_irq); |
ffe9ee47 CD |
66 | } |
67 | ||
1da177e4 | 68 | /* |
224dc50e | 69 | * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect |
1da177e4 LT |
70 | */ |
71 | static unsigned int __init estimate_cpu_frequency(void) | |
72 | { | |
73 | unsigned int prid = read_c0_prid() & 0xffff00; | |
74 | unsigned int count; | |
75 | ||
41c594ab | 76 | #if defined(CONFIG_MIPS_SEAD) || defined(CONFIG_MIPS_SIM) |
1da177e4 LT |
77 | /* |
78 | * The SEAD board doesn't have a real time clock, so we can't | |
79 | * really calculate the timer frequency | |
80 | * For now we hardwire the SEAD board frequency to 12MHz. | |
81 | */ | |
42a3b4f2 | 82 | |
1da177e4 LT |
83 | if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) || |
84 | (prid == (PRID_COMP_MIPS | PRID_IMP_25KF))) | |
85 | count = 12000000; | |
86 | else | |
87 | count = 6000000; | |
88 | #endif | |
2157bc68 | 89 | #ifdef CONFIG_MIPS_MALTA |
e79f55a8 | 90 | unsigned long flags; |
70e46f48 | 91 | unsigned int start; |
1da177e4 LT |
92 | |
93 | local_irq_save(flags); | |
94 | ||
95 | /* Start counter exactly on falling edge of update flag */ | |
96 | while (CMOS_READ(RTC_REG_A) & RTC_UIP); | |
97 | while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); | |
98 | ||
99 | /* Start r4k counter. */ | |
70e46f48 | 100 | start = read_c0_count(); |
1da177e4 LT |
101 | |
102 | /* Read counter exactly on falling edge of update flag */ | |
103 | while (CMOS_READ(RTC_REG_A) & RTC_UIP); | |
104 | while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); | |
105 | ||
70e46f48 | 106 | count = read_c0_count() - start; |
1da177e4 LT |
107 | |
108 | /* restore interrupts */ | |
109 | local_irq_restore(flags); | |
110 | #endif | |
111 | ||
112 | mips_hpt_frequency = count; | |
113 | if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && | |
114 | (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) | |
115 | count *= 2; | |
116 | ||
117 | count += 5000; /* round */ | |
118 | count -= count%10000; | |
119 | ||
120 | return count; | |
121 | } | |
122 | ||
4b550488 | 123 | unsigned long read_persistent_clock(void) |
1da177e4 LT |
124 | { |
125 | return mc146818_get_cmos_time(); | |
126 | } | |
127 | ||
b31dc3c4 | 128 | static void __init plat_perf_setup(void) |
ffe9ee47 | 129 | { |
f75f369f | 130 | #ifdef MSC01E_INT_BASE |
e01402b1 | 131 | if (cpu_has_veic) { |
49a89efb | 132 | set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch); |
39b8d525 | 133 | mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; |
f75f369f AN |
134 | } else |
135 | #endif | |
3b1d4ed5 RB |
136 | if (cp0_perfcount_irq >= 0) { |
137 | if (cpu_has_vint) | |
138 | set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch); | |
39b8d525 | 139 | mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; |
ffe9ee47 | 140 | #ifdef CONFIG_SMP |
39b8d525 | 141 | set_irq_handler(mips_cpu_perf_irq, handle_percpu_irq); |
ffe9ee47 | 142 | #endif |
e01402b1 | 143 | } |
ffe9ee47 | 144 | } |
e01402b1 | 145 | |
234fcd14 | 146 | unsigned int __cpuinit get_c0_compare_int(void) |
ffe9ee47 | 147 | { |
7b4f4ec2 | 148 | #ifdef MSC01E_INT_BASE |
ffe9ee47 | 149 | if (cpu_has_veic) { |
49a89efb | 150 | set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); |
ffe9ee47 | 151 | mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; |
38760d40 | 152 | } else |
7b4f4ec2 CD |
153 | #endif |
154 | { | |
ffe9ee47 | 155 | if (cpu_has_vint) |
3b1d4ed5 RB |
156 | set_vi_handler(cp0_compare_irq, mips_timer_dispatch); |
157 | mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; | |
ffe9ee47 | 158 | } |
e01402b1 | 159 | |
38760d40 RB |
160 | return mips_cpu_timer_irq; |
161 | } | |
162 | ||
163 | void __init plat_time_init(void) | |
164 | { | |
165 | unsigned int est_freq; | |
166 | ||
167 | /* Set Data mode - binary. */ | |
168 | CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); | |
169 | ||
170 | est_freq = estimate_cpu_frequency(); | |
171 | ||
172 | printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, | |
173 | (est_freq%1000000)*100/1000000); | |
174 | ||
175 | cpu_khz = est_freq / 1000; | |
176 | ||
177 | mips_scroll_message(); | |
178 | #ifdef CONFIG_I8253 /* Only Malta has a PIT */ | |
179 | setup_pit_timer(); | |
340ee4b9 | 180 | #endif |
ffe9ee47 | 181 | |
91a2fcc8 | 182 | plat_perf_setup(); |
1da177e4 | 183 | } |