[deliverable/linux.git] / arch / mips / mips-boards / malta / malta_int.c

/*
 * Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
 * Copyright (C) 2001 Ralf Baechle
 *
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * Routines for generic manipulation of the interrupts found on the MIPS
 * Malta board.
 * The interrupt controller is located in the South Bridge a PIIX4 device
 * with two internal 82C95 interrupt controllers.
 */
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/random.h>

#include <asm/i8259.h>
#include <asm/irq_cpu.h>
#include <asm/io.h>
#include <asm/mips-boards/malta.h>
#include <asm/mips-boards/maltaint.h>
#include <asm/mips-boards/piix4.h>
#include <asm/gt64120.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/msc01_pci.h>
#include <asm/msc01_ic.h>

extern void mips_timer_interrupt(void);

static DEFINE_SPINLOCK(mips_irq_lock);

static inline int mips_pcibios_iack(void)
{
	int irq;
        u32 dummy;

	/*
	 * Determine highest priority pending interrupt by performing
	 * a PCI Interrupt Acknowledge cycle.
	 */
	switch(mips_revision_corid) {
	case MIPS_REVISION_CORID_CORE_MSC:
	case MIPS_REVISION_CORID_CORE_FPGA2:
	case MIPS_REVISION_CORID_CORE_FPGA3:
	case MIPS_REVISION_CORID_CORE_24K:
	case MIPS_REVISION_CORID_CORE_EMUL_MSC:
	        MSC_READ(MSC01_PCI_IACK, irq);
		irq &= 0xff;
		break;
	case MIPS_REVISION_CORID_QED_RM5261:
	case MIPS_REVISION_CORID_CORE_LV:
	case MIPS_REVISION_CORID_CORE_FPGA:
	case MIPS_REVISION_CORID_CORE_FPGAR2:
		irq = GT_READ(GT_PCI0_IACK_OFS);
		irq &= 0xff;
		break;
	case MIPS_REVISION_CORID_BONITO64:
	case MIPS_REVISION_CORID_CORE_20K:
	case MIPS_REVISION_CORID_CORE_EMUL_BON:
		/* The following will generate a PCI IACK cycle on the
		 * Bonito controller. It's a little bit kludgy, but it
		 * was the easiest way to implement it in hardware at
		 * the given time.
		 */
		BONITO_PCIMAP_CFG = 0x20000;

		/* Flush Bonito register block */
		dummy = BONITO_PCIMAP_CFG;
		iob();    /* sync */

		irq = *(volatile u32 *)(_pcictrl_bonito_pcicfg);
		iob();    /* sync */
		irq &= 0xff;
		BONITO_PCIMAP_CFG = 0;
		break;
	default:
	        printk("Unknown Core card, don't know the system controller.\n");
		return -1;
	}
	return irq;
}

static inline int get_int(void)
{
	unsigned long flags;
	int irq;
	spin_lock_irqsave(&mips_irq_lock, flags);

	irq = mips_pcibios_iack();

	/*
	 * The only way we can decide if an interrupt is spurious
	 * is by checking the 8259 registers.  This needs a spinlock
	 * on an SMP system,  so leave it up to the generic code...
	 */

	spin_unlock_irqrestore(&mips_irq_lock, flags);

	return irq;
}

static void malta_hw0_irqdispatch(void)
{
	int irq;

	irq = get_int();
	if (irq < 0) {
		return;  /* interrupt has already been cleared */
	}

	do_IRQ(MALTA_INT_BASE + irq);
}

static void corehi_irqdispatch(void)
{
	unsigned int intedge, intsteer, pcicmd, pcibadaddr;
        unsigned int pcimstat, intisr, inten, intpol;
	unsigned int intrcause,datalo,datahi;
	struct pt_regs *regs;

        printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
        printk("epc   : %08lx\nStatus: %08lx\n"
	       "Cause : %08lx\nbadVaddr : %08lx\n",
	       regs->cp0_epc, regs->cp0_status,
	       regs->cp0_cause, regs->cp0_badvaddr);

	/* Read all the registers and then print them as there is a
	   problem with interspersed printk's upsetting the Bonito controller.
	   Do it for the others too.
	*/

        switch(mips_revision_corid) {
        case MIPS_REVISION_CORID_CORE_MSC:
        case MIPS_REVISION_CORID_CORE_FPGA2:
        case MIPS_REVISION_CORID_CORE_FPGA3:
        case MIPS_REVISION_CORID_CORE_24K:
        case MIPS_REVISION_CORID_CORE_EMUL_MSC:
                ll_msc_irq();
                break;
        case MIPS_REVISION_CORID_QED_RM5261:
        case MIPS_REVISION_CORID_CORE_LV:
        case MIPS_REVISION_CORID_CORE_FPGA:
        case MIPS_REVISION_CORID_CORE_FPGAR2:
                intrcause = GT_READ(GT_INTRCAUSE_OFS);
                datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
                datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
                printk("GT_INTRCAUSE = %08x\n", intrcause);
                printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, datalo);
                break;
        case MIPS_REVISION_CORID_BONITO64:
        case MIPS_REVISION_CORID_CORE_20K:
        case MIPS_REVISION_CORID_CORE_EMUL_BON:
                pcibadaddr = BONITO_PCIBADADDR;
                pcimstat = BONITO_PCIMSTAT;
                intisr = BONITO_INTISR;
                inten = BONITO_INTEN;
                intpol = BONITO_INTPOL;
                intedge = BONITO_INTEDGE;
                intsteer = BONITO_INTSTEER;
                pcicmd = BONITO_PCICMD;
                printk("BONITO_INTISR = %08x\n", intisr);
                printk("BONITO_INTEN = %08x\n", inten);
                printk("BONITO_INTPOL = %08x\n", intpol);
                printk("BONITO_INTEDGE = %08x\n", intedge);
                printk("BONITO_INTSTEER = %08x\n", intsteer);
                printk("BONITO_PCICMD = %08x\n", pcicmd);
                printk("BONITO_PCIBADADDR = %08x\n", pcibadaddr);
                printk("BONITO_PCIMSTAT = %08x\n", pcimstat);
                break;
        }

        /* We die here*/
        die("CoreHi interrupt", regs);
}

static inline int clz(unsigned long x)
{
	__asm__ (
	"	.set	push					\n"
	"	.set	mips32					\n"
	"	clz	%0, %1					\n"
	"	.set	pop					\n"
	: "=r" (x)
	: "r" (x));

	return x;
}

/*
 * Version of ffs that only looks at bits 12..15.
 */
static inline unsigned int irq_ffs(unsigned int pending)
{
#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
	return -clz(pending) + 31 - CAUSEB_IP;
#else
	unsigned int a0 = 7;
	unsigned int t0;

	t0 = pending & 0xf000;
	t0 = t0 < 1;
	t0 = t0 << 2;
	a0 = a0 - t0;
	pending = pending << t0;

	t0 = pending & 0xc000;
	t0 = t0 < 1;
	t0 = t0 << 1;
	a0 = a0 - t0;
	pending = pending << t0;

	t0 = pending & 0x8000;
	t0 = t0 < 1;
	//t0 = t0 << 2;
	a0 = a0 - t0;
	//pending = pending << t0;

	return a0;
#endif
}

/*
 * IRQs on the Malta board look basically (barring software IRQs which we
 * don't use at all and all external interrupt sources are combined together
 * on hardware interrupt 0 (MIPS IRQ 2)) like:
 *
 *	MIPS IRQ	Source
 *      --------        ------
 *             0	Software (ignored)
 *             1        Software (ignored)
 *             2        Combined hardware interrupt (hw0)
 *             3        Hardware (ignored)
 *             4        Hardware (ignored)
 *             5        Hardware (ignored)
 *             6        Hardware (ignored)
 *             7        R4k timer (what we use)
 *
 * We handle the IRQ according to _our_ priority which is:
 *
 * Highest ----     R4k Timer
 * Lowest  ----     Combined hardware interrupt
 *
 * then we just return, if multiple IRQs are pending then we will just take
 * another exception, big deal.
 */

asmlinkage void plat_irq_dispatch(void)
{
	unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
	int irq;

	irq = irq_ffs(pending);

	if (irq == MIPSCPU_INT_I8259A)
		malta_hw0_irqdispatch();
	else if (irq > 0)
		do_IRQ(MIPSCPU_INT_BASE + irq);
	else
		spurious_interrupt();
}

static struct irqaction i8259irq = {
	.handler = no_action,
	.name = "XT-PIC cascade"
};

static struct irqaction corehi_irqaction = {
	.handler = no_action,
	.name = "CoreHi"
};

msc_irqmap_t __initdata msc_irqmap[] = {
	{MSC01C_INT_TMR,		MSC01_IRQ_EDGE, 0},
	{MSC01C_INT_PCI,		MSC01_IRQ_LEVEL, 0},
};
int __initdata msc_nr_irqs = sizeof(msc_irqmap)/sizeof(msc_irqmap_t);

msc_irqmap_t __initdata msc_eicirqmap[] = {
	{MSC01E_INT_SW0,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_SW1,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_I8259A,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_SMI,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_COREHI,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_CORELO,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_TMR,		MSC01_IRQ_EDGE, 0},
	{MSC01E_INT_PCI,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_PERFCTR,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_CPUCTR,		MSC01_IRQ_LEVEL, 0}
};
int __initdata msc_nr_eicirqs = sizeof(msc_eicirqmap)/sizeof(msc_irqmap_t);

void __init arch_init_irq(void)
{
	init_i8259_irqs();

	if (!cpu_has_veic)
		mips_cpu_irq_init (MIPSCPU_INT_BASE);

        switch(mips_revision_corid) {
        case MIPS_REVISION_CORID_CORE_MSC:
        case MIPS_REVISION_CORID_CORE_FPGA2:
        case MIPS_REVISION_CORID_CORE_FPGA3:
        case MIPS_REVISION_CORID_CORE_24K:
        case MIPS_REVISION_CORID_CORE_EMUL_MSC:
		if (cpu_has_veic)
			init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
		else
			init_msc_irqs (MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
	}

	if (cpu_has_veic) {
		set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch);
		set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch);
		setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
		setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
	}
	else if (cpu_has_vint) {
		set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
		set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch);
#ifdef CONFIG_MIPS_MT_SMTC
		setup_irq_smtc (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq,
			(0x100 << MIPSCPU_INT_I8259A));
		setup_irq_smtc (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI,
			&corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
#else /* Not SMTC */
		setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
		setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
#endif /* CONFIG_MIPS_MT_SMTC */
	}
	else {
		setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
		setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
	}
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Carsten Langgaard, carstenl@mips.com
	3	* Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
	4	* Copyright (C) 2001 Ralf Baechle
	5	*
	6	* This program is free software; you can distribute it and/or modify it
	7	* under the terms of the GNU General Public License (Version 2) as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	13	* for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License along
	16	* with this program; if not, write to the Free Software Foundation, Inc.,
	17	* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
	18	*
	19	* Routines for generic manipulation of the interrupts found on the MIPS
	20	* Malta board.
	21	* The interrupt controller is located in the South Bridge a PIIX4 device
	22	* with two internal 82C95 interrupt controllers.
	23	*/
	24	#include <linux/init.h>
	25	#include <linux/irq.h>
	26	#include <linux/sched.h>
	27	#include <linux/slab.h>
	28	#include <linux/interrupt.h>
	29	#include <linux/kernel_stat.h>
	30	#include <linux/random.h>
	31
	32	#include <asm/i8259.h>
e01402b1	33	#include <asm/irq_cpu.h>
1da177e4 LT	34	#include <asm/io.h>
	35	#include <asm/mips-boards/malta.h>
	36	#include <asm/mips-boards/maltaint.h>
	37	#include <asm/mips-boards/piix4.h>
	38	#include <asm/gt64120.h>
	39	#include <asm/mips-boards/generic.h>
	40	#include <asm/mips-boards/msc01_pci.h>
e01402b1	41	#include <asm/msc01_ic.h>
1da177e4	42
e01402b1	43	extern void mips_timer_interrupt(void);
1da177e4 LT	44
	45	static DEFINE_SPINLOCK(mips_irq_lock);
	46
	47	static inline int mips_pcibios_iack(void)
	48	{
	49	int irq;
	50	u32 dummy;
	51
	52	/*
	53	* Determine highest priority pending interrupt by performing
	54	* a PCI Interrupt Acknowledge cycle.
	55	*/
	56	switch(mips_revision_corid) {
	57	case MIPS_REVISION_CORID_CORE_MSC:
	58	case MIPS_REVISION_CORID_CORE_FPGA2:
479a0e3e	59	case MIPS_REVISION_CORID_CORE_FPGA3:
7a834196	60	case MIPS_REVISION_CORID_CORE_24K:
1da177e4 LT	61	case MIPS_REVISION_CORID_CORE_EMUL_MSC:
	62	MSC_READ(MSC01_PCI_IACK, irq);
	63	irq &= 0xff;
	64	break;
	65	case MIPS_REVISION_CORID_QED_RM5261:
	66	case MIPS_REVISION_CORID_CORE_LV:
	67	case MIPS_REVISION_CORID_CORE_FPGA:
	68	case MIPS_REVISION_CORID_CORE_FPGAR2:
	69	irq = GT_READ(GT_PCI0_IACK_OFS);
	70	irq &= 0xff;
	71	break;
	72	case MIPS_REVISION_CORID_BONITO64:
	73	case MIPS_REVISION_CORID_CORE_20K:
	74	case MIPS_REVISION_CORID_CORE_EMUL_BON:
	75	/* The following will generate a PCI IACK cycle on the
	76	* Bonito controller. It's a little bit kludgy, but it
	77	* was the easiest way to implement it in hardware at
	78	* the given time.
	79	*/
	80	BONITO_PCIMAP_CFG = 0x20000;
	81
	82	/* Flush Bonito register block */
	83	dummy = BONITO_PCIMAP_CFG;
	84	iob(); /* sync */
	85
	86	irq = (volatile u32 )(_pcictrl_bonito_pcicfg);
	87	iob(); /* sync */
	88	irq &= 0xff;
	89	BONITO_PCIMAP_CFG = 0;
	90	break;
	91	default:
	92	printk("Unknown Core card, don't know the system controller.\n");
	93	return -1;
	94	}
	95	return irq;
	96	}
	97
e01402b1	98	static inline int get_int(void)
1da177e4 LT	99	{
1da177e4 LT	100	unsigned long flags;
e01402b1	101	int irq;
1da177e4 LT	102	spin_lock_irqsave(&mips_irq_lock, flags);
1da177e4 LT	103
e01402b1	104	irq = mips_pcibios_iack();
1da177e4 LT	105
1da177e4 LT	106	/*
479a0e3e RB	107	* The only way we can decide if an interrupt is spurious
	108	* is by checking the 8259 registers. This needs a spinlock
	109	* on an SMP system, so leave it up to the generic code...
1da177e4	110	*/
1da177e4 LT	111
	112	spin_unlock_irqrestore(&mips_irq_lock, flags);
	113
e01402b1	114	return irq;
1da177e4 LT	115	}
1da177e4 LT	116
937a8015	117	static void malta_hw0_irqdispatch(void)
1da177e4 LT	118	{
	119	int irq;
	120
e01402b1	121	irq = get_int();
41c594ab	122	if (irq < 0) {
e01402b1	123	return; /* interrupt has already been cleared */
41c594ab	124	}
1da177e4	125
937a8015	126	do_IRQ(MALTA_INT_BASE + irq);
1da177e4 LT	127	}
1da177e4 LT	128
937a8015	129	static void corehi_irqdispatch(void)
1da177e4	130	{
937a8015 RB	131	unsigned int intedge, intsteer, pcicmd, pcibadaddr;
937a8015 RB	132	unsigned int pcimstat, intisr, inten, intpol;
e01402b1	133	unsigned int intrcause,datalo,datahi;
937a8015	134	struct pt_regs *regs;
1da177e4 LT	135
1da177e4 LT	136	printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
937a8015 RB	137	printk("epc : %08lx\nStatus: %08lx\n"
	138	"Cause : %08lx\nbadVaddr : %08lx\n",
	139	regs->cp0_epc, regs->cp0_status,
	140	regs->cp0_cause, regs->cp0_badvaddr);
e01402b1 RB	141
	142	/* Read all the registers and then print them as there is a
	143	problem with interspersed printk's upsetting the Bonito controller.
	144	Do it for the others too.
	145	*/
	146
1da177e4 LT	147	switch(mips_revision_corid) {
	148	case MIPS_REVISION_CORID_CORE_MSC:
	149	case MIPS_REVISION_CORID_CORE_FPGA2:
479a0e3e	150	case MIPS_REVISION_CORID_CORE_FPGA3:
7a834196	151	case MIPS_REVISION_CORID_CORE_24K:
e01402b1	152	case MIPS_REVISION_CORID_CORE_EMUL_MSC:
937a8015	153	ll_msc_irq();
1da177e4 LT	154	break;
	155	case MIPS_REVISION_CORID_QED_RM5261:
	156	case MIPS_REVISION_CORID_CORE_LV:
	157	case MIPS_REVISION_CORID_CORE_FPGA:
	158	case MIPS_REVISION_CORID_CORE_FPGAR2:
e01402b1 RB	159	intrcause = GT_READ(GT_INTRCAUSE_OFS);
e01402b1 RB	160	datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
1da177e4	161	datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
e01402b1 RB	162	printk("GT_INTRCAUSE = %08x\n", intrcause);
e01402b1 RB	163	printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, datalo);
1da177e4 LT	164	break;
	165	case MIPS_REVISION_CORID_BONITO64:
	166	case MIPS_REVISION_CORID_CORE_20K:
	167	case MIPS_REVISION_CORID_CORE_EMUL_BON:
e01402b1 RB	168	pcibadaddr = BONITO_PCIBADADDR;
	169	pcimstat = BONITO_PCIMSTAT;
	170	intisr = BONITO_INTISR;
	171	inten = BONITO_INTEN;
	172	intpol = BONITO_INTPOL;
	173	intedge = BONITO_INTEDGE;
	174	intsteer = BONITO_INTSTEER;
	175	pcicmd = BONITO_PCICMD;
	176	printk("BONITO_INTISR = %08x\n", intisr);
	177	printk("BONITO_INTEN = %08x\n", inten);
	178	printk("BONITO_INTPOL = %08x\n", intpol);
	179	printk("BONITO_INTEDGE = %08x\n", intedge);
	180	printk("BONITO_INTSTEER = %08x\n", intsteer);
	181	printk("BONITO_PCICMD = %08x\n", pcicmd);
	182	printk("BONITO_PCIBADADDR = %08x\n", pcibadaddr);
	183	printk("BONITO_PCIMSTAT = %08x\n", pcimstat);
1da177e4 LT	184	break;
	185	}
	186
	187	/* We die here*/
	188	die("CoreHi interrupt", regs);
	189	}
	190
e4ac58af RB	191	static inline int clz(unsigned long x)
	192	{
	193	__asm__ (
	194	" .set push \n"
	195	" .set mips32 \n"
	196	" clz %0, %1 \n"
	197	" .set pop \n"
	198	: "=r" (x)
	199	: "r" (x));
	200
	201	return x;
	202	}
	203
	204	/*
	205	* Version of ffs that only looks at bits 12..15.
	206	*/
	207	static inline unsigned int irq_ffs(unsigned int pending)
	208	{
	209	#if defined(CONFIG_CPU_MIPS32) \|\| defined(CONFIG_CPU_MIPS64)
	210	return -clz(pending) + 31 - CAUSEB_IP;
	211	#else
	212	unsigned int a0 = 7;
	213	unsigned int t0;
	214
0118c3ca	215	t0 = pending & 0xf000;
e4ac58af RB	216	t0 = t0 < 1;
	217	t0 = t0 << 2;
	218	a0 = a0 - t0;
0118c3ca	219	pending = pending << t0;
e4ac58af	220
0118c3ca	221	t0 = pending & 0xc000;
e4ac58af RB	222	t0 = t0 < 1;
	223	t0 = t0 << 1;
	224	a0 = a0 - t0;
0118c3ca	225	pending = pending << t0;
e4ac58af	226
0118c3ca	227	t0 = pending & 0x8000;
e4ac58af RB	228	t0 = t0 < 1;
	229	//t0 = t0 << 2;
	230	a0 = a0 - t0;
0118c3ca	231	//pending = pending << t0;
e4ac58af RB	232
	233	return a0;
	234	#endif
	235	}
	236
	237	/*
	238	* IRQs on the Malta board look basically (barring software IRQs which we
	239	* don't use at all and all external interrupt sources are combined together
	240	* on hardware interrupt 0 (MIPS IRQ 2)) like:
	241	*
	242	* MIPS IRQ Source
	243	* -------- ------
	244	* 0 Software (ignored)
	245	* 1 Software (ignored)
	246	* 2 Combined hardware interrupt (hw0)
	247	* 3 Hardware (ignored)
	248	* 4 Hardware (ignored)
	249	* 5 Hardware (ignored)
	250	* 6 Hardware (ignored)
	251	* 7 R4k timer (what we use)
	252	*
	253	* We handle the IRQ according to _our_ priority which is:
	254	*
	255	* Highest ---- R4k Timer
	256	* Lowest ---- Combined hardware interrupt
	257	*
	258	* then we just return, if multiple IRQs are pending then we will just take
	259	* another exception, big deal.
	260	*/
	261
937a8015	262	asmlinkage void plat_irq_dispatch(void)
e4ac58af RB	263	{
	264	unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
	265	int irq;
	266
	267	irq = irq_ffs(pending);
	268
	269	if (irq == MIPSCPU_INT_I8259A)
937a8015	270	malta_hw0_irqdispatch();
e4ac58af	271	else if (irq > 0)
937a8015	272	do_IRQ(MIPSCPU_INT_BASE + irq);
e4ac58af	273	else
937a8015	274	spurious_interrupt();
e4ac58af RB	275	}
e4ac58af RB	276
e01402b1 RB	277	static struct irqaction i8259irq = {
	278	.handler = no_action,
	279	.name = "XT-PIC cascade"
	280	};
	281
	282	static struct irqaction corehi_irqaction = {
	283	.handler = no_action,
	284	.name = "CoreHi"
	285	};
	286
	287	msc_irqmap_t __initdata msc_irqmap[] = {
	288	{MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0},
	289	{MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0},
	290	};
	291	int __initdata msc_nr_irqs = sizeof(msc_irqmap)/sizeof(msc_irqmap_t);
	292
	293	msc_irqmap_t __initdata msc_eicirqmap[] = {
	294	{MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
	295	{MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0},
	296	{MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0},
	297	{MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0},
	298	{MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0},
	299	{MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0},
	300	{MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0},
	301	{MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0},
	302	{MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0},
	303	{MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}
	304	};
	305	int __initdata msc_nr_eicirqs = sizeof(msc_eicirqmap)/sizeof(msc_irqmap_t);
	306
1da177e4 LT	307	void __init arch_init_irq(void)
1da177e4 LT	308	{
1da177e4	309	init_i8259_irqs();
e01402b1 RB	310
	311	if (!cpu_has_veic)
	312	mips_cpu_irq_init (MIPSCPU_INT_BASE);
	313
	314	switch(mips_revision_corid) {
	315	case MIPS_REVISION_CORID_CORE_MSC:
	316	case MIPS_REVISION_CORID_CORE_FPGA2:
479a0e3e	317	case MIPS_REVISION_CORID_CORE_FPGA3:
7a834196	318	case MIPS_REVISION_CORID_CORE_24K:
e01402b1 RB	319	case MIPS_REVISION_CORID_CORE_EMUL_MSC:
	320	if (cpu_has_veic)
	321	init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
	322	else
	323	init_msc_irqs (MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
	324	}
	325
	326	if (cpu_has_veic) {
	327	set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch);
	328	set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch);
	329	setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
	330	setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
	331	}
	332	else if (cpu_has_vint) {
	333	set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
	334	set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch);
41c594ab RB	335	#ifdef CONFIG_MIPS_MT_SMTC
	336	setup_irq_smtc (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq,
	337	(0x100 << MIPSCPU_INT_I8259A));
	338	setup_irq_smtc (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI,
	339	&corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
	340	#else /* Not SMTC */
e01402b1 RB	341	setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
e01402b1 RB	342	setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
41c594ab	343	#endif /* CONFIG_MIPS_MT_SMTC */
e01402b1 RB	344	}
e01402b1 RB	345	else {
e01402b1 RB	346	setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
	347	setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
	348	}
1da177e4	349	}