[deliverable/linux.git] / arch / mips / mips-boards / malta / malta_int.c

/*
 * Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
 * Copyright (C) 2001 Ralf Baechle
 *
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * Routines for generic manipulation of the interrupts found on the MIPS
 * Malta board.
 * The interrupt controller is located in the South Bridge a PIIX4 device
 * with two internal 82C95 interrupt controllers.
 */
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/random.h>

#include <asm/i8259.h>
#include <asm/irq_cpu.h>
#include <asm/io.h>
#include <asm/mips-boards/malta.h>
#include <asm/mips-boards/maltaint.h>
#include <asm/mips-boards/piix4.h>
#include <asm/gt64120.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/msc01_pci.h>
#include <asm/msc01_ic.h>

extern asmlinkage void mipsIRQ(void);
extern void mips_timer_interrupt(void);

static DEFINE_SPINLOCK(mips_irq_lock);

static inline int mips_pcibios_iack(void)
{
	int irq;
        u32 dummy;

	/*
	 * Determine highest priority pending interrupt by performing
	 * a PCI Interrupt Acknowledge cycle.
	 */
	switch(mips_revision_corid) {
	case MIPS_REVISION_CORID_CORE_MSC:
	case MIPS_REVISION_CORID_CORE_FPGA2:
	case MIPS_REVISION_CORID_CORE_FPGA3:
	case MIPS_REVISION_CORID_CORE_EMUL_MSC:
	        MSC_READ(MSC01_PCI_IACK, irq);
		irq &= 0xff;
		break;
	case MIPS_REVISION_CORID_QED_RM5261:
	case MIPS_REVISION_CORID_CORE_LV:
	case MIPS_REVISION_CORID_CORE_FPGA:
	case MIPS_REVISION_CORID_CORE_FPGAR2:
		irq = GT_READ(GT_PCI0_IACK_OFS);
		irq &= 0xff;
		break;
	case MIPS_REVISION_CORID_BONITO64:
	case MIPS_REVISION_CORID_CORE_20K:
	case MIPS_REVISION_CORID_CORE_EMUL_BON:
		/* The following will generate a PCI IACK cycle on the
		 * Bonito controller. It's a little bit kludgy, but it
		 * was the easiest way to implement it in hardware at
		 * the given time.
		 */
		BONITO_PCIMAP_CFG = 0x20000;

		/* Flush Bonito register block */
		dummy = BONITO_PCIMAP_CFG;
		iob();    /* sync */

		irq = *(volatile u32 *)(_pcictrl_bonito_pcicfg);
		iob();    /* sync */
		irq &= 0xff;
		BONITO_PCIMAP_CFG = 0;
		break;
	default:
	        printk("Unknown Core card, don't know the system controller.\n");
		return -1;
	}
	return irq;
}

static inline int get_int(void)
{
	unsigned long flags;
	int irq;
	spin_lock_irqsave(&mips_irq_lock, flags);

	irq = mips_pcibios_iack();

	/*
	 * The only way we can decide if an interrupt is spurious
	 * is by checking the 8259 registers.  This needs a spinlock
	 * on an SMP system,  so leave it up to the generic code...
	 */

	spin_unlock_irqrestore(&mips_irq_lock, flags);

	return irq;
}

void malta_hw0_irqdispatch(struct pt_regs *regs)
{
	int irq;

	irq = get_int();
	if (irq < 0)
		return;  /* interrupt has already been cleared */

	do_IRQ(MALTA_INT_BASE+irq, regs);
}

void corehi_irqdispatch(struct pt_regs *regs)
{
	unsigned int intrcause,datalo,datahi;
        unsigned int pcimstat, intisr, inten, intpol, intedge, intsteer, pcicmd, pcibadaddr;

        printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
        printk("epc   : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n"
, regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr);

	/* Read all the registers and then print them as there is a
	   problem with interspersed printk's upsetting the Bonito controller.
	   Do it for the others too.
	*/

        switch(mips_revision_corid) {
        case MIPS_REVISION_CORID_CORE_MSC:
        case MIPS_REVISION_CORID_CORE_FPGA2:
        case MIPS_REVISION_CORID_CORE_FPGA3:
        case MIPS_REVISION_CORID_CORE_EMUL_MSC:
                ll_msc_irq(regs);
                break;
        case MIPS_REVISION_CORID_QED_RM5261:
        case MIPS_REVISION_CORID_CORE_LV:
        case MIPS_REVISION_CORID_CORE_FPGA:
        case MIPS_REVISION_CORID_CORE_FPGAR2:
                intrcause = GT_READ(GT_INTRCAUSE_OFS);
                datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
                datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
                printk("GT_INTRCAUSE = %08x\n", intrcause);
                printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, datalo);
                break;
        case MIPS_REVISION_CORID_BONITO64:
        case MIPS_REVISION_CORID_CORE_20K:
        case MIPS_REVISION_CORID_CORE_EMUL_BON:
                pcibadaddr = BONITO_PCIBADADDR;
                pcimstat = BONITO_PCIMSTAT;
                intisr = BONITO_INTISR;
                inten = BONITO_INTEN;
                intpol = BONITO_INTPOL;
                intedge = BONITO_INTEDGE;
                intsteer = BONITO_INTSTEER;
                pcicmd = BONITO_PCICMD;
                printk("BONITO_INTISR = %08x\n", intisr);
                printk("BONITO_INTEN = %08x\n", inten);
                printk("BONITO_INTPOL = %08x\n", intpol);
                printk("BONITO_INTEDGE = %08x\n", intedge);
                printk("BONITO_INTSTEER = %08x\n", intsteer);
                printk("BONITO_PCICMD = %08x\n", pcicmd);
                printk("BONITO_PCIBADADDR = %08x\n", pcibadaddr);
                printk("BONITO_PCIMSTAT = %08x\n", pcimstat);
                break;
        }

        /* We die here*/
        die("CoreHi interrupt", regs);
}

static struct irqaction i8259irq = {
	.handler = no_action,
	.name = "XT-PIC cascade"
};

static struct irqaction corehi_irqaction = {
	.handler = no_action,
	.name = "CoreHi"
};

msc_irqmap_t __initdata msc_irqmap[] = {
	{MSC01C_INT_TMR,		MSC01_IRQ_EDGE, 0},
	{MSC01C_INT_PCI,		MSC01_IRQ_LEVEL, 0},
};
int __initdata msc_nr_irqs = sizeof(msc_irqmap)/sizeof(msc_irqmap_t);

msc_irqmap_t __initdata msc_eicirqmap[] = {
	{MSC01E_INT_SW0,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_SW1,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_I8259A,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_SMI,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_COREHI,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_CORELO,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_TMR,		MSC01_IRQ_EDGE, 0},
	{MSC01E_INT_PCI,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_PERFCTR,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_CPUCTR,		MSC01_IRQ_LEVEL, 0}
};
int __initdata msc_nr_eicirqs = sizeof(msc_eicirqmap)/sizeof(msc_irqmap_t);

void __init arch_init_irq(void)
{
	set_except_vector(0, mipsIRQ);
	init_i8259_irqs();

	if (!cpu_has_veic)
		mips_cpu_irq_init (MIPSCPU_INT_BASE);

        switch(mips_revision_corid) {
        case MIPS_REVISION_CORID_CORE_MSC:
        case MIPS_REVISION_CORID_CORE_FPGA2:
        case MIPS_REVISION_CORID_CORE_FPGA3:
        case MIPS_REVISION_CORID_CORE_EMUL_MSC:
		if (cpu_has_veic)
			init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
		else
			init_msc_irqs (MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
	}

	if (cpu_has_veic) {
		set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch);
		set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch);
		setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
		setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
	}
	else if (cpu_has_vint) {
		set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
		set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch);

		setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
		setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
	}
	else {
		set_except_vector(0, mipsIRQ);
		setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
		setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
	}
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Carsten Langgaard, carstenl@mips.com
	3	* Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
	4	* Copyright (C) 2001 Ralf Baechle
	5	*
	6	* This program is free software; you can distribute it and/or modify it
	7	* under the terms of the GNU General Public License (Version 2) as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	13	* for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License along
	16	* with this program; if not, write to the Free Software Foundation, Inc.,
	17	* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
	18	*
	19	* Routines for generic manipulation of the interrupts found on the MIPS
	20	* Malta board.
	21	* The interrupt controller is located in the South Bridge a PIIX4 device
	22	* with two internal 82C95 interrupt controllers.
	23	*/
	24	#include <linux/init.h>
	25	#include <linux/irq.h>
	26	#include <linux/sched.h>
	27	#include <linux/slab.h>
	28	#include <linux/interrupt.h>
	29	#include <linux/kernel_stat.h>
	30	#include <linux/random.h>
	31
	32	#include <asm/i8259.h>
e01402b1	33	#include <asm/irq_cpu.h>
1da177e4 LT	34	#include <asm/io.h>
	35	#include <asm/mips-boards/malta.h>
	36	#include <asm/mips-boards/maltaint.h>
	37	#include <asm/mips-boards/piix4.h>
	38	#include <asm/gt64120.h>
	39	#include <asm/mips-boards/generic.h>
	40	#include <asm/mips-boards/msc01_pci.h>
e01402b1	41	#include <asm/msc01_ic.h>
1da177e4 LT	42
1da177e4 LT	43	extern asmlinkage void mipsIRQ(void);
e01402b1	44	extern void mips_timer_interrupt(void);
1da177e4 LT	45
	46	static DEFINE_SPINLOCK(mips_irq_lock);
	47
	48	static inline int mips_pcibios_iack(void)
	49	{
	50	int irq;
	51	u32 dummy;
	52
	53	/*
	54	* Determine highest priority pending interrupt by performing
	55	* a PCI Interrupt Acknowledge cycle.
	56	*/
	57	switch(mips_revision_corid) {
	58	case MIPS_REVISION_CORID_CORE_MSC:
	59	case MIPS_REVISION_CORID_CORE_FPGA2:
479a0e3e	60	case MIPS_REVISION_CORID_CORE_FPGA3:
1da177e4 LT	61	case MIPS_REVISION_CORID_CORE_EMUL_MSC:
	62	MSC_READ(MSC01_PCI_IACK, irq);
	63	irq &= 0xff;
	64	break;
	65	case MIPS_REVISION_CORID_QED_RM5261:
	66	case MIPS_REVISION_CORID_CORE_LV:
	67	case MIPS_REVISION_CORID_CORE_FPGA:
	68	case MIPS_REVISION_CORID_CORE_FPGAR2:
	69	irq = GT_READ(GT_PCI0_IACK_OFS);
	70	irq &= 0xff;
	71	break;
	72	case MIPS_REVISION_CORID_BONITO64:
	73	case MIPS_REVISION_CORID_CORE_20K:
	74	case MIPS_REVISION_CORID_CORE_EMUL_BON:
	75	/* The following will generate a PCI IACK cycle on the
	76	* Bonito controller. It's a little bit kludgy, but it
	77	* was the easiest way to implement it in hardware at
	78	* the given time.
	79	*/
	80	BONITO_PCIMAP_CFG = 0x20000;
	81
	82	/* Flush Bonito register block */
	83	dummy = BONITO_PCIMAP_CFG;
	84	iob(); /* sync */
	85
	86	irq = (volatile u32 )(_pcictrl_bonito_pcicfg);
	87	iob(); /* sync */
	88	irq &= 0xff;
	89	BONITO_PCIMAP_CFG = 0;
	90	break;
	91	default:
	92	printk("Unknown Core card, don't know the system controller.\n");
	93	return -1;
	94	}
	95	return irq;
	96	}
	97
e01402b1	98	static inline int get_int(void)
1da177e4 LT	99	{
1da177e4 LT	100	unsigned long flags;
e01402b1	101	int irq;
1da177e4 LT	102	spin_lock_irqsave(&mips_irq_lock, flags);
1da177e4 LT	103
e01402b1	104	irq = mips_pcibios_iack();
1da177e4 LT	105
1da177e4 LT	106	/*
479a0e3e RB	107	* The only way we can decide if an interrupt is spurious
	108	* is by checking the 8259 registers. This needs a spinlock
	109	* on an SMP system, so leave it up to the generic code...
1da177e4	110	*/
1da177e4 LT	111
	112	spin_unlock_irqrestore(&mips_irq_lock, flags);
	113
e01402b1	114	return irq;
1da177e4 LT	115	}
	116
	117	void malta_hw0_irqdispatch(struct pt_regs *regs)
	118	{
	119	int irq;
	120
e01402b1 RB	121	irq = get_int();
	122	if (irq < 0)
	123	return; /* interrupt has already been cleared */
1da177e4	124
e01402b1	125	do_IRQ(MALTA_INT_BASE+irq, regs);
1da177e4 LT	126	}
	127
	128	void corehi_irqdispatch(struct pt_regs *regs)
	129	{
e01402b1 RB	130	unsigned int intrcause,datalo,datahi;
e01402b1 RB	131	unsigned int pcimstat, intisr, inten, intpol, intedge, intsteer, pcicmd, pcibadaddr;
1da177e4 LT	132
	133	printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
	134	printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n"
	135	, regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr);
e01402b1 RB	136
	137	/* Read all the registers and then print them as there is a
	138	problem with interspersed printk's upsetting the Bonito controller.
	139	Do it for the others too.
	140	*/
	141
1da177e4 LT	142	switch(mips_revision_corid) {
	143	case MIPS_REVISION_CORID_CORE_MSC:
	144	case MIPS_REVISION_CORID_CORE_FPGA2:
479a0e3e	145	case MIPS_REVISION_CORID_CORE_FPGA3:
e01402b1 RB	146	case MIPS_REVISION_CORID_CORE_EMUL_MSC:
e01402b1 RB	147	ll_msc_irq(regs);
1da177e4 LT	148	break;
	149	case MIPS_REVISION_CORID_QED_RM5261:
	150	case MIPS_REVISION_CORID_CORE_LV:
	151	case MIPS_REVISION_CORID_CORE_FPGA:
	152	case MIPS_REVISION_CORID_CORE_FPGAR2:
e01402b1 RB	153	intrcause = GT_READ(GT_INTRCAUSE_OFS);
e01402b1 RB	154	datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
1da177e4	155	datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
e01402b1 RB	156	printk("GT_INTRCAUSE = %08x\n", intrcause);
e01402b1 RB	157	printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, datalo);
1da177e4 LT	158	break;
	159	case MIPS_REVISION_CORID_BONITO64:
	160	case MIPS_REVISION_CORID_CORE_20K:
	161	case MIPS_REVISION_CORID_CORE_EMUL_BON:
e01402b1 RB	162	pcibadaddr = BONITO_PCIBADADDR;
	163	pcimstat = BONITO_PCIMSTAT;
	164	intisr = BONITO_INTISR;
	165	inten = BONITO_INTEN;
	166	intpol = BONITO_INTPOL;
	167	intedge = BONITO_INTEDGE;
	168	intsteer = BONITO_INTSTEER;
	169	pcicmd = BONITO_PCICMD;
	170	printk("BONITO_INTISR = %08x\n", intisr);
	171	printk("BONITO_INTEN = %08x\n", inten);
	172	printk("BONITO_INTPOL = %08x\n", intpol);
	173	printk("BONITO_INTEDGE = %08x\n", intedge);
	174	printk("BONITO_INTSTEER = %08x\n", intsteer);
	175	printk("BONITO_PCICMD = %08x\n", pcicmd);
	176	printk("BONITO_PCIBADADDR = %08x\n", pcibadaddr);
	177	printk("BONITO_PCIMSTAT = %08x\n", pcimstat);
1da177e4 LT	178	break;
	179	}
	180
	181	/* We die here*/
	182	die("CoreHi interrupt", regs);
	183	}
	184
e01402b1 RB	185	static struct irqaction i8259irq = {
	186	.handler = no_action,
	187	.name = "XT-PIC cascade"
	188	};
	189
	190	static struct irqaction corehi_irqaction = {
	191	.handler = no_action,
	192	.name = "CoreHi"
	193	};
	194
	195	msc_irqmap_t __initdata msc_irqmap[] = {
	196	{MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0},
	197	{MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0},
	198	};
	199	int __initdata msc_nr_irqs = sizeof(msc_irqmap)/sizeof(msc_irqmap_t);
	200
	201	msc_irqmap_t __initdata msc_eicirqmap[] = {
	202	{MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
	203	{MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0},
	204	{MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0},
	205	{MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0},
	206	{MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0},
	207	{MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0},
	208	{MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0},
	209	{MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0},
	210	{MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0},
	211	{MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}
	212	};
	213	int __initdata msc_nr_eicirqs = sizeof(msc_eicirqmap)/sizeof(msc_irqmap_t);
	214
1da177e4 LT	215	void __init arch_init_irq(void)
	216	{
	217	set_except_vector(0, mipsIRQ);
	218	init_i8259_irqs();
e01402b1 RB	219
	220	if (!cpu_has_veic)
	221	mips_cpu_irq_init (MIPSCPU_INT_BASE);
	222
	223	switch(mips_revision_corid) {
	224	case MIPS_REVISION_CORID_CORE_MSC:
	225	case MIPS_REVISION_CORID_CORE_FPGA2:
479a0e3e	226	case MIPS_REVISION_CORID_CORE_FPGA3:
e01402b1 RB	227	case MIPS_REVISION_CORID_CORE_EMUL_MSC:
	228	if (cpu_has_veic)
	229	init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
	230	else
	231	init_msc_irqs (MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
	232	}
	233
	234	if (cpu_has_veic) {
	235	set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch);
	236	set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch);
	237	setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
	238	setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
	239	}
	240	else if (cpu_has_vint) {
	241	set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
	242	set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch);
	243
	244	setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
	245	setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
	246	}
	247	else {
	248	set_except_vector(0, mipsIRQ);
	249	setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
	250	setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
	251	}
1da177e4	252	}