Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
79add627 | 6 | * Copyright (C) 1996 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
7 | * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org) |
8 | * Copyright (C) 1999, 2000 Silicon Graphics, Inc. | |
9 | */ | |
a754f708 | 10 | #include <linux/hardirq.h> |
1da177e4 | 11 | #include <linux/init.h> |
db813fe5 | 12 | #include <linux/highmem.h> |
1da177e4 | 13 | #include <linux/kernel.h> |
641e97f3 | 14 | #include <linux/linkage.h> |
ff522058 | 15 | #include <linux/preempt.h> |
1da177e4 | 16 | #include <linux/sched.h> |
631330f5 | 17 | #include <linux/smp.h> |
1da177e4 | 18 | #include <linux/mm.h> |
35133692 | 19 | #include <linux/module.h> |
1da177e4 LT |
20 | #include <linux/bitops.h> |
21 | ||
22 | #include <asm/bcache.h> | |
23 | #include <asm/bootinfo.h> | |
ec74e361 | 24 | #include <asm/cache.h> |
1da177e4 LT |
25 | #include <asm/cacheops.h> |
26 | #include <asm/cpu.h> | |
27 | #include <asm/cpu-features.h> | |
69f24d17 | 28 | #include <asm/cpu-type.h> |
1da177e4 LT |
29 | #include <asm/io.h> |
30 | #include <asm/page.h> | |
31 | #include <asm/pgtable.h> | |
32 | #include <asm/r4kcache.h> | |
e001e528 | 33 | #include <asm/sections.h> |
1da177e4 LT |
34 | #include <asm/mmu_context.h> |
35 | #include <asm/war.h> | |
ba5187db | 36 | #include <asm/cacheflush.h> /* for run_uncached() */ |
9cd9669b | 37 | #include <asm/traps.h> |
b6d92b4a | 38 | #include <asm/dma-coherence.h> |
7f3f1d01 RB |
39 | |
40 | /* | |
41 | * Special Variant of smp_call_function for use by cache functions: | |
42 | * | |
43 | * o No return value | |
44 | * o collapses to normal function call on UP kernels | |
45 | * o collapses to normal function call on systems with a single shared | |
46 | * primary cache. | |
c8c5f3fd | 47 | * o doesn't disable interrupts on the local CPU |
7f3f1d01 | 48 | */ |
48a26e60 | 49 | static inline void r4k_on_each_cpu(void (*func) (void *info), void *info) |
7f3f1d01 RB |
50 | { |
51 | preempt_disable(); | |
52 | ||
53 | #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC) | |
48a26e60 | 54 | smp_call_function(func, info, 1); |
7f3f1d01 RB |
55 | #endif |
56 | func(info); | |
57 | preempt_enable(); | |
58 | } | |
59 | ||
0ee958e1 | 60 | #if defined(CONFIG_MIPS_CMP) || defined(CONFIG_MIPS_CPS) |
39b8d525 RB |
61 | #define cpu_has_safe_index_cacheops 0 |
62 | #else | |
63 | #define cpu_has_safe_index_cacheops 1 | |
64 | #endif | |
65 | ||
ec74e361 RB |
66 | /* |
67 | * Must die. | |
68 | */ | |
69 | static unsigned long icache_size __read_mostly; | |
70 | static unsigned long dcache_size __read_mostly; | |
71 | static unsigned long scache_size __read_mostly; | |
1da177e4 LT |
72 | |
73 | /* | |
74 | * Dummy cache handling routines for machines without boardcaches | |
75 | */ | |
73f40352 | 76 | static void cache_noop(void) {} |
1da177e4 LT |
77 | |
78 | static struct bcache_ops no_sc_ops = { | |
73f40352 CD |
79 | .bc_enable = (void *)cache_noop, |
80 | .bc_disable = (void *)cache_noop, | |
81 | .bc_wback_inv = (void *)cache_noop, | |
82 | .bc_inv = (void *)cache_noop | |
1da177e4 LT |
83 | }; |
84 | ||
85 | struct bcache_ops *bcops = &no_sc_ops; | |
86 | ||
330cfe01 TS |
87 | #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) |
88 | #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) | |
1da177e4 LT |
89 | |
90 | #define R4600_HIT_CACHEOP_WAR_IMPL \ | |
91 | do { \ | |
92 | if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \ | |
93 | *(volatile unsigned long *)CKSEG1; \ | |
94 | if (R4600_V1_HIT_CACHEOP_WAR) \ | |
95 | __asm__ __volatile__("nop;nop;nop;nop"); \ | |
96 | } while (0) | |
97 | ||
98 | static void (*r4k_blast_dcache_page)(unsigned long addr); | |
99 | ||
100 | static inline void r4k_blast_dcache_page_dc32(unsigned long addr) | |
101 | { | |
102 | R4600_HIT_CACHEOP_WAR_IMPL; | |
103 | blast_dcache32_page(addr); | |
104 | } | |
105 | ||
605b7ef7 KC |
106 | static inline void r4k_blast_dcache_page_dc64(unsigned long addr) |
107 | { | |
108 | R4600_HIT_CACHEOP_WAR_IMPL; | |
109 | blast_dcache64_page(addr); | |
110 | } | |
111 | ||
078a55fc | 112 | static void r4k_blast_dcache_page_setup(void) |
1da177e4 LT |
113 | { |
114 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
115 | ||
73f40352 CD |
116 | if (dc_lsize == 0) |
117 | r4k_blast_dcache_page = (void *)cache_noop; | |
118 | else if (dc_lsize == 16) | |
1da177e4 LT |
119 | r4k_blast_dcache_page = blast_dcache16_page; |
120 | else if (dc_lsize == 32) | |
121 | r4k_blast_dcache_page = r4k_blast_dcache_page_dc32; | |
605b7ef7 KC |
122 | else if (dc_lsize == 64) |
123 | r4k_blast_dcache_page = r4k_blast_dcache_page_dc64; | |
1da177e4 LT |
124 | } |
125 | ||
4caa906e LY |
126 | #ifndef CONFIG_EVA |
127 | #define r4k_blast_dcache_user_page r4k_blast_dcache_page | |
128 | #else | |
129 | ||
130 | static void (*r4k_blast_dcache_user_page)(unsigned long addr); | |
131 | ||
132 | static void r4k_blast_dcache_user_page_setup(void) | |
133 | { | |
134 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
135 | ||
136 | if (dc_lsize == 0) | |
137 | r4k_blast_dcache_user_page = (void *)cache_noop; | |
138 | else if (dc_lsize == 16) | |
139 | r4k_blast_dcache_user_page = blast_dcache16_user_page; | |
140 | else if (dc_lsize == 32) | |
141 | r4k_blast_dcache_user_page = blast_dcache32_user_page; | |
142 | else if (dc_lsize == 64) | |
143 | r4k_blast_dcache_user_page = blast_dcache64_user_page; | |
144 | } | |
145 | ||
146 | #endif | |
147 | ||
1da177e4 LT |
148 | static void (* r4k_blast_dcache_page_indexed)(unsigned long addr); |
149 | ||
078a55fc | 150 | static void r4k_blast_dcache_page_indexed_setup(void) |
1da177e4 LT |
151 | { |
152 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
153 | ||
73f40352 CD |
154 | if (dc_lsize == 0) |
155 | r4k_blast_dcache_page_indexed = (void *)cache_noop; | |
156 | else if (dc_lsize == 16) | |
1da177e4 LT |
157 | r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; |
158 | else if (dc_lsize == 32) | |
159 | r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; | |
605b7ef7 KC |
160 | else if (dc_lsize == 64) |
161 | r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed; | |
1da177e4 LT |
162 | } |
163 | ||
f2e3656d SL |
164 | void (* r4k_blast_dcache)(void); |
165 | EXPORT_SYMBOL(r4k_blast_dcache); | |
1da177e4 | 166 | |
078a55fc | 167 | static void r4k_blast_dcache_setup(void) |
1da177e4 LT |
168 | { |
169 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
170 | ||
73f40352 CD |
171 | if (dc_lsize == 0) |
172 | r4k_blast_dcache = (void *)cache_noop; | |
173 | else if (dc_lsize == 16) | |
1da177e4 LT |
174 | r4k_blast_dcache = blast_dcache16; |
175 | else if (dc_lsize == 32) | |
176 | r4k_blast_dcache = blast_dcache32; | |
605b7ef7 KC |
177 | else if (dc_lsize == 64) |
178 | r4k_blast_dcache = blast_dcache64; | |
1da177e4 LT |
179 | } |
180 | ||
181 | /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */ | |
182 | #define JUMP_TO_ALIGN(order) \ | |
183 | __asm__ __volatile__( \ | |
184 | "b\t1f\n\t" \ | |
185 | ".align\t" #order "\n\t" \ | |
186 | "1:\n\t" \ | |
187 | ) | |
188 | #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */ | |
70342287 | 189 | #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11) |
1da177e4 LT |
190 | |
191 | static inline void blast_r4600_v1_icache32(void) | |
192 | { | |
193 | unsigned long flags; | |
194 | ||
195 | local_irq_save(flags); | |
196 | blast_icache32(); | |
197 | local_irq_restore(flags); | |
198 | } | |
199 | ||
200 | static inline void tx49_blast_icache32(void) | |
201 | { | |
202 | unsigned long start = INDEX_BASE; | |
203 | unsigned long end = start + current_cpu_data.icache.waysize; | |
204 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; | |
205 | unsigned long ws_end = current_cpu_data.icache.ways << | |
70342287 | 206 | current_cpu_data.icache.waybit; |
1da177e4 LT |
207 | unsigned long ws, addr; |
208 | ||
209 | CACHE32_UNROLL32_ALIGN2; | |
210 | /* I'm in even chunk. blast odd chunks */ | |
42a3b4f2 RB |
211 | for (ws = 0; ws < ws_end; ws += ws_inc) |
212 | for (addr = start + 0x400; addr < end; addr += 0x400 * 2) | |
21a151d8 | 213 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
214 | CACHE32_UNROLL32_ALIGN; |
215 | /* I'm in odd chunk. blast even chunks */ | |
42a3b4f2 RB |
216 | for (ws = 0; ws < ws_end; ws += ws_inc) |
217 | for (addr = start; addr < end; addr += 0x400 * 2) | |
21a151d8 | 218 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
219 | } |
220 | ||
221 | static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page) | |
222 | { | |
223 | unsigned long flags; | |
224 | ||
225 | local_irq_save(flags); | |
226 | blast_icache32_page_indexed(page); | |
227 | local_irq_restore(flags); | |
228 | } | |
229 | ||
230 | static inline void tx49_blast_icache32_page_indexed(unsigned long page) | |
231 | { | |
67a3f6de AN |
232 | unsigned long indexmask = current_cpu_data.icache.waysize - 1; |
233 | unsigned long start = INDEX_BASE + (page & indexmask); | |
1da177e4 LT |
234 | unsigned long end = start + PAGE_SIZE; |
235 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; | |
236 | unsigned long ws_end = current_cpu_data.icache.ways << | |
70342287 | 237 | current_cpu_data.icache.waybit; |
1da177e4 LT |
238 | unsigned long ws, addr; |
239 | ||
240 | CACHE32_UNROLL32_ALIGN2; | |
241 | /* I'm in even chunk. blast odd chunks */ | |
42a3b4f2 RB |
242 | for (ws = 0; ws < ws_end; ws += ws_inc) |
243 | for (addr = start + 0x400; addr < end; addr += 0x400 * 2) | |
21a151d8 | 244 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
245 | CACHE32_UNROLL32_ALIGN; |
246 | /* I'm in odd chunk. blast even chunks */ | |
42a3b4f2 RB |
247 | for (ws = 0; ws < ws_end; ws += ws_inc) |
248 | for (addr = start; addr < end; addr += 0x400 * 2) | |
21a151d8 | 249 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
250 | } |
251 | ||
252 | static void (* r4k_blast_icache_page)(unsigned long addr); | |
253 | ||
078a55fc | 254 | static void r4k_blast_icache_page_setup(void) |
1da177e4 LT |
255 | { |
256 | unsigned long ic_lsize = cpu_icache_line_size(); | |
257 | ||
73f40352 CD |
258 | if (ic_lsize == 0) |
259 | r4k_blast_icache_page = (void *)cache_noop; | |
260 | else if (ic_lsize == 16) | |
1da177e4 | 261 | r4k_blast_icache_page = blast_icache16_page; |
43a06847 AK |
262 | else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2) |
263 | r4k_blast_icache_page = loongson2_blast_icache32_page; | |
1da177e4 LT |
264 | else if (ic_lsize == 32) |
265 | r4k_blast_icache_page = blast_icache32_page; | |
266 | else if (ic_lsize == 64) | |
267 | r4k_blast_icache_page = blast_icache64_page; | |
268 | } | |
269 | ||
4caa906e LY |
270 | #ifndef CONFIG_EVA |
271 | #define r4k_blast_icache_user_page r4k_blast_icache_page | |
272 | #else | |
273 | ||
274 | static void (*r4k_blast_icache_user_page)(unsigned long addr); | |
275 | ||
276 | static void __cpuinit r4k_blast_icache_user_page_setup(void) | |
277 | { | |
278 | unsigned long ic_lsize = cpu_icache_line_size(); | |
279 | ||
280 | if (ic_lsize == 0) | |
281 | r4k_blast_icache_user_page = (void *)cache_noop; | |
282 | else if (ic_lsize == 16) | |
283 | r4k_blast_icache_user_page = blast_icache16_user_page; | |
284 | else if (ic_lsize == 32) | |
285 | r4k_blast_icache_user_page = blast_icache32_user_page; | |
286 | else if (ic_lsize == 64) | |
287 | r4k_blast_icache_user_page = blast_icache64_user_page; | |
288 | } | |
289 | ||
290 | #endif | |
1da177e4 LT |
291 | |
292 | static void (* r4k_blast_icache_page_indexed)(unsigned long addr); | |
293 | ||
078a55fc | 294 | static void r4k_blast_icache_page_indexed_setup(void) |
1da177e4 LT |
295 | { |
296 | unsigned long ic_lsize = cpu_icache_line_size(); | |
297 | ||
73f40352 CD |
298 | if (ic_lsize == 0) |
299 | r4k_blast_icache_page_indexed = (void *)cache_noop; | |
300 | else if (ic_lsize == 16) | |
1da177e4 LT |
301 | r4k_blast_icache_page_indexed = blast_icache16_page_indexed; |
302 | else if (ic_lsize == 32) { | |
02fe2c9c | 303 | if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) |
1da177e4 LT |
304 | r4k_blast_icache_page_indexed = |
305 | blast_icache32_r4600_v1_page_indexed; | |
02fe2c9c TS |
306 | else if (TX49XX_ICACHE_INDEX_INV_WAR) |
307 | r4k_blast_icache_page_indexed = | |
308 | tx49_blast_icache32_page_indexed; | |
43a06847 AK |
309 | else if (current_cpu_type() == CPU_LOONGSON2) |
310 | r4k_blast_icache_page_indexed = | |
311 | loongson2_blast_icache32_page_indexed; | |
1da177e4 LT |
312 | else |
313 | r4k_blast_icache_page_indexed = | |
314 | blast_icache32_page_indexed; | |
315 | } else if (ic_lsize == 64) | |
316 | r4k_blast_icache_page_indexed = blast_icache64_page_indexed; | |
317 | } | |
318 | ||
f2e3656d SL |
319 | void (* r4k_blast_icache)(void); |
320 | EXPORT_SYMBOL(r4k_blast_icache); | |
1da177e4 | 321 | |
078a55fc | 322 | static void r4k_blast_icache_setup(void) |
1da177e4 LT |
323 | { |
324 | unsigned long ic_lsize = cpu_icache_line_size(); | |
325 | ||
73f40352 CD |
326 | if (ic_lsize == 0) |
327 | r4k_blast_icache = (void *)cache_noop; | |
328 | else if (ic_lsize == 16) | |
1da177e4 LT |
329 | r4k_blast_icache = blast_icache16; |
330 | else if (ic_lsize == 32) { | |
331 | if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) | |
332 | r4k_blast_icache = blast_r4600_v1_icache32; | |
333 | else if (TX49XX_ICACHE_INDEX_INV_WAR) | |
334 | r4k_blast_icache = tx49_blast_icache32; | |
43a06847 AK |
335 | else if (current_cpu_type() == CPU_LOONGSON2) |
336 | r4k_blast_icache = loongson2_blast_icache32; | |
1da177e4 LT |
337 | else |
338 | r4k_blast_icache = blast_icache32; | |
339 | } else if (ic_lsize == 64) | |
340 | r4k_blast_icache = blast_icache64; | |
341 | } | |
342 | ||
343 | static void (* r4k_blast_scache_page)(unsigned long addr); | |
344 | ||
078a55fc | 345 | static void r4k_blast_scache_page_setup(void) |
1da177e4 LT |
346 | { |
347 | unsigned long sc_lsize = cpu_scache_line_size(); | |
348 | ||
4debe4f9 | 349 | if (scache_size == 0) |
73f40352 | 350 | r4k_blast_scache_page = (void *)cache_noop; |
4debe4f9 | 351 | else if (sc_lsize == 16) |
1da177e4 LT |
352 | r4k_blast_scache_page = blast_scache16_page; |
353 | else if (sc_lsize == 32) | |
354 | r4k_blast_scache_page = blast_scache32_page; | |
355 | else if (sc_lsize == 64) | |
356 | r4k_blast_scache_page = blast_scache64_page; | |
357 | else if (sc_lsize == 128) | |
358 | r4k_blast_scache_page = blast_scache128_page; | |
359 | } | |
360 | ||
361 | static void (* r4k_blast_scache_page_indexed)(unsigned long addr); | |
362 | ||
078a55fc | 363 | static void r4k_blast_scache_page_indexed_setup(void) |
1da177e4 LT |
364 | { |
365 | unsigned long sc_lsize = cpu_scache_line_size(); | |
366 | ||
4debe4f9 | 367 | if (scache_size == 0) |
73f40352 | 368 | r4k_blast_scache_page_indexed = (void *)cache_noop; |
4debe4f9 | 369 | else if (sc_lsize == 16) |
1da177e4 LT |
370 | r4k_blast_scache_page_indexed = blast_scache16_page_indexed; |
371 | else if (sc_lsize == 32) | |
372 | r4k_blast_scache_page_indexed = blast_scache32_page_indexed; | |
373 | else if (sc_lsize == 64) | |
374 | r4k_blast_scache_page_indexed = blast_scache64_page_indexed; | |
375 | else if (sc_lsize == 128) | |
376 | r4k_blast_scache_page_indexed = blast_scache128_page_indexed; | |
377 | } | |
378 | ||
379 | static void (* r4k_blast_scache)(void); | |
380 | ||
078a55fc | 381 | static void r4k_blast_scache_setup(void) |
1da177e4 LT |
382 | { |
383 | unsigned long sc_lsize = cpu_scache_line_size(); | |
384 | ||
4debe4f9 | 385 | if (scache_size == 0) |
73f40352 | 386 | r4k_blast_scache = (void *)cache_noop; |
4debe4f9 | 387 | else if (sc_lsize == 16) |
1da177e4 LT |
388 | r4k_blast_scache = blast_scache16; |
389 | else if (sc_lsize == 32) | |
390 | r4k_blast_scache = blast_scache32; | |
391 | else if (sc_lsize == 64) | |
392 | r4k_blast_scache = blast_scache64; | |
393 | else if (sc_lsize == 128) | |
394 | r4k_blast_scache = blast_scache128; | |
395 | } | |
396 | ||
1da177e4 LT |
397 | static inline void local_r4k___flush_cache_all(void * args) |
398 | { | |
10cc3529 | 399 | switch (current_cpu_type()) { |
14bd8c08 | 400 | case CPU_LOONGSON2: |
1da177e4 LT |
401 | case CPU_R4000SC: |
402 | case CPU_R4000MC: | |
403 | case CPU_R4400SC: | |
404 | case CPU_R4400MC: | |
405 | case CPU_R10000: | |
406 | case CPU_R12000: | |
44d921b2 | 407 | case CPU_R14000: |
14bd8c08 RB |
408 | /* |
409 | * These caches are inclusive caches, that is, if something | |
410 | * is not cached in the S-cache, we know it also won't be | |
411 | * in one of the primary caches. | |
412 | */ | |
1da177e4 | 413 | r4k_blast_scache(); |
14bd8c08 RB |
414 | break; |
415 | ||
416 | default: | |
417 | r4k_blast_dcache(); | |
418 | r4k_blast_icache(); | |
419 | break; | |
1da177e4 LT |
420 | } |
421 | } | |
422 | ||
423 | static void r4k___flush_cache_all(void) | |
424 | { | |
48a26e60 | 425 | r4k_on_each_cpu(local_r4k___flush_cache_all, NULL); |
1da177e4 LT |
426 | } |
427 | ||
a76ab5c1 RB |
428 | static inline int has_valid_asid(const struct mm_struct *mm) |
429 | { | |
430 | #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) | |
431 | int i; | |
432 | ||
433 | for_each_online_cpu(i) | |
434 | if (cpu_context(i, mm)) | |
435 | return 1; | |
436 | ||
437 | return 0; | |
438 | #else | |
439 | return cpu_context(smp_processor_id(), mm); | |
440 | #endif | |
441 | } | |
442 | ||
9c5a3d72 RB |
443 | static void r4k__flush_cache_vmap(void) |
444 | { | |
445 | r4k_blast_dcache(); | |
446 | } | |
447 | ||
448 | static void r4k__flush_cache_vunmap(void) | |
449 | { | |
450 | r4k_blast_dcache(); | |
451 | } | |
452 | ||
1da177e4 LT |
453 | static inline void local_r4k_flush_cache_range(void * args) |
454 | { | |
455 | struct vm_area_struct *vma = args; | |
2eaa7ec2 | 456 | int exec = vma->vm_flags & VM_EXEC; |
1da177e4 | 457 | |
a76ab5c1 | 458 | if (!(has_valid_asid(vma->vm_mm))) |
1da177e4 LT |
459 | return; |
460 | ||
0550d9d1 | 461 | r4k_blast_dcache(); |
2eaa7ec2 RB |
462 | if (exec) |
463 | r4k_blast_icache(); | |
1da177e4 LT |
464 | } |
465 | ||
466 | static void r4k_flush_cache_range(struct vm_area_struct *vma, | |
467 | unsigned long start, unsigned long end) | |
468 | { | |
2eaa7ec2 | 469 | int exec = vma->vm_flags & VM_EXEC; |
0550d9d1 | 470 | |
2eaa7ec2 | 471 | if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) |
48a26e60 | 472 | r4k_on_each_cpu(local_r4k_flush_cache_range, vma); |
1da177e4 LT |
473 | } |
474 | ||
475 | static inline void local_r4k_flush_cache_mm(void * args) | |
476 | { | |
477 | struct mm_struct *mm = args; | |
478 | ||
a76ab5c1 | 479 | if (!has_valid_asid(mm)) |
1da177e4 LT |
480 | return; |
481 | ||
1da177e4 LT |
482 | /* |
483 | * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we | |
484 | * only flush the primary caches but R10000 and R12000 behave sane ... | |
617667ba RB |
485 | * R4000SC and R4400SC indexed S-cache ops also invalidate primary |
486 | * caches, so we can bail out early. | |
1da177e4 | 487 | */ |
10cc3529 RB |
488 | if (current_cpu_type() == CPU_R4000SC || |
489 | current_cpu_type() == CPU_R4000MC || | |
490 | current_cpu_type() == CPU_R4400SC || | |
491 | current_cpu_type() == CPU_R4400MC) { | |
1da177e4 | 492 | r4k_blast_scache(); |
617667ba RB |
493 | return; |
494 | } | |
495 | ||
496 | r4k_blast_dcache(); | |
1da177e4 LT |
497 | } |
498 | ||
499 | static void r4k_flush_cache_mm(struct mm_struct *mm) | |
500 | { | |
501 | if (!cpu_has_dc_aliases) | |
502 | return; | |
503 | ||
48a26e60 | 504 | r4k_on_each_cpu(local_r4k_flush_cache_mm, mm); |
1da177e4 LT |
505 | } |
506 | ||
507 | struct flush_cache_page_args { | |
508 | struct vm_area_struct *vma; | |
6ec25809 | 509 | unsigned long addr; |
de62893b | 510 | unsigned long pfn; |
1da177e4 LT |
511 | }; |
512 | ||
513 | static inline void local_r4k_flush_cache_page(void *args) | |
514 | { | |
515 | struct flush_cache_page_args *fcp_args = args; | |
516 | struct vm_area_struct *vma = fcp_args->vma; | |
6ec25809 | 517 | unsigned long addr = fcp_args->addr; |
db813fe5 | 518 | struct page *page = pfn_to_page(fcp_args->pfn); |
1da177e4 LT |
519 | int exec = vma->vm_flags & VM_EXEC; |
520 | struct mm_struct *mm = vma->vm_mm; | |
c9c5023d | 521 | int map_coherent = 0; |
1da177e4 | 522 | pgd_t *pgdp; |
c6e8b587 | 523 | pud_t *pudp; |
1da177e4 LT |
524 | pmd_t *pmdp; |
525 | pte_t *ptep; | |
db813fe5 | 526 | void *vaddr; |
1da177e4 | 527 | |
79acf83e RB |
528 | /* |
529 | * If ownes no valid ASID yet, cannot possibly have gotten | |
530 | * this page into the cache. | |
531 | */ | |
a76ab5c1 | 532 | if (!has_valid_asid(mm)) |
79acf83e RB |
533 | return; |
534 | ||
6ec25809 RB |
535 | addr &= PAGE_MASK; |
536 | pgdp = pgd_offset(mm, addr); | |
537 | pudp = pud_offset(pgdp, addr); | |
538 | pmdp = pmd_offset(pudp, addr); | |
539 | ptep = pte_offset(pmdp, addr); | |
1da177e4 LT |
540 | |
541 | /* | |
542 | * If the page isn't marked valid, the page cannot possibly be | |
543 | * in the cache. | |
544 | */ | |
526af35e | 545 | if (!(pte_present(*ptep))) |
1da177e4 LT |
546 | return; |
547 | ||
db813fe5 RB |
548 | if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) |
549 | vaddr = NULL; | |
550 | else { | |
551 | /* | |
552 | * Use kmap_coherent or kmap_atomic to do flushes for | |
553 | * another ASID than the current one. | |
554 | */ | |
c9c5023d RB |
555 | map_coherent = (cpu_has_dc_aliases && |
556 | page_mapped(page) && !Page_dcache_dirty(page)); | |
557 | if (map_coherent) | |
db813fe5 RB |
558 | vaddr = kmap_coherent(page, addr); |
559 | else | |
9c02048f | 560 | vaddr = kmap_atomic(page); |
db813fe5 | 561 | addr = (unsigned long)vaddr; |
1da177e4 LT |
562 | } |
563 | ||
1da177e4 | 564 | if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { |
db813fe5 | 565 | r4k_blast_dcache_page(addr); |
39b8d525 RB |
566 | if (exec && !cpu_icache_snoops_remote_store) |
567 | r4k_blast_scache_page(addr); | |
1da177e4 LT |
568 | } |
569 | if (exec) { | |
db813fe5 | 570 | if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) { |
1da177e4 LT |
571 | int cpu = smp_processor_id(); |
572 | ||
26a51b27 TS |
573 | if (cpu_context(cpu, mm) != 0) |
574 | drop_mmu_context(mm, cpu); | |
1da177e4 | 575 | } else |
db813fe5 RB |
576 | r4k_blast_icache_page(addr); |
577 | } | |
578 | ||
579 | if (vaddr) { | |
c9c5023d | 580 | if (map_coherent) |
db813fe5 RB |
581 | kunmap_coherent(); |
582 | else | |
9c02048f | 583 | kunmap_atomic(vaddr); |
1da177e4 LT |
584 | } |
585 | } | |
586 | ||
6ec25809 RB |
587 | static void r4k_flush_cache_page(struct vm_area_struct *vma, |
588 | unsigned long addr, unsigned long pfn) | |
1da177e4 LT |
589 | { |
590 | struct flush_cache_page_args args; | |
591 | ||
1da177e4 | 592 | args.vma = vma; |
6ec25809 | 593 | args.addr = addr; |
de62893b | 594 | args.pfn = pfn; |
1da177e4 | 595 | |
48a26e60 | 596 | r4k_on_each_cpu(local_r4k_flush_cache_page, &args); |
1da177e4 LT |
597 | } |
598 | ||
599 | static inline void local_r4k_flush_data_cache_page(void * addr) | |
600 | { | |
601 | r4k_blast_dcache_page((unsigned long) addr); | |
602 | } | |
603 | ||
604 | static void r4k_flush_data_cache_page(unsigned long addr) | |
605 | { | |
a754f708 RB |
606 | if (in_atomic()) |
607 | local_r4k_flush_data_cache_page((void *)addr); | |
608 | else | |
48a26e60 | 609 | r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr); |
1da177e4 LT |
610 | } |
611 | ||
612 | struct flush_icache_range_args { | |
d4264f18 AN |
613 | unsigned long start; |
614 | unsigned long end; | |
1da177e4 LT |
615 | }; |
616 | ||
e0cee3ee | 617 | static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end) |
1da177e4 | 618 | { |
1da177e4 | 619 | if (!cpu_has_ic_fills_f_dc) { |
73f40352 | 620 | if (end - start >= dcache_size) { |
1da177e4 LT |
621 | r4k_blast_dcache(); |
622 | } else { | |
10a3dabd | 623 | R4600_HIT_CACHEOP_WAR_IMPL; |
41700e73 | 624 | protected_blast_dcache_range(start, end); |
1da177e4 | 625 | } |
1da177e4 LT |
626 | } |
627 | ||
628 | if (end - start > icache_size) | |
629 | r4k_blast_icache(); | |
14bd8c08 RB |
630 | else { |
631 | switch (boot_cpu_type()) { | |
632 | case CPU_LOONGSON2: | |
bad009fe | 633 | protected_loongson2_blast_icache_range(start, end); |
14bd8c08 RB |
634 | break; |
635 | ||
636 | default: | |
bad009fe | 637 | protected_blast_icache_range(start, end); |
14bd8c08 RB |
638 | break; |
639 | } | |
640 | } | |
1da177e4 LT |
641 | } |
642 | ||
e0cee3ee TB |
643 | static inline void local_r4k_flush_icache_range_ipi(void *args) |
644 | { | |
645 | struct flush_icache_range_args *fir_args = args; | |
646 | unsigned long start = fir_args->start; | |
647 | unsigned long end = fir_args->end; | |
648 | ||
649 | local_r4k_flush_icache_range(start, end); | |
650 | } | |
651 | ||
d4264f18 | 652 | static void r4k_flush_icache_range(unsigned long start, unsigned long end) |
1da177e4 LT |
653 | { |
654 | struct flush_icache_range_args args; | |
655 | ||
656 | args.start = start; | |
657 | args.end = end; | |
658 | ||
48a26e60 | 659 | r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args); |
cc61c1fe | 660 | instruction_hazard(); |
1da177e4 LT |
661 | } |
662 | ||
1da177e4 LT |
663 | #ifdef CONFIG_DMA_NONCOHERENT |
664 | ||
665 | static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) | |
666 | { | |
1da177e4 LT |
667 | /* Catch bad driver code */ |
668 | BUG_ON(size == 0); | |
669 | ||
ff522058 | 670 | preempt_disable(); |
fc5d2d27 | 671 | if (cpu_has_inclusive_pcaches) { |
41700e73 | 672 | if (size >= scache_size) |
1da177e4 | 673 | r4k_blast_scache(); |
41700e73 AN |
674 | else |
675 | blast_scache_range(addr, addr + size); | |
5596b0b2 | 676 | preempt_enable(); |
d0023c4a | 677 | __sync(); |
1da177e4 LT |
678 | return; |
679 | } | |
680 | ||
681 | /* | |
682 | * Either no secondary cache or the available caches don't have the | |
683 | * subset property so we have to flush the primary caches | |
684 | * explicitly | |
685 | */ | |
39b8d525 | 686 | if (cpu_has_safe_index_cacheops && size >= dcache_size) { |
1da177e4 LT |
687 | r4k_blast_dcache(); |
688 | } else { | |
1da177e4 | 689 | R4600_HIT_CACHEOP_WAR_IMPL; |
41700e73 | 690 | blast_dcache_range(addr, addr + size); |
1da177e4 | 691 | } |
ff522058 | 692 | preempt_enable(); |
1da177e4 LT |
693 | |
694 | bc_wback_inv(addr, size); | |
d0023c4a | 695 | __sync(); |
1da177e4 LT |
696 | } |
697 | ||
698 | static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) | |
699 | { | |
1da177e4 LT |
700 | /* Catch bad driver code */ |
701 | BUG_ON(size == 0); | |
702 | ||
ff522058 | 703 | preempt_disable(); |
fc5d2d27 | 704 | if (cpu_has_inclusive_pcaches) { |
41700e73 | 705 | if (size >= scache_size) |
1da177e4 | 706 | r4k_blast_scache(); |
a8ca8b64 | 707 | else { |
a8ca8b64 RB |
708 | /* |
709 | * There is no clearly documented alignment requirement | |
710 | * for the cache instruction on MIPS processors and | |
711 | * some processors, among them the RM5200 and RM7000 | |
712 | * QED processors will throw an address error for cache | |
70342287 | 713 | * hit ops with insufficient alignment. Solved by |
a8ca8b64 RB |
714 | * aligning the address to cache line size. |
715 | */ | |
e9c33572 | 716 | blast_inv_scache_range(addr, addr + size); |
a8ca8b64 | 717 | } |
5596b0b2 | 718 | preempt_enable(); |
d0023c4a | 719 | __sync(); |
1da177e4 LT |
720 | return; |
721 | } | |
722 | ||
39b8d525 | 723 | if (cpu_has_safe_index_cacheops && size >= dcache_size) { |
1da177e4 LT |
724 | r4k_blast_dcache(); |
725 | } else { | |
1da177e4 | 726 | R4600_HIT_CACHEOP_WAR_IMPL; |
e9c33572 | 727 | blast_inv_dcache_range(addr, addr + size); |
1da177e4 | 728 | } |
ff522058 | 729 | preempt_enable(); |
1da177e4 LT |
730 | |
731 | bc_inv(addr, size); | |
d0023c4a | 732 | __sync(); |
1da177e4 LT |
733 | } |
734 | #endif /* CONFIG_DMA_NONCOHERENT */ | |
735 | ||
736 | /* | |
737 | * While we're protected against bad userland addresses we don't care | |
738 | * very much about what happens in that case. Usually a segmentation | |
739 | * fault will dump the process later on anyway ... | |
740 | */ | |
741 | static void local_r4k_flush_cache_sigtramp(void * arg) | |
742 | { | |
02fe2c9c TS |
743 | unsigned long ic_lsize = cpu_icache_line_size(); |
744 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
745 | unsigned long sc_lsize = cpu_scache_line_size(); | |
1da177e4 LT |
746 | unsigned long addr = (unsigned long) arg; |
747 | ||
748 | R4600_HIT_CACHEOP_WAR_IMPL; | |
73f40352 CD |
749 | if (dc_lsize) |
750 | protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); | |
4debe4f9 | 751 | if (!cpu_icache_snoops_remote_store && scache_size) |
1da177e4 | 752 | protected_writeback_scache_line(addr & ~(sc_lsize - 1)); |
73f40352 CD |
753 | if (ic_lsize) |
754 | protected_flush_icache_line(addr & ~(ic_lsize - 1)); | |
1da177e4 LT |
755 | if (MIPS4K_ICACHE_REFILL_WAR) { |
756 | __asm__ __volatile__ ( | |
757 | ".set push\n\t" | |
758 | ".set noat\n\t" | |
759 | ".set mips3\n\t" | |
875d43e7 | 760 | #ifdef CONFIG_32BIT |
1da177e4 LT |
761 | "la $at,1f\n\t" |
762 | #endif | |
875d43e7 | 763 | #ifdef CONFIG_64BIT |
1da177e4 LT |
764 | "dla $at,1f\n\t" |
765 | #endif | |
766 | "cache %0,($at)\n\t" | |
767 | "nop; nop; nop\n" | |
768 | "1:\n\t" | |
769 | ".set pop" | |
770 | : | |
771 | : "i" (Hit_Invalidate_I)); | |
772 | } | |
773 | if (MIPS_CACHE_SYNC_WAR) | |
774 | __asm__ __volatile__ ("sync"); | |
775 | } | |
776 | ||
777 | static void r4k_flush_cache_sigtramp(unsigned long addr) | |
778 | { | |
48a26e60 | 779 | r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr); |
1da177e4 LT |
780 | } |
781 | ||
782 | static void r4k_flush_icache_all(void) | |
783 | { | |
784 | if (cpu_has_vtag_icache) | |
785 | r4k_blast_icache(); | |
786 | } | |
787 | ||
d9cdc901 RB |
788 | struct flush_kernel_vmap_range_args { |
789 | unsigned long vaddr; | |
790 | int size; | |
791 | }; | |
792 | ||
793 | static inline void local_r4k_flush_kernel_vmap_range(void *args) | |
794 | { | |
795 | struct flush_kernel_vmap_range_args *vmra = args; | |
796 | unsigned long vaddr = vmra->vaddr; | |
797 | int size = vmra->size; | |
798 | ||
799 | /* | |
800 | * Aliases only affect the primary caches so don't bother with | |
801 | * S-caches or T-caches. | |
802 | */ | |
803 | if (cpu_has_safe_index_cacheops && size >= dcache_size) | |
804 | r4k_blast_dcache(); | |
805 | else { | |
806 | R4600_HIT_CACHEOP_WAR_IMPL; | |
807 | blast_dcache_range(vaddr, vaddr + size); | |
808 | } | |
809 | } | |
810 | ||
811 | static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size) | |
812 | { | |
813 | struct flush_kernel_vmap_range_args args; | |
814 | ||
815 | args.vaddr = (unsigned long) vaddr; | |
816 | args.size = size; | |
817 | ||
818 | r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range, &args); | |
819 | } | |
820 | ||
1da177e4 LT |
821 | static inline void rm7k_erratum31(void) |
822 | { | |
823 | const unsigned long ic_lsize = 32; | |
824 | unsigned long addr; | |
825 | ||
826 | /* RM7000 erratum #31. The icache is screwed at startup. */ | |
827 | write_c0_taglo(0); | |
828 | write_c0_taghi(0); | |
829 | ||
830 | for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) { | |
831 | __asm__ __volatile__ ( | |
d8748a3a | 832 | ".set push\n\t" |
1da177e4 LT |
833 | ".set noreorder\n\t" |
834 | ".set mips3\n\t" | |
835 | "cache\t%1, 0(%0)\n\t" | |
836 | "cache\t%1, 0x1000(%0)\n\t" | |
837 | "cache\t%1, 0x2000(%0)\n\t" | |
838 | "cache\t%1, 0x3000(%0)\n\t" | |
839 | "cache\t%2, 0(%0)\n\t" | |
840 | "cache\t%2, 0x1000(%0)\n\t" | |
841 | "cache\t%2, 0x2000(%0)\n\t" | |
842 | "cache\t%2, 0x3000(%0)\n\t" | |
843 | "cache\t%1, 0(%0)\n\t" | |
844 | "cache\t%1, 0x1000(%0)\n\t" | |
845 | "cache\t%1, 0x2000(%0)\n\t" | |
846 | "cache\t%1, 0x3000(%0)\n\t" | |
d8748a3a | 847 | ".set pop\n" |
1da177e4 LT |
848 | : |
849 | : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill)); | |
850 | } | |
851 | } | |
852 | ||
006a851b SH |
853 | static inline void alias_74k_erratum(struct cpuinfo_mips *c) |
854 | { | |
9213ad77 MR |
855 | unsigned int imp = c->processor_id & PRID_IMP_MASK; |
856 | unsigned int rev = c->processor_id & PRID_REV_MASK; | |
857 | ||
006a851b SH |
858 | /* |
859 | * Early versions of the 74K do not update the cache tags on a | |
860 | * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG | |
861 | * aliases. In this case it is better to treat the cache as always | |
862 | * having aliases. | |
863 | */ | |
9213ad77 MR |
864 | switch (imp) { |
865 | case PRID_IMP_74K: | |
866 | if (rev <= PRID_REV_ENCODE_332(2, 4, 0)) | |
867 | c->dcache.flags |= MIPS_CACHE_VTAG; | |
868 | if (rev == PRID_REV_ENCODE_332(2, 4, 0)) | |
869 | write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); | |
870 | break; | |
871 | case PRID_IMP_1074K: | |
872 | if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) { | |
873 | c->dcache.flags |= MIPS_CACHE_VTAG; | |
874 | write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); | |
875 | } | |
876 | break; | |
877 | default: | |
878 | BUG(); | |
006a851b SH |
879 | } |
880 | } | |
881 | ||
078a55fc | 882 | static char *way_string[] = { NULL, "direct mapped", "2-way", |
1da177e4 LT |
883 | "3-way", "4-way", "5-way", "6-way", "7-way", "8-way" |
884 | }; | |
885 | ||
078a55fc | 886 | static void probe_pcache(void) |
1da177e4 LT |
887 | { |
888 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
889 | unsigned int config = read_c0_config(); | |
890 | unsigned int prid = read_c0_prid(); | |
891 | unsigned long config1; | |
892 | unsigned int lsize; | |
893 | ||
69f24d17 | 894 | switch (current_cpu_type()) { |
1da177e4 LT |
895 | case CPU_R4600: /* QED style two way caches? */ |
896 | case CPU_R4700: | |
897 | case CPU_R5000: | |
898 | case CPU_NEVADA: | |
899 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
900 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
901 | c->icache.ways = 2; | |
3c68da79 | 902 | c->icache.waybit = __ffs(icache_size/2); |
1da177e4 LT |
903 | |
904 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
905 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
906 | c->dcache.ways = 2; | |
3c68da79 | 907 | c->dcache.waybit= __ffs(dcache_size/2); |
1da177e4 LT |
908 | |
909 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
910 | break; | |
911 | ||
912 | case CPU_R5432: | |
913 | case CPU_R5500: | |
914 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
915 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
916 | c->icache.ways = 2; | |
917 | c->icache.waybit= 0; | |
918 | ||
919 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
920 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
921 | c->dcache.ways = 2; | |
922 | c->dcache.waybit = 0; | |
923 | ||
5864810b | 924 | c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH; |
1da177e4 LT |
925 | break; |
926 | ||
927 | case CPU_TX49XX: | |
928 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
929 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
930 | c->icache.ways = 4; | |
931 | c->icache.waybit= 0; | |
932 | ||
933 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
934 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
935 | c->dcache.ways = 4; | |
936 | c->dcache.waybit = 0; | |
937 | ||
938 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
de862b48 | 939 | c->options |= MIPS_CPU_PREFETCH; |
1da177e4 LT |
940 | break; |
941 | ||
942 | case CPU_R4000PC: | |
943 | case CPU_R4000SC: | |
944 | case CPU_R4000MC: | |
945 | case CPU_R4400PC: | |
946 | case CPU_R4400SC: | |
947 | case CPU_R4400MC: | |
948 | case CPU_R4300: | |
949 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
950 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
951 | c->icache.ways = 1; | |
70342287 | 952 | c->icache.waybit = 0; /* doesn't matter */ |
1da177e4 LT |
953 | |
954 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
955 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
956 | c->dcache.ways = 1; | |
957 | c->dcache.waybit = 0; /* does not matter */ | |
958 | ||
959 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
960 | break; | |
961 | ||
962 | case CPU_R10000: | |
963 | case CPU_R12000: | |
44d921b2 | 964 | case CPU_R14000: |
1da177e4 LT |
965 | icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29)); |
966 | c->icache.linesz = 64; | |
967 | c->icache.ways = 2; | |
968 | c->icache.waybit = 0; | |
969 | ||
970 | dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26)); | |
971 | c->dcache.linesz = 32; | |
972 | c->dcache.ways = 2; | |
973 | c->dcache.waybit = 0; | |
974 | ||
975 | c->options |= MIPS_CPU_PREFETCH; | |
976 | break; | |
977 | ||
978 | case CPU_VR4133: | |
2874fe55 | 979 | write_c0_config(config & ~VR41_CONF_P4K); |
1da177e4 LT |
980 | case CPU_VR4131: |
981 | /* Workaround for cache instruction bug of VR4131 */ | |
982 | if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || | |
983 | c->processor_id == 0x0c82U) { | |
4e8ab361 YY |
984 | config |= 0x00400000U; |
985 | if (c->processor_id == 0x0c80U) | |
986 | config |= VR41_CONF_BP; | |
1da177e4 | 987 | write_c0_config(config); |
1058ecda YY |
988 | } else |
989 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
990 | ||
1da177e4 LT |
991 | icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); |
992 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
993 | c->icache.ways = 2; | |
3c68da79 | 994 | c->icache.waybit = __ffs(icache_size/2); |
1da177e4 LT |
995 | |
996 | dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); | |
997 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
998 | c->dcache.ways = 2; | |
3c68da79 | 999 | c->dcache.waybit = __ffs(dcache_size/2); |
1da177e4 LT |
1000 | break; |
1001 | ||
1002 | case CPU_VR41XX: | |
1003 | case CPU_VR4111: | |
1004 | case CPU_VR4121: | |
1005 | case CPU_VR4122: | |
1006 | case CPU_VR4181: | |
1007 | case CPU_VR4181A: | |
1008 | icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); | |
1009 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
1010 | c->icache.ways = 1; | |
70342287 | 1011 | c->icache.waybit = 0; /* doesn't matter */ |
1da177e4 LT |
1012 | |
1013 | dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); | |
1014 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
1015 | c->dcache.ways = 1; | |
1016 | c->dcache.waybit = 0; /* does not matter */ | |
1017 | ||
1018 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
1019 | break; | |
1020 | ||
1021 | case CPU_RM7000: | |
1022 | rm7k_erratum31(); | |
1023 | ||
1da177e4 LT |
1024 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); |
1025 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
1026 | c->icache.ways = 4; | |
3c68da79 | 1027 | c->icache.waybit = __ffs(icache_size / c->icache.ways); |
1da177e4 LT |
1028 | |
1029 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
1030 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
1031 | c->dcache.ways = 4; | |
3c68da79 | 1032 | c->dcache.waybit = __ffs(dcache_size / c->dcache.ways); |
1da177e4 | 1033 | |
1da177e4 | 1034 | c->options |= MIPS_CPU_CACHE_CDEX_P; |
1da177e4 LT |
1035 | c->options |= MIPS_CPU_PREFETCH; |
1036 | break; | |
1037 | ||
2a21c730 FZ |
1038 | case CPU_LOONGSON2: |
1039 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
1040 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
1041 | if (prid & 0x3) | |
1042 | c->icache.ways = 4; | |
1043 | else | |
1044 | c->icache.ways = 2; | |
1045 | c->icache.waybit = 0; | |
1046 | ||
1047 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
1048 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
1049 | if (prid & 0x3) | |
1050 | c->dcache.ways = 4; | |
1051 | else | |
1052 | c->dcache.ways = 2; | |
1053 | c->dcache.waybit = 0; | |
1054 | break; | |
1055 | ||
1da177e4 LT |
1056 | default: |
1057 | if (!(config & MIPS_CONF_M)) | |
1058 | panic("Don't know how to probe P-caches on this cpu."); | |
1059 | ||
1060 | /* | |
1061 | * So we seem to be a MIPS32 or MIPS64 CPU | |
1062 | * So let's probe the I-cache ... | |
1063 | */ | |
1064 | config1 = read_c0_config1(); | |
1065 | ||
175cba8c MC |
1066 | lsize = (config1 >> 19) & 7; |
1067 | ||
1068 | /* IL == 7 is reserved */ | |
1069 | if (lsize == 7) | |
1070 | panic("Invalid icache line size"); | |
1071 | ||
1072 | c->icache.linesz = lsize ? 2 << lsize : 0; | |
1073 | ||
dc34b05f | 1074 | c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); |
1da177e4 LT |
1075 | c->icache.ways = 1 + ((config1 >> 16) & 7); |
1076 | ||
1077 | icache_size = c->icache.sets * | |
70342287 RB |
1078 | c->icache.ways * |
1079 | c->icache.linesz; | |
3c68da79 | 1080 | c->icache.waybit = __ffs(icache_size/c->icache.ways); |
1da177e4 LT |
1081 | |
1082 | if (config & 0x8) /* VI bit */ | |
1083 | c->icache.flags |= MIPS_CACHE_VTAG; | |
1084 | ||
1085 | /* | |
1086 | * Now probe the MIPS32 / MIPS64 data cache. | |
1087 | */ | |
1088 | c->dcache.flags = 0; | |
1089 | ||
175cba8c MC |
1090 | lsize = (config1 >> 10) & 7; |
1091 | ||
1092 | /* DL == 7 is reserved */ | |
1093 | if (lsize == 7) | |
1094 | panic("Invalid dcache line size"); | |
1095 | ||
1096 | c->dcache.linesz = lsize ? 2 << lsize : 0; | |
1097 | ||
dc34b05f | 1098 | c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); |
1da177e4 LT |
1099 | c->dcache.ways = 1 + ((config1 >> 7) & 7); |
1100 | ||
1101 | dcache_size = c->dcache.sets * | |
70342287 RB |
1102 | c->dcache.ways * |
1103 | c->dcache.linesz; | |
3c68da79 | 1104 | c->dcache.waybit = __ffs(dcache_size/c->dcache.ways); |
1da177e4 LT |
1105 | |
1106 | c->options |= MIPS_CPU_PREFETCH; | |
1107 | break; | |
1108 | } | |
1109 | ||
1110 | /* | |
1111 | * Processor configuration sanity check for the R4000SC erratum | |
70342287 | 1112 | * #5. With page sizes larger than 32kB there is no possibility |
1da177e4 LT |
1113 | * to get a VCE exception anymore so we don't care about this |
1114 | * misconfiguration. The case is rather theoretical anyway; | |
1115 | * presumably no vendor is shipping his hardware in the "bad" | |
1116 | * configuration. | |
1117 | */ | |
8ff374b9 MR |
1118 | if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 && |
1119 | (prid & PRID_REV_MASK) < PRID_REV_R4400 && | |
1da177e4 LT |
1120 | !(config & CONF_SC) && c->icache.linesz != 16 && |
1121 | PAGE_SIZE <= 0x8000) | |
1122 | panic("Improper R4000SC processor configuration detected"); | |
1123 | ||
1124 | /* compute a couple of other cache variables */ | |
1125 | c->icache.waysize = icache_size / c->icache.ways; | |
1126 | c->dcache.waysize = dcache_size / c->dcache.ways; | |
1127 | ||
73f40352 CD |
1128 | c->icache.sets = c->icache.linesz ? |
1129 | icache_size / (c->icache.linesz * c->icache.ways) : 0; | |
1130 | c->dcache.sets = c->dcache.linesz ? | |
1131 | dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; | |
1da177e4 LT |
1132 | |
1133 | /* | |
1134 | * R10000 and R12000 P-caches are odd in a positive way. They're 32kB | |
1135 | * 2-way virtually indexed so normally would suffer from aliases. So | |
1136 | * normally they'd suffer from aliases but magic in the hardware deals | |
1137 | * with that for us so we don't need to take care ourselves. | |
1138 | */ | |
69f24d17 | 1139 | switch (current_cpu_type()) { |
a95970f3 | 1140 | case CPU_20KC: |
505403b6 | 1141 | case CPU_25KF: |
641e97f3 RB |
1142 | case CPU_SB1: |
1143 | case CPU_SB1A: | |
efa0f81c | 1144 | case CPU_XLR: |
de62893b | 1145 | c->dcache.flags |= MIPS_CACHE_PINDEX; |
641e97f3 RB |
1146 | break; |
1147 | ||
d1e344e5 RB |
1148 | case CPU_R10000: |
1149 | case CPU_R12000: | |
44d921b2 | 1150 | case CPU_R14000: |
d1e344e5 | 1151 | break; |
641e97f3 | 1152 | |
113c62d9 | 1153 | case CPU_M14KC: |
f8fa4811 | 1154 | case CPU_M14KEC: |
d1e344e5 | 1155 | case CPU_24K: |
98a41de9 | 1156 | case CPU_34K: |
2e78ae3f | 1157 | case CPU_74K: |
39b8d525 | 1158 | case CPU_1004K: |
442e14a2 | 1159 | case CPU_1074K: |
26ab96df | 1160 | case CPU_INTERAPTIV: |
aced4cbd | 1161 | case CPU_P5600: |
708ac4b8 | 1162 | case CPU_PROAPTIV: |
442e14a2 | 1163 | if ((c->cputype == CPU_74K) || (c->cputype == CPU_1074K)) |
006a851b | 1164 | alias_74k_erratum(c); |
02dc6bfb MC |
1165 | if (!(read_c0_config7() & MIPS_CONF7_IAR) && |
1166 | (c->icache.waysize > PAGE_SIZE)) | |
1167 | c->icache.flags |= MIPS_CACHE_ALIASES; | |
1168 | if (read_c0_config7() & MIPS_CONF7_AR) { | |
1169 | /* | |
1170 | * Effectively physically indexed dcache, | |
1171 | * thus no virtual aliases. | |
1172 | */ | |
beab375a RB |
1173 | c->dcache.flags |= MIPS_CACHE_PINDEX; |
1174 | break; | |
1175 | } | |
d1e344e5 | 1176 | default: |
beab375a RB |
1177 | if (c->dcache.waysize > PAGE_SIZE) |
1178 | c->dcache.flags |= MIPS_CACHE_ALIASES; | |
d1e344e5 | 1179 | } |
1da177e4 | 1180 | |
69f24d17 | 1181 | switch (current_cpu_type()) { |
1da177e4 LT |
1182 | case CPU_20KC: |
1183 | /* | |
1184 | * Some older 20Kc chips doesn't have the 'VI' bit in | |
1185 | * the config register. | |
1186 | */ | |
1187 | c->icache.flags |= MIPS_CACHE_VTAG; | |
1188 | break; | |
1189 | ||
270717a8 | 1190 | case CPU_ALCHEMY: |
1da177e4 LT |
1191 | c->icache.flags |= MIPS_CACHE_IC_F_DC; |
1192 | break; | |
1da177e4 | 1193 | |
14bd8c08 RB |
1194 | case CPU_LOONGSON2: |
1195 | /* | |
1196 | * LOONGSON2 has 4 way icache, but when using indexed cache op, | |
1197 | * one op will act on all 4 ways | |
1198 | */ | |
1199 | c->icache.ways = 1; | |
1200 | } | |
2a21c730 | 1201 | |
1da177e4 LT |
1202 | printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", |
1203 | icache_size >> 10, | |
7fc7316a | 1204 | c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", |
1da177e4 LT |
1205 | way_string[c->icache.ways], c->icache.linesz); |
1206 | ||
64bfca5c RB |
1207 | printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", |
1208 | dcache_size >> 10, way_string[c->dcache.ways], | |
1209 | (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT", | |
1210 | (c->dcache.flags & MIPS_CACHE_ALIASES) ? | |
1211 | "cache aliases" : "no aliases", | |
1212 | c->dcache.linesz); | |
1da177e4 LT |
1213 | } |
1214 | ||
1215 | /* | |
1216 | * If you even _breathe_ on this function, look at the gcc output and make sure | |
1217 | * it does not pop things on and off the stack for the cache sizing loop that | |
1218 | * executes in KSEG1 space or else you will crash and burn badly. You have | |
1219 | * been warned. | |
1220 | */ | |
078a55fc | 1221 | static int probe_scache(void) |
1da177e4 | 1222 | { |
1da177e4 LT |
1223 | unsigned long flags, addr, begin, end, pow2; |
1224 | unsigned int config = read_c0_config(); | |
1225 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1da177e4 LT |
1226 | |
1227 | if (config & CONF_SC) | |
1228 | return 0; | |
1229 | ||
e001e528 | 1230 | begin = (unsigned long) &_stext; |
1da177e4 LT |
1231 | begin &= ~((4 * 1024 * 1024) - 1); |
1232 | end = begin + (4 * 1024 * 1024); | |
1233 | ||
1234 | /* | |
1235 | * This is such a bitch, you'd think they would make it easy to do | |
1236 | * this. Away you daemons of stupidity! | |
1237 | */ | |
1238 | local_irq_save(flags); | |
1239 | ||
1240 | /* Fill each size-multiple cache line with a valid tag. */ | |
1241 | pow2 = (64 * 1024); | |
1242 | for (addr = begin; addr < end; addr = (begin + pow2)) { | |
1243 | unsigned long *p = (unsigned long *) addr; | |
1244 | __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */ | |
1245 | pow2 <<= 1; | |
1246 | } | |
1247 | ||
1248 | /* Load first line with zero (therefore invalid) tag. */ | |
1249 | write_c0_taglo(0); | |
1250 | write_c0_taghi(0); | |
1251 | __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */ | |
1252 | cache_op(Index_Store_Tag_I, begin); | |
1253 | cache_op(Index_Store_Tag_D, begin); | |
1254 | cache_op(Index_Store_Tag_SD, begin); | |
1255 | ||
1256 | /* Now search for the wrap around point. */ | |
1257 | pow2 = (128 * 1024); | |
1da177e4 LT |
1258 | for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) { |
1259 | cache_op(Index_Load_Tag_SD, addr); | |
1260 | __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */ | |
1261 | if (!read_c0_taglo()) | |
1262 | break; | |
1263 | pow2 <<= 1; | |
1264 | } | |
1265 | local_irq_restore(flags); | |
1266 | addr -= begin; | |
1267 | ||
1268 | scache_size = addr; | |
1269 | c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22); | |
1270 | c->scache.ways = 1; | |
1271 | c->dcache.waybit = 0; /* does not matter */ | |
1272 | ||
1273 | return 1; | |
1274 | } | |
1275 | ||
2a21c730 FZ |
1276 | static void __init loongson2_sc_init(void) |
1277 | { | |
1278 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1279 | ||
1280 | scache_size = 512*1024; | |
1281 | c->scache.linesz = 32; | |
1282 | c->scache.ways = 4; | |
1283 | c->scache.waybit = 0; | |
1284 | c->scache.waysize = scache_size / (c->scache.ways); | |
1285 | c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); | |
1286 | pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", | |
1287 | scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); | |
1288 | ||
1289 | c->options |= MIPS_CPU_INCLUSIVE_CACHES; | |
1290 | } | |
2a21c730 | 1291 | |
1da177e4 LT |
1292 | extern int r5k_sc_init(void); |
1293 | extern int rm7k_sc_init(void); | |
9318c51a | 1294 | extern int mips_sc_init(void); |
1da177e4 | 1295 | |
078a55fc | 1296 | static void setup_scache(void) |
1da177e4 LT |
1297 | { |
1298 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1299 | unsigned int config = read_c0_config(); | |
1da177e4 LT |
1300 | int sc_present = 0; |
1301 | ||
1302 | /* | |
1303 | * Do the probing thing on R4000SC and R4400SC processors. Other | |
1304 | * processors don't have a S-cache that would be relevant to the | |
603e82ed | 1305 | * Linux memory management. |
1da177e4 | 1306 | */ |
69f24d17 | 1307 | switch (current_cpu_type()) { |
1da177e4 LT |
1308 | case CPU_R4000SC: |
1309 | case CPU_R4000MC: | |
1310 | case CPU_R4400SC: | |
1311 | case CPU_R4400MC: | |
ba5187db | 1312 | sc_present = run_uncached(probe_scache); |
1da177e4 LT |
1313 | if (sc_present) |
1314 | c->options |= MIPS_CPU_CACHE_CDEX_S; | |
1315 | break; | |
1316 | ||
1317 | case CPU_R10000: | |
1318 | case CPU_R12000: | |
44d921b2 | 1319 | case CPU_R14000: |
1da177e4 LT |
1320 | scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16); |
1321 | c->scache.linesz = 64 << ((config >> 13) & 1); | |
1322 | c->scache.ways = 2; | |
1323 | c->scache.waybit= 0; | |
1324 | sc_present = 1; | |
1325 | break; | |
1326 | ||
1327 | case CPU_R5000: | |
1328 | case CPU_NEVADA: | |
1329 | #ifdef CONFIG_R5000_CPU_SCACHE | |
1330 | r5k_sc_init(); | |
1331 | #endif | |
70342287 | 1332 | return; |
1da177e4 LT |
1333 | |
1334 | case CPU_RM7000: | |
1da177e4 LT |
1335 | #ifdef CONFIG_RM7000_CPU_SCACHE |
1336 | rm7k_sc_init(); | |
1337 | #endif | |
1338 | return; | |
1339 | ||
2a21c730 FZ |
1340 | case CPU_LOONGSON2: |
1341 | loongson2_sc_init(); | |
1342 | return; | |
14bd8c08 | 1343 | |
a3d4fb2d J |
1344 | case CPU_XLP: |
1345 | /* don't need to worry about L2, fully coherent */ | |
1346 | return; | |
2a21c730 | 1347 | |
1da177e4 | 1348 | default: |
adb37892 DCZ |
1349 | if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | |
1350 | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) { | |
9318c51a CD |
1351 | #ifdef CONFIG_MIPS_CPU_SCACHE |
1352 | if (mips_sc_init ()) { | |
1353 | scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; | |
1354 | printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n", | |
1355 | scache_size >> 10, | |
1356 | way_string[c->scache.ways], c->scache.linesz); | |
1357 | } | |
1358 | #else | |
1359 | if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) | |
1360 | panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); | |
1361 | #endif | |
1362 | return; | |
1363 | } | |
1da177e4 LT |
1364 | sc_present = 0; |
1365 | } | |
1366 | ||
1367 | if (!sc_present) | |
1368 | return; | |
1369 | ||
1da177e4 LT |
1370 | /* compute a couple of other cache variables */ |
1371 | c->scache.waysize = scache_size / c->scache.ways; | |
1372 | ||
1373 | c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); | |
1374 | ||
1375 | printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n", | |
1376 | scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); | |
1377 | ||
fc5d2d27 | 1378 | c->options |= MIPS_CPU_INCLUSIVE_CACHES; |
1da177e4 LT |
1379 | } |
1380 | ||
9370b351 SS |
1381 | void au1x00_fixup_config_od(void) |
1382 | { | |
1383 | /* | |
1384 | * c0_config.od (bit 19) was write only (and read as 0) | |
1385 | * on the early revisions of Alchemy SOCs. It disables the bus | |
1386 | * transaction overlapping and needs to be set to fix various errata. | |
1387 | */ | |
1388 | switch (read_c0_prid()) { | |
1389 | case 0x00030100: /* Au1000 DA */ | |
1390 | case 0x00030201: /* Au1000 HA */ | |
1391 | case 0x00030202: /* Au1000 HB */ | |
1392 | case 0x01030200: /* Au1500 AB */ | |
1393 | /* | |
1394 | * Au1100 errata actually keeps silence about this bit, so we set it | |
1395 | * just in case for those revisions that require it to be set according | |
270717a8 | 1396 | * to the (now gone) cpu table. |
9370b351 SS |
1397 | */ |
1398 | case 0x02030200: /* Au1100 AB */ | |
1399 | case 0x02030201: /* Au1100 BA */ | |
1400 | case 0x02030202: /* Au1100 BC */ | |
1401 | set_c0_config(1 << 19); | |
1402 | break; | |
1403 | } | |
1404 | } | |
1405 | ||
89052bd7 RB |
1406 | /* CP0 hazard avoidance. */ |
1407 | #define NXP_BARRIER() \ | |
1408 | __asm__ __volatile__( \ | |
1409 | ".set noreorder\n\t" \ | |
1410 | "nop; nop; nop; nop; nop; nop;\n\t" \ | |
1411 | ".set reorder\n\t") | |
1412 | ||
1413 | static void nxp_pr4450_fixup_config(void) | |
1414 | { | |
1415 | unsigned long config0; | |
1416 | ||
1417 | config0 = read_c0_config(); | |
1418 | ||
1419 | /* clear all three cache coherency fields */ | |
1420 | config0 &= ~(0x7 | (7 << 25) | (7 << 28)); | |
1421 | config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) | | |
1422 | ((_page_cachable_default >> _CACHE_SHIFT) << 25) | | |
1423 | ((_page_cachable_default >> _CACHE_SHIFT) << 28)); | |
1424 | write_c0_config(config0); | |
1425 | NXP_BARRIER(); | |
1426 | } | |
1427 | ||
078a55fc | 1428 | static int cca = -1; |
35133692 CD |
1429 | |
1430 | static int __init cca_setup(char *str) | |
1431 | { | |
1432 | get_option(&str, &cca); | |
1433 | ||
b5b64f2b | 1434 | return 0; |
35133692 CD |
1435 | } |
1436 | ||
b5b64f2b | 1437 | early_param("cca", cca_setup); |
35133692 | 1438 | |
078a55fc | 1439 | static void coherency_setup(void) |
1da177e4 | 1440 | { |
35133692 CD |
1441 | if (cca < 0 || cca > 7) |
1442 | cca = read_c0_config() & CONF_CM_CMASK; | |
1443 | _page_cachable_default = cca << _CACHE_SHIFT; | |
1444 | ||
1445 | pr_debug("Using cache attribute %d\n", cca); | |
1446 | change_c0_config(CONF_CM_CMASK, cca); | |
1da177e4 LT |
1447 | |
1448 | /* | |
1449 | * c0_status.cu=0 specifies that updates by the sc instruction use | |
1450 | * the coherency mode specified by the TLB; 1 means cachable | |
1451 | * coherent update on write will be used. Not all processors have | |
1452 | * this bit and; some wire it to zero, others like Toshiba had the | |
1453 | * silly idea of putting something else there ... | |
1454 | */ | |
10cc3529 | 1455 | switch (current_cpu_type()) { |
1da177e4 LT |
1456 | case CPU_R4000PC: |
1457 | case CPU_R4000SC: | |
1458 | case CPU_R4000MC: | |
1459 | case CPU_R4400PC: | |
1460 | case CPU_R4400SC: | |
1461 | case CPU_R4400MC: | |
1462 | clear_c0_config(CONF_CU); | |
1463 | break; | |
9370b351 | 1464 | /* |
df586d59 | 1465 | * We need to catch the early Alchemy SOCs with |
270717a8 ML |
1466 | * the write-only co_config.od bit and set it back to one on: |
1467 | * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB | |
9370b351 | 1468 | */ |
270717a8 | 1469 | case CPU_ALCHEMY: |
9370b351 SS |
1470 | au1x00_fixup_config_od(); |
1471 | break; | |
89052bd7 RB |
1472 | |
1473 | case PRID_IMP_PR4450: | |
1474 | nxp_pr4450_fixup_config(); | |
1475 | break; | |
1da177e4 LT |
1476 | } |
1477 | } | |
1478 | ||
078a55fc | 1479 | static void r4k_cache_error_setup(void) |
1da177e4 | 1480 | { |
641e97f3 RB |
1481 | extern char __weak except_vec2_generic; |
1482 | extern char __weak except_vec2_sb1; | |
1da177e4 | 1483 | |
69f24d17 | 1484 | switch (current_cpu_type()) { |
641e97f3 RB |
1485 | case CPU_SB1: |
1486 | case CPU_SB1A: | |
1487 | set_uncached_handler(0x100, &except_vec2_sb1, 0x80); | |
1488 | break; | |
1489 | ||
1490 | default: | |
1491 | set_uncached_handler(0x100, &except_vec2_generic, 0x80); | |
1492 | break; | |
1493 | } | |
9cd9669b DD |
1494 | } |
1495 | ||
078a55fc | 1496 | void r4k_cache_init(void) |
9cd9669b DD |
1497 | { |
1498 | extern void build_clear_page(void); | |
1499 | extern void build_copy_page(void); | |
1500 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1da177e4 LT |
1501 | |
1502 | probe_pcache(); | |
1503 | setup_scache(); | |
1504 | ||
1da177e4 LT |
1505 | r4k_blast_dcache_page_setup(); |
1506 | r4k_blast_dcache_page_indexed_setup(); | |
1507 | r4k_blast_dcache_setup(); | |
1508 | r4k_blast_icache_page_setup(); | |
1509 | r4k_blast_icache_page_indexed_setup(); | |
1510 | r4k_blast_icache_setup(); | |
1511 | r4k_blast_scache_page_setup(); | |
1512 | r4k_blast_scache_page_indexed_setup(); | |
1513 | r4k_blast_scache_setup(); | |
4caa906e LY |
1514 | #ifdef CONFIG_EVA |
1515 | r4k_blast_dcache_user_page_setup(); | |
1516 | r4k_blast_icache_user_page_setup(); | |
1517 | #endif | |
1da177e4 LT |
1518 | |
1519 | /* | |
1520 | * Some MIPS32 and MIPS64 processors have physically indexed caches. | |
1521 | * This code supports virtually indexed processors and will be | |
1522 | * unnecessarily inefficient on physically indexed processors. | |
1523 | */ | |
73f40352 CD |
1524 | if (c->dcache.linesz) |
1525 | shm_align_mask = max_t( unsigned long, | |
1526 | c->dcache.sets * c->dcache.linesz - 1, | |
1527 | PAGE_SIZE - 1); | |
1528 | else | |
1529 | shm_align_mask = PAGE_SIZE-1; | |
9c5a3d72 RB |
1530 | |
1531 | __flush_cache_vmap = r4k__flush_cache_vmap; | |
1532 | __flush_cache_vunmap = r4k__flush_cache_vunmap; | |
1533 | ||
db813fe5 | 1534 | flush_cache_all = cache_noop; |
1da177e4 LT |
1535 | __flush_cache_all = r4k___flush_cache_all; |
1536 | flush_cache_mm = r4k_flush_cache_mm; | |
1537 | flush_cache_page = r4k_flush_cache_page; | |
1da177e4 LT |
1538 | flush_cache_range = r4k_flush_cache_range; |
1539 | ||
d9cdc901 RB |
1540 | __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range; |
1541 | ||
1da177e4 LT |
1542 | flush_cache_sigtramp = r4k_flush_cache_sigtramp; |
1543 | flush_icache_all = r4k_flush_icache_all; | |
7e3bfc7c | 1544 | local_flush_data_cache_page = local_r4k_flush_data_cache_page; |
1da177e4 LT |
1545 | flush_data_cache_page = r4k_flush_data_cache_page; |
1546 | flush_icache_range = r4k_flush_icache_range; | |
e0cee3ee | 1547 | local_flush_icache_range = local_r4k_flush_icache_range; |
1da177e4 | 1548 | |
39b8d525 RB |
1549 | #if defined(CONFIG_DMA_NONCOHERENT) |
1550 | if (coherentio) { | |
1551 | _dma_cache_wback_inv = (void *)cache_noop; | |
1552 | _dma_cache_wback = (void *)cache_noop; | |
1553 | _dma_cache_inv = (void *)cache_noop; | |
1554 | } else { | |
1555 | _dma_cache_wback_inv = r4k_dma_cache_wback_inv; | |
1556 | _dma_cache_wback = r4k_dma_cache_wback_inv; | |
1557 | _dma_cache_inv = r4k_dma_cache_inv; | |
1558 | } | |
1da177e4 LT |
1559 | #endif |
1560 | ||
1da177e4 LT |
1561 | build_clear_page(); |
1562 | build_copy_page(); | |
b6d92b4a SH |
1563 | |
1564 | /* | |
1565 | * We want to run CMP kernels on core with and without coherent | |
1566 | * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether | |
1567 | * or not to flush caches. | |
1568 | */ | |
1d40cfcd | 1569 | local_r4k___flush_cache_all(NULL); |
b6d92b4a | 1570 | |
1d40cfcd | 1571 | coherency_setup(); |
9cd9669b | 1572 | board_cache_error_setup = r4k_cache_error_setup; |
1da177e4 | 1573 | } |