Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
79add627 | 6 | * Copyright (C) 1996 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
7 | * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org) |
8 | * Copyright (C) 1999, 2000 Silicon Graphics, Inc. | |
9 | */ | |
61d73044 | 10 | #include <linux/cpu_pm.h> |
a754f708 | 11 | #include <linux/hardirq.h> |
1da177e4 | 12 | #include <linux/init.h> |
db813fe5 | 13 | #include <linux/highmem.h> |
1da177e4 | 14 | #include <linux/kernel.h> |
641e97f3 | 15 | #include <linux/linkage.h> |
ff522058 | 16 | #include <linux/preempt.h> |
1da177e4 | 17 | #include <linux/sched.h> |
631330f5 | 18 | #include <linux/smp.h> |
1da177e4 | 19 | #include <linux/mm.h> |
35133692 | 20 | #include <linux/module.h> |
1da177e4 LT |
21 | #include <linux/bitops.h> |
22 | ||
23 | #include <asm/bcache.h> | |
24 | #include <asm/bootinfo.h> | |
ec74e361 | 25 | #include <asm/cache.h> |
1da177e4 LT |
26 | #include <asm/cacheops.h> |
27 | #include <asm/cpu.h> | |
28 | #include <asm/cpu-features.h> | |
69f24d17 | 29 | #include <asm/cpu-type.h> |
1da177e4 LT |
30 | #include <asm/io.h> |
31 | #include <asm/page.h> | |
32 | #include <asm/pgtable.h> | |
33 | #include <asm/r4kcache.h> | |
e001e528 | 34 | #include <asm/sections.h> |
1da177e4 LT |
35 | #include <asm/mmu_context.h> |
36 | #include <asm/war.h> | |
ba5187db | 37 | #include <asm/cacheflush.h> /* for run_uncached() */ |
9cd9669b | 38 | #include <asm/traps.h> |
b6d92b4a | 39 | #include <asm/dma-coherence.h> |
7f3f1d01 RB |
40 | |
41 | /* | |
42 | * Special Variant of smp_call_function for use by cache functions: | |
43 | * | |
44 | * o No return value | |
45 | * o collapses to normal function call on UP kernels | |
46 | * o collapses to normal function call on systems with a single shared | |
47 | * primary cache. | |
c8c5f3fd | 48 | * o doesn't disable interrupts on the local CPU |
7f3f1d01 | 49 | */ |
48a26e60 | 50 | static inline void r4k_on_each_cpu(void (*func) (void *info), void *info) |
7f3f1d01 RB |
51 | { |
52 | preempt_disable(); | |
53 | ||
b633648c | 54 | #ifndef CONFIG_MIPS_MT_SMP |
48a26e60 | 55 | smp_call_function(func, info, 1); |
7f3f1d01 RB |
56 | #endif |
57 | func(info); | |
58 | preempt_enable(); | |
59 | } | |
60 | ||
0ee958e1 | 61 | #if defined(CONFIG_MIPS_CMP) || defined(CONFIG_MIPS_CPS) |
39b8d525 RB |
62 | #define cpu_has_safe_index_cacheops 0 |
63 | #else | |
64 | #define cpu_has_safe_index_cacheops 1 | |
65 | #endif | |
66 | ||
ec74e361 RB |
67 | /* |
68 | * Must die. | |
69 | */ | |
70 | static unsigned long icache_size __read_mostly; | |
71 | static unsigned long dcache_size __read_mostly; | |
72 | static unsigned long scache_size __read_mostly; | |
1da177e4 LT |
73 | |
74 | /* | |
75 | * Dummy cache handling routines for machines without boardcaches | |
76 | */ | |
73f40352 | 77 | static void cache_noop(void) {} |
1da177e4 LT |
78 | |
79 | static struct bcache_ops no_sc_ops = { | |
73f40352 CD |
80 | .bc_enable = (void *)cache_noop, |
81 | .bc_disable = (void *)cache_noop, | |
82 | .bc_wback_inv = (void *)cache_noop, | |
83 | .bc_inv = (void *)cache_noop | |
1da177e4 LT |
84 | }; |
85 | ||
86 | struct bcache_ops *bcops = &no_sc_ops; | |
87 | ||
330cfe01 TS |
88 | #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) |
89 | #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) | |
1da177e4 LT |
90 | |
91 | #define R4600_HIT_CACHEOP_WAR_IMPL \ | |
92 | do { \ | |
93 | if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \ | |
94 | *(volatile unsigned long *)CKSEG1; \ | |
95 | if (R4600_V1_HIT_CACHEOP_WAR) \ | |
96 | __asm__ __volatile__("nop;nop;nop;nop"); \ | |
97 | } while (0) | |
98 | ||
99 | static void (*r4k_blast_dcache_page)(unsigned long addr); | |
100 | ||
101 | static inline void r4k_blast_dcache_page_dc32(unsigned long addr) | |
102 | { | |
103 | R4600_HIT_CACHEOP_WAR_IMPL; | |
104 | blast_dcache32_page(addr); | |
105 | } | |
106 | ||
605b7ef7 KC |
107 | static inline void r4k_blast_dcache_page_dc64(unsigned long addr) |
108 | { | |
605b7ef7 KC |
109 | blast_dcache64_page(addr); |
110 | } | |
111 | ||
18a8cd63 DD |
112 | static inline void r4k_blast_dcache_page_dc128(unsigned long addr) |
113 | { | |
114 | blast_dcache128_page(addr); | |
115 | } | |
116 | ||
078a55fc | 117 | static void r4k_blast_dcache_page_setup(void) |
1da177e4 LT |
118 | { |
119 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
120 | ||
18a8cd63 DD |
121 | switch (dc_lsize) { |
122 | case 0: | |
73f40352 | 123 | r4k_blast_dcache_page = (void *)cache_noop; |
18a8cd63 DD |
124 | break; |
125 | case 16: | |
1da177e4 | 126 | r4k_blast_dcache_page = blast_dcache16_page; |
18a8cd63 DD |
127 | break; |
128 | case 32: | |
1da177e4 | 129 | r4k_blast_dcache_page = r4k_blast_dcache_page_dc32; |
18a8cd63 DD |
130 | break; |
131 | case 64: | |
605b7ef7 | 132 | r4k_blast_dcache_page = r4k_blast_dcache_page_dc64; |
18a8cd63 DD |
133 | break; |
134 | case 128: | |
135 | r4k_blast_dcache_page = r4k_blast_dcache_page_dc128; | |
136 | break; | |
137 | default: | |
138 | break; | |
139 | } | |
1da177e4 LT |
140 | } |
141 | ||
4caa906e LY |
142 | #ifndef CONFIG_EVA |
143 | #define r4k_blast_dcache_user_page r4k_blast_dcache_page | |
144 | #else | |
145 | ||
146 | static void (*r4k_blast_dcache_user_page)(unsigned long addr); | |
147 | ||
148 | static void r4k_blast_dcache_user_page_setup(void) | |
149 | { | |
150 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
151 | ||
152 | if (dc_lsize == 0) | |
153 | r4k_blast_dcache_user_page = (void *)cache_noop; | |
154 | else if (dc_lsize == 16) | |
155 | r4k_blast_dcache_user_page = blast_dcache16_user_page; | |
156 | else if (dc_lsize == 32) | |
157 | r4k_blast_dcache_user_page = blast_dcache32_user_page; | |
158 | else if (dc_lsize == 64) | |
159 | r4k_blast_dcache_user_page = blast_dcache64_user_page; | |
160 | } | |
161 | ||
162 | #endif | |
163 | ||
1da177e4 LT |
164 | static void (* r4k_blast_dcache_page_indexed)(unsigned long addr); |
165 | ||
078a55fc | 166 | static void r4k_blast_dcache_page_indexed_setup(void) |
1da177e4 LT |
167 | { |
168 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
169 | ||
73f40352 CD |
170 | if (dc_lsize == 0) |
171 | r4k_blast_dcache_page_indexed = (void *)cache_noop; | |
172 | else if (dc_lsize == 16) | |
1da177e4 LT |
173 | r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; |
174 | else if (dc_lsize == 32) | |
175 | r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; | |
605b7ef7 KC |
176 | else if (dc_lsize == 64) |
177 | r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed; | |
18a8cd63 DD |
178 | else if (dc_lsize == 128) |
179 | r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed; | |
1da177e4 LT |
180 | } |
181 | ||
f2e3656d SL |
182 | void (* r4k_blast_dcache)(void); |
183 | EXPORT_SYMBOL(r4k_blast_dcache); | |
1da177e4 | 184 | |
078a55fc | 185 | static void r4k_blast_dcache_setup(void) |
1da177e4 LT |
186 | { |
187 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
188 | ||
73f40352 CD |
189 | if (dc_lsize == 0) |
190 | r4k_blast_dcache = (void *)cache_noop; | |
191 | else if (dc_lsize == 16) | |
1da177e4 LT |
192 | r4k_blast_dcache = blast_dcache16; |
193 | else if (dc_lsize == 32) | |
194 | r4k_blast_dcache = blast_dcache32; | |
605b7ef7 KC |
195 | else if (dc_lsize == 64) |
196 | r4k_blast_dcache = blast_dcache64; | |
18a8cd63 DD |
197 | else if (dc_lsize == 128) |
198 | r4k_blast_dcache = blast_dcache128; | |
1da177e4 LT |
199 | } |
200 | ||
201 | /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */ | |
202 | #define JUMP_TO_ALIGN(order) \ | |
203 | __asm__ __volatile__( \ | |
204 | "b\t1f\n\t" \ | |
205 | ".align\t" #order "\n\t" \ | |
206 | "1:\n\t" \ | |
207 | ) | |
208 | #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */ | |
70342287 | 209 | #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11) |
1da177e4 LT |
210 | |
211 | static inline void blast_r4600_v1_icache32(void) | |
212 | { | |
213 | unsigned long flags; | |
214 | ||
215 | local_irq_save(flags); | |
216 | blast_icache32(); | |
217 | local_irq_restore(flags); | |
218 | } | |
219 | ||
220 | static inline void tx49_blast_icache32(void) | |
221 | { | |
222 | unsigned long start = INDEX_BASE; | |
223 | unsigned long end = start + current_cpu_data.icache.waysize; | |
224 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; | |
225 | unsigned long ws_end = current_cpu_data.icache.ways << | |
70342287 | 226 | current_cpu_data.icache.waybit; |
1da177e4 LT |
227 | unsigned long ws, addr; |
228 | ||
229 | CACHE32_UNROLL32_ALIGN2; | |
230 | /* I'm in even chunk. blast odd chunks */ | |
42a3b4f2 RB |
231 | for (ws = 0; ws < ws_end; ws += ws_inc) |
232 | for (addr = start + 0x400; addr < end; addr += 0x400 * 2) | |
21a151d8 | 233 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
234 | CACHE32_UNROLL32_ALIGN; |
235 | /* I'm in odd chunk. blast even chunks */ | |
42a3b4f2 RB |
236 | for (ws = 0; ws < ws_end; ws += ws_inc) |
237 | for (addr = start; addr < end; addr += 0x400 * 2) | |
21a151d8 | 238 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
239 | } |
240 | ||
241 | static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page) | |
242 | { | |
243 | unsigned long flags; | |
244 | ||
245 | local_irq_save(flags); | |
246 | blast_icache32_page_indexed(page); | |
247 | local_irq_restore(flags); | |
248 | } | |
249 | ||
250 | static inline void tx49_blast_icache32_page_indexed(unsigned long page) | |
251 | { | |
67a3f6de AN |
252 | unsigned long indexmask = current_cpu_data.icache.waysize - 1; |
253 | unsigned long start = INDEX_BASE + (page & indexmask); | |
1da177e4 LT |
254 | unsigned long end = start + PAGE_SIZE; |
255 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; | |
256 | unsigned long ws_end = current_cpu_data.icache.ways << | |
70342287 | 257 | current_cpu_data.icache.waybit; |
1da177e4 LT |
258 | unsigned long ws, addr; |
259 | ||
260 | CACHE32_UNROLL32_ALIGN2; | |
261 | /* I'm in even chunk. blast odd chunks */ | |
42a3b4f2 RB |
262 | for (ws = 0; ws < ws_end; ws += ws_inc) |
263 | for (addr = start + 0x400; addr < end; addr += 0x400 * 2) | |
21a151d8 | 264 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
265 | CACHE32_UNROLL32_ALIGN; |
266 | /* I'm in odd chunk. blast even chunks */ | |
42a3b4f2 RB |
267 | for (ws = 0; ws < ws_end; ws += ws_inc) |
268 | for (addr = start; addr < end; addr += 0x400 * 2) | |
21a151d8 | 269 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
270 | } |
271 | ||
272 | static void (* r4k_blast_icache_page)(unsigned long addr); | |
273 | ||
078a55fc | 274 | static void r4k_blast_icache_page_setup(void) |
1da177e4 LT |
275 | { |
276 | unsigned long ic_lsize = cpu_icache_line_size(); | |
277 | ||
73f40352 CD |
278 | if (ic_lsize == 0) |
279 | r4k_blast_icache_page = (void *)cache_noop; | |
280 | else if (ic_lsize == 16) | |
1da177e4 | 281 | r4k_blast_icache_page = blast_icache16_page; |
43a06847 AK |
282 | else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2) |
283 | r4k_blast_icache_page = loongson2_blast_icache32_page; | |
1da177e4 LT |
284 | else if (ic_lsize == 32) |
285 | r4k_blast_icache_page = blast_icache32_page; | |
286 | else if (ic_lsize == 64) | |
287 | r4k_blast_icache_page = blast_icache64_page; | |
18a8cd63 DD |
288 | else if (ic_lsize == 128) |
289 | r4k_blast_icache_page = blast_icache128_page; | |
1da177e4 LT |
290 | } |
291 | ||
4caa906e LY |
292 | #ifndef CONFIG_EVA |
293 | #define r4k_blast_icache_user_page r4k_blast_icache_page | |
294 | #else | |
295 | ||
296 | static void (*r4k_blast_icache_user_page)(unsigned long addr); | |
297 | ||
298 | static void __cpuinit r4k_blast_icache_user_page_setup(void) | |
299 | { | |
300 | unsigned long ic_lsize = cpu_icache_line_size(); | |
301 | ||
302 | if (ic_lsize == 0) | |
303 | r4k_blast_icache_user_page = (void *)cache_noop; | |
304 | else if (ic_lsize == 16) | |
305 | r4k_blast_icache_user_page = blast_icache16_user_page; | |
306 | else if (ic_lsize == 32) | |
307 | r4k_blast_icache_user_page = blast_icache32_user_page; | |
308 | else if (ic_lsize == 64) | |
309 | r4k_blast_icache_user_page = blast_icache64_user_page; | |
310 | } | |
311 | ||
312 | #endif | |
1da177e4 LT |
313 | |
314 | static void (* r4k_blast_icache_page_indexed)(unsigned long addr); | |
315 | ||
078a55fc | 316 | static void r4k_blast_icache_page_indexed_setup(void) |
1da177e4 LT |
317 | { |
318 | unsigned long ic_lsize = cpu_icache_line_size(); | |
319 | ||
73f40352 CD |
320 | if (ic_lsize == 0) |
321 | r4k_blast_icache_page_indexed = (void *)cache_noop; | |
322 | else if (ic_lsize == 16) | |
1da177e4 LT |
323 | r4k_blast_icache_page_indexed = blast_icache16_page_indexed; |
324 | else if (ic_lsize == 32) { | |
02fe2c9c | 325 | if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) |
1da177e4 LT |
326 | r4k_blast_icache_page_indexed = |
327 | blast_icache32_r4600_v1_page_indexed; | |
02fe2c9c TS |
328 | else if (TX49XX_ICACHE_INDEX_INV_WAR) |
329 | r4k_blast_icache_page_indexed = | |
330 | tx49_blast_icache32_page_indexed; | |
43a06847 AK |
331 | else if (current_cpu_type() == CPU_LOONGSON2) |
332 | r4k_blast_icache_page_indexed = | |
333 | loongson2_blast_icache32_page_indexed; | |
1da177e4 LT |
334 | else |
335 | r4k_blast_icache_page_indexed = | |
336 | blast_icache32_page_indexed; | |
337 | } else if (ic_lsize == 64) | |
338 | r4k_blast_icache_page_indexed = blast_icache64_page_indexed; | |
339 | } | |
340 | ||
f2e3656d SL |
341 | void (* r4k_blast_icache)(void); |
342 | EXPORT_SYMBOL(r4k_blast_icache); | |
1da177e4 | 343 | |
078a55fc | 344 | static void r4k_blast_icache_setup(void) |
1da177e4 LT |
345 | { |
346 | unsigned long ic_lsize = cpu_icache_line_size(); | |
347 | ||
73f40352 CD |
348 | if (ic_lsize == 0) |
349 | r4k_blast_icache = (void *)cache_noop; | |
350 | else if (ic_lsize == 16) | |
1da177e4 LT |
351 | r4k_blast_icache = blast_icache16; |
352 | else if (ic_lsize == 32) { | |
353 | if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) | |
354 | r4k_blast_icache = blast_r4600_v1_icache32; | |
355 | else if (TX49XX_ICACHE_INDEX_INV_WAR) | |
356 | r4k_blast_icache = tx49_blast_icache32; | |
43a06847 AK |
357 | else if (current_cpu_type() == CPU_LOONGSON2) |
358 | r4k_blast_icache = loongson2_blast_icache32; | |
1da177e4 LT |
359 | else |
360 | r4k_blast_icache = blast_icache32; | |
361 | } else if (ic_lsize == 64) | |
362 | r4k_blast_icache = blast_icache64; | |
18a8cd63 DD |
363 | else if (ic_lsize == 128) |
364 | r4k_blast_icache = blast_icache128; | |
1da177e4 LT |
365 | } |
366 | ||
367 | static void (* r4k_blast_scache_page)(unsigned long addr); | |
368 | ||
078a55fc | 369 | static void r4k_blast_scache_page_setup(void) |
1da177e4 LT |
370 | { |
371 | unsigned long sc_lsize = cpu_scache_line_size(); | |
372 | ||
4debe4f9 | 373 | if (scache_size == 0) |
73f40352 | 374 | r4k_blast_scache_page = (void *)cache_noop; |
4debe4f9 | 375 | else if (sc_lsize == 16) |
1da177e4 LT |
376 | r4k_blast_scache_page = blast_scache16_page; |
377 | else if (sc_lsize == 32) | |
378 | r4k_blast_scache_page = blast_scache32_page; | |
379 | else if (sc_lsize == 64) | |
380 | r4k_blast_scache_page = blast_scache64_page; | |
381 | else if (sc_lsize == 128) | |
382 | r4k_blast_scache_page = blast_scache128_page; | |
383 | } | |
384 | ||
385 | static void (* r4k_blast_scache_page_indexed)(unsigned long addr); | |
386 | ||
078a55fc | 387 | static void r4k_blast_scache_page_indexed_setup(void) |
1da177e4 LT |
388 | { |
389 | unsigned long sc_lsize = cpu_scache_line_size(); | |
390 | ||
4debe4f9 | 391 | if (scache_size == 0) |
73f40352 | 392 | r4k_blast_scache_page_indexed = (void *)cache_noop; |
4debe4f9 | 393 | else if (sc_lsize == 16) |
1da177e4 LT |
394 | r4k_blast_scache_page_indexed = blast_scache16_page_indexed; |
395 | else if (sc_lsize == 32) | |
396 | r4k_blast_scache_page_indexed = blast_scache32_page_indexed; | |
397 | else if (sc_lsize == 64) | |
398 | r4k_blast_scache_page_indexed = blast_scache64_page_indexed; | |
399 | else if (sc_lsize == 128) | |
400 | r4k_blast_scache_page_indexed = blast_scache128_page_indexed; | |
401 | } | |
402 | ||
403 | static void (* r4k_blast_scache)(void); | |
404 | ||
078a55fc | 405 | static void r4k_blast_scache_setup(void) |
1da177e4 LT |
406 | { |
407 | unsigned long sc_lsize = cpu_scache_line_size(); | |
408 | ||
4debe4f9 | 409 | if (scache_size == 0) |
73f40352 | 410 | r4k_blast_scache = (void *)cache_noop; |
4debe4f9 | 411 | else if (sc_lsize == 16) |
1da177e4 LT |
412 | r4k_blast_scache = blast_scache16; |
413 | else if (sc_lsize == 32) | |
414 | r4k_blast_scache = blast_scache32; | |
415 | else if (sc_lsize == 64) | |
416 | r4k_blast_scache = blast_scache64; | |
417 | else if (sc_lsize == 128) | |
418 | r4k_blast_scache = blast_scache128; | |
419 | } | |
420 | ||
1da177e4 LT |
421 | static inline void local_r4k___flush_cache_all(void * args) |
422 | { | |
10cc3529 | 423 | switch (current_cpu_type()) { |
14bd8c08 | 424 | case CPU_LOONGSON2: |
c579d310 | 425 | case CPU_LOONGSON3: |
1da177e4 LT |
426 | case CPU_R4000SC: |
427 | case CPU_R4000MC: | |
428 | case CPU_R4400SC: | |
429 | case CPU_R4400MC: | |
430 | case CPU_R10000: | |
431 | case CPU_R12000: | |
44d921b2 | 432 | case CPU_R14000: |
14bd8c08 RB |
433 | /* |
434 | * These caches are inclusive caches, that is, if something | |
435 | * is not cached in the S-cache, we know it also won't be | |
436 | * in one of the primary caches. | |
437 | */ | |
1da177e4 | 438 | r4k_blast_scache(); |
14bd8c08 RB |
439 | break; |
440 | ||
441 | default: | |
442 | r4k_blast_dcache(); | |
443 | r4k_blast_icache(); | |
444 | break; | |
1da177e4 LT |
445 | } |
446 | } | |
447 | ||
448 | static void r4k___flush_cache_all(void) | |
449 | { | |
48a26e60 | 450 | r4k_on_each_cpu(local_r4k___flush_cache_all, NULL); |
1da177e4 LT |
451 | } |
452 | ||
a76ab5c1 RB |
453 | static inline int has_valid_asid(const struct mm_struct *mm) |
454 | { | |
b633648c | 455 | #ifdef CONFIG_MIPS_MT_SMP |
a76ab5c1 RB |
456 | int i; |
457 | ||
458 | for_each_online_cpu(i) | |
459 | if (cpu_context(i, mm)) | |
460 | return 1; | |
461 | ||
462 | return 0; | |
463 | #else | |
464 | return cpu_context(smp_processor_id(), mm); | |
465 | #endif | |
466 | } | |
467 | ||
9c5a3d72 RB |
468 | static void r4k__flush_cache_vmap(void) |
469 | { | |
470 | r4k_blast_dcache(); | |
471 | } | |
472 | ||
473 | static void r4k__flush_cache_vunmap(void) | |
474 | { | |
475 | r4k_blast_dcache(); | |
476 | } | |
477 | ||
1da177e4 LT |
478 | static inline void local_r4k_flush_cache_range(void * args) |
479 | { | |
480 | struct vm_area_struct *vma = args; | |
2eaa7ec2 | 481 | int exec = vma->vm_flags & VM_EXEC; |
1da177e4 | 482 | |
a76ab5c1 | 483 | if (!(has_valid_asid(vma->vm_mm))) |
1da177e4 LT |
484 | return; |
485 | ||
0550d9d1 | 486 | r4k_blast_dcache(); |
2eaa7ec2 RB |
487 | if (exec) |
488 | r4k_blast_icache(); | |
1da177e4 LT |
489 | } |
490 | ||
491 | static void r4k_flush_cache_range(struct vm_area_struct *vma, | |
492 | unsigned long start, unsigned long end) | |
493 | { | |
2eaa7ec2 | 494 | int exec = vma->vm_flags & VM_EXEC; |
0550d9d1 | 495 | |
2eaa7ec2 | 496 | if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) |
48a26e60 | 497 | r4k_on_each_cpu(local_r4k_flush_cache_range, vma); |
1da177e4 LT |
498 | } |
499 | ||
500 | static inline void local_r4k_flush_cache_mm(void * args) | |
501 | { | |
502 | struct mm_struct *mm = args; | |
503 | ||
a76ab5c1 | 504 | if (!has_valid_asid(mm)) |
1da177e4 LT |
505 | return; |
506 | ||
1da177e4 LT |
507 | /* |
508 | * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we | |
509 | * only flush the primary caches but R10000 and R12000 behave sane ... | |
617667ba RB |
510 | * R4000SC and R4400SC indexed S-cache ops also invalidate primary |
511 | * caches, so we can bail out early. | |
1da177e4 | 512 | */ |
10cc3529 RB |
513 | if (current_cpu_type() == CPU_R4000SC || |
514 | current_cpu_type() == CPU_R4000MC || | |
515 | current_cpu_type() == CPU_R4400SC || | |
516 | current_cpu_type() == CPU_R4400MC) { | |
1da177e4 | 517 | r4k_blast_scache(); |
617667ba RB |
518 | return; |
519 | } | |
520 | ||
521 | r4k_blast_dcache(); | |
1da177e4 LT |
522 | } |
523 | ||
524 | static void r4k_flush_cache_mm(struct mm_struct *mm) | |
525 | { | |
526 | if (!cpu_has_dc_aliases) | |
527 | return; | |
528 | ||
48a26e60 | 529 | r4k_on_each_cpu(local_r4k_flush_cache_mm, mm); |
1da177e4 LT |
530 | } |
531 | ||
532 | struct flush_cache_page_args { | |
533 | struct vm_area_struct *vma; | |
6ec25809 | 534 | unsigned long addr; |
de62893b | 535 | unsigned long pfn; |
1da177e4 LT |
536 | }; |
537 | ||
538 | static inline void local_r4k_flush_cache_page(void *args) | |
539 | { | |
540 | struct flush_cache_page_args *fcp_args = args; | |
541 | struct vm_area_struct *vma = fcp_args->vma; | |
6ec25809 | 542 | unsigned long addr = fcp_args->addr; |
db813fe5 | 543 | struct page *page = pfn_to_page(fcp_args->pfn); |
1da177e4 LT |
544 | int exec = vma->vm_flags & VM_EXEC; |
545 | struct mm_struct *mm = vma->vm_mm; | |
c9c5023d | 546 | int map_coherent = 0; |
1da177e4 | 547 | pgd_t *pgdp; |
c6e8b587 | 548 | pud_t *pudp; |
1da177e4 LT |
549 | pmd_t *pmdp; |
550 | pte_t *ptep; | |
db813fe5 | 551 | void *vaddr; |
1da177e4 | 552 | |
79acf83e RB |
553 | /* |
554 | * If ownes no valid ASID yet, cannot possibly have gotten | |
555 | * this page into the cache. | |
556 | */ | |
a76ab5c1 | 557 | if (!has_valid_asid(mm)) |
79acf83e RB |
558 | return; |
559 | ||
6ec25809 RB |
560 | addr &= PAGE_MASK; |
561 | pgdp = pgd_offset(mm, addr); | |
562 | pudp = pud_offset(pgdp, addr); | |
563 | pmdp = pmd_offset(pudp, addr); | |
564 | ptep = pte_offset(pmdp, addr); | |
1da177e4 LT |
565 | |
566 | /* | |
567 | * If the page isn't marked valid, the page cannot possibly be | |
568 | * in the cache. | |
569 | */ | |
526af35e | 570 | if (!(pte_present(*ptep))) |
1da177e4 LT |
571 | return; |
572 | ||
db813fe5 RB |
573 | if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) |
574 | vaddr = NULL; | |
575 | else { | |
576 | /* | |
577 | * Use kmap_coherent or kmap_atomic to do flushes for | |
578 | * another ASID than the current one. | |
579 | */ | |
c9c5023d RB |
580 | map_coherent = (cpu_has_dc_aliases && |
581 | page_mapped(page) && !Page_dcache_dirty(page)); | |
582 | if (map_coherent) | |
db813fe5 RB |
583 | vaddr = kmap_coherent(page, addr); |
584 | else | |
9c02048f | 585 | vaddr = kmap_atomic(page); |
db813fe5 | 586 | addr = (unsigned long)vaddr; |
1da177e4 LT |
587 | } |
588 | ||
1da177e4 | 589 | if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { |
80ca69f4 MC |
590 | vaddr ? r4k_blast_dcache_page(addr) : |
591 | r4k_blast_dcache_user_page(addr); | |
39b8d525 RB |
592 | if (exec && !cpu_icache_snoops_remote_store) |
593 | r4k_blast_scache_page(addr); | |
1da177e4 LT |
594 | } |
595 | if (exec) { | |
db813fe5 | 596 | if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) { |
1da177e4 LT |
597 | int cpu = smp_processor_id(); |
598 | ||
26a51b27 TS |
599 | if (cpu_context(cpu, mm) != 0) |
600 | drop_mmu_context(mm, cpu); | |
1da177e4 | 601 | } else |
80ca69f4 MC |
602 | vaddr ? r4k_blast_icache_page(addr) : |
603 | r4k_blast_icache_user_page(addr); | |
db813fe5 RB |
604 | } |
605 | ||
606 | if (vaddr) { | |
c9c5023d | 607 | if (map_coherent) |
db813fe5 RB |
608 | kunmap_coherent(); |
609 | else | |
9c02048f | 610 | kunmap_atomic(vaddr); |
1da177e4 LT |
611 | } |
612 | } | |
613 | ||
6ec25809 RB |
614 | static void r4k_flush_cache_page(struct vm_area_struct *vma, |
615 | unsigned long addr, unsigned long pfn) | |
1da177e4 LT |
616 | { |
617 | struct flush_cache_page_args args; | |
618 | ||
1da177e4 | 619 | args.vma = vma; |
6ec25809 | 620 | args.addr = addr; |
de62893b | 621 | args.pfn = pfn; |
1da177e4 | 622 | |
48a26e60 | 623 | r4k_on_each_cpu(local_r4k_flush_cache_page, &args); |
1da177e4 LT |
624 | } |
625 | ||
626 | static inline void local_r4k_flush_data_cache_page(void * addr) | |
627 | { | |
628 | r4k_blast_dcache_page((unsigned long) addr); | |
629 | } | |
630 | ||
631 | static void r4k_flush_data_cache_page(unsigned long addr) | |
632 | { | |
a754f708 RB |
633 | if (in_atomic()) |
634 | local_r4k_flush_data_cache_page((void *)addr); | |
635 | else | |
48a26e60 | 636 | r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr); |
1da177e4 LT |
637 | } |
638 | ||
639 | struct flush_icache_range_args { | |
d4264f18 AN |
640 | unsigned long start; |
641 | unsigned long end; | |
1da177e4 LT |
642 | }; |
643 | ||
e0cee3ee | 644 | static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end) |
1da177e4 | 645 | { |
1da177e4 | 646 | if (!cpu_has_ic_fills_f_dc) { |
73f40352 | 647 | if (end - start >= dcache_size) { |
1da177e4 LT |
648 | r4k_blast_dcache(); |
649 | } else { | |
10a3dabd | 650 | R4600_HIT_CACHEOP_WAR_IMPL; |
41700e73 | 651 | protected_blast_dcache_range(start, end); |
1da177e4 | 652 | } |
1da177e4 LT |
653 | } |
654 | ||
655 | if (end - start > icache_size) | |
656 | r4k_blast_icache(); | |
14bd8c08 RB |
657 | else { |
658 | switch (boot_cpu_type()) { | |
659 | case CPU_LOONGSON2: | |
bad009fe | 660 | protected_loongson2_blast_icache_range(start, end); |
14bd8c08 RB |
661 | break; |
662 | ||
663 | default: | |
bad009fe | 664 | protected_blast_icache_range(start, end); |
14bd8c08 RB |
665 | break; |
666 | } | |
667 | } | |
4676f935 LY |
668 | #ifdef CONFIG_EVA |
669 | /* | |
670 | * Due to all possible segment mappings, there might cache aliases | |
671 | * caused by the bootloader being in non-EVA mode, and the CPU switching | |
672 | * to EVA during early kernel init. It's best to flush the scache | |
673 | * to avoid having secondary cores fetching stale data and lead to | |
674 | * kernel crashes. | |
675 | */ | |
676 | bc_wback_inv(start, (end - start)); | |
677 | __sync(); | |
678 | #endif | |
1da177e4 LT |
679 | } |
680 | ||
e0cee3ee TB |
681 | static inline void local_r4k_flush_icache_range_ipi(void *args) |
682 | { | |
683 | struct flush_icache_range_args *fir_args = args; | |
684 | unsigned long start = fir_args->start; | |
685 | unsigned long end = fir_args->end; | |
686 | ||
687 | local_r4k_flush_icache_range(start, end); | |
688 | } | |
689 | ||
d4264f18 | 690 | static void r4k_flush_icache_range(unsigned long start, unsigned long end) |
1da177e4 LT |
691 | { |
692 | struct flush_icache_range_args args; | |
693 | ||
694 | args.start = start; | |
695 | args.end = end; | |
696 | ||
48a26e60 | 697 | r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args); |
cc61c1fe | 698 | instruction_hazard(); |
1da177e4 LT |
699 | } |
700 | ||
8005711c | 701 | #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT) |
1da177e4 LT |
702 | |
703 | static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) | |
704 | { | |
1da177e4 LT |
705 | /* Catch bad driver code */ |
706 | BUG_ON(size == 0); | |
707 | ||
ff522058 | 708 | preempt_disable(); |
fc5d2d27 | 709 | if (cpu_has_inclusive_pcaches) { |
41700e73 | 710 | if (size >= scache_size) |
1da177e4 | 711 | r4k_blast_scache(); |
41700e73 AN |
712 | else |
713 | blast_scache_range(addr, addr + size); | |
5596b0b2 | 714 | preempt_enable(); |
d0023c4a | 715 | __sync(); |
1da177e4 LT |
716 | return; |
717 | } | |
718 | ||
719 | /* | |
720 | * Either no secondary cache or the available caches don't have the | |
721 | * subset property so we have to flush the primary caches | |
722 | * explicitly | |
723 | */ | |
39b8d525 | 724 | if (cpu_has_safe_index_cacheops && size >= dcache_size) { |
1da177e4 LT |
725 | r4k_blast_dcache(); |
726 | } else { | |
1da177e4 | 727 | R4600_HIT_CACHEOP_WAR_IMPL; |
41700e73 | 728 | blast_dcache_range(addr, addr + size); |
1da177e4 | 729 | } |
ff522058 | 730 | preempt_enable(); |
1da177e4 LT |
731 | |
732 | bc_wback_inv(addr, size); | |
d0023c4a | 733 | __sync(); |
1da177e4 LT |
734 | } |
735 | ||
736 | static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) | |
737 | { | |
1da177e4 LT |
738 | /* Catch bad driver code */ |
739 | BUG_ON(size == 0); | |
740 | ||
ff522058 | 741 | preempt_disable(); |
fc5d2d27 | 742 | if (cpu_has_inclusive_pcaches) { |
41700e73 | 743 | if (size >= scache_size) |
1da177e4 | 744 | r4k_blast_scache(); |
a8ca8b64 | 745 | else { |
a8ca8b64 RB |
746 | /* |
747 | * There is no clearly documented alignment requirement | |
748 | * for the cache instruction on MIPS processors and | |
749 | * some processors, among them the RM5200 and RM7000 | |
750 | * QED processors will throw an address error for cache | |
70342287 | 751 | * hit ops with insufficient alignment. Solved by |
a8ca8b64 RB |
752 | * aligning the address to cache line size. |
753 | */ | |
e9c33572 | 754 | blast_inv_scache_range(addr, addr + size); |
a8ca8b64 | 755 | } |
5596b0b2 | 756 | preempt_enable(); |
d0023c4a | 757 | __sync(); |
1da177e4 LT |
758 | return; |
759 | } | |
760 | ||
39b8d525 | 761 | if (cpu_has_safe_index_cacheops && size >= dcache_size) { |
1da177e4 LT |
762 | r4k_blast_dcache(); |
763 | } else { | |
1da177e4 | 764 | R4600_HIT_CACHEOP_WAR_IMPL; |
e9c33572 | 765 | blast_inv_dcache_range(addr, addr + size); |
1da177e4 | 766 | } |
ff522058 | 767 | preempt_enable(); |
1da177e4 LT |
768 | |
769 | bc_inv(addr, size); | |
d0023c4a | 770 | __sync(); |
1da177e4 | 771 | } |
8005711c | 772 | #endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */ |
1da177e4 LT |
773 | |
774 | /* | |
775 | * While we're protected against bad userland addresses we don't care | |
776 | * very much about what happens in that case. Usually a segmentation | |
777 | * fault will dump the process later on anyway ... | |
778 | */ | |
779 | static void local_r4k_flush_cache_sigtramp(void * arg) | |
780 | { | |
02fe2c9c TS |
781 | unsigned long ic_lsize = cpu_icache_line_size(); |
782 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
783 | unsigned long sc_lsize = cpu_scache_line_size(); | |
1da177e4 LT |
784 | unsigned long addr = (unsigned long) arg; |
785 | ||
786 | R4600_HIT_CACHEOP_WAR_IMPL; | |
73f40352 CD |
787 | if (dc_lsize) |
788 | protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); | |
4debe4f9 | 789 | if (!cpu_icache_snoops_remote_store && scache_size) |
1da177e4 | 790 | protected_writeback_scache_line(addr & ~(sc_lsize - 1)); |
73f40352 CD |
791 | if (ic_lsize) |
792 | protected_flush_icache_line(addr & ~(ic_lsize - 1)); | |
1da177e4 LT |
793 | if (MIPS4K_ICACHE_REFILL_WAR) { |
794 | __asm__ __volatile__ ( | |
795 | ".set push\n\t" | |
796 | ".set noat\n\t" | |
4ee48627 | 797 | ".set "MIPS_ISA_LEVEL"\n\t" |
875d43e7 | 798 | #ifdef CONFIG_32BIT |
1da177e4 LT |
799 | "la $at,1f\n\t" |
800 | #endif | |
875d43e7 | 801 | #ifdef CONFIG_64BIT |
1da177e4 LT |
802 | "dla $at,1f\n\t" |
803 | #endif | |
804 | "cache %0,($at)\n\t" | |
805 | "nop; nop; nop\n" | |
806 | "1:\n\t" | |
807 | ".set pop" | |
808 | : | |
809 | : "i" (Hit_Invalidate_I)); | |
810 | } | |
811 | if (MIPS_CACHE_SYNC_WAR) | |
812 | __asm__ __volatile__ ("sync"); | |
813 | } | |
814 | ||
815 | static void r4k_flush_cache_sigtramp(unsigned long addr) | |
816 | { | |
48a26e60 | 817 | r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr); |
1da177e4 LT |
818 | } |
819 | ||
820 | static void r4k_flush_icache_all(void) | |
821 | { | |
822 | if (cpu_has_vtag_icache) | |
823 | r4k_blast_icache(); | |
824 | } | |
825 | ||
d9cdc901 RB |
826 | struct flush_kernel_vmap_range_args { |
827 | unsigned long vaddr; | |
828 | int size; | |
829 | }; | |
830 | ||
831 | static inline void local_r4k_flush_kernel_vmap_range(void *args) | |
832 | { | |
833 | struct flush_kernel_vmap_range_args *vmra = args; | |
834 | unsigned long vaddr = vmra->vaddr; | |
835 | int size = vmra->size; | |
836 | ||
837 | /* | |
838 | * Aliases only affect the primary caches so don't bother with | |
839 | * S-caches or T-caches. | |
840 | */ | |
841 | if (cpu_has_safe_index_cacheops && size >= dcache_size) | |
842 | r4k_blast_dcache(); | |
843 | else { | |
844 | R4600_HIT_CACHEOP_WAR_IMPL; | |
845 | blast_dcache_range(vaddr, vaddr + size); | |
846 | } | |
847 | } | |
848 | ||
849 | static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size) | |
850 | { | |
851 | struct flush_kernel_vmap_range_args args; | |
852 | ||
853 | args.vaddr = (unsigned long) vaddr; | |
854 | args.size = size; | |
855 | ||
856 | r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range, &args); | |
857 | } | |
858 | ||
1da177e4 LT |
859 | static inline void rm7k_erratum31(void) |
860 | { | |
861 | const unsigned long ic_lsize = 32; | |
862 | unsigned long addr; | |
863 | ||
864 | /* RM7000 erratum #31. The icache is screwed at startup. */ | |
865 | write_c0_taglo(0); | |
866 | write_c0_taghi(0); | |
867 | ||
868 | for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) { | |
869 | __asm__ __volatile__ ( | |
d8748a3a | 870 | ".set push\n\t" |
1da177e4 LT |
871 | ".set noreorder\n\t" |
872 | ".set mips3\n\t" | |
873 | "cache\t%1, 0(%0)\n\t" | |
874 | "cache\t%1, 0x1000(%0)\n\t" | |
875 | "cache\t%1, 0x2000(%0)\n\t" | |
876 | "cache\t%1, 0x3000(%0)\n\t" | |
877 | "cache\t%2, 0(%0)\n\t" | |
878 | "cache\t%2, 0x1000(%0)\n\t" | |
879 | "cache\t%2, 0x2000(%0)\n\t" | |
880 | "cache\t%2, 0x3000(%0)\n\t" | |
881 | "cache\t%1, 0(%0)\n\t" | |
882 | "cache\t%1, 0x1000(%0)\n\t" | |
883 | "cache\t%1, 0x2000(%0)\n\t" | |
884 | "cache\t%1, 0x3000(%0)\n\t" | |
d8748a3a | 885 | ".set pop\n" |
1da177e4 LT |
886 | : |
887 | : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill)); | |
888 | } | |
889 | } | |
890 | ||
006a851b SH |
891 | static inline void alias_74k_erratum(struct cpuinfo_mips *c) |
892 | { | |
9213ad77 MR |
893 | unsigned int imp = c->processor_id & PRID_IMP_MASK; |
894 | unsigned int rev = c->processor_id & PRID_REV_MASK; | |
895 | ||
006a851b SH |
896 | /* |
897 | * Early versions of the 74K do not update the cache tags on a | |
898 | * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG | |
899 | * aliases. In this case it is better to treat the cache as always | |
900 | * having aliases. | |
901 | */ | |
9213ad77 MR |
902 | switch (imp) { |
903 | case PRID_IMP_74K: | |
904 | if (rev <= PRID_REV_ENCODE_332(2, 4, 0)) | |
905 | c->dcache.flags |= MIPS_CACHE_VTAG; | |
906 | if (rev == PRID_REV_ENCODE_332(2, 4, 0)) | |
907 | write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); | |
908 | break; | |
909 | case PRID_IMP_1074K: | |
910 | if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) { | |
911 | c->dcache.flags |= MIPS_CACHE_VTAG; | |
912 | write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); | |
913 | } | |
914 | break; | |
915 | default: | |
916 | BUG(); | |
006a851b SH |
917 | } |
918 | } | |
919 | ||
d74b0172 KC |
920 | static void b5k_instruction_hazard(void) |
921 | { | |
922 | __sync(); | |
923 | __sync(); | |
924 | __asm__ __volatile__( | |
925 | " nop; nop; nop; nop; nop; nop; nop; nop\n" | |
926 | " nop; nop; nop; nop; nop; nop; nop; nop\n" | |
927 | " nop; nop; nop; nop; nop; nop; nop; nop\n" | |
928 | " nop; nop; nop; nop; nop; nop; nop; nop\n" | |
929 | : : : "memory"); | |
930 | } | |
931 | ||
078a55fc | 932 | static char *way_string[] = { NULL, "direct mapped", "2-way", |
1da177e4 LT |
933 | "3-way", "4-way", "5-way", "6-way", "7-way", "8-way" |
934 | }; | |
935 | ||
078a55fc | 936 | static void probe_pcache(void) |
1da177e4 LT |
937 | { |
938 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
939 | unsigned int config = read_c0_config(); | |
940 | unsigned int prid = read_c0_prid(); | |
941 | unsigned long config1; | |
942 | unsigned int lsize; | |
943 | ||
69f24d17 | 944 | switch (current_cpu_type()) { |
1da177e4 LT |
945 | case CPU_R4600: /* QED style two way caches? */ |
946 | case CPU_R4700: | |
947 | case CPU_R5000: | |
948 | case CPU_NEVADA: | |
949 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
950 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
951 | c->icache.ways = 2; | |
3c68da79 | 952 | c->icache.waybit = __ffs(icache_size/2); |
1da177e4 LT |
953 | |
954 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
955 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
956 | c->dcache.ways = 2; | |
3c68da79 | 957 | c->dcache.waybit= __ffs(dcache_size/2); |
1da177e4 LT |
958 | |
959 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
960 | break; | |
961 | ||
962 | case CPU_R5432: | |
963 | case CPU_R5500: | |
964 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
965 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
966 | c->icache.ways = 2; | |
967 | c->icache.waybit= 0; | |
968 | ||
969 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
970 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
971 | c->dcache.ways = 2; | |
972 | c->dcache.waybit = 0; | |
973 | ||
5864810b | 974 | c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH; |
1da177e4 LT |
975 | break; |
976 | ||
977 | case CPU_TX49XX: | |
978 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
979 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
980 | c->icache.ways = 4; | |
981 | c->icache.waybit= 0; | |
982 | ||
983 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
984 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
985 | c->dcache.ways = 4; | |
986 | c->dcache.waybit = 0; | |
987 | ||
988 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
de862b48 | 989 | c->options |= MIPS_CPU_PREFETCH; |
1da177e4 LT |
990 | break; |
991 | ||
992 | case CPU_R4000PC: | |
993 | case CPU_R4000SC: | |
994 | case CPU_R4000MC: | |
995 | case CPU_R4400PC: | |
996 | case CPU_R4400SC: | |
997 | case CPU_R4400MC: | |
998 | case CPU_R4300: | |
999 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
1000 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
1001 | c->icache.ways = 1; | |
70342287 | 1002 | c->icache.waybit = 0; /* doesn't matter */ |
1da177e4 LT |
1003 | |
1004 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
1005 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
1006 | c->dcache.ways = 1; | |
1007 | c->dcache.waybit = 0; /* does not matter */ | |
1008 | ||
1009 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
1010 | break; | |
1011 | ||
1012 | case CPU_R10000: | |
1013 | case CPU_R12000: | |
44d921b2 | 1014 | case CPU_R14000: |
1da177e4 LT |
1015 | icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29)); |
1016 | c->icache.linesz = 64; | |
1017 | c->icache.ways = 2; | |
1018 | c->icache.waybit = 0; | |
1019 | ||
1020 | dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26)); | |
1021 | c->dcache.linesz = 32; | |
1022 | c->dcache.ways = 2; | |
1023 | c->dcache.waybit = 0; | |
1024 | ||
1025 | c->options |= MIPS_CPU_PREFETCH; | |
1026 | break; | |
1027 | ||
1028 | case CPU_VR4133: | |
2874fe55 | 1029 | write_c0_config(config & ~VR41_CONF_P4K); |
1da177e4 LT |
1030 | case CPU_VR4131: |
1031 | /* Workaround for cache instruction bug of VR4131 */ | |
1032 | if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || | |
1033 | c->processor_id == 0x0c82U) { | |
4e8ab361 YY |
1034 | config |= 0x00400000U; |
1035 | if (c->processor_id == 0x0c80U) | |
1036 | config |= VR41_CONF_BP; | |
1da177e4 | 1037 | write_c0_config(config); |
1058ecda YY |
1038 | } else |
1039 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
1040 | ||
1da177e4 LT |
1041 | icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); |
1042 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
1043 | c->icache.ways = 2; | |
3c68da79 | 1044 | c->icache.waybit = __ffs(icache_size/2); |
1da177e4 LT |
1045 | |
1046 | dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); | |
1047 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
1048 | c->dcache.ways = 2; | |
3c68da79 | 1049 | c->dcache.waybit = __ffs(dcache_size/2); |
1da177e4 LT |
1050 | break; |
1051 | ||
1052 | case CPU_VR41XX: | |
1053 | case CPU_VR4111: | |
1054 | case CPU_VR4121: | |
1055 | case CPU_VR4122: | |
1056 | case CPU_VR4181: | |
1057 | case CPU_VR4181A: | |
1058 | icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); | |
1059 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
1060 | c->icache.ways = 1; | |
70342287 | 1061 | c->icache.waybit = 0; /* doesn't matter */ |
1da177e4 LT |
1062 | |
1063 | dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); | |
1064 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
1065 | c->dcache.ways = 1; | |
1066 | c->dcache.waybit = 0; /* does not matter */ | |
1067 | ||
1068 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
1069 | break; | |
1070 | ||
1071 | case CPU_RM7000: | |
1072 | rm7k_erratum31(); | |
1073 | ||
1da177e4 LT |
1074 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); |
1075 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
1076 | c->icache.ways = 4; | |
3c68da79 | 1077 | c->icache.waybit = __ffs(icache_size / c->icache.ways); |
1da177e4 LT |
1078 | |
1079 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
1080 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
1081 | c->dcache.ways = 4; | |
3c68da79 | 1082 | c->dcache.waybit = __ffs(dcache_size / c->dcache.ways); |
1da177e4 | 1083 | |
1da177e4 | 1084 | c->options |= MIPS_CPU_CACHE_CDEX_P; |
1da177e4 LT |
1085 | c->options |= MIPS_CPU_PREFETCH; |
1086 | break; | |
1087 | ||
2a21c730 FZ |
1088 | case CPU_LOONGSON2: |
1089 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
1090 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
1091 | if (prid & 0x3) | |
1092 | c->icache.ways = 4; | |
1093 | else | |
1094 | c->icache.ways = 2; | |
1095 | c->icache.waybit = 0; | |
1096 | ||
1097 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
1098 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
1099 | if (prid & 0x3) | |
1100 | c->dcache.ways = 4; | |
1101 | else | |
1102 | c->dcache.ways = 2; | |
1103 | c->dcache.waybit = 0; | |
1104 | break; | |
1105 | ||
c579d310 HC |
1106 | case CPU_LOONGSON3: |
1107 | config1 = read_c0_config1(); | |
1108 | lsize = (config1 >> 19) & 7; | |
1109 | if (lsize) | |
1110 | c->icache.linesz = 2 << lsize; | |
1111 | else | |
1112 | c->icache.linesz = 0; | |
1113 | c->icache.sets = 64 << ((config1 >> 22) & 7); | |
1114 | c->icache.ways = 1 + ((config1 >> 16) & 7); | |
1115 | icache_size = c->icache.sets * | |
1116 | c->icache.ways * | |
1117 | c->icache.linesz; | |
1118 | c->icache.waybit = 0; | |
1119 | ||
1120 | lsize = (config1 >> 10) & 7; | |
1121 | if (lsize) | |
1122 | c->dcache.linesz = 2 << lsize; | |
1123 | else | |
1124 | c->dcache.linesz = 0; | |
1125 | c->dcache.sets = 64 << ((config1 >> 13) & 7); | |
1126 | c->dcache.ways = 1 + ((config1 >> 7) & 7); | |
1127 | dcache_size = c->dcache.sets * | |
1128 | c->dcache.ways * | |
1129 | c->dcache.linesz; | |
1130 | c->dcache.waybit = 0; | |
1131 | break; | |
1132 | ||
18a8cd63 DD |
1133 | case CPU_CAVIUM_OCTEON3: |
1134 | /* For now lie about the number of ways. */ | |
1135 | c->icache.linesz = 128; | |
1136 | c->icache.sets = 16; | |
1137 | c->icache.ways = 8; | |
1138 | c->icache.flags |= MIPS_CACHE_VTAG; | |
1139 | icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; | |
1140 | ||
1141 | c->dcache.linesz = 128; | |
1142 | c->dcache.ways = 8; | |
1143 | c->dcache.sets = 8; | |
1144 | dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; | |
1145 | c->options |= MIPS_CPU_PREFETCH; | |
1146 | break; | |
1147 | ||
1da177e4 LT |
1148 | default: |
1149 | if (!(config & MIPS_CONF_M)) | |
1150 | panic("Don't know how to probe P-caches on this cpu."); | |
1151 | ||
1152 | /* | |
1153 | * So we seem to be a MIPS32 or MIPS64 CPU | |
1154 | * So let's probe the I-cache ... | |
1155 | */ | |
1156 | config1 = read_c0_config1(); | |
1157 | ||
175cba8c MC |
1158 | lsize = (config1 >> 19) & 7; |
1159 | ||
1160 | /* IL == 7 is reserved */ | |
1161 | if (lsize == 7) | |
1162 | panic("Invalid icache line size"); | |
1163 | ||
1164 | c->icache.linesz = lsize ? 2 << lsize : 0; | |
1165 | ||
dc34b05f | 1166 | c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); |
1da177e4 LT |
1167 | c->icache.ways = 1 + ((config1 >> 16) & 7); |
1168 | ||
1169 | icache_size = c->icache.sets * | |
70342287 RB |
1170 | c->icache.ways * |
1171 | c->icache.linesz; | |
3c68da79 | 1172 | c->icache.waybit = __ffs(icache_size/c->icache.ways); |
1da177e4 LT |
1173 | |
1174 | if (config & 0x8) /* VI bit */ | |
1175 | c->icache.flags |= MIPS_CACHE_VTAG; | |
1176 | ||
1177 | /* | |
1178 | * Now probe the MIPS32 / MIPS64 data cache. | |
1179 | */ | |
1180 | c->dcache.flags = 0; | |
1181 | ||
175cba8c MC |
1182 | lsize = (config1 >> 10) & 7; |
1183 | ||
1184 | /* DL == 7 is reserved */ | |
1185 | if (lsize == 7) | |
1186 | panic("Invalid dcache line size"); | |
1187 | ||
1188 | c->dcache.linesz = lsize ? 2 << lsize : 0; | |
1189 | ||
dc34b05f | 1190 | c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); |
1da177e4 LT |
1191 | c->dcache.ways = 1 + ((config1 >> 7) & 7); |
1192 | ||
1193 | dcache_size = c->dcache.sets * | |
70342287 RB |
1194 | c->dcache.ways * |
1195 | c->dcache.linesz; | |
3c68da79 | 1196 | c->dcache.waybit = __ffs(dcache_size/c->dcache.ways); |
1da177e4 LT |
1197 | |
1198 | c->options |= MIPS_CPU_PREFETCH; | |
1199 | break; | |
1200 | } | |
1201 | ||
1202 | /* | |
1203 | * Processor configuration sanity check for the R4000SC erratum | |
70342287 | 1204 | * #5. With page sizes larger than 32kB there is no possibility |
1da177e4 LT |
1205 | * to get a VCE exception anymore so we don't care about this |
1206 | * misconfiguration. The case is rather theoretical anyway; | |
1207 | * presumably no vendor is shipping his hardware in the "bad" | |
1208 | * configuration. | |
1209 | */ | |
8ff374b9 MR |
1210 | if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 && |
1211 | (prid & PRID_REV_MASK) < PRID_REV_R4400 && | |
1da177e4 LT |
1212 | !(config & CONF_SC) && c->icache.linesz != 16 && |
1213 | PAGE_SIZE <= 0x8000) | |
1214 | panic("Improper R4000SC processor configuration detected"); | |
1215 | ||
1216 | /* compute a couple of other cache variables */ | |
1217 | c->icache.waysize = icache_size / c->icache.ways; | |
1218 | c->dcache.waysize = dcache_size / c->dcache.ways; | |
1219 | ||
73f40352 CD |
1220 | c->icache.sets = c->icache.linesz ? |
1221 | icache_size / (c->icache.linesz * c->icache.ways) : 0; | |
1222 | c->dcache.sets = c->dcache.linesz ? | |
1223 | dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; | |
1da177e4 LT |
1224 | |
1225 | /* | |
1226 | * R10000 and R12000 P-caches are odd in a positive way. They're 32kB | |
1227 | * 2-way virtually indexed so normally would suffer from aliases. So | |
1228 | * normally they'd suffer from aliases but magic in the hardware deals | |
1229 | * with that for us so we don't need to take care ourselves. | |
1230 | */ | |
69f24d17 | 1231 | switch (current_cpu_type()) { |
a95970f3 | 1232 | case CPU_20KC: |
505403b6 | 1233 | case CPU_25KF: |
641e97f3 RB |
1234 | case CPU_SB1: |
1235 | case CPU_SB1A: | |
efa0f81c | 1236 | case CPU_XLR: |
de62893b | 1237 | c->dcache.flags |= MIPS_CACHE_PINDEX; |
641e97f3 RB |
1238 | break; |
1239 | ||
d1e344e5 RB |
1240 | case CPU_R10000: |
1241 | case CPU_R12000: | |
44d921b2 | 1242 | case CPU_R14000: |
d1e344e5 | 1243 | break; |
641e97f3 | 1244 | |
bf4aac07 MR |
1245 | case CPU_74K: |
1246 | case CPU_1074K: | |
1247 | alias_74k_erratum(c); | |
1248 | /* Fall through. */ | |
113c62d9 | 1249 | case CPU_M14KC: |
f8fa4811 | 1250 | case CPU_M14KEC: |
d1e344e5 | 1251 | case CPU_24K: |
98a41de9 | 1252 | case CPU_34K: |
39b8d525 | 1253 | case CPU_1004K: |
26ab96df | 1254 | case CPU_INTERAPTIV: |
aced4cbd | 1255 | case CPU_P5600: |
708ac4b8 | 1256 | case CPU_PROAPTIV: |
f36c4720 | 1257 | case CPU_M5150: |
4695089f | 1258 | case CPU_QEMU_GENERIC: |
02dc6bfb MC |
1259 | if (!(read_c0_config7() & MIPS_CONF7_IAR) && |
1260 | (c->icache.waysize > PAGE_SIZE)) | |
1261 | c->icache.flags |= MIPS_CACHE_ALIASES; | |
1262 | if (read_c0_config7() & MIPS_CONF7_AR) { | |
1263 | /* | |
1264 | * Effectively physically indexed dcache, | |
1265 | * thus no virtual aliases. | |
1266 | */ | |
beab375a RB |
1267 | c->dcache.flags |= MIPS_CACHE_PINDEX; |
1268 | break; | |
1269 | } | |
d1e344e5 | 1270 | default: |
beab375a RB |
1271 | if (c->dcache.waysize > PAGE_SIZE) |
1272 | c->dcache.flags |= MIPS_CACHE_ALIASES; | |
d1e344e5 | 1273 | } |
1da177e4 | 1274 | |
69f24d17 | 1275 | switch (current_cpu_type()) { |
1da177e4 LT |
1276 | case CPU_20KC: |
1277 | /* | |
1278 | * Some older 20Kc chips doesn't have the 'VI' bit in | |
1279 | * the config register. | |
1280 | */ | |
1281 | c->icache.flags |= MIPS_CACHE_VTAG; | |
1282 | break; | |
1283 | ||
270717a8 | 1284 | case CPU_ALCHEMY: |
1da177e4 LT |
1285 | c->icache.flags |= MIPS_CACHE_IC_F_DC; |
1286 | break; | |
1da177e4 | 1287 | |
14bd8c08 RB |
1288 | case CPU_LOONGSON2: |
1289 | /* | |
1290 | * LOONGSON2 has 4 way icache, but when using indexed cache op, | |
1291 | * one op will act on all 4 ways | |
1292 | */ | |
1293 | c->icache.ways = 1; | |
1294 | } | |
2a21c730 | 1295 | |
1da177e4 LT |
1296 | printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", |
1297 | icache_size >> 10, | |
7fc7316a | 1298 | c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", |
1da177e4 LT |
1299 | way_string[c->icache.ways], c->icache.linesz); |
1300 | ||
64bfca5c RB |
1301 | printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", |
1302 | dcache_size >> 10, way_string[c->dcache.ways], | |
1303 | (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT", | |
1304 | (c->dcache.flags & MIPS_CACHE_ALIASES) ? | |
1305 | "cache aliases" : "no aliases", | |
1306 | c->dcache.linesz); | |
1da177e4 LT |
1307 | } |
1308 | ||
1309 | /* | |
1310 | * If you even _breathe_ on this function, look at the gcc output and make sure | |
1311 | * it does not pop things on and off the stack for the cache sizing loop that | |
1312 | * executes in KSEG1 space or else you will crash and burn badly. You have | |
1313 | * been warned. | |
1314 | */ | |
078a55fc | 1315 | static int probe_scache(void) |
1da177e4 | 1316 | { |
1da177e4 LT |
1317 | unsigned long flags, addr, begin, end, pow2; |
1318 | unsigned int config = read_c0_config(); | |
1319 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1da177e4 LT |
1320 | |
1321 | if (config & CONF_SC) | |
1322 | return 0; | |
1323 | ||
e001e528 | 1324 | begin = (unsigned long) &_stext; |
1da177e4 LT |
1325 | begin &= ~((4 * 1024 * 1024) - 1); |
1326 | end = begin + (4 * 1024 * 1024); | |
1327 | ||
1328 | /* | |
1329 | * This is such a bitch, you'd think they would make it easy to do | |
1330 | * this. Away you daemons of stupidity! | |
1331 | */ | |
1332 | local_irq_save(flags); | |
1333 | ||
1334 | /* Fill each size-multiple cache line with a valid tag. */ | |
1335 | pow2 = (64 * 1024); | |
1336 | for (addr = begin; addr < end; addr = (begin + pow2)) { | |
1337 | unsigned long *p = (unsigned long *) addr; | |
1338 | __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */ | |
1339 | pow2 <<= 1; | |
1340 | } | |
1341 | ||
1342 | /* Load first line with zero (therefore invalid) tag. */ | |
1343 | write_c0_taglo(0); | |
1344 | write_c0_taghi(0); | |
1345 | __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */ | |
1346 | cache_op(Index_Store_Tag_I, begin); | |
1347 | cache_op(Index_Store_Tag_D, begin); | |
1348 | cache_op(Index_Store_Tag_SD, begin); | |
1349 | ||
1350 | /* Now search for the wrap around point. */ | |
1351 | pow2 = (128 * 1024); | |
1da177e4 LT |
1352 | for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) { |
1353 | cache_op(Index_Load_Tag_SD, addr); | |
1354 | __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */ | |
1355 | if (!read_c0_taglo()) | |
1356 | break; | |
1357 | pow2 <<= 1; | |
1358 | } | |
1359 | local_irq_restore(flags); | |
1360 | addr -= begin; | |
1361 | ||
1362 | scache_size = addr; | |
1363 | c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22); | |
1364 | c->scache.ways = 1; | |
1365 | c->dcache.waybit = 0; /* does not matter */ | |
1366 | ||
1367 | return 1; | |
1368 | } | |
1369 | ||
2a21c730 FZ |
1370 | static void __init loongson2_sc_init(void) |
1371 | { | |
1372 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1373 | ||
1374 | scache_size = 512*1024; | |
1375 | c->scache.linesz = 32; | |
1376 | c->scache.ways = 4; | |
1377 | c->scache.waybit = 0; | |
1378 | c->scache.waysize = scache_size / (c->scache.ways); | |
1379 | c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); | |
1380 | pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", | |
1381 | scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); | |
1382 | ||
1383 | c->options |= MIPS_CPU_INCLUSIVE_CACHES; | |
1384 | } | |
2a21c730 | 1385 | |
c579d310 HC |
1386 | static void __init loongson3_sc_init(void) |
1387 | { | |
1388 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1389 | unsigned int config2, lsize; | |
1390 | ||
1391 | config2 = read_c0_config2(); | |
1392 | lsize = (config2 >> 4) & 15; | |
1393 | if (lsize) | |
1394 | c->scache.linesz = 2 << lsize; | |
1395 | else | |
1396 | c->scache.linesz = 0; | |
1397 | c->scache.sets = 64 << ((config2 >> 8) & 15); | |
1398 | c->scache.ways = 1 + (config2 & 15); | |
1399 | ||
1400 | scache_size = c->scache.sets * | |
1401 | c->scache.ways * | |
1402 | c->scache.linesz; | |
1403 | /* Loongson-3 has 4 cores, 1MB scache for each. scaches are shared */ | |
1404 | scache_size *= 4; | |
1405 | c->scache.waybit = 0; | |
1406 | pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", | |
1407 | scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); | |
1408 | if (scache_size) | |
1409 | c->options |= MIPS_CPU_INCLUSIVE_CACHES; | |
1410 | return; | |
1411 | } | |
1412 | ||
1da177e4 LT |
1413 | extern int r5k_sc_init(void); |
1414 | extern int rm7k_sc_init(void); | |
9318c51a | 1415 | extern int mips_sc_init(void); |
1da177e4 | 1416 | |
078a55fc | 1417 | static void setup_scache(void) |
1da177e4 LT |
1418 | { |
1419 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1420 | unsigned int config = read_c0_config(); | |
1da177e4 LT |
1421 | int sc_present = 0; |
1422 | ||
1423 | /* | |
1424 | * Do the probing thing on R4000SC and R4400SC processors. Other | |
1425 | * processors don't have a S-cache that would be relevant to the | |
603e82ed | 1426 | * Linux memory management. |
1da177e4 | 1427 | */ |
69f24d17 | 1428 | switch (current_cpu_type()) { |
1da177e4 LT |
1429 | case CPU_R4000SC: |
1430 | case CPU_R4000MC: | |
1431 | case CPU_R4400SC: | |
1432 | case CPU_R4400MC: | |
ba5187db | 1433 | sc_present = run_uncached(probe_scache); |
1da177e4 LT |
1434 | if (sc_present) |
1435 | c->options |= MIPS_CPU_CACHE_CDEX_S; | |
1436 | break; | |
1437 | ||
1438 | case CPU_R10000: | |
1439 | case CPU_R12000: | |
44d921b2 | 1440 | case CPU_R14000: |
1da177e4 LT |
1441 | scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16); |
1442 | c->scache.linesz = 64 << ((config >> 13) & 1); | |
1443 | c->scache.ways = 2; | |
1444 | c->scache.waybit= 0; | |
1445 | sc_present = 1; | |
1446 | break; | |
1447 | ||
1448 | case CPU_R5000: | |
1449 | case CPU_NEVADA: | |
1450 | #ifdef CONFIG_R5000_CPU_SCACHE | |
1451 | r5k_sc_init(); | |
1452 | #endif | |
70342287 | 1453 | return; |
1da177e4 LT |
1454 | |
1455 | case CPU_RM7000: | |
1da177e4 LT |
1456 | #ifdef CONFIG_RM7000_CPU_SCACHE |
1457 | rm7k_sc_init(); | |
1458 | #endif | |
1459 | return; | |
1460 | ||
2a21c730 FZ |
1461 | case CPU_LOONGSON2: |
1462 | loongson2_sc_init(); | |
1463 | return; | |
14bd8c08 | 1464 | |
c579d310 HC |
1465 | case CPU_LOONGSON3: |
1466 | loongson3_sc_init(); | |
1467 | return; | |
1468 | ||
18a8cd63 | 1469 | case CPU_CAVIUM_OCTEON3: |
a3d4fb2d J |
1470 | case CPU_XLP: |
1471 | /* don't need to worry about L2, fully coherent */ | |
1472 | return; | |
2a21c730 | 1473 | |
1da177e4 | 1474 | default: |
adb37892 DCZ |
1475 | if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | |
1476 | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) { | |
9318c51a CD |
1477 | #ifdef CONFIG_MIPS_CPU_SCACHE |
1478 | if (mips_sc_init ()) { | |
1479 | scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; | |
1480 | printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n", | |
1481 | scache_size >> 10, | |
1482 | way_string[c->scache.ways], c->scache.linesz); | |
1483 | } | |
1484 | #else | |
1485 | if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) | |
1486 | panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); | |
1487 | #endif | |
1488 | return; | |
1489 | } | |
1da177e4 LT |
1490 | sc_present = 0; |
1491 | } | |
1492 | ||
1493 | if (!sc_present) | |
1494 | return; | |
1495 | ||
1da177e4 LT |
1496 | /* compute a couple of other cache variables */ |
1497 | c->scache.waysize = scache_size / c->scache.ways; | |
1498 | ||
1499 | c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); | |
1500 | ||
1501 | printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n", | |
1502 | scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); | |
1503 | ||
fc5d2d27 | 1504 | c->options |= MIPS_CPU_INCLUSIVE_CACHES; |
1da177e4 LT |
1505 | } |
1506 | ||
9370b351 SS |
1507 | void au1x00_fixup_config_od(void) |
1508 | { | |
1509 | /* | |
1510 | * c0_config.od (bit 19) was write only (and read as 0) | |
1511 | * on the early revisions of Alchemy SOCs. It disables the bus | |
1512 | * transaction overlapping and needs to be set to fix various errata. | |
1513 | */ | |
1514 | switch (read_c0_prid()) { | |
1515 | case 0x00030100: /* Au1000 DA */ | |
1516 | case 0x00030201: /* Au1000 HA */ | |
1517 | case 0x00030202: /* Au1000 HB */ | |
1518 | case 0x01030200: /* Au1500 AB */ | |
1519 | /* | |
1520 | * Au1100 errata actually keeps silence about this bit, so we set it | |
1521 | * just in case for those revisions that require it to be set according | |
270717a8 | 1522 | * to the (now gone) cpu table. |
9370b351 SS |
1523 | */ |
1524 | case 0x02030200: /* Au1100 AB */ | |
1525 | case 0x02030201: /* Au1100 BA */ | |
1526 | case 0x02030202: /* Au1100 BC */ | |
1527 | set_c0_config(1 << 19); | |
1528 | break; | |
1529 | } | |
1530 | } | |
1531 | ||
89052bd7 RB |
1532 | /* CP0 hazard avoidance. */ |
1533 | #define NXP_BARRIER() \ | |
1534 | __asm__ __volatile__( \ | |
1535 | ".set noreorder\n\t" \ | |
1536 | "nop; nop; nop; nop; nop; nop;\n\t" \ | |
1537 | ".set reorder\n\t") | |
1538 | ||
1539 | static void nxp_pr4450_fixup_config(void) | |
1540 | { | |
1541 | unsigned long config0; | |
1542 | ||
1543 | config0 = read_c0_config(); | |
1544 | ||
1545 | /* clear all three cache coherency fields */ | |
1546 | config0 &= ~(0x7 | (7 << 25) | (7 << 28)); | |
1547 | config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) | | |
1548 | ((_page_cachable_default >> _CACHE_SHIFT) << 25) | | |
1549 | ((_page_cachable_default >> _CACHE_SHIFT) << 28)); | |
1550 | write_c0_config(config0); | |
1551 | NXP_BARRIER(); | |
1552 | } | |
1553 | ||
078a55fc | 1554 | static int cca = -1; |
35133692 CD |
1555 | |
1556 | static int __init cca_setup(char *str) | |
1557 | { | |
1558 | get_option(&str, &cca); | |
1559 | ||
b5b64f2b | 1560 | return 0; |
35133692 CD |
1561 | } |
1562 | ||
b5b64f2b | 1563 | early_param("cca", cca_setup); |
35133692 | 1564 | |
078a55fc | 1565 | static void coherency_setup(void) |
1da177e4 | 1566 | { |
35133692 CD |
1567 | if (cca < 0 || cca > 7) |
1568 | cca = read_c0_config() & CONF_CM_CMASK; | |
1569 | _page_cachable_default = cca << _CACHE_SHIFT; | |
1570 | ||
1571 | pr_debug("Using cache attribute %d\n", cca); | |
1572 | change_c0_config(CONF_CM_CMASK, cca); | |
1da177e4 LT |
1573 | |
1574 | /* | |
1575 | * c0_status.cu=0 specifies that updates by the sc instruction use | |
1576 | * the coherency mode specified by the TLB; 1 means cachable | |
1577 | * coherent update on write will be used. Not all processors have | |
1578 | * this bit and; some wire it to zero, others like Toshiba had the | |
1579 | * silly idea of putting something else there ... | |
1580 | */ | |
10cc3529 | 1581 | switch (current_cpu_type()) { |
1da177e4 LT |
1582 | case CPU_R4000PC: |
1583 | case CPU_R4000SC: | |
1584 | case CPU_R4000MC: | |
1585 | case CPU_R4400PC: | |
1586 | case CPU_R4400SC: | |
1587 | case CPU_R4400MC: | |
1588 | clear_c0_config(CONF_CU); | |
1589 | break; | |
9370b351 | 1590 | /* |
df586d59 | 1591 | * We need to catch the early Alchemy SOCs with |
270717a8 ML |
1592 | * the write-only co_config.od bit and set it back to one on: |
1593 | * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB | |
9370b351 | 1594 | */ |
270717a8 | 1595 | case CPU_ALCHEMY: |
9370b351 SS |
1596 | au1x00_fixup_config_od(); |
1597 | break; | |
89052bd7 RB |
1598 | |
1599 | case PRID_IMP_PR4450: | |
1600 | nxp_pr4450_fixup_config(); | |
1601 | break; | |
1da177e4 LT |
1602 | } |
1603 | } | |
1604 | ||
078a55fc | 1605 | static void r4k_cache_error_setup(void) |
1da177e4 | 1606 | { |
641e97f3 RB |
1607 | extern char __weak except_vec2_generic; |
1608 | extern char __weak except_vec2_sb1; | |
1da177e4 | 1609 | |
69f24d17 | 1610 | switch (current_cpu_type()) { |
641e97f3 RB |
1611 | case CPU_SB1: |
1612 | case CPU_SB1A: | |
1613 | set_uncached_handler(0x100, &except_vec2_sb1, 0x80); | |
1614 | break; | |
1615 | ||
1616 | default: | |
1617 | set_uncached_handler(0x100, &except_vec2_generic, 0x80); | |
1618 | break; | |
1619 | } | |
9cd9669b DD |
1620 | } |
1621 | ||
078a55fc | 1622 | void r4k_cache_init(void) |
9cd9669b DD |
1623 | { |
1624 | extern void build_clear_page(void); | |
1625 | extern void build_copy_page(void); | |
1626 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1da177e4 LT |
1627 | |
1628 | probe_pcache(); | |
1629 | setup_scache(); | |
1630 | ||
1da177e4 LT |
1631 | r4k_blast_dcache_page_setup(); |
1632 | r4k_blast_dcache_page_indexed_setup(); | |
1633 | r4k_blast_dcache_setup(); | |
1634 | r4k_blast_icache_page_setup(); | |
1635 | r4k_blast_icache_page_indexed_setup(); | |
1636 | r4k_blast_icache_setup(); | |
1637 | r4k_blast_scache_page_setup(); | |
1638 | r4k_blast_scache_page_indexed_setup(); | |
1639 | r4k_blast_scache_setup(); | |
4caa906e LY |
1640 | #ifdef CONFIG_EVA |
1641 | r4k_blast_dcache_user_page_setup(); | |
1642 | r4k_blast_icache_user_page_setup(); | |
1643 | #endif | |
1da177e4 LT |
1644 | |
1645 | /* | |
1646 | * Some MIPS32 and MIPS64 processors have physically indexed caches. | |
1647 | * This code supports virtually indexed processors and will be | |
1648 | * unnecessarily inefficient on physically indexed processors. | |
1649 | */ | |
73f40352 CD |
1650 | if (c->dcache.linesz) |
1651 | shm_align_mask = max_t( unsigned long, | |
1652 | c->dcache.sets * c->dcache.linesz - 1, | |
1653 | PAGE_SIZE - 1); | |
1654 | else | |
1655 | shm_align_mask = PAGE_SIZE-1; | |
9c5a3d72 RB |
1656 | |
1657 | __flush_cache_vmap = r4k__flush_cache_vmap; | |
1658 | __flush_cache_vunmap = r4k__flush_cache_vunmap; | |
1659 | ||
db813fe5 | 1660 | flush_cache_all = cache_noop; |
1da177e4 LT |
1661 | __flush_cache_all = r4k___flush_cache_all; |
1662 | flush_cache_mm = r4k_flush_cache_mm; | |
1663 | flush_cache_page = r4k_flush_cache_page; | |
1da177e4 LT |
1664 | flush_cache_range = r4k_flush_cache_range; |
1665 | ||
d9cdc901 RB |
1666 | __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range; |
1667 | ||
1da177e4 LT |
1668 | flush_cache_sigtramp = r4k_flush_cache_sigtramp; |
1669 | flush_icache_all = r4k_flush_icache_all; | |
7e3bfc7c | 1670 | local_flush_data_cache_page = local_r4k_flush_data_cache_page; |
1da177e4 LT |
1671 | flush_data_cache_page = r4k_flush_data_cache_page; |
1672 | flush_icache_range = r4k_flush_icache_range; | |
e0cee3ee | 1673 | local_flush_icache_range = local_r4k_flush_icache_range; |
1da177e4 | 1674 | |
8005711c | 1675 | #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT) |
39b8d525 RB |
1676 | if (coherentio) { |
1677 | _dma_cache_wback_inv = (void *)cache_noop; | |
1678 | _dma_cache_wback = (void *)cache_noop; | |
1679 | _dma_cache_inv = (void *)cache_noop; | |
1680 | } else { | |
1681 | _dma_cache_wback_inv = r4k_dma_cache_wback_inv; | |
1682 | _dma_cache_wback = r4k_dma_cache_wback_inv; | |
1683 | _dma_cache_inv = r4k_dma_cache_inv; | |
1684 | } | |
1da177e4 LT |
1685 | #endif |
1686 | ||
1da177e4 LT |
1687 | build_clear_page(); |
1688 | build_copy_page(); | |
b6d92b4a SH |
1689 | |
1690 | /* | |
1691 | * We want to run CMP kernels on core with and without coherent | |
1692 | * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether | |
1693 | * or not to flush caches. | |
1694 | */ | |
1d40cfcd | 1695 | local_r4k___flush_cache_all(NULL); |
b6d92b4a | 1696 | |
1d40cfcd | 1697 | coherency_setup(); |
9cd9669b | 1698 | board_cache_error_setup = r4k_cache_error_setup; |
d74b0172 KC |
1699 | |
1700 | /* | |
1701 | * Per-CPU overrides | |
1702 | */ | |
1703 | switch (current_cpu_type()) { | |
1704 | case CPU_BMIPS4350: | |
1705 | case CPU_BMIPS4380: | |
1706 | /* No IPI is needed because all CPUs share the same D$ */ | |
1707 | flush_data_cache_page = r4k_blast_dcache_page; | |
1708 | break; | |
1709 | case CPU_BMIPS5000: | |
1710 | /* We lose our superpowers if L2 is disabled */ | |
1711 | if (c->scache.flags & MIPS_CACHE_NOT_PRESENT) | |
1712 | break; | |
1713 | ||
1714 | /* I$ fills from D$ just by emptying the write buffers */ | |
1715 | flush_cache_page = (void *)b5k_instruction_hazard; | |
1716 | flush_cache_range = (void *)b5k_instruction_hazard; | |
1717 | flush_cache_sigtramp = (void *)b5k_instruction_hazard; | |
1718 | local_flush_data_cache_page = (void *)b5k_instruction_hazard; | |
1719 | flush_data_cache_page = (void *)b5k_instruction_hazard; | |
1720 | flush_icache_range = (void *)b5k_instruction_hazard; | |
1721 | local_flush_icache_range = (void *)b5k_instruction_hazard; | |
1722 | ||
1723 | /* Cache aliases are handled in hardware; allow HIGHMEM */ | |
1724 | current_cpu_data.dcache.flags &= ~MIPS_CACHE_ALIASES; | |
1725 | ||
1726 | /* Optimization: an L2 flush implicitly flushes the L1 */ | |
1727 | current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES; | |
1728 | break; | |
1729 | } | |
1da177e4 | 1730 | } |
61d73044 JH |
1731 | |
1732 | static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd, | |
1733 | void *v) | |
1734 | { | |
1735 | switch (cmd) { | |
1736 | case CPU_PM_ENTER_FAILED: | |
1737 | case CPU_PM_EXIT: | |
1738 | coherency_setup(); | |
1739 | break; | |
1740 | } | |
1741 | ||
1742 | return NOTIFY_OK; | |
1743 | } | |
1744 | ||
1745 | static struct notifier_block r4k_cache_pm_notifier_block = { | |
1746 | .notifier_call = r4k_cache_pm_notifier, | |
1747 | }; | |
1748 | ||
1749 | int __init r4k_cache_init_pm(void) | |
1750 | { | |
1751 | return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block); | |
1752 | } | |
1753 | arch_initcall(r4k_cache_init_pm); |