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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) | |
7 | * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org) | |
8 | * Copyright (C) 1999, 2000 Silicon Graphics, Inc. | |
9 | */ | |
10 | #include <linux/config.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/sched.h> | |
14 | #include <linux/mm.h> | |
15 | #include <linux/bitops.h> | |
16 | ||
17 | #include <asm/bcache.h> | |
18 | #include <asm/bootinfo.h> | |
ec74e361 | 19 | #include <asm/cache.h> |
1da177e4 LT |
20 | #include <asm/cacheops.h> |
21 | #include <asm/cpu.h> | |
22 | #include <asm/cpu-features.h> | |
23 | #include <asm/io.h> | |
24 | #include <asm/page.h> | |
25 | #include <asm/pgtable.h> | |
26 | #include <asm/r4kcache.h> | |
27 | #include <asm/system.h> | |
28 | #include <asm/mmu_context.h> | |
29 | #include <asm/war.h> | |
ba5187db | 30 | #include <asm/cacheflush.h> /* for run_uncached() */ |
1da177e4 | 31 | |
ec74e361 RB |
32 | /* |
33 | * Must die. | |
34 | */ | |
35 | static unsigned long icache_size __read_mostly; | |
36 | static unsigned long dcache_size __read_mostly; | |
37 | static unsigned long scache_size __read_mostly; | |
1da177e4 LT |
38 | |
39 | /* | |
40 | * Dummy cache handling routines for machines without boardcaches | |
41 | */ | |
42 | static void no_sc_noop(void) {} | |
43 | ||
44 | static struct bcache_ops no_sc_ops = { | |
45 | .bc_enable = (void *)no_sc_noop, | |
46 | .bc_disable = (void *)no_sc_noop, | |
47 | .bc_wback_inv = (void *)no_sc_noop, | |
48 | .bc_inv = (void *)no_sc_noop | |
49 | }; | |
50 | ||
51 | struct bcache_ops *bcops = &no_sc_ops; | |
52 | ||
53 | #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x2010) | |
54 | #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x2020) | |
55 | ||
56 | #define R4600_HIT_CACHEOP_WAR_IMPL \ | |
57 | do { \ | |
58 | if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \ | |
59 | *(volatile unsigned long *)CKSEG1; \ | |
60 | if (R4600_V1_HIT_CACHEOP_WAR) \ | |
61 | __asm__ __volatile__("nop;nop;nop;nop"); \ | |
62 | } while (0) | |
63 | ||
64 | static void (*r4k_blast_dcache_page)(unsigned long addr); | |
65 | ||
66 | static inline void r4k_blast_dcache_page_dc32(unsigned long addr) | |
67 | { | |
68 | R4600_HIT_CACHEOP_WAR_IMPL; | |
69 | blast_dcache32_page(addr); | |
70 | } | |
71 | ||
72 | static inline void r4k_blast_dcache_page_setup(void) | |
73 | { | |
74 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
75 | ||
76 | if (dc_lsize == 16) | |
77 | r4k_blast_dcache_page = blast_dcache16_page; | |
78 | else if (dc_lsize == 32) | |
79 | r4k_blast_dcache_page = r4k_blast_dcache_page_dc32; | |
80 | } | |
81 | ||
82 | static void (* r4k_blast_dcache_page_indexed)(unsigned long addr); | |
83 | ||
84 | static inline void r4k_blast_dcache_page_indexed_setup(void) | |
85 | { | |
86 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
87 | ||
88 | if (dc_lsize == 16) | |
89 | r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; | |
90 | else if (dc_lsize == 32) | |
91 | r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; | |
92 | } | |
93 | ||
94 | static void (* r4k_blast_dcache)(void); | |
95 | ||
96 | static inline void r4k_blast_dcache_setup(void) | |
97 | { | |
98 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
99 | ||
100 | if (dc_lsize == 16) | |
101 | r4k_blast_dcache = blast_dcache16; | |
102 | else if (dc_lsize == 32) | |
103 | r4k_blast_dcache = blast_dcache32; | |
104 | } | |
105 | ||
106 | /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */ | |
107 | #define JUMP_TO_ALIGN(order) \ | |
108 | __asm__ __volatile__( \ | |
109 | "b\t1f\n\t" \ | |
110 | ".align\t" #order "\n\t" \ | |
111 | "1:\n\t" \ | |
112 | ) | |
113 | #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */ | |
114 | #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11) | |
115 | ||
116 | static inline void blast_r4600_v1_icache32(void) | |
117 | { | |
118 | unsigned long flags; | |
119 | ||
120 | local_irq_save(flags); | |
121 | blast_icache32(); | |
122 | local_irq_restore(flags); | |
123 | } | |
124 | ||
125 | static inline void tx49_blast_icache32(void) | |
126 | { | |
127 | unsigned long start = INDEX_BASE; | |
128 | unsigned long end = start + current_cpu_data.icache.waysize; | |
129 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; | |
130 | unsigned long ws_end = current_cpu_data.icache.ways << | |
131 | current_cpu_data.icache.waybit; | |
132 | unsigned long ws, addr; | |
133 | ||
134 | CACHE32_UNROLL32_ALIGN2; | |
135 | /* I'm in even chunk. blast odd chunks */ | |
42a3b4f2 RB |
136 | for (ws = 0; ws < ws_end; ws += ws_inc) |
137 | for (addr = start + 0x400; addr < end; addr += 0x400 * 2) | |
1da177e4 LT |
138 | cache32_unroll32(addr|ws,Index_Invalidate_I); |
139 | CACHE32_UNROLL32_ALIGN; | |
140 | /* I'm in odd chunk. blast even chunks */ | |
42a3b4f2 RB |
141 | for (ws = 0; ws < ws_end; ws += ws_inc) |
142 | for (addr = start; addr < end; addr += 0x400 * 2) | |
1da177e4 LT |
143 | cache32_unroll32(addr|ws,Index_Invalidate_I); |
144 | } | |
145 | ||
146 | static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page) | |
147 | { | |
148 | unsigned long flags; | |
149 | ||
150 | local_irq_save(flags); | |
151 | blast_icache32_page_indexed(page); | |
152 | local_irq_restore(flags); | |
153 | } | |
154 | ||
155 | static inline void tx49_blast_icache32_page_indexed(unsigned long page) | |
156 | { | |
157 | unsigned long start = page; | |
158 | unsigned long end = start + PAGE_SIZE; | |
159 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; | |
160 | unsigned long ws_end = current_cpu_data.icache.ways << | |
161 | current_cpu_data.icache.waybit; | |
162 | unsigned long ws, addr; | |
163 | ||
164 | CACHE32_UNROLL32_ALIGN2; | |
165 | /* I'm in even chunk. blast odd chunks */ | |
42a3b4f2 RB |
166 | for (ws = 0; ws < ws_end; ws += ws_inc) |
167 | for (addr = start + 0x400; addr < end; addr += 0x400 * 2) | |
1da177e4 LT |
168 | cache32_unroll32(addr|ws,Index_Invalidate_I); |
169 | CACHE32_UNROLL32_ALIGN; | |
170 | /* I'm in odd chunk. blast even chunks */ | |
42a3b4f2 RB |
171 | for (ws = 0; ws < ws_end; ws += ws_inc) |
172 | for (addr = start; addr < end; addr += 0x400 * 2) | |
1da177e4 LT |
173 | cache32_unroll32(addr|ws,Index_Invalidate_I); |
174 | } | |
175 | ||
176 | static void (* r4k_blast_icache_page)(unsigned long addr); | |
177 | ||
178 | static inline void r4k_blast_icache_page_setup(void) | |
179 | { | |
180 | unsigned long ic_lsize = cpu_icache_line_size(); | |
181 | ||
182 | if (ic_lsize == 16) | |
183 | r4k_blast_icache_page = blast_icache16_page; | |
184 | else if (ic_lsize == 32) | |
185 | r4k_blast_icache_page = blast_icache32_page; | |
186 | else if (ic_lsize == 64) | |
187 | r4k_blast_icache_page = blast_icache64_page; | |
188 | } | |
189 | ||
190 | ||
191 | static void (* r4k_blast_icache_page_indexed)(unsigned long addr); | |
192 | ||
193 | static inline void r4k_blast_icache_page_indexed_setup(void) | |
194 | { | |
195 | unsigned long ic_lsize = cpu_icache_line_size(); | |
196 | ||
197 | if (ic_lsize == 16) | |
198 | r4k_blast_icache_page_indexed = blast_icache16_page_indexed; | |
199 | else if (ic_lsize == 32) { | |
200 | if (TX49XX_ICACHE_INDEX_INV_WAR) | |
201 | r4k_blast_icache_page_indexed = | |
202 | tx49_blast_icache32_page_indexed; | |
203 | else if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) | |
204 | r4k_blast_icache_page_indexed = | |
205 | blast_icache32_r4600_v1_page_indexed; | |
206 | else | |
207 | r4k_blast_icache_page_indexed = | |
208 | blast_icache32_page_indexed; | |
209 | } else if (ic_lsize == 64) | |
210 | r4k_blast_icache_page_indexed = blast_icache64_page_indexed; | |
211 | } | |
212 | ||
213 | static void (* r4k_blast_icache)(void); | |
214 | ||
215 | static inline void r4k_blast_icache_setup(void) | |
216 | { | |
217 | unsigned long ic_lsize = cpu_icache_line_size(); | |
218 | ||
219 | if (ic_lsize == 16) | |
220 | r4k_blast_icache = blast_icache16; | |
221 | else if (ic_lsize == 32) { | |
222 | if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) | |
223 | r4k_blast_icache = blast_r4600_v1_icache32; | |
224 | else if (TX49XX_ICACHE_INDEX_INV_WAR) | |
225 | r4k_blast_icache = tx49_blast_icache32; | |
226 | else | |
227 | r4k_blast_icache = blast_icache32; | |
228 | } else if (ic_lsize == 64) | |
229 | r4k_blast_icache = blast_icache64; | |
230 | } | |
231 | ||
232 | static void (* r4k_blast_scache_page)(unsigned long addr); | |
233 | ||
234 | static inline void r4k_blast_scache_page_setup(void) | |
235 | { | |
236 | unsigned long sc_lsize = cpu_scache_line_size(); | |
237 | ||
238 | if (sc_lsize == 16) | |
239 | r4k_blast_scache_page = blast_scache16_page; | |
240 | else if (sc_lsize == 32) | |
241 | r4k_blast_scache_page = blast_scache32_page; | |
242 | else if (sc_lsize == 64) | |
243 | r4k_blast_scache_page = blast_scache64_page; | |
244 | else if (sc_lsize == 128) | |
245 | r4k_blast_scache_page = blast_scache128_page; | |
246 | } | |
247 | ||
248 | static void (* r4k_blast_scache_page_indexed)(unsigned long addr); | |
249 | ||
250 | static inline void r4k_blast_scache_page_indexed_setup(void) | |
251 | { | |
252 | unsigned long sc_lsize = cpu_scache_line_size(); | |
253 | ||
254 | if (sc_lsize == 16) | |
255 | r4k_blast_scache_page_indexed = blast_scache16_page_indexed; | |
256 | else if (sc_lsize == 32) | |
257 | r4k_blast_scache_page_indexed = blast_scache32_page_indexed; | |
258 | else if (sc_lsize == 64) | |
259 | r4k_blast_scache_page_indexed = blast_scache64_page_indexed; | |
260 | else if (sc_lsize == 128) | |
261 | r4k_blast_scache_page_indexed = blast_scache128_page_indexed; | |
262 | } | |
263 | ||
264 | static void (* r4k_blast_scache)(void); | |
265 | ||
266 | static inline void r4k_blast_scache_setup(void) | |
267 | { | |
268 | unsigned long sc_lsize = cpu_scache_line_size(); | |
269 | ||
270 | if (sc_lsize == 16) | |
271 | r4k_blast_scache = blast_scache16; | |
272 | else if (sc_lsize == 32) | |
273 | r4k_blast_scache = blast_scache32; | |
274 | else if (sc_lsize == 64) | |
275 | r4k_blast_scache = blast_scache64; | |
276 | else if (sc_lsize == 128) | |
277 | r4k_blast_scache = blast_scache128; | |
278 | } | |
279 | ||
280 | /* | |
281 | * This is former mm's flush_cache_all() which really should be | |
282 | * flush_cache_vunmap these days ... | |
283 | */ | |
284 | static inline void local_r4k_flush_cache_all(void * args) | |
285 | { | |
286 | r4k_blast_dcache(); | |
287 | r4k_blast_icache(); | |
288 | } | |
289 | ||
290 | static void r4k_flush_cache_all(void) | |
291 | { | |
292 | if (!cpu_has_dc_aliases) | |
293 | return; | |
294 | ||
295 | on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1); | |
296 | } | |
297 | ||
298 | static inline void local_r4k___flush_cache_all(void * args) | |
299 | { | |
300 | r4k_blast_dcache(); | |
301 | r4k_blast_icache(); | |
302 | ||
303 | switch (current_cpu_data.cputype) { | |
304 | case CPU_R4000SC: | |
305 | case CPU_R4000MC: | |
306 | case CPU_R4400SC: | |
307 | case CPU_R4400MC: | |
308 | case CPU_R10000: | |
309 | case CPU_R12000: | |
310 | r4k_blast_scache(); | |
311 | } | |
312 | } | |
313 | ||
314 | static void r4k___flush_cache_all(void) | |
315 | { | |
316 | on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1); | |
317 | } | |
318 | ||
319 | static inline void local_r4k_flush_cache_range(void * args) | |
320 | { | |
321 | struct vm_area_struct *vma = args; | |
322 | int exec; | |
323 | ||
324 | if (!(cpu_context(smp_processor_id(), vma->vm_mm))) | |
325 | return; | |
326 | ||
327 | exec = vma->vm_flags & VM_EXEC; | |
328 | if (cpu_has_dc_aliases || exec) | |
329 | r4k_blast_dcache(); | |
330 | if (exec) | |
331 | r4k_blast_icache(); | |
332 | } | |
333 | ||
334 | static void r4k_flush_cache_range(struct vm_area_struct *vma, | |
335 | unsigned long start, unsigned long end) | |
336 | { | |
337 | on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1); | |
338 | } | |
339 | ||
340 | static inline void local_r4k_flush_cache_mm(void * args) | |
341 | { | |
342 | struct mm_struct *mm = args; | |
343 | ||
344 | if (!cpu_context(smp_processor_id(), mm)) | |
345 | return; | |
346 | ||
347 | r4k_blast_dcache(); | |
348 | r4k_blast_icache(); | |
349 | ||
350 | /* | |
351 | * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we | |
352 | * only flush the primary caches but R10000 and R12000 behave sane ... | |
353 | */ | |
354 | if (current_cpu_data.cputype == CPU_R4000SC || | |
355 | current_cpu_data.cputype == CPU_R4000MC || | |
356 | current_cpu_data.cputype == CPU_R4400SC || | |
357 | current_cpu_data.cputype == CPU_R4400MC) | |
358 | r4k_blast_scache(); | |
359 | } | |
360 | ||
361 | static void r4k_flush_cache_mm(struct mm_struct *mm) | |
362 | { | |
363 | if (!cpu_has_dc_aliases) | |
364 | return; | |
365 | ||
366 | on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1); | |
367 | } | |
368 | ||
369 | struct flush_cache_page_args { | |
370 | struct vm_area_struct *vma; | |
371 | unsigned long page; | |
372 | }; | |
373 | ||
374 | static inline void local_r4k_flush_cache_page(void *args) | |
375 | { | |
376 | struct flush_cache_page_args *fcp_args = args; | |
377 | struct vm_area_struct *vma = fcp_args->vma; | |
378 | unsigned long page = fcp_args->page; | |
379 | int exec = vma->vm_flags & VM_EXEC; | |
380 | struct mm_struct *mm = vma->vm_mm; | |
381 | pgd_t *pgdp; | |
c6e8b587 | 382 | pud_t *pudp; |
1da177e4 LT |
383 | pmd_t *pmdp; |
384 | pte_t *ptep; | |
385 | ||
79acf83e RB |
386 | /* |
387 | * If ownes no valid ASID yet, cannot possibly have gotten | |
388 | * this page into the cache. | |
389 | */ | |
26a51b27 | 390 | if (cpu_context(smp_processor_id(), mm) == 0) |
79acf83e RB |
391 | return; |
392 | ||
1da177e4 LT |
393 | page &= PAGE_MASK; |
394 | pgdp = pgd_offset(mm, page); | |
c6e8b587 RB |
395 | pudp = pud_offset(pgdp, page); |
396 | pmdp = pmd_offset(pudp, page); | |
1da177e4 LT |
397 | ptep = pte_offset(pmdp, page); |
398 | ||
399 | /* | |
400 | * If the page isn't marked valid, the page cannot possibly be | |
401 | * in the cache. | |
402 | */ | |
403 | if (!(pte_val(*ptep) & _PAGE_PRESENT)) | |
404 | return; | |
405 | ||
406 | /* | |
407 | * Doing flushes for another ASID than the current one is | |
408 | * too difficult since stupid R4k caches do a TLB translation | |
409 | * for every cache flush operation. So we do indexed flushes | |
410 | * in that case, which doesn't overly flush the cache too much. | |
411 | */ | |
412 | if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) { | |
413 | if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { | |
414 | r4k_blast_dcache_page(page); | |
415 | if (exec && !cpu_icache_snoops_remote_store) | |
416 | r4k_blast_scache_page(page); | |
417 | } | |
418 | if (exec) | |
419 | r4k_blast_icache_page(page); | |
420 | ||
421 | return; | |
422 | } | |
423 | ||
424 | /* | |
425 | * Do indexed flush, too much work to get the (possible) TLB refills | |
426 | * to work correctly. | |
427 | */ | |
428 | page = INDEX_BASE + (page & (dcache_size - 1)); | |
429 | if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { | |
430 | r4k_blast_dcache_page_indexed(page); | |
431 | if (exec && !cpu_icache_snoops_remote_store) | |
432 | r4k_blast_scache_page_indexed(page); | |
433 | } | |
434 | if (exec) { | |
435 | if (cpu_has_vtag_icache) { | |
436 | int cpu = smp_processor_id(); | |
437 | ||
26a51b27 TS |
438 | if (cpu_context(cpu, mm) != 0) |
439 | drop_mmu_context(mm, cpu); | |
1da177e4 LT |
440 | } else |
441 | r4k_blast_icache_page_indexed(page); | |
442 | } | |
443 | } | |
444 | ||
445 | static void r4k_flush_cache_page(struct vm_area_struct *vma, unsigned long page, unsigned long pfn) | |
446 | { | |
447 | struct flush_cache_page_args args; | |
448 | ||
1da177e4 LT |
449 | args.vma = vma; |
450 | args.page = page; | |
451 | ||
452 | on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1); | |
453 | } | |
454 | ||
455 | static inline void local_r4k_flush_data_cache_page(void * addr) | |
456 | { | |
457 | r4k_blast_dcache_page((unsigned long) addr); | |
458 | } | |
459 | ||
460 | static void r4k_flush_data_cache_page(unsigned long addr) | |
461 | { | |
462 | on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1); | |
463 | } | |
464 | ||
465 | struct flush_icache_range_args { | |
fe00f943 RB |
466 | unsigned long __user start; |
467 | unsigned long __user end; | |
1da177e4 LT |
468 | }; |
469 | ||
470 | static inline void local_r4k_flush_icache_range(void *args) | |
471 | { | |
472 | struct flush_icache_range_args *fir_args = args; | |
473 | unsigned long dc_lsize = current_cpu_data.dcache.linesz; | |
474 | unsigned long ic_lsize = current_cpu_data.icache.linesz; | |
475 | unsigned long sc_lsize = current_cpu_data.scache.linesz; | |
476 | unsigned long start = fir_args->start; | |
477 | unsigned long end = fir_args->end; | |
478 | unsigned long addr, aend; | |
479 | ||
480 | if (!cpu_has_ic_fills_f_dc) { | |
481 | if (end - start > dcache_size) { | |
482 | r4k_blast_dcache(); | |
483 | } else { | |
484 | addr = start & ~(dc_lsize - 1); | |
485 | aend = (end - 1) & ~(dc_lsize - 1); | |
486 | ||
487 | while (1) { | |
488 | /* Hit_Writeback_Inv_D */ | |
489 | protected_writeback_dcache_line(addr); | |
490 | if (addr == aend) | |
491 | break; | |
492 | addr += dc_lsize; | |
493 | } | |
494 | } | |
495 | ||
496 | if (!cpu_icache_snoops_remote_store) { | |
497 | if (end - start > scache_size) { | |
498 | r4k_blast_scache(); | |
499 | } else { | |
500 | addr = start & ~(sc_lsize - 1); | |
501 | aend = (end - 1) & ~(sc_lsize - 1); | |
502 | ||
503 | while (1) { | |
504 | /* Hit_Writeback_Inv_D */ | |
505 | protected_writeback_scache_line(addr); | |
506 | if (addr == aend) | |
507 | break; | |
508 | addr += sc_lsize; | |
509 | } | |
510 | } | |
511 | } | |
512 | } | |
513 | ||
514 | if (end - start > icache_size) | |
515 | r4k_blast_icache(); | |
516 | else { | |
517 | addr = start & ~(ic_lsize - 1); | |
518 | aend = (end - 1) & ~(ic_lsize - 1); | |
519 | while (1) { | |
520 | /* Hit_Invalidate_I */ | |
521 | protected_flush_icache_line(addr); | |
522 | if (addr == aend) | |
523 | break; | |
524 | addr += ic_lsize; | |
525 | } | |
526 | } | |
527 | } | |
528 | ||
fe00f943 RB |
529 | static void r4k_flush_icache_range(unsigned long __user start, |
530 | unsigned long __user end) | |
1da177e4 LT |
531 | { |
532 | struct flush_icache_range_args args; | |
533 | ||
534 | args.start = start; | |
535 | args.end = end; | |
536 | ||
537 | on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1); | |
cc61c1fe | 538 | instruction_hazard(); |
1da177e4 LT |
539 | } |
540 | ||
541 | /* | |
542 | * Ok, this seriously sucks. We use them to flush a user page but don't | |
543 | * know the virtual address, so we have to blast away the whole icache | |
544 | * which is significantly more expensive than the real thing. Otoh we at | |
545 | * least know the kernel address of the page so we can flush it | |
546 | * selectivly. | |
547 | */ | |
548 | ||
549 | struct flush_icache_page_args { | |
550 | struct vm_area_struct *vma; | |
551 | struct page *page; | |
552 | }; | |
553 | ||
554 | static inline void local_r4k_flush_icache_page(void *args) | |
555 | { | |
556 | struct flush_icache_page_args *fip_args = args; | |
557 | struct vm_area_struct *vma = fip_args->vma; | |
558 | struct page *page = fip_args->page; | |
559 | ||
560 | /* | |
561 | * Tricky ... Because we don't know the virtual address we've got the | |
562 | * choice of either invalidating the entire primary and secondary | |
563 | * caches or invalidating the secondary caches also. With the subset | |
564 | * enforcment on R4000SC, R4400SC, R10000 and R12000 invalidating the | |
565 | * secondary cache will result in any entries in the primary caches | |
566 | * also getting invalidated which hopefully is a bit more economical. | |
567 | */ | |
568 | if (cpu_has_subset_pcaches) { | |
569 | unsigned long addr = (unsigned long) page_address(page); | |
570 | ||
571 | r4k_blast_scache_page(addr); | |
572 | ClearPageDcacheDirty(page); | |
573 | ||
574 | return; | |
575 | } | |
576 | ||
577 | if (!cpu_has_ic_fills_f_dc) { | |
578 | unsigned long addr = (unsigned long) page_address(page); | |
579 | r4k_blast_dcache_page(addr); | |
580 | if (!cpu_icache_snoops_remote_store) | |
581 | r4k_blast_scache_page(addr); | |
582 | ClearPageDcacheDirty(page); | |
583 | } | |
584 | ||
585 | /* | |
586 | * We're not sure of the virtual address(es) involved here, so | |
587 | * we have to flush the entire I-cache. | |
588 | */ | |
589 | if (cpu_has_vtag_icache) { | |
590 | int cpu = smp_processor_id(); | |
591 | ||
592 | if (cpu_context(cpu, vma->vm_mm) != 0) | |
593 | drop_mmu_context(vma->vm_mm, cpu); | |
594 | } else | |
595 | r4k_blast_icache(); | |
596 | } | |
597 | ||
598 | static void r4k_flush_icache_page(struct vm_area_struct *vma, | |
599 | struct page *page) | |
600 | { | |
601 | struct flush_icache_page_args args; | |
602 | ||
603 | /* | |
604 | * If there's no context yet, or the page isn't executable, no I-cache | |
605 | * flush is needed. | |
606 | */ | |
607 | if (!(vma->vm_flags & VM_EXEC)) | |
608 | return; | |
609 | ||
610 | args.vma = vma; | |
611 | args.page = page; | |
612 | ||
613 | on_each_cpu(local_r4k_flush_icache_page, &args, 1, 1); | |
614 | } | |
615 | ||
616 | ||
617 | #ifdef CONFIG_DMA_NONCOHERENT | |
618 | ||
619 | static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) | |
620 | { | |
621 | unsigned long end, a; | |
622 | ||
623 | /* Catch bad driver code */ | |
624 | BUG_ON(size == 0); | |
625 | ||
626 | if (cpu_has_subset_pcaches) { | |
627 | unsigned long sc_lsize = current_cpu_data.scache.linesz; | |
628 | ||
629 | if (size >= scache_size) { | |
630 | r4k_blast_scache(); | |
631 | return; | |
632 | } | |
633 | ||
634 | a = addr & ~(sc_lsize - 1); | |
635 | end = (addr + size - 1) & ~(sc_lsize - 1); | |
636 | while (1) { | |
637 | flush_scache_line(a); /* Hit_Writeback_Inv_SD */ | |
638 | if (a == end) | |
639 | break; | |
640 | a += sc_lsize; | |
641 | } | |
642 | return; | |
643 | } | |
644 | ||
645 | /* | |
646 | * Either no secondary cache or the available caches don't have the | |
647 | * subset property so we have to flush the primary caches | |
648 | * explicitly | |
649 | */ | |
650 | if (size >= dcache_size) { | |
651 | r4k_blast_dcache(); | |
652 | } else { | |
653 | unsigned long dc_lsize = current_cpu_data.dcache.linesz; | |
654 | ||
655 | R4600_HIT_CACHEOP_WAR_IMPL; | |
656 | a = addr & ~(dc_lsize - 1); | |
657 | end = (addr + size - 1) & ~(dc_lsize - 1); | |
658 | while (1) { | |
659 | flush_dcache_line(a); /* Hit_Writeback_Inv_D */ | |
660 | if (a == end) | |
661 | break; | |
662 | a += dc_lsize; | |
663 | } | |
664 | } | |
665 | ||
666 | bc_wback_inv(addr, size); | |
667 | } | |
668 | ||
669 | static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) | |
670 | { | |
671 | unsigned long end, a; | |
672 | ||
673 | /* Catch bad driver code */ | |
674 | BUG_ON(size == 0); | |
675 | ||
676 | if (cpu_has_subset_pcaches) { | |
677 | unsigned long sc_lsize = current_cpu_data.scache.linesz; | |
678 | ||
679 | if (size >= scache_size) { | |
680 | r4k_blast_scache(); | |
681 | return; | |
682 | } | |
683 | ||
684 | a = addr & ~(sc_lsize - 1); | |
685 | end = (addr + size - 1) & ~(sc_lsize - 1); | |
686 | while (1) { | |
687 | flush_scache_line(a); /* Hit_Writeback_Inv_SD */ | |
688 | if (a == end) | |
689 | break; | |
690 | a += sc_lsize; | |
691 | } | |
692 | return; | |
693 | } | |
694 | ||
695 | if (size >= dcache_size) { | |
696 | r4k_blast_dcache(); | |
697 | } else { | |
698 | unsigned long dc_lsize = current_cpu_data.dcache.linesz; | |
699 | ||
700 | R4600_HIT_CACHEOP_WAR_IMPL; | |
701 | a = addr & ~(dc_lsize - 1); | |
702 | end = (addr + size - 1) & ~(dc_lsize - 1); | |
703 | while (1) { | |
704 | flush_dcache_line(a); /* Hit_Writeback_Inv_D */ | |
705 | if (a == end) | |
706 | break; | |
707 | a += dc_lsize; | |
708 | } | |
709 | } | |
710 | ||
711 | bc_inv(addr, size); | |
712 | } | |
713 | #endif /* CONFIG_DMA_NONCOHERENT */ | |
714 | ||
715 | /* | |
716 | * While we're protected against bad userland addresses we don't care | |
717 | * very much about what happens in that case. Usually a segmentation | |
718 | * fault will dump the process later on anyway ... | |
719 | */ | |
720 | static void local_r4k_flush_cache_sigtramp(void * arg) | |
721 | { | |
722 | unsigned long ic_lsize = current_cpu_data.icache.linesz; | |
723 | unsigned long dc_lsize = current_cpu_data.dcache.linesz; | |
724 | unsigned long sc_lsize = current_cpu_data.scache.linesz; | |
725 | unsigned long addr = (unsigned long) arg; | |
726 | ||
727 | R4600_HIT_CACHEOP_WAR_IMPL; | |
728 | protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); | |
729 | if (!cpu_icache_snoops_remote_store) | |
730 | protected_writeback_scache_line(addr & ~(sc_lsize - 1)); | |
731 | protected_flush_icache_line(addr & ~(ic_lsize - 1)); | |
732 | if (MIPS4K_ICACHE_REFILL_WAR) { | |
733 | __asm__ __volatile__ ( | |
734 | ".set push\n\t" | |
735 | ".set noat\n\t" | |
736 | ".set mips3\n\t" | |
875d43e7 | 737 | #ifdef CONFIG_32BIT |
1da177e4 LT |
738 | "la $at,1f\n\t" |
739 | #endif | |
875d43e7 | 740 | #ifdef CONFIG_64BIT |
1da177e4 LT |
741 | "dla $at,1f\n\t" |
742 | #endif | |
743 | "cache %0,($at)\n\t" | |
744 | "nop; nop; nop\n" | |
745 | "1:\n\t" | |
746 | ".set pop" | |
747 | : | |
748 | : "i" (Hit_Invalidate_I)); | |
749 | } | |
750 | if (MIPS_CACHE_SYNC_WAR) | |
751 | __asm__ __volatile__ ("sync"); | |
752 | } | |
753 | ||
754 | static void r4k_flush_cache_sigtramp(unsigned long addr) | |
755 | { | |
756 | on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1, 1); | |
757 | } | |
758 | ||
759 | static void r4k_flush_icache_all(void) | |
760 | { | |
761 | if (cpu_has_vtag_icache) | |
762 | r4k_blast_icache(); | |
763 | } | |
764 | ||
765 | static inline void rm7k_erratum31(void) | |
766 | { | |
767 | const unsigned long ic_lsize = 32; | |
768 | unsigned long addr; | |
769 | ||
770 | /* RM7000 erratum #31. The icache is screwed at startup. */ | |
771 | write_c0_taglo(0); | |
772 | write_c0_taghi(0); | |
773 | ||
774 | for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) { | |
775 | __asm__ __volatile__ ( | |
776 | ".set noreorder\n\t" | |
777 | ".set mips3\n\t" | |
778 | "cache\t%1, 0(%0)\n\t" | |
779 | "cache\t%1, 0x1000(%0)\n\t" | |
780 | "cache\t%1, 0x2000(%0)\n\t" | |
781 | "cache\t%1, 0x3000(%0)\n\t" | |
782 | "cache\t%2, 0(%0)\n\t" | |
783 | "cache\t%2, 0x1000(%0)\n\t" | |
784 | "cache\t%2, 0x2000(%0)\n\t" | |
785 | "cache\t%2, 0x3000(%0)\n\t" | |
786 | "cache\t%1, 0(%0)\n\t" | |
787 | "cache\t%1, 0x1000(%0)\n\t" | |
788 | "cache\t%1, 0x2000(%0)\n\t" | |
789 | "cache\t%1, 0x3000(%0)\n\t" | |
790 | ".set\tmips0\n\t" | |
791 | ".set\treorder\n\t" | |
792 | : | |
793 | : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill)); | |
794 | } | |
795 | } | |
796 | ||
797 | static char *way_string[] __initdata = { NULL, "direct mapped", "2-way", | |
798 | "3-way", "4-way", "5-way", "6-way", "7-way", "8-way" | |
799 | }; | |
800 | ||
801 | static void __init probe_pcache(void) | |
802 | { | |
803 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
804 | unsigned int config = read_c0_config(); | |
805 | unsigned int prid = read_c0_prid(); | |
806 | unsigned long config1; | |
807 | unsigned int lsize; | |
808 | ||
809 | switch (c->cputype) { | |
810 | case CPU_R4600: /* QED style two way caches? */ | |
811 | case CPU_R4700: | |
812 | case CPU_R5000: | |
813 | case CPU_NEVADA: | |
814 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
815 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
816 | c->icache.ways = 2; | |
817 | c->icache.waybit = ffs(icache_size/2) - 1; | |
818 | ||
819 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
820 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
821 | c->dcache.ways = 2; | |
822 | c->dcache.waybit= ffs(dcache_size/2) - 1; | |
823 | ||
824 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
825 | break; | |
826 | ||
827 | case CPU_R5432: | |
828 | case CPU_R5500: | |
829 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
830 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
831 | c->icache.ways = 2; | |
832 | c->icache.waybit= 0; | |
833 | ||
834 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
835 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
836 | c->dcache.ways = 2; | |
837 | c->dcache.waybit = 0; | |
838 | ||
839 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
840 | break; | |
841 | ||
842 | case CPU_TX49XX: | |
843 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
844 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
845 | c->icache.ways = 4; | |
846 | c->icache.waybit= 0; | |
847 | ||
848 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
849 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
850 | c->dcache.ways = 4; | |
851 | c->dcache.waybit = 0; | |
852 | ||
853 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
854 | break; | |
855 | ||
856 | case CPU_R4000PC: | |
857 | case CPU_R4000SC: | |
858 | case CPU_R4000MC: | |
859 | case CPU_R4400PC: | |
860 | case CPU_R4400SC: | |
861 | case CPU_R4400MC: | |
862 | case CPU_R4300: | |
863 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
864 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
865 | c->icache.ways = 1; | |
866 | c->icache.waybit = 0; /* doesn't matter */ | |
867 | ||
868 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
869 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
870 | c->dcache.ways = 1; | |
871 | c->dcache.waybit = 0; /* does not matter */ | |
872 | ||
873 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
874 | break; | |
875 | ||
876 | case CPU_R10000: | |
877 | case CPU_R12000: | |
878 | icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29)); | |
879 | c->icache.linesz = 64; | |
880 | c->icache.ways = 2; | |
881 | c->icache.waybit = 0; | |
882 | ||
883 | dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26)); | |
884 | c->dcache.linesz = 32; | |
885 | c->dcache.ways = 2; | |
886 | c->dcache.waybit = 0; | |
887 | ||
888 | c->options |= MIPS_CPU_PREFETCH; | |
889 | break; | |
890 | ||
891 | case CPU_VR4133: | |
892 | write_c0_config(config & ~CONF_EB); | |
893 | case CPU_VR4131: | |
894 | /* Workaround for cache instruction bug of VR4131 */ | |
895 | if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || | |
896 | c->processor_id == 0x0c82U) { | |
897 | config &= ~0x00000030U; | |
898 | config |= 0x00410000U; | |
899 | write_c0_config(config); | |
900 | } | |
901 | icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); | |
902 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
903 | c->icache.ways = 2; | |
904 | c->icache.waybit = ffs(icache_size/2) - 1; | |
905 | ||
906 | dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); | |
907 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
908 | c->dcache.ways = 2; | |
909 | c->dcache.waybit = ffs(dcache_size/2) - 1; | |
910 | ||
911 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
912 | break; | |
913 | ||
914 | case CPU_VR41XX: | |
915 | case CPU_VR4111: | |
916 | case CPU_VR4121: | |
917 | case CPU_VR4122: | |
918 | case CPU_VR4181: | |
919 | case CPU_VR4181A: | |
920 | icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); | |
921 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
922 | c->icache.ways = 1; | |
923 | c->icache.waybit = 0; /* doesn't matter */ | |
924 | ||
925 | dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); | |
926 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
927 | c->dcache.ways = 1; | |
928 | c->dcache.waybit = 0; /* does not matter */ | |
929 | ||
930 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
931 | break; | |
932 | ||
933 | case CPU_RM7000: | |
934 | rm7k_erratum31(); | |
935 | ||
936 | case CPU_RM9000: | |
937 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
938 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
939 | c->icache.ways = 4; | |
940 | c->icache.waybit = ffs(icache_size / c->icache.ways) - 1; | |
941 | ||
942 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
943 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
944 | c->dcache.ways = 4; | |
945 | c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1; | |
946 | ||
947 | #if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR) | |
948 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
949 | #endif | |
950 | c->options |= MIPS_CPU_PREFETCH; | |
951 | break; | |
952 | ||
953 | default: | |
954 | if (!(config & MIPS_CONF_M)) | |
955 | panic("Don't know how to probe P-caches on this cpu."); | |
956 | ||
957 | /* | |
958 | * So we seem to be a MIPS32 or MIPS64 CPU | |
959 | * So let's probe the I-cache ... | |
960 | */ | |
961 | config1 = read_c0_config1(); | |
962 | ||
963 | if ((lsize = ((config1 >> 19) & 7))) | |
964 | c->icache.linesz = 2 << lsize; | |
965 | else | |
966 | c->icache.linesz = lsize; | |
967 | c->icache.sets = 64 << ((config1 >> 22) & 7); | |
968 | c->icache.ways = 1 + ((config1 >> 16) & 7); | |
969 | ||
970 | icache_size = c->icache.sets * | |
971 | c->icache.ways * | |
972 | c->icache.linesz; | |
973 | c->icache.waybit = ffs(icache_size/c->icache.ways) - 1; | |
974 | ||
975 | if (config & 0x8) /* VI bit */ | |
976 | c->icache.flags |= MIPS_CACHE_VTAG; | |
977 | ||
978 | /* | |
979 | * Now probe the MIPS32 / MIPS64 data cache. | |
980 | */ | |
981 | c->dcache.flags = 0; | |
982 | ||
983 | if ((lsize = ((config1 >> 10) & 7))) | |
984 | c->dcache.linesz = 2 << lsize; | |
985 | else | |
986 | c->dcache.linesz= lsize; | |
987 | c->dcache.sets = 64 << ((config1 >> 13) & 7); | |
988 | c->dcache.ways = 1 + ((config1 >> 7) & 7); | |
989 | ||
990 | dcache_size = c->dcache.sets * | |
991 | c->dcache.ways * | |
992 | c->dcache.linesz; | |
993 | c->dcache.waybit = ffs(dcache_size/c->dcache.ways) - 1; | |
994 | ||
995 | c->options |= MIPS_CPU_PREFETCH; | |
996 | break; | |
997 | } | |
998 | ||
999 | /* | |
1000 | * Processor configuration sanity check for the R4000SC erratum | |
1001 | * #5. With page sizes larger than 32kB there is no possibility | |
1002 | * to get a VCE exception anymore so we don't care about this | |
1003 | * misconfiguration. The case is rather theoretical anyway; | |
1004 | * presumably no vendor is shipping his hardware in the "bad" | |
1005 | * configuration. | |
1006 | */ | |
1007 | if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 && | |
1008 | !(config & CONF_SC) && c->icache.linesz != 16 && | |
1009 | PAGE_SIZE <= 0x8000) | |
1010 | panic("Improper R4000SC processor configuration detected"); | |
1011 | ||
1012 | /* compute a couple of other cache variables */ | |
1013 | c->icache.waysize = icache_size / c->icache.ways; | |
1014 | c->dcache.waysize = dcache_size / c->dcache.ways; | |
1015 | ||
1016 | c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways); | |
1017 | c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways); | |
1018 | ||
1019 | /* | |
1020 | * R10000 and R12000 P-caches are odd in a positive way. They're 32kB | |
1021 | * 2-way virtually indexed so normally would suffer from aliases. So | |
1022 | * normally they'd suffer from aliases but magic in the hardware deals | |
1023 | * with that for us so we don't need to take care ourselves. | |
1024 | */ | |
d1e344e5 | 1025 | switch (c->cputype) { |
a95970f3 | 1026 | case CPU_20KC: |
505403b6 | 1027 | case CPU_25KF: |
d1e344e5 RB |
1028 | case CPU_R10000: |
1029 | case CPU_R12000: | |
a95970f3 | 1030 | case CPU_SB1: |
d1e344e5 RB |
1031 | break; |
1032 | case CPU_24K: | |
1033 | if (!(read_c0_config7() & (1 << 16))) | |
1034 | default: | |
ae6aafe3 RB |
1035 | if (c->dcache.waysize > PAGE_SIZE) |
1036 | c->dcache.flags |= MIPS_CACHE_ALIASES; | |
d1e344e5 | 1037 | } |
1da177e4 LT |
1038 | |
1039 | switch (c->cputype) { | |
1040 | case CPU_20KC: | |
1041 | /* | |
1042 | * Some older 20Kc chips doesn't have the 'VI' bit in | |
1043 | * the config register. | |
1044 | */ | |
1045 | c->icache.flags |= MIPS_CACHE_VTAG; | |
1046 | break; | |
1047 | ||
e3ad1c23 | 1048 | case CPU_AU1000: |
1da177e4 | 1049 | case CPU_AU1500: |
e3ad1c23 PP |
1050 | case CPU_AU1100: |
1051 | case CPU_AU1550: | |
1052 | case CPU_AU1200: | |
1da177e4 LT |
1053 | c->icache.flags |= MIPS_CACHE_IC_F_DC; |
1054 | break; | |
1055 | } | |
1056 | ||
1057 | printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", | |
1058 | icache_size >> 10, | |
1059 | cpu_has_vtag_icache ? "virtually tagged" : "physically tagged", | |
1060 | way_string[c->icache.ways], c->icache.linesz); | |
1061 | ||
1062 | printk("Primary data cache %ldkB, %s, linesize %d bytes.\n", | |
1063 | dcache_size >> 10, way_string[c->dcache.ways], c->dcache.linesz); | |
1064 | } | |
1065 | ||
1066 | /* | |
1067 | * If you even _breathe_ on this function, look at the gcc output and make sure | |
1068 | * it does not pop things on and off the stack for the cache sizing loop that | |
1069 | * executes in KSEG1 space or else you will crash and burn badly. You have | |
1070 | * been warned. | |
1071 | */ | |
1072 | static int __init probe_scache(void) | |
1073 | { | |
1074 | extern unsigned long stext; | |
1075 | unsigned long flags, addr, begin, end, pow2; | |
1076 | unsigned int config = read_c0_config(); | |
1077 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1078 | int tmp; | |
1079 | ||
1080 | if (config & CONF_SC) | |
1081 | return 0; | |
1082 | ||
1083 | begin = (unsigned long) &stext; | |
1084 | begin &= ~((4 * 1024 * 1024) - 1); | |
1085 | end = begin + (4 * 1024 * 1024); | |
1086 | ||
1087 | /* | |
1088 | * This is such a bitch, you'd think they would make it easy to do | |
1089 | * this. Away you daemons of stupidity! | |
1090 | */ | |
1091 | local_irq_save(flags); | |
1092 | ||
1093 | /* Fill each size-multiple cache line with a valid tag. */ | |
1094 | pow2 = (64 * 1024); | |
1095 | for (addr = begin; addr < end; addr = (begin + pow2)) { | |
1096 | unsigned long *p = (unsigned long *) addr; | |
1097 | __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */ | |
1098 | pow2 <<= 1; | |
1099 | } | |
1100 | ||
1101 | /* Load first line with zero (therefore invalid) tag. */ | |
1102 | write_c0_taglo(0); | |
1103 | write_c0_taghi(0); | |
1104 | __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */ | |
1105 | cache_op(Index_Store_Tag_I, begin); | |
1106 | cache_op(Index_Store_Tag_D, begin); | |
1107 | cache_op(Index_Store_Tag_SD, begin); | |
1108 | ||
1109 | /* Now search for the wrap around point. */ | |
1110 | pow2 = (128 * 1024); | |
1111 | tmp = 0; | |
1112 | for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) { | |
1113 | cache_op(Index_Load_Tag_SD, addr); | |
1114 | __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */ | |
1115 | if (!read_c0_taglo()) | |
1116 | break; | |
1117 | pow2 <<= 1; | |
1118 | } | |
1119 | local_irq_restore(flags); | |
1120 | addr -= begin; | |
1121 | ||
1122 | scache_size = addr; | |
1123 | c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22); | |
1124 | c->scache.ways = 1; | |
1125 | c->dcache.waybit = 0; /* does not matter */ | |
1126 | ||
1127 | return 1; | |
1128 | } | |
1129 | ||
1da177e4 LT |
1130 | extern int r5k_sc_init(void); |
1131 | extern int rm7k_sc_init(void); | |
1132 | ||
1133 | static void __init setup_scache(void) | |
1134 | { | |
1135 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1136 | unsigned int config = read_c0_config(); | |
1da177e4 LT |
1137 | int sc_present = 0; |
1138 | ||
1139 | /* | |
1140 | * Do the probing thing on R4000SC and R4400SC processors. Other | |
1141 | * processors don't have a S-cache that would be relevant to the | |
1142 | * Linux memory managment. | |
1143 | */ | |
1144 | switch (c->cputype) { | |
1145 | case CPU_R4000SC: | |
1146 | case CPU_R4000MC: | |
1147 | case CPU_R4400SC: | |
1148 | case CPU_R4400MC: | |
ba5187db | 1149 | sc_present = run_uncached(probe_scache); |
1da177e4 LT |
1150 | if (sc_present) |
1151 | c->options |= MIPS_CPU_CACHE_CDEX_S; | |
1152 | break; | |
1153 | ||
1154 | case CPU_R10000: | |
1155 | case CPU_R12000: | |
1156 | scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16); | |
1157 | c->scache.linesz = 64 << ((config >> 13) & 1); | |
1158 | c->scache.ways = 2; | |
1159 | c->scache.waybit= 0; | |
1160 | sc_present = 1; | |
1161 | break; | |
1162 | ||
1163 | case CPU_R5000: | |
1164 | case CPU_NEVADA: | |
1165 | #ifdef CONFIG_R5000_CPU_SCACHE | |
1166 | r5k_sc_init(); | |
1167 | #endif | |
1168 | return; | |
1169 | ||
1170 | case CPU_RM7000: | |
1171 | case CPU_RM9000: | |
1172 | #ifdef CONFIG_RM7000_CPU_SCACHE | |
1173 | rm7k_sc_init(); | |
1174 | #endif | |
1175 | return; | |
1176 | ||
1177 | default: | |
1178 | sc_present = 0; | |
1179 | } | |
1180 | ||
1181 | if (!sc_present) | |
1182 | return; | |
1183 | ||
1184 | if ((c->isa_level == MIPS_CPU_ISA_M32 || | |
1185 | c->isa_level == MIPS_CPU_ISA_M64) && | |
1186 | !(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) | |
1187 | panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); | |
1188 | ||
1189 | /* compute a couple of other cache variables */ | |
1190 | c->scache.waysize = scache_size / c->scache.ways; | |
1191 | ||
1192 | c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); | |
1193 | ||
1194 | printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n", | |
1195 | scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); | |
1196 | ||
1197 | c->options |= MIPS_CPU_SUBSET_CACHES; | |
1198 | } | |
1199 | ||
1200 | static inline void coherency_setup(void) | |
1201 | { | |
1202 | change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT); | |
1203 | ||
1204 | /* | |
1205 | * c0_status.cu=0 specifies that updates by the sc instruction use | |
1206 | * the coherency mode specified by the TLB; 1 means cachable | |
1207 | * coherent update on write will be used. Not all processors have | |
1208 | * this bit and; some wire it to zero, others like Toshiba had the | |
1209 | * silly idea of putting something else there ... | |
1210 | */ | |
1211 | switch (current_cpu_data.cputype) { | |
1212 | case CPU_R4000PC: | |
1213 | case CPU_R4000SC: | |
1214 | case CPU_R4000MC: | |
1215 | case CPU_R4400PC: | |
1216 | case CPU_R4400SC: | |
1217 | case CPU_R4400MC: | |
1218 | clear_c0_config(CONF_CU); | |
1219 | break; | |
1220 | } | |
1221 | } | |
1222 | ||
1223 | void __init ld_mmu_r4xx0(void) | |
1224 | { | |
1225 | extern void build_clear_page(void); | |
1226 | extern void build_copy_page(void); | |
1227 | extern char except_vec2_generic; | |
1228 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1229 | ||
1230 | /* Default cache error handler for R4000 and R5000 family */ | |
e01402b1 | 1231 | set_uncached_handler (0x100, &except_vec2_generic, 0x80); |
1da177e4 LT |
1232 | |
1233 | probe_pcache(); | |
1234 | setup_scache(); | |
1235 | ||
1da177e4 LT |
1236 | r4k_blast_dcache_page_setup(); |
1237 | r4k_blast_dcache_page_indexed_setup(); | |
1238 | r4k_blast_dcache_setup(); | |
1239 | r4k_blast_icache_page_setup(); | |
1240 | r4k_blast_icache_page_indexed_setup(); | |
1241 | r4k_blast_icache_setup(); | |
1242 | r4k_blast_scache_page_setup(); | |
1243 | r4k_blast_scache_page_indexed_setup(); | |
1244 | r4k_blast_scache_setup(); | |
1245 | ||
1246 | /* | |
1247 | * Some MIPS32 and MIPS64 processors have physically indexed caches. | |
1248 | * This code supports virtually indexed processors and will be | |
1249 | * unnecessarily inefficient on physically indexed processors. | |
1250 | */ | |
1251 | shm_align_mask = max_t( unsigned long, | |
1252 | c->dcache.sets * c->dcache.linesz - 1, | |
1253 | PAGE_SIZE - 1); | |
1254 | ||
1255 | flush_cache_all = r4k_flush_cache_all; | |
1256 | __flush_cache_all = r4k___flush_cache_all; | |
1257 | flush_cache_mm = r4k_flush_cache_mm; | |
1258 | flush_cache_page = r4k_flush_cache_page; | |
1259 | flush_icache_page = r4k_flush_icache_page; | |
1260 | flush_cache_range = r4k_flush_cache_range; | |
1261 | ||
1262 | flush_cache_sigtramp = r4k_flush_cache_sigtramp; | |
1263 | flush_icache_all = r4k_flush_icache_all; | |
1264 | flush_data_cache_page = r4k_flush_data_cache_page; | |
1265 | flush_icache_range = r4k_flush_icache_range; | |
1266 | ||
1267 | #ifdef CONFIG_DMA_NONCOHERENT | |
1268 | _dma_cache_wback_inv = r4k_dma_cache_wback_inv; | |
1269 | _dma_cache_wback = r4k_dma_cache_wback_inv; | |
1270 | _dma_cache_inv = r4k_dma_cache_inv; | |
1271 | #endif | |
1272 | ||
1273 | __flush_cache_all(); | |
1274 | coherency_setup(); | |
1275 | ||
1276 | build_clear_page(); | |
1277 | build_copy_page(); | |
1278 | } |