[deliverable/linux.git] / arch / mips / mm / c-tx39.c

/*
 * r2300.c: R2000 and R3000 specific mmu/cache code.
 *
 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
 *
 * with a lot of changes to make this thing work for R3000s
 * Tx39XX R4k style caches added. HK
 * Copyright (C) 1998, 1999, 2000 Harald Koerfgen
 * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/mm.h>

#include <asm/cacheops.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/mmu_context.h>
#include <asm/system.h>
#include <asm/isadep.h>
#include <asm/io.h>
#include <asm/bootinfo.h>
#include <asm/cpu.h>

/* For R3000 cores with R4000 style caches */
static unsigned long icache_size, dcache_size;		/* Size in bytes */

#include <asm/r4kcache.h>

extern int r3k_have_wired_reg;	/* in r3k-tlb.c */

/* This sequence is required to ensure icache is disabled immediately */
#define TX39_STOP_STREAMING() \
__asm__ __volatile__( \
	".set    push\n\t" \
	".set    noreorder\n\t" \
	"b       1f\n\t" \
	"nop\n\t" \
	"1:\n\t" \
	".set pop" \
	)

/* TX39H-style cache flush routines. */
static void tx39h_flush_icache_all(void)
{
	unsigned long flags, config;

	/* disable icache (set ICE#) */
	local_irq_save(flags);
	config = read_c0_conf();
	write_c0_conf(config & ~TX39_CONF_ICE);
	TX39_STOP_STREAMING();
	blast_icache16();
	write_c0_conf(config);
	local_irq_restore(flags);
}

static void tx39h_dma_cache_wback_inv(unsigned long addr, unsigned long size)
{
	/* Catch bad driver code */
	BUG_ON(size == 0);

	iob();
	blast_inv_dcache_range(addr, addr + size);
}


/* TX39H2,TX39H3 */
static inline void tx39_blast_dcache_page(unsigned long addr)
{
	if (current_cpu_type() != CPU_TX3912)
		blast_dcache16_page(addr);
}

static inline void tx39_blast_dcache_page_indexed(unsigned long addr)
{
	blast_dcache16_page_indexed(addr);
}

static inline void tx39_blast_dcache(void)
{
	blast_dcache16();
}

static inline void tx39_blast_icache_page(unsigned long addr)
{
	unsigned long flags, config;
	/* disable icache (set ICE#) */
	local_irq_save(flags);
	config = read_c0_conf();
	write_c0_conf(config & ~TX39_CONF_ICE);
	TX39_STOP_STREAMING();
	blast_icache16_page(addr);
	write_c0_conf(config);
	local_irq_restore(flags);
}

static inline void tx39_blast_icache_page_indexed(unsigned long addr)
{
	unsigned long flags, config;
	/* disable icache (set ICE#) */
	local_irq_save(flags);
	config = read_c0_conf();
	write_c0_conf(config & ~TX39_CONF_ICE);
	TX39_STOP_STREAMING();
	blast_icache16_page_indexed(addr);
	write_c0_conf(config);
	local_irq_restore(flags);
}

static inline void tx39_blast_icache(void)
{
	unsigned long flags, config;
	/* disable icache (set ICE#) */
	local_irq_save(flags);
	config = read_c0_conf();
	write_c0_conf(config & ~TX39_CONF_ICE);
	TX39_STOP_STREAMING();
	blast_icache16();
	write_c0_conf(config);
	local_irq_restore(flags);
}

static void tx39__flush_cache_vmap(void)
{
	tx39_blast_dcache();
}

static void tx39__flush_cache_vunmap(void)
{
	tx39_blast_dcache();
}

static inline void tx39_flush_cache_all(void)
{
	if (!cpu_has_dc_aliases)
		return;

	tx39_blast_dcache();
}

static inline void tx39___flush_cache_all(void)
{
	tx39_blast_dcache();
	tx39_blast_icache();
}

static void tx39_flush_cache_mm(struct mm_struct *mm)
{
	if (!cpu_has_dc_aliases)
		return;

	if (cpu_context(smp_processor_id(), mm) != 0)
		tx39_blast_dcache();
}

static void tx39_flush_cache_range(struct vm_area_struct *vma,
	unsigned long start, unsigned long end)
{
	if (!cpu_has_dc_aliases)
		return;
	if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
		return;

	tx39_blast_dcache();
}

static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page, unsigned long pfn)
{
	int exec = vma->vm_flags & VM_EXEC;
	struct mm_struct *mm = vma->vm_mm;
	pgd_t *pgdp;
	pud_t *pudp;
	pmd_t *pmdp;
	pte_t *ptep;

	/*
	 * If ownes no valid ASID yet, cannot possibly have gotten
	 * this page into the cache.
	 */
	if (cpu_context(smp_processor_id(), mm) == 0)
		return;

	page &= PAGE_MASK;
	pgdp = pgd_offset(mm, page);
	pudp = pud_offset(pgdp, page);
	pmdp = pmd_offset(pudp, page);
	ptep = pte_offset(pmdp, page);

	/*
	 * If the page isn't marked valid, the page cannot possibly be
	 * in the cache.
	 */
	if (!(pte_val(*ptep) & _PAGE_PRESENT))
		return;

	/*
	 * Doing flushes for another ASID than the current one is
	 * too difficult since stupid R4k caches do a TLB translation
	 * for every cache flush operation.  So we do indexed flushes
	 * in that case, which doesn't overly flush the cache too much.
	 */
	if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
		if (cpu_has_dc_aliases || exec)
			tx39_blast_dcache_page(page);
		if (exec)
			tx39_blast_icache_page(page);

		return;
	}

	/*
	 * Do indexed flush, too much work to get the (possible) TLB refills
	 * to work correctly.
	 */
	if (cpu_has_dc_aliases || exec)
		tx39_blast_dcache_page_indexed(page);
	if (exec)
		tx39_blast_icache_page_indexed(page);
}

static void local_tx39_flush_data_cache_page(void * addr)
{
	tx39_blast_dcache_page((unsigned long)addr);
}

static void tx39_flush_data_cache_page(unsigned long addr)
{
	tx39_blast_dcache_page(addr);
}

static void tx39_flush_icache_range(unsigned long start, unsigned long end)
{
	if (end - start > dcache_size)
		tx39_blast_dcache();
	else
		protected_blast_dcache_range(start, end);

	if (end - start > icache_size)
		tx39_blast_icache();
	else {
		unsigned long flags, config;
		/* disable icache (set ICE#) */
		local_irq_save(flags);
		config = read_c0_conf();
		write_c0_conf(config & ~TX39_CONF_ICE);
		TX39_STOP_STREAMING();
		protected_blast_icache_range(start, end);
		write_c0_conf(config);
		local_irq_restore(flags);
	}
}

static void tx39_flush_kernel_vmap_range(unsigned long vaddr, int size)
{
	BUG();
}

static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size)
{
	unsigned long end;

	if (((size | addr) & (PAGE_SIZE - 1)) == 0) {
		end = addr + size;
		do {
			tx39_blast_dcache_page(addr);
			addr += PAGE_SIZE;
		} while(addr != end);
	} else if (size > dcache_size) {
		tx39_blast_dcache();
	} else {
		blast_dcache_range(addr, addr + size);
	}
}

static void tx39_dma_cache_inv(unsigned long addr, unsigned long size)
{
	unsigned long end;

	if (((size | addr) & (PAGE_SIZE - 1)) == 0) {
		end = addr + size;
		do {
			tx39_blast_dcache_page(addr);
			addr += PAGE_SIZE;
		} while(addr != end);
	} else if (size > dcache_size) {
		tx39_blast_dcache();
	} else {
		blast_inv_dcache_range(addr, addr + size);
	}
}

static void tx39_flush_cache_sigtramp(unsigned long addr)
{
	unsigned long ic_lsize = current_cpu_data.icache.linesz;
	unsigned long dc_lsize = current_cpu_data.dcache.linesz;
	unsigned long config;
	unsigned long flags;

	protected_writeback_dcache_line(addr & ~(dc_lsize - 1));

	/* disable icache (set ICE#) */
	local_irq_save(flags);
	config = read_c0_conf();
	write_c0_conf(config & ~TX39_CONF_ICE);
	TX39_STOP_STREAMING();
	protected_flush_icache_line(addr & ~(ic_lsize - 1));
	write_c0_conf(config);
	local_irq_restore(flags);
}

static __init void tx39_probe_cache(void)
{
	unsigned long config;

	config = read_c0_conf();

	icache_size = 1 << (10 + ((config & TX39_CONF_ICS_MASK) >>
				  TX39_CONF_ICS_SHIFT));
	dcache_size = 1 << (10 + ((config & TX39_CONF_DCS_MASK) >>
				  TX39_CONF_DCS_SHIFT));

	current_cpu_data.icache.linesz = 16;
	switch (current_cpu_type()) {
	case CPU_TX3912:
		current_cpu_data.icache.ways = 1;
		current_cpu_data.dcache.ways = 1;
		current_cpu_data.dcache.linesz = 4;
		break;

	case CPU_TX3927:
		current_cpu_data.icache.ways = 2;
		current_cpu_data.dcache.ways = 2;
		current_cpu_data.dcache.linesz = 16;
		break;

	case CPU_TX3922:
	default:
		current_cpu_data.icache.ways = 1;
		current_cpu_data.dcache.ways = 1;
		current_cpu_data.dcache.linesz = 16;
		break;
	}
}

void __cpuinit tx39_cache_init(void)
{
	extern void build_clear_page(void);
	extern void build_copy_page(void);
	unsigned long config;

	config = read_c0_conf();
	config &= ~TX39_CONF_WBON;
	write_c0_conf(config);

	tx39_probe_cache();

	switch (current_cpu_type()) {
	case CPU_TX3912:
		/* TX39/H core (writethru direct-map cache) */
		__flush_cache_vmap	= tx39__flush_cache_vmap;
		__flush_cache_vunmap	= tx39__flush_cache_vunmap;
		flush_cache_all	= tx39h_flush_icache_all;
		__flush_cache_all	= tx39h_flush_icache_all;
		flush_cache_mm		= (void *) tx39h_flush_icache_all;
		flush_cache_range	= (void *) tx39h_flush_icache_all;
		flush_cache_page	= (void *) tx39h_flush_icache_all;
		flush_icache_range	= (void *) tx39h_flush_icache_all;
		local_flush_icache_range = (void *) tx39h_flush_icache_all;

		flush_cache_sigtramp	= (void *) tx39h_flush_icache_all;
		local_flush_data_cache_page	= (void *) tx39h_flush_icache_all;
		flush_data_cache_page	= (void *) tx39h_flush_icache_all;

		_dma_cache_wback_inv	= tx39h_dma_cache_wback_inv;

		shm_align_mask		= PAGE_SIZE - 1;

		break;

	case CPU_TX3922:
	case CPU_TX3927:
	default:
		/* TX39/H2,H3 core (writeback 2way-set-associative cache) */
		r3k_have_wired_reg = 1;
		write_c0_wired(0);	/* set 8 on reset... */
		/* board-dependent init code may set WBON */

		__flush_cache_vmap	= tx39__flush_cache_vmap;
		__flush_cache_vunmap	= tx39__flush_cache_vunmap;

		flush_cache_all = tx39_flush_cache_all;
		__flush_cache_all = tx39___flush_cache_all;
		flush_cache_mm = tx39_flush_cache_mm;
		flush_cache_range = tx39_flush_cache_range;
		flush_cache_page = tx39_flush_cache_page;
		flush_icache_range = tx39_flush_icache_range;
		local_flush_icache_range = tx39_flush_icache_range;

		__flush_kernel_vmap_range = tx39_flush_kernel_vmap_range;

		flush_cache_sigtramp = tx39_flush_cache_sigtramp;
		local_flush_data_cache_page = local_tx39_flush_data_cache_page;
		flush_data_cache_page = tx39_flush_data_cache_page;

		_dma_cache_wback_inv = tx39_dma_cache_wback_inv;
		_dma_cache_wback = tx39_dma_cache_wback_inv;
		_dma_cache_inv = tx39_dma_cache_inv;

		shm_align_mask = max_t(unsigned long,
		                       (dcache_size / current_cpu_data.dcache.ways) - 1,
		                       PAGE_SIZE - 1);

		break;
	}

	current_cpu_data.icache.waysize = icache_size / current_cpu_data.icache.ways;
	current_cpu_data.dcache.waysize = dcache_size / current_cpu_data.dcache.ways;

	current_cpu_data.icache.sets =
		current_cpu_data.icache.waysize / current_cpu_data.icache.linesz;
	current_cpu_data.dcache.sets =
		current_cpu_data.dcache.waysize / current_cpu_data.dcache.linesz;

	if (current_cpu_data.dcache.waysize > PAGE_SIZE)
		current_cpu_data.dcache.flags |= MIPS_CACHE_ALIASES;

	current_cpu_data.icache.waybit = 0;
	current_cpu_data.dcache.waybit = 0;

	printk("Primary instruction cache %ldkB, linesize %d bytes\n",
		icache_size >> 10, current_cpu_data.icache.linesz);
	printk("Primary data cache %ldkB, linesize %d bytes\n",
		dcache_size >> 10, current_cpu_data.dcache.linesz);

	build_clear_page();
	build_copy_page();
	tx39h_flush_icache_all();
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* r2300.c: R2000 and R3000 specific mmu/cache code.
	3	*
79add627	4	* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
1da177e4 LT	5	*
	6	* with a lot of changes to make this thing work for R3000s
	7	* Tx39XX R4k style caches added. HK
	8	* Copyright (C) 1998, 1999, 2000 Harald Koerfgen
	9	* Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
	10	*/
	11	#include <linux/init.h>
	12	#include <linux/kernel.h>
	13	#include <linux/sched.h>
631330f5	14	#include <linux/smp.h>
1da177e4 LT	15	#include <linux/mm.h>
	16
	17	#include <asm/cacheops.h>
	18	#include <asm/page.h>
	19	#include <asm/pgtable.h>
	20	#include <asm/mmu_context.h>
	21	#include <asm/system.h>
	22	#include <asm/isadep.h>
	23	#include <asm/io.h>
	24	#include <asm/bootinfo.h>
	25	#include <asm/cpu.h>
	26
	27	/* For R3000 cores with R4000 style caches */
	28	static unsigned long icache_size, dcache_size; /* Size in bytes */
	29
	30	#include <asm/r4kcache.h>
	31
	32	extern int r3k_have_wired_reg; /* in r3k-tlb.c */
	33
	34	/* This sequence is required to ensure icache is disabled immediately */
	35	#define TX39_STOP_STREAMING() \
	36	__asm__ __volatile__( \
	37	".set push\n\t" \
	38	".set noreorder\n\t" \
	39	"b 1f\n\t" \
	40	"nop\n\t" \
	41	"1:\n\t" \
	42	".set pop" \
	43	)
	44
	45	/* TX39H-style cache flush routines. */
	46	static void tx39h_flush_icache_all(void)
	47	{
1da177e4 LT	48	unsigned long flags, config;
	49
	50	/* disable icache (set ICE#) */
	51	local_irq_save(flags);
	52	config = read_c0_conf();
	53	write_c0_conf(config & ~TX39_CONF_ICE);
	54	TX39_STOP_STREAMING();
41700e73	55	blast_icache16();
1da177e4 LT	56	write_c0_conf(config);
	57	local_irq_restore(flags);
	58	}
	59
	60	static void tx39h_dma_cache_wback_inv(unsigned long addr, unsigned long size)
	61	{
1da177e4 LT	62	/* Catch bad driver code */
	63	BUG_ON(size == 0);
	64
	65	iob();
41700e73	66	blast_inv_dcache_range(addr, addr + size);
1da177e4 LT	67	}
	68
	69
	70	/* TX39H2,TX39H3 */
	71	static inline void tx39_blast_dcache_page(unsigned long addr)
	72	{
10cc3529	73	if (current_cpu_type() != CPU_TX3912)
1da177e4 LT	74	blast_dcache16_page(addr);
	75	}
	76
	77	static inline void tx39_blast_dcache_page_indexed(unsigned long addr)
	78	{
	79	blast_dcache16_page_indexed(addr);
	80	}
	81
	82	static inline void tx39_blast_dcache(void)
	83	{
	84	blast_dcache16();
	85	}
	86
	87	static inline void tx39_blast_icache_page(unsigned long addr)
	88	{
	89	unsigned long flags, config;
	90	/* disable icache (set ICE#) */
	91	local_irq_save(flags);
	92	config = read_c0_conf();
	93	write_c0_conf(config & ~TX39_CONF_ICE);
	94	TX39_STOP_STREAMING();
	95	blast_icache16_page(addr);
	96	write_c0_conf(config);
	97	local_irq_restore(flags);
	98	}
	99
	100	static inline void tx39_blast_icache_page_indexed(unsigned long addr)
	101	{
	102	unsigned long flags, config;
	103	/* disable icache (set ICE#) */
	104	local_irq_save(flags);
	105	config = read_c0_conf();
	106	write_c0_conf(config & ~TX39_CONF_ICE);
	107	TX39_STOP_STREAMING();
	108	blast_icache16_page_indexed(addr);
	109	write_c0_conf(config);
	110	local_irq_restore(flags);
	111	}
	112
	113	static inline void tx39_blast_icache(void)
	114	{
	115	unsigned long flags, config;
	116	/* disable icache (set ICE#) */
	117	local_irq_save(flags);
	118	config = read_c0_conf();
	119	write_c0_conf(config & ~TX39_CONF_ICE);
	120	TX39_STOP_STREAMING();
	121	blast_icache16();
	122	write_c0_conf(config);
	123	local_irq_restore(flags);
	124	}
	125
9c5a3d72 RB	126	static void tx39__flush_cache_vmap(void)
	127	{
	128	tx39_blast_dcache();
	129	}
	130
	131	static void tx39__flush_cache_vunmap(void)
	132	{
	133	tx39_blast_dcache();
	134	}
	135
1da177e4 LT	136	static inline void tx39_flush_cache_all(void)
	137	{
	138	if (!cpu_has_dc_aliases)
	139	return;
	140
	141	tx39_blast_dcache();
1da177e4 LT	142	}
	143
	144	static inline void tx39___flush_cache_all(void)
	145	{
	146	tx39_blast_dcache();
	147	tx39_blast_icache();
	148	}
	149
	150	static void tx39_flush_cache_mm(struct mm_struct *mm)
	151	{
	152	if (!cpu_has_dc_aliases)
	153	return;
	154
a5664c40 AN	155	if (cpu_context(smp_processor_id(), mm) != 0)
a5664c40 AN	156	tx39_blast_dcache();
1da177e4 LT	157	}
	158
	159	static void tx39_flush_cache_range(struct vm_area_struct *vma,
	160	unsigned long start, unsigned long end)
	161	{
a5664c40 AN	162	if (!cpu_has_dc_aliases)
a5664c40 AN	163	return;
9043f7e9	164	if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
1da177e4 LT	165	return;
1da177e4 LT	166
a5664c40	167	tx39_blast_dcache();
1da177e4 LT	168	}
	169
	170	static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page, unsigned long pfn)
	171	{
	172	int exec = vma->vm_flags & VM_EXEC;
	173	struct mm_struct *mm = vma->vm_mm;
	174	pgd_t *pgdp;
c6e8b587	175	pud_t *pudp;
1da177e4 LT	176	pmd_t *pmdp;
	177	pte_t *ptep;
	178
	179	/*
	180	* If ownes no valid ASID yet, cannot possibly have gotten
	181	* this page into the cache.
	182	*/
	183	if (cpu_context(smp_processor_id(), mm) == 0)
	184	return;
	185
	186	page &= PAGE_MASK;
	187	pgdp = pgd_offset(mm, page);
c6e8b587 RB	188	pudp = pud_offset(pgdp, page);
c6e8b587 RB	189	pmdp = pmd_offset(pudp, page);
1da177e4 LT	190	ptep = pte_offset(pmdp, page);
	191
	192	/*
	193	* If the page isn't marked valid, the page cannot possibly be
	194	* in the cache.
	195	*/
	196	if (!(pte_val(*ptep) & _PAGE_PRESENT))
	197	return;
	198
	199	/*
	200	* Doing flushes for another ASID than the current one is
	201	* too difficult since stupid R4k caches do a TLB translation
	202	* for every cache flush operation. So we do indexed flushes
	203	* in that case, which doesn't overly flush the cache too much.
	204	*/
	205	if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
	206	if (cpu_has_dc_aliases \|\| exec)
	207	tx39_blast_dcache_page(page);
	208	if (exec)
	209	tx39_blast_icache_page(page);
	210
	211	return;
	212	}
	213
	214	/*
	215	* Do indexed flush, too much work to get the (possible) TLB refills
	216	* to work correctly.
	217	*/
1da177e4 LT	218	if (cpu_has_dc_aliases \|\| exec)
	219	tx39_blast_dcache_page_indexed(page);
	220	if (exec)
	221	tx39_blast_icache_page_indexed(page);
	222	}
	223
7e3bfc7c RB	224	static void local_tx39_flush_data_cache_page(void * addr)
7e3bfc7c RB	225	{
a5664c40	226	tx39_blast_dcache_page((unsigned long)addr);
7e3bfc7c RB	227	}
7e3bfc7c RB	228
1da177e4 LT	229	static void tx39_flush_data_cache_page(unsigned long addr)
	230	{
	231	tx39_blast_dcache_page(addr);
	232	}
	233
	234	static void tx39_flush_icache_range(unsigned long start, unsigned long end)
	235	{
1da177e4 LT	236	if (end - start > dcache_size)
1da177e4 LT	237	tx39_blast_dcache();
41700e73 AN	238	else
41700e73 AN	239	protected_blast_dcache_range(start, end);
1da177e4 LT	240
	241	if (end - start > icache_size)
	242	tx39_blast_icache();
	243	else {
	244	unsigned long flags, config;
1da177e4 LT	245	/* disable icache (set ICE#) */
	246	local_irq_save(flags);
	247	config = read_c0_conf();
	248	write_c0_conf(config & ~TX39_CONF_ICE);
	249	TX39_STOP_STREAMING();
41700e73	250	protected_blast_icache_range(start, end);
1da177e4 LT	251	write_c0_conf(config);
	252	local_irq_restore(flags);
	253	}
	254	}
	255
d9cdc901 RB	256	static void tx39_flush_kernel_vmap_range(unsigned long vaddr, int size)
	257	{
	258	BUG();
	259	}
	260
1da177e4 LT	261	static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size)
1da177e4 LT	262	{
41700e73	263	unsigned long end;
1da177e4 LT	264
	265	if (((size \| addr) & (PAGE_SIZE - 1)) == 0) {
	266	end = addr + size;
	267	do {
	268	tx39_blast_dcache_page(addr);
	269	addr += PAGE_SIZE;
	270	} while(addr != end);
	271	} else if (size > dcache_size) {
	272	tx39_blast_dcache();
	273	} else {
41700e73	274	blast_dcache_range(addr, addr + size);
1da177e4 LT	275	}
	276	}
	277
	278	static void tx39_dma_cache_inv(unsigned long addr, unsigned long size)
	279	{
41700e73	280	unsigned long end;
1da177e4 LT	281
	282	if (((size \| addr) & (PAGE_SIZE - 1)) == 0) {
	283	end = addr + size;
	284	do {
	285	tx39_blast_dcache_page(addr);
	286	addr += PAGE_SIZE;
	287	} while(addr != end);
	288	} else if (size > dcache_size) {
	289	tx39_blast_dcache();
	290	} else {
41700e73	291	blast_inv_dcache_range(addr, addr + size);
1da177e4 LT	292	}
	293	}
	294
	295	static void tx39_flush_cache_sigtramp(unsigned long addr)
	296	{
	297	unsigned long ic_lsize = current_cpu_data.icache.linesz;
	298	unsigned long dc_lsize = current_cpu_data.dcache.linesz;
	299	unsigned long config;
	300	unsigned long flags;
	301
	302	protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
	303
	304	/* disable icache (set ICE#) */
	305	local_irq_save(flags);
	306	config = read_c0_conf();
	307	write_c0_conf(config & ~TX39_CONF_ICE);
	308	TX39_STOP_STREAMING();
	309	protected_flush_icache_line(addr & ~(ic_lsize - 1));
	310	write_c0_conf(config);
	311	local_irq_restore(flags);
	312	}
	313
	314	static __init void tx39_probe_cache(void)
	315	{
	316	unsigned long config;
	317
	318	config = read_c0_conf();
	319
	320	icache_size = 1 << (10 + ((config & TX39_CONF_ICS_MASK) >>
	321	TX39_CONF_ICS_SHIFT));
	322	dcache_size = 1 << (10 + ((config & TX39_CONF_DCS_MASK) >>
	323	TX39_CONF_DCS_SHIFT));
	324
	325	current_cpu_data.icache.linesz = 16;
10cc3529	326	switch (current_cpu_type()) {
1da177e4 LT	327	case CPU_TX3912:
	328	current_cpu_data.icache.ways = 1;
	329	current_cpu_data.dcache.ways = 1;
	330	current_cpu_data.dcache.linesz = 4;
	331	break;
	332
	333	case CPU_TX3927:
	334	current_cpu_data.icache.ways = 2;
	335	current_cpu_data.dcache.ways = 2;
	336	current_cpu_data.dcache.linesz = 16;
	337	break;
	338
	339	case CPU_TX3922:
	340	default:
	341	current_cpu_data.icache.ways = 1;
	342	current_cpu_data.dcache.ways = 1;
	343	current_cpu_data.dcache.linesz = 16;
	344	break;
	345	}
	346	}
	347
234fcd14	348	void __cpuinit tx39_cache_init(void)
1da177e4 LT	349	{
	350	extern void build_clear_page(void);
	351	extern void build_copy_page(void);
	352	unsigned long config;
	353
	354	config = read_c0_conf();
	355	config &= ~TX39_CONF_WBON;
	356	write_c0_conf(config);
	357
	358	tx39_probe_cache();
	359
10cc3529	360	switch (current_cpu_type()) {
1da177e4 LT	361	case CPU_TX3912:
1da177e4 LT	362	/* TX39/H core (writethru direct-map cache) */
9c5a3d72 RB	363	__flush_cache_vmap = tx39__flush_cache_vmap;
9c5a3d72 RB	364	__flush_cache_vunmap = tx39__flush_cache_vunmap;
1da177e4 LT	365	flush_cache_all = tx39h_flush_icache_all;
	366	__flush_cache_all = tx39h_flush_icache_all;
	367	flush_cache_mm = (void *) tx39h_flush_icache_all;
	368	flush_cache_range = (void *) tx39h_flush_icache_all;
	369	flush_cache_page = (void *) tx39h_flush_icache_all;
1da177e4	370	flush_icache_range = (void *) tx39h_flush_icache_all;
e0cee3ee	371	local_flush_icache_range = (void *) tx39h_flush_icache_all;
1da177e4 LT	372
1da177e4 LT	373	flush_cache_sigtramp = (void *) tx39h_flush_icache_all;
7e3bfc7c	374	local_flush_data_cache_page = (void *) tx39h_flush_icache_all;
1da177e4 LT	375	flush_data_cache_page = (void *) tx39h_flush_icache_all;
	376
	377	_dma_cache_wback_inv = tx39h_dma_cache_wback_inv;
	378
	379	shm_align_mask = PAGE_SIZE - 1;
	380
	381	break;
	382
	383	case CPU_TX3922:
	384	case CPU_TX3927:
	385	default:
	386	/* TX39/H2,H3 core (writeback 2way-set-associative cache) */
	387	r3k_have_wired_reg = 1;
	388	write_c0_wired(0); /* set 8 on reset... */
	389	/* board-dependent init code may set WBON */
	390
9c5a3d72 RB	391	__flush_cache_vmap = tx39__flush_cache_vmap;
	392	__flush_cache_vunmap = tx39__flush_cache_vunmap;
	393
1da177e4 LT	394	flush_cache_all = tx39_flush_cache_all;
	395	__flush_cache_all = tx39___flush_cache_all;
	396	flush_cache_mm = tx39_flush_cache_mm;
	397	flush_cache_range = tx39_flush_cache_range;
	398	flush_cache_page = tx39_flush_cache_page;
1da177e4	399	flush_icache_range = tx39_flush_icache_range;
3885ec8c	400	local_flush_icache_range = tx39_flush_icache_range;
1da177e4	401
d9cdc901 RB	402	__flush_kernel_vmap_range = tx39_flush_kernel_vmap_range;
d9cdc901 RB	403
1da177e4	404	flush_cache_sigtramp = tx39_flush_cache_sigtramp;
7e3bfc7c	405	local_flush_data_cache_page = local_tx39_flush_data_cache_page;
1da177e4 LT	406	flush_data_cache_page = tx39_flush_data_cache_page;
	407
	408	_dma_cache_wback_inv = tx39_dma_cache_wback_inv;
	409	_dma_cache_wback = tx39_dma_cache_wback_inv;
	410	_dma_cache_inv = tx39_dma_cache_inv;
	411
	412	shm_align_mask = max_t(unsigned long,
	413	(dcache_size / current_cpu_data.dcache.ways) - 1,
	414	PAGE_SIZE - 1);
	415
	416	break;
	417	}
	418
	419	current_cpu_data.icache.waysize = icache_size / current_cpu_data.icache.ways;
	420	current_cpu_data.dcache.waysize = dcache_size / current_cpu_data.dcache.ways;
	421
	422	current_cpu_data.icache.sets =
	423	current_cpu_data.icache.waysize / current_cpu_data.icache.linesz;
	424	current_cpu_data.dcache.sets =
	425	current_cpu_data.dcache.waysize / current_cpu_data.dcache.linesz;
	426
	427	if (current_cpu_data.dcache.waysize > PAGE_SIZE)
	428	current_cpu_data.dcache.flags \|= MIPS_CACHE_ALIASES;
	429
	430	current_cpu_data.icache.waybit = 0;
	431	current_cpu_data.dcache.waybit = 0;
	432
	433	printk("Primary instruction cache %ldkB, linesize %d bytes\n",
	434	icache_size >> 10, current_cpu_data.icache.linesz);
	435	printk("Primary data cache %ldkB, linesize %d bytes\n",
	436	dcache_size >> 10, current_cpu_data.dcache.linesz);
	437
	438	build_clear_page();
	439	build_copy_page();
1d40cfcd	440	tx39h_flush_icache_all();
1da177e4	441	}