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fb2a27e7 TS |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2003, 04, 05 Ralf Baechle (ralf@linux-mips.org) | |
7 | * Copyright (C) 2007 Maciej W. Rozycki | |
8 | * Copyright (C) 2008 Thiemo Seufer | |
c0226306 | 9 | * Copyright (C) 2012 MIPS Technologies, Inc. |
fb2a27e7 TS |
10 | */ |
11 | #include <linux/init.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/sched.h> | |
631330f5 | 14 | #include <linux/smp.h> |
fb2a27e7 TS |
15 | #include <linux/mm.h> |
16 | #include <linux/module.h> | |
17 | #include <linux/proc_fs.h> | |
18 | ||
19 | #include <asm/bugs.h> | |
20 | #include <asm/cacheops.h> | |
21 | #include <asm/inst.h> | |
22 | #include <asm/io.h> | |
23 | #include <asm/page.h> | |
24 | #include <asm/pgtable.h> | |
25 | #include <asm/prefetch.h> | |
fb2a27e7 TS |
26 | #include <asm/bootinfo.h> |
27 | #include <asm/mipsregs.h> | |
28 | #include <asm/mmu_context.h> | |
29 | #include <asm/cpu.h> | |
30 | #include <asm/war.h> | |
31 | ||
32 | #ifdef CONFIG_SIBYTE_DMA_PAGEOPS | |
33 | #include <asm/sibyte/sb1250.h> | |
34 | #include <asm/sibyte/sb1250_regs.h> | |
35 | #include <asm/sibyte/sb1250_dma.h> | |
36 | #endif | |
37 | ||
3482d713 | 38 | #include <asm/uasm.h> |
fb2a27e7 TS |
39 | |
40 | /* Registers used in the assembled routines. */ | |
41 | #define ZERO 0 | |
42 | #define AT 2 | |
43 | #define A0 4 | |
44 | #define A1 5 | |
45 | #define A2 6 | |
46 | #define T0 8 | |
47 | #define T1 9 | |
48 | #define T2 10 | |
49 | #define T3 11 | |
50 | #define T9 25 | |
51 | #define RA 31 | |
52 | ||
53 | /* Handle labels (which must be positive integers). */ | |
54 | enum label_id { | |
55 | label_clear_nopref = 1, | |
56 | label_clear_pref, | |
57 | label_copy_nopref, | |
58 | label_copy_pref_both, | |
59 | label_copy_pref_store, | |
60 | }; | |
61 | ||
62 | UASM_L_LA(_clear_nopref) | |
63 | UASM_L_LA(_clear_pref) | |
64 | UASM_L_LA(_copy_nopref) | |
65 | UASM_L_LA(_copy_pref_both) | |
66 | UASM_L_LA(_copy_pref_store) | |
67 | ||
68 | /* We need one branch and therefore one relocation per target label. */ | |
69 | static struct uasm_label __cpuinitdata labels[5]; | |
70 | static struct uasm_reloc __cpuinitdata relocs[5]; | |
71 | ||
72 | #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) | |
73 | #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) | |
74 | ||
fb2a27e7 TS |
75 | static int pref_bias_clear_store __cpuinitdata; |
76 | static int pref_bias_copy_load __cpuinitdata; | |
77 | static int pref_bias_copy_store __cpuinitdata; | |
78 | ||
79 | static u32 pref_src_mode __cpuinitdata; | |
80 | static u32 pref_dst_mode __cpuinitdata; | |
81 | ||
82 | static int clear_word_size __cpuinitdata; | |
83 | static int copy_word_size __cpuinitdata; | |
84 | ||
85 | static int half_clear_loop_size __cpuinitdata; | |
86 | static int half_copy_loop_size __cpuinitdata; | |
87 | ||
88 | static int cache_line_size __cpuinitdata; | |
89 | #define cache_line_mask() (cache_line_size - 1) | |
90 | ||
91 | static inline void __cpuinit | |
92 | pg_addiu(u32 **buf, unsigned int reg1, unsigned int reg2, unsigned int off) | |
93 | { | |
94 | if (cpu_has_64bit_gp_regs && DADDI_WAR && r4k_daddiu_bug()) { | |
95 | if (off > 0x7fff) { | |
96 | uasm_i_lui(buf, T9, uasm_rel_hi(off)); | |
97 | uasm_i_addiu(buf, T9, T9, uasm_rel_lo(off)); | |
98 | } else | |
99 | uasm_i_addiu(buf, T9, ZERO, off); | |
100 | uasm_i_daddu(buf, reg1, reg2, T9); | |
101 | } else { | |
102 | if (off > 0x7fff) { | |
103 | uasm_i_lui(buf, T9, uasm_rel_hi(off)); | |
104 | uasm_i_addiu(buf, T9, T9, uasm_rel_lo(off)); | |
105 | UASM_i_ADDU(buf, reg1, reg2, T9); | |
106 | } else | |
107 | UASM_i_ADDIU(buf, reg1, reg2, off); | |
108 | } | |
109 | } | |
110 | ||
111 | static void __cpuinit set_prefetch_parameters(void) | |
112 | { | |
113 | if (cpu_has_64bit_gp_regs || cpu_has_64bit_zero_reg) | |
114 | clear_word_size = 8; | |
115 | else | |
116 | clear_word_size = 4; | |
117 | ||
118 | if (cpu_has_64bit_gp_regs) | |
119 | copy_word_size = 8; | |
120 | else | |
121 | copy_word_size = 4; | |
122 | ||
123 | /* | |
124 | * The pref's used here are using "streaming" hints, which cause the | |
125 | * copied data to be kicked out of the cache sooner. A page copy often | |
126 | * ends up copying a lot more data than is commonly used, so this seems | |
127 | * to make sense in terms of reducing cache pollution, but I've no real | |
128 | * performance data to back this up. | |
129 | */ | |
130 | if (cpu_has_prefetch) { | |
131 | /* | |
132 | * XXX: Most prefetch bias values in here are based on | |
133 | * guesswork. | |
134 | */ | |
135 | cache_line_size = cpu_dcache_line_size(); | |
136 | switch (current_cpu_type()) { | |
a644b277 | 137 | case CPU_R5500: |
fb2a27e7 | 138 | case CPU_TX49XX: |
a644b277 | 139 | /* These processors only support the Pref_Load. */ |
fb2a27e7 TS |
140 | pref_bias_copy_load = 256; |
141 | break; | |
142 | ||
fb2a27e7 TS |
143 | case CPU_R10000: |
144 | case CPU_R12000: | |
145 | case CPU_R14000: | |
146 | /* | |
147 | * Those values have been experimentally tuned for an | |
148 | * Origin 200. | |
149 | */ | |
150 | pref_bias_clear_store = 512; | |
151 | pref_bias_copy_load = 256; | |
152 | pref_bias_copy_store = 256; | |
153 | pref_src_mode = Pref_LoadStreamed; | |
154 | pref_dst_mode = Pref_StoreStreamed; | |
155 | break; | |
156 | ||
157 | case CPU_SB1: | |
158 | case CPU_SB1A: | |
159 | pref_bias_clear_store = 128; | |
160 | pref_bias_copy_load = 128; | |
161 | pref_bias_copy_store = 128; | |
162 | /* | |
163 | * SB1 pass1 Pref_LoadStreamed/Pref_StoreStreamed | |
164 | * hints are broken. | |
165 | */ | |
166 | if (current_cpu_type() == CPU_SB1 && | |
167 | (current_cpu_data.processor_id & 0xff) < 0x02) { | |
168 | pref_src_mode = Pref_Load; | |
169 | pref_dst_mode = Pref_Store; | |
170 | } else { | |
171 | pref_src_mode = Pref_LoadStreamed; | |
172 | pref_dst_mode = Pref_StoreStreamed; | |
173 | } | |
174 | break; | |
175 | ||
176 | default: | |
177 | pref_bias_clear_store = 128; | |
178 | pref_bias_copy_load = 256; | |
179 | pref_bias_copy_store = 128; | |
180 | pref_src_mode = Pref_LoadStreamed; | |
181 | pref_dst_mode = Pref_PrepareForStore; | |
182 | break; | |
183 | } | |
184 | } else { | |
185 | if (cpu_has_cache_cdex_s) | |
186 | cache_line_size = cpu_scache_line_size(); | |
187 | else if (cpu_has_cache_cdex_p) | |
188 | cache_line_size = cpu_dcache_line_size(); | |
189 | } | |
190 | /* | |
191 | * Too much unrolling will overflow the available space in | |
14defd90 | 192 | * clear_space_array / copy_page_array. |
fb2a27e7 | 193 | */ |
14defd90 | 194 | half_clear_loop_size = min(16 * clear_word_size, |
fb2a27e7 TS |
195 | max(cache_line_size >> 1, |
196 | 4 * clear_word_size)); | |
14defd90 | 197 | half_copy_loop_size = min(16 * copy_word_size, |
fb2a27e7 TS |
198 | max(cache_line_size >> 1, |
199 | 4 * copy_word_size)); | |
200 | } | |
201 | ||
202 | static void __cpuinit build_clear_store(u32 **buf, int off) | |
203 | { | |
204 | if (cpu_has_64bit_gp_regs || cpu_has_64bit_zero_reg) { | |
205 | uasm_i_sd(buf, ZERO, off, A0); | |
206 | } else { | |
207 | uasm_i_sw(buf, ZERO, off, A0); | |
208 | } | |
209 | } | |
210 | ||
211 | static inline void __cpuinit build_clear_pref(u32 **buf, int off) | |
212 | { | |
213 | if (off & cache_line_mask()) | |
214 | return; | |
215 | ||
216 | if (pref_bias_clear_store) { | |
217 | uasm_i_pref(buf, pref_dst_mode, pref_bias_clear_store + off, | |
218 | A0); | |
14defd90 TB |
219 | } else if (cache_line_size == (half_clear_loop_size << 1)) { |
220 | if (cpu_has_cache_cdex_s) { | |
221 | uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0); | |
222 | } else if (cpu_has_cache_cdex_p) { | |
223 | if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) { | |
224 | uasm_i_nop(buf); | |
225 | uasm_i_nop(buf); | |
226 | uasm_i_nop(buf); | |
227 | uasm_i_nop(buf); | |
228 | } | |
fb2a27e7 | 229 | |
14defd90 TB |
230 | if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) |
231 | uasm_i_lw(buf, ZERO, ZERO, AT); | |
fb2a27e7 | 232 | |
14defd90 TB |
233 | uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0); |
234 | } | |
235 | } | |
fb2a27e7 TS |
236 | } |
237 | ||
c0226306 SH |
238 | extern u32 __clear_page_start; |
239 | extern u32 __clear_page_end; | |
240 | extern u32 __copy_page_start; | |
241 | extern u32 __copy_page_end; | |
242 | ||
fb2a27e7 TS |
243 | void __cpuinit build_clear_page(void) |
244 | { | |
245 | int off; | |
c0226306 | 246 | u32 *buf = &__clear_page_start; |
fb2a27e7 TS |
247 | struct uasm_label *l = labels; |
248 | struct uasm_reloc *r = relocs; | |
249 | int i; | |
250 | ||
251 | memset(labels, 0, sizeof(labels)); | |
252 | memset(relocs, 0, sizeof(relocs)); | |
253 | ||
254 | set_prefetch_parameters(); | |
255 | ||
256 | /* | |
257 | * This algorithm makes the following assumptions: | |
258 | * - The prefetch bias is a multiple of 2 words. | |
259 | * - The prefetch bias is less than one page. | |
260 | */ | |
261 | BUG_ON(pref_bias_clear_store % (2 * clear_word_size)); | |
262 | BUG_ON(PAGE_SIZE < pref_bias_clear_store); | |
263 | ||
264 | off = PAGE_SIZE - pref_bias_clear_store; | |
265 | if (off > 0xffff || !pref_bias_clear_store) | |
266 | pg_addiu(&buf, A2, A0, off); | |
267 | else | |
268 | uasm_i_ori(&buf, A2, A0, off); | |
269 | ||
270 | if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) | |
271 | uasm_i_lui(&buf, AT, 0xa000); | |
272 | ||
cd9da13d | 273 | off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size) |
70342287 | 274 | * cache_line_size : 0; |
fb2a27e7 TS |
275 | while (off) { |
276 | build_clear_pref(&buf, -off); | |
277 | off -= cache_line_size; | |
278 | } | |
279 | uasm_l_clear_pref(&l, buf); | |
280 | do { | |
281 | build_clear_pref(&buf, off); | |
282 | build_clear_store(&buf, off); | |
283 | off += clear_word_size; | |
284 | } while (off < half_clear_loop_size); | |
285 | pg_addiu(&buf, A0, A0, 2 * off); | |
286 | off = -off; | |
287 | do { | |
288 | build_clear_pref(&buf, off); | |
289 | if (off == -clear_word_size) | |
290 | uasm_il_bne(&buf, &r, A0, A2, label_clear_pref); | |
291 | build_clear_store(&buf, off); | |
292 | off += clear_word_size; | |
293 | } while (off < 0); | |
294 | ||
295 | if (pref_bias_clear_store) { | |
296 | pg_addiu(&buf, A2, A0, pref_bias_clear_store); | |
297 | uasm_l_clear_nopref(&l, buf); | |
298 | off = 0; | |
299 | do { | |
300 | build_clear_store(&buf, off); | |
301 | off += clear_word_size; | |
302 | } while (off < half_clear_loop_size); | |
303 | pg_addiu(&buf, A0, A0, 2 * off); | |
304 | off = -off; | |
305 | do { | |
306 | if (off == -clear_word_size) | |
307 | uasm_il_bne(&buf, &r, A0, A2, | |
308 | label_clear_nopref); | |
309 | build_clear_store(&buf, off); | |
310 | off += clear_word_size; | |
311 | } while (off < 0); | |
312 | } | |
313 | ||
314 | uasm_i_jr(&buf, RA); | |
315 | uasm_i_nop(&buf); | |
316 | ||
c0226306 | 317 | BUG_ON(buf > &__clear_page_end); |
fb2a27e7 TS |
318 | |
319 | uasm_resolve_relocs(relocs, labels); | |
320 | ||
321 | pr_debug("Synthesized clear page handler (%u instructions).\n", | |
c0226306 | 322 | (u32)(buf - &__clear_page_start)); |
fb2a27e7 TS |
323 | |
324 | pr_debug("\t.set push\n"); | |
325 | pr_debug("\t.set noreorder\n"); | |
c0226306 SH |
326 | for (i = 0; i < (buf - &__clear_page_start); i++) |
327 | pr_debug("\t.word 0x%08x\n", (&__clear_page_start)[i]); | |
fb2a27e7 TS |
328 | pr_debug("\t.set pop\n"); |
329 | } | |
330 | ||
331 | static void __cpuinit build_copy_load(u32 **buf, int reg, int off) | |
332 | { | |
333 | if (cpu_has_64bit_gp_regs) { | |
334 | uasm_i_ld(buf, reg, off, A1); | |
335 | } else { | |
336 | uasm_i_lw(buf, reg, off, A1); | |
337 | } | |
338 | } | |
339 | ||
340 | static void __cpuinit build_copy_store(u32 **buf, int reg, int off) | |
341 | { | |
342 | if (cpu_has_64bit_gp_regs) { | |
343 | uasm_i_sd(buf, reg, off, A0); | |
344 | } else { | |
345 | uasm_i_sw(buf, reg, off, A0); | |
346 | } | |
347 | } | |
348 | ||
349 | static inline void build_copy_load_pref(u32 **buf, int off) | |
350 | { | |
351 | if (off & cache_line_mask()) | |
352 | return; | |
353 | ||
354 | if (pref_bias_copy_load) | |
355 | uasm_i_pref(buf, pref_src_mode, pref_bias_copy_load + off, A1); | |
356 | } | |
357 | ||
358 | static inline void build_copy_store_pref(u32 **buf, int off) | |
359 | { | |
360 | if (off & cache_line_mask()) | |
361 | return; | |
362 | ||
363 | if (pref_bias_copy_store) { | |
364 | uasm_i_pref(buf, pref_dst_mode, pref_bias_copy_store + off, | |
365 | A0); | |
14defd90 TB |
366 | } else if (cache_line_size == (half_copy_loop_size << 1)) { |
367 | if (cpu_has_cache_cdex_s) { | |
368 | uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0); | |
369 | } else if (cpu_has_cache_cdex_p) { | |
370 | if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) { | |
371 | uasm_i_nop(buf); | |
372 | uasm_i_nop(buf); | |
373 | uasm_i_nop(buf); | |
374 | uasm_i_nop(buf); | |
375 | } | |
fb2a27e7 | 376 | |
14defd90 TB |
377 | if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) |
378 | uasm_i_lw(buf, ZERO, ZERO, AT); | |
fb2a27e7 | 379 | |
14defd90 TB |
380 | uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0); |
381 | } | |
fb2a27e7 TS |
382 | } |
383 | } | |
384 | ||
385 | void __cpuinit build_copy_page(void) | |
386 | { | |
387 | int off; | |
c0226306 | 388 | u32 *buf = &__copy_page_start; |
fb2a27e7 TS |
389 | struct uasm_label *l = labels; |
390 | struct uasm_reloc *r = relocs; | |
391 | int i; | |
392 | ||
393 | memset(labels, 0, sizeof(labels)); | |
394 | memset(relocs, 0, sizeof(relocs)); | |
395 | ||
396 | set_prefetch_parameters(); | |
397 | ||
398 | /* | |
399 | * This algorithm makes the following assumptions: | |
400 | * - All prefetch biases are multiples of 8 words. | |
401 | * - The prefetch biases are less than one page. | |
402 | * - The store prefetch bias isn't greater than the load | |
403 | * prefetch bias. | |
404 | */ | |
405 | BUG_ON(pref_bias_copy_load % (8 * copy_word_size)); | |
406 | BUG_ON(pref_bias_copy_store % (8 * copy_word_size)); | |
407 | BUG_ON(PAGE_SIZE < pref_bias_copy_load); | |
408 | BUG_ON(pref_bias_copy_store > pref_bias_copy_load); | |
409 | ||
410 | off = PAGE_SIZE - pref_bias_copy_load; | |
411 | if (off > 0xffff || !pref_bias_copy_load) | |
412 | pg_addiu(&buf, A2, A0, off); | |
413 | else | |
414 | uasm_i_ori(&buf, A2, A0, off); | |
415 | ||
416 | if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) | |
417 | uasm_i_lui(&buf, AT, 0xa000); | |
418 | ||
cd9da13d | 419 | off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) * |
70342287 | 420 | cache_line_size : 0; |
fb2a27e7 TS |
421 | while (off) { |
422 | build_copy_load_pref(&buf, -off); | |
423 | off -= cache_line_size; | |
424 | } | |
7bd0fea2 | 425 | off = cache_line_size ? min(8, pref_bias_copy_store / cache_line_size) * |
70342287 | 426 | cache_line_size : 0; |
fb2a27e7 TS |
427 | while (off) { |
428 | build_copy_store_pref(&buf, -off); | |
429 | off -= cache_line_size; | |
430 | } | |
431 | uasm_l_copy_pref_both(&l, buf); | |
432 | do { | |
433 | build_copy_load_pref(&buf, off); | |
434 | build_copy_load(&buf, T0, off); | |
435 | build_copy_load_pref(&buf, off + copy_word_size); | |
436 | build_copy_load(&buf, T1, off + copy_word_size); | |
437 | build_copy_load_pref(&buf, off + 2 * copy_word_size); | |
438 | build_copy_load(&buf, T2, off + 2 * copy_word_size); | |
439 | build_copy_load_pref(&buf, off + 3 * copy_word_size); | |
440 | build_copy_load(&buf, T3, off + 3 * copy_word_size); | |
441 | build_copy_store_pref(&buf, off); | |
442 | build_copy_store(&buf, T0, off); | |
443 | build_copy_store_pref(&buf, off + copy_word_size); | |
444 | build_copy_store(&buf, T1, off + copy_word_size); | |
445 | build_copy_store_pref(&buf, off + 2 * copy_word_size); | |
446 | build_copy_store(&buf, T2, off + 2 * copy_word_size); | |
447 | build_copy_store_pref(&buf, off + 3 * copy_word_size); | |
448 | build_copy_store(&buf, T3, off + 3 * copy_word_size); | |
449 | off += 4 * copy_word_size; | |
450 | } while (off < half_copy_loop_size); | |
451 | pg_addiu(&buf, A1, A1, 2 * off); | |
452 | pg_addiu(&buf, A0, A0, 2 * off); | |
453 | off = -off; | |
454 | do { | |
455 | build_copy_load_pref(&buf, off); | |
456 | build_copy_load(&buf, T0, off); | |
457 | build_copy_load_pref(&buf, off + copy_word_size); | |
458 | build_copy_load(&buf, T1, off + copy_word_size); | |
459 | build_copy_load_pref(&buf, off + 2 * copy_word_size); | |
460 | build_copy_load(&buf, T2, off + 2 * copy_word_size); | |
461 | build_copy_load_pref(&buf, off + 3 * copy_word_size); | |
462 | build_copy_load(&buf, T3, off + 3 * copy_word_size); | |
463 | build_copy_store_pref(&buf, off); | |
464 | build_copy_store(&buf, T0, off); | |
465 | build_copy_store_pref(&buf, off + copy_word_size); | |
466 | build_copy_store(&buf, T1, off + copy_word_size); | |
467 | build_copy_store_pref(&buf, off + 2 * copy_word_size); | |
468 | build_copy_store(&buf, T2, off + 2 * copy_word_size); | |
469 | build_copy_store_pref(&buf, off + 3 * copy_word_size); | |
470 | if (off == -(4 * copy_word_size)) | |
471 | uasm_il_bne(&buf, &r, A2, A0, label_copy_pref_both); | |
472 | build_copy_store(&buf, T3, off + 3 * copy_word_size); | |
473 | off += 4 * copy_word_size; | |
474 | } while (off < 0); | |
475 | ||
476 | if (pref_bias_copy_load - pref_bias_copy_store) { | |
477 | pg_addiu(&buf, A2, A0, | |
478 | pref_bias_copy_load - pref_bias_copy_store); | |
479 | uasm_l_copy_pref_store(&l, buf); | |
480 | off = 0; | |
481 | do { | |
482 | build_copy_load(&buf, T0, off); | |
483 | build_copy_load(&buf, T1, off + copy_word_size); | |
484 | build_copy_load(&buf, T2, off + 2 * copy_word_size); | |
485 | build_copy_load(&buf, T3, off + 3 * copy_word_size); | |
486 | build_copy_store_pref(&buf, off); | |
487 | build_copy_store(&buf, T0, off); | |
488 | build_copy_store_pref(&buf, off + copy_word_size); | |
489 | build_copy_store(&buf, T1, off + copy_word_size); | |
490 | build_copy_store_pref(&buf, off + 2 * copy_word_size); | |
491 | build_copy_store(&buf, T2, off + 2 * copy_word_size); | |
492 | build_copy_store_pref(&buf, off + 3 * copy_word_size); | |
493 | build_copy_store(&buf, T3, off + 3 * copy_word_size); | |
494 | off += 4 * copy_word_size; | |
495 | } while (off < half_copy_loop_size); | |
496 | pg_addiu(&buf, A1, A1, 2 * off); | |
497 | pg_addiu(&buf, A0, A0, 2 * off); | |
498 | off = -off; | |
499 | do { | |
500 | build_copy_load(&buf, T0, off); | |
501 | build_copy_load(&buf, T1, off + copy_word_size); | |
502 | build_copy_load(&buf, T2, off + 2 * copy_word_size); | |
503 | build_copy_load(&buf, T3, off + 3 * copy_word_size); | |
504 | build_copy_store_pref(&buf, off); | |
505 | build_copy_store(&buf, T0, off); | |
506 | build_copy_store_pref(&buf, off + copy_word_size); | |
507 | build_copy_store(&buf, T1, off + copy_word_size); | |
508 | build_copy_store_pref(&buf, off + 2 * copy_word_size); | |
509 | build_copy_store(&buf, T2, off + 2 * copy_word_size); | |
510 | build_copy_store_pref(&buf, off + 3 * copy_word_size); | |
511 | if (off == -(4 * copy_word_size)) | |
512 | uasm_il_bne(&buf, &r, A2, A0, | |
513 | label_copy_pref_store); | |
514 | build_copy_store(&buf, T3, off + 3 * copy_word_size); | |
515 | off += 4 * copy_word_size; | |
516 | } while (off < 0); | |
517 | } | |
518 | ||
519 | if (pref_bias_copy_store) { | |
520 | pg_addiu(&buf, A2, A0, pref_bias_copy_store); | |
521 | uasm_l_copy_nopref(&l, buf); | |
522 | off = 0; | |
523 | do { | |
524 | build_copy_load(&buf, T0, off); | |
525 | build_copy_load(&buf, T1, off + copy_word_size); | |
526 | build_copy_load(&buf, T2, off + 2 * copy_word_size); | |
527 | build_copy_load(&buf, T3, off + 3 * copy_word_size); | |
528 | build_copy_store(&buf, T0, off); | |
529 | build_copy_store(&buf, T1, off + copy_word_size); | |
530 | build_copy_store(&buf, T2, off + 2 * copy_word_size); | |
531 | build_copy_store(&buf, T3, off + 3 * copy_word_size); | |
532 | off += 4 * copy_word_size; | |
533 | } while (off < half_copy_loop_size); | |
534 | pg_addiu(&buf, A1, A1, 2 * off); | |
535 | pg_addiu(&buf, A0, A0, 2 * off); | |
536 | off = -off; | |
537 | do { | |
538 | build_copy_load(&buf, T0, off); | |
539 | build_copy_load(&buf, T1, off + copy_word_size); | |
540 | build_copy_load(&buf, T2, off + 2 * copy_word_size); | |
541 | build_copy_load(&buf, T3, off + 3 * copy_word_size); | |
542 | build_copy_store(&buf, T0, off); | |
543 | build_copy_store(&buf, T1, off + copy_word_size); | |
544 | build_copy_store(&buf, T2, off + 2 * copy_word_size); | |
545 | if (off == -(4 * copy_word_size)) | |
546 | uasm_il_bne(&buf, &r, A2, A0, | |
547 | label_copy_nopref); | |
548 | build_copy_store(&buf, T3, off + 3 * copy_word_size); | |
549 | off += 4 * copy_word_size; | |
550 | } while (off < 0); | |
551 | } | |
552 | ||
553 | uasm_i_jr(&buf, RA); | |
554 | uasm_i_nop(&buf); | |
555 | ||
c0226306 | 556 | BUG_ON(buf > &__copy_page_end); |
fb2a27e7 TS |
557 | |
558 | uasm_resolve_relocs(relocs, labels); | |
559 | ||
560 | pr_debug("Synthesized copy page handler (%u instructions).\n", | |
c0226306 | 561 | (u32)(buf - &__copy_page_start)); |
fb2a27e7 TS |
562 | |
563 | pr_debug("\t.set push\n"); | |
564 | pr_debug("\t.set noreorder\n"); | |
c0226306 SH |
565 | for (i = 0; i < (buf - &__copy_page_start); i++) |
566 | pr_debug("\t.word 0x%08x\n", (&__copy_page_start)[i]); | |
fb2a27e7 TS |
567 | pr_debug("\t.set pop\n"); |
568 | } | |
569 | ||
570 | #ifdef CONFIG_SIBYTE_DMA_PAGEOPS | |
c0226306 SH |
571 | extern void clear_page_cpu(void *page); |
572 | extern void copy_page_cpu(void *to, void *from); | |
fb2a27e7 TS |
573 | |
574 | /* | |
575 | * Pad descriptors to cacheline, since each is exclusively owned by a | |
576 | * particular CPU. | |
577 | */ | |
578 | struct dmadscr { | |
579 | u64 dscr_a; | |
580 | u64 dscr_b; | |
581 | u64 pad_a; | |
582 | u64 pad_b; | |
583 | } ____cacheline_aligned_in_smp page_descr[DM_NUM_CHANNELS]; | |
584 | ||
585 | void sb1_dma_init(void) | |
586 | { | |
587 | int i; | |
588 | ||
589 | for (i = 0; i < DM_NUM_CHANNELS; i++) { | |
590 | const u64 base_val = CPHYSADDR((unsigned long)&page_descr[i]) | | |
591 | V_DM_DSCR_BASE_RINGSZ(1); | |
592 | void *base_reg = IOADDR(A_DM_REGISTER(i, R_DM_DSCR_BASE)); | |
593 | ||
594 | __raw_writeq(base_val, base_reg); | |
595 | __raw_writeq(base_val | M_DM_DSCR_BASE_RESET, base_reg); | |
596 | __raw_writeq(base_val | M_DM_DSCR_BASE_ENABL, base_reg); | |
597 | } | |
598 | } | |
599 | ||
600 | void clear_page(void *page) | |
601 | { | |
602 | u64 to_phys = CPHYSADDR((unsigned long)page); | |
603 | unsigned int cpu = smp_processor_id(); | |
604 | ||
605 | /* if the page is not in KSEG0, use old way */ | |
606 | if ((long)KSEGX((unsigned long)page) != (long)CKSEG0) | |
607 | return clear_page_cpu(page); | |
608 | ||
609 | page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_ZERO_MEM | | |
610 | M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT; | |
611 | page_descr[cpu].dscr_b = V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE); | |
612 | __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); | |
613 | ||
614 | /* | |
615 | * Don't really want to do it this way, but there's no | |
616 | * reliable way to delay completion detection. | |
617 | */ | |
618 | while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG))) | |
619 | & M_DM_DSCR_BASE_INTERRUPT)) | |
620 | ; | |
621 | __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); | |
622 | } | |
623 | ||
624 | void copy_page(void *to, void *from) | |
625 | { | |
626 | u64 from_phys = CPHYSADDR((unsigned long)from); | |
627 | u64 to_phys = CPHYSADDR((unsigned long)to); | |
628 | unsigned int cpu = smp_processor_id(); | |
629 | ||
630 | /* if any page is not in KSEG0, use old way */ | |
631 | if ((long)KSEGX((unsigned long)to) != (long)CKSEG0 | |
632 | || (long)KSEGX((unsigned long)from) != (long)CKSEG0) | |
633 | return copy_page_cpu(to, from); | |
634 | ||
635 | page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_L2C_DEST | | |
636 | M_DM_DSCRA_INTERRUPT; | |
637 | page_descr[cpu].dscr_b = from_phys | V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE); | |
638 | __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); | |
639 | ||
640 | /* | |
641 | * Don't really want to do it this way, but there's no | |
642 | * reliable way to delay completion detection. | |
643 | */ | |
644 | while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG))) | |
645 | & M_DM_DSCR_BASE_INTERRUPT)) | |
646 | ; | |
647 | __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); | |
648 | } | |
649 | ||
650 | #endif /* CONFIG_SIBYTE_DMA_PAGEOPS */ |