[deliverable/linux.git] / arch / mips / mm / tlb-r4k.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
 * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org
 * Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2002 MIPS Technologies, Inc.  All rights reserved.
 */
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/mm.h>
#include <linux/hugetlb.h>

#include <asm/cpu.h>
#include <asm/bootinfo.h>
#include <asm/mmu_context.h>
#include <asm/pgtable.h>
#include <asm/tlbmisc.h>

extern void build_tlb_refill_handler(void);

/*
 * Make sure all entries differ.  If they're not different
 * MIPS32 will take revenge ...
 */
#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))

/* Atomicity and interruptability */
#ifdef CONFIG_MIPS_MT_SMTC

#include <asm/smtc.h>
#include <asm/mipsmtregs.h>

#define ENTER_CRITICAL(flags) \
	{ \
	unsigned int mvpflags; \
	local_irq_save(flags);\
	mvpflags = dvpe()
#define EXIT_CRITICAL(flags) \
	evpe(mvpflags); \
	local_irq_restore(flags); \
	}
#else

#define ENTER_CRITICAL(flags) local_irq_save(flags)
#define EXIT_CRITICAL(flags) local_irq_restore(flags)

#endif /* CONFIG_MIPS_MT_SMTC */

#if defined(CONFIG_CPU_LOONGSON2)
/*
 * LOONGSON2 has a 4 entry itlb which is a subset of dtlb,
 * unfortrunately, itlb is not totally transparent to software.
 */
#define FLUSH_ITLB write_c0_diag(4);

#define FLUSH_ITLB_VM(vma) { if ((vma)->vm_flags & VM_EXEC)  write_c0_diag(4); }

#else

#define FLUSH_ITLB
#define FLUSH_ITLB_VM(vma)

#endif

void local_flush_tlb_all(void)
{
	unsigned long flags;
	unsigned long old_ctx;
	int entry;

	ENTER_CRITICAL(flags);
	/* Save old context and create impossible VPN2 value */
	old_ctx = read_c0_entryhi();
	write_c0_entrylo0(0);
	write_c0_entrylo1(0);

	entry = read_c0_wired();

	/* Blast 'em all away. */
	while (entry < current_cpu_data.tlbsize) {
		/* Make sure all entries differ. */
		write_c0_entryhi(UNIQUE_ENTRYHI(entry));
		write_c0_index(entry);
		mtc0_tlbw_hazard();
		tlb_write_indexed();
		entry++;
	}
	tlbw_use_hazard();
	write_c0_entryhi(old_ctx);
	FLUSH_ITLB;
	EXIT_CRITICAL(flags);
}

/* All entries common to a mm share an asid.  To effectively flush
   these entries, we just bump the asid. */
void local_flush_tlb_mm(struct mm_struct *mm)
{
	int cpu;

	preempt_disable();

	cpu = smp_processor_id();

	if (cpu_context(cpu, mm) != 0) {
		drop_mmu_context(mm, cpu);
	}

	preempt_enable();
}

void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
	unsigned long end)
{
	struct mm_struct *mm = vma->vm_mm;
	int cpu = smp_processor_id();

	if (cpu_context(cpu, mm) != 0) {
		unsigned long size, flags;

		ENTER_CRITICAL(flags);
		start = round_down(start, PAGE_SIZE << 1);
		end = round_up(end, PAGE_SIZE << 1);
		size = (end - start) >> (PAGE_SHIFT + 1);
		if (size <= current_cpu_data.tlbsize/2) {
			int oldpid = read_c0_entryhi();
			int newpid = cpu_asid(cpu, mm);

			while (start < end) {
				int idx;

				write_c0_entryhi(start | newpid);
				start += (PAGE_SIZE << 1);
				mtc0_tlbw_hazard();
				tlb_probe();
				tlb_probe_hazard();
				idx = read_c0_index();
				write_c0_entrylo0(0);
				write_c0_entrylo1(0);
				if (idx < 0)
					continue;
				/* Make sure all entries differ. */
				write_c0_entryhi(UNIQUE_ENTRYHI(idx));
				mtc0_tlbw_hazard();
				tlb_write_indexed();
			}
			tlbw_use_hazard();
			write_c0_entryhi(oldpid);
		} else {
			drop_mmu_context(mm, cpu);
		}
		FLUSH_ITLB;
		EXIT_CRITICAL(flags);
	}
}

void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
{
	unsigned long size, flags;

	ENTER_CRITICAL(flags);
	size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
	size = (size + 1) >> 1;
	if (size <= current_cpu_data.tlbsize / 2) {
		int pid = read_c0_entryhi();

		start &= (PAGE_MASK << 1);
		end += ((PAGE_SIZE << 1) - 1);
		end &= (PAGE_MASK << 1);

		while (start < end) {
			int idx;

			write_c0_entryhi(start);
			start += (PAGE_SIZE << 1);
			mtc0_tlbw_hazard();
			tlb_probe();
			tlb_probe_hazard();
			idx = read_c0_index();
			write_c0_entrylo0(0);
			write_c0_entrylo1(0);
			if (idx < 0)
				continue;
			/* Make sure all entries differ. */
			write_c0_entryhi(UNIQUE_ENTRYHI(idx));
			mtc0_tlbw_hazard();
			tlb_write_indexed();
		}
		tlbw_use_hazard();
		write_c0_entryhi(pid);
	} else {
		local_flush_tlb_all();
	}
	FLUSH_ITLB;
	EXIT_CRITICAL(flags);
}

void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
{
	int cpu = smp_processor_id();

	if (cpu_context(cpu, vma->vm_mm) != 0) {
		unsigned long flags;
		int oldpid, newpid, idx;

		newpid = cpu_asid(cpu, vma->vm_mm);
		page &= (PAGE_MASK << 1);
		ENTER_CRITICAL(flags);
		oldpid = read_c0_entryhi();
		write_c0_entryhi(page | newpid);
		mtc0_tlbw_hazard();
		tlb_probe();
		tlb_probe_hazard();
		idx = read_c0_index();
		write_c0_entrylo0(0);
		write_c0_entrylo1(0);
		if (idx < 0)
			goto finish;
		/* Make sure all entries differ. */
		write_c0_entryhi(UNIQUE_ENTRYHI(idx));
		mtc0_tlbw_hazard();
		tlb_write_indexed();
		tlbw_use_hazard();

	finish:
		write_c0_entryhi(oldpid);
		FLUSH_ITLB_VM(vma);
		EXIT_CRITICAL(flags);
	}
}

/*
 * This one is only used for pages with the global bit set so we don't care
 * much about the ASID.
 */
void local_flush_tlb_one(unsigned long page)
{
	unsigned long flags;
	int oldpid, idx;

	ENTER_CRITICAL(flags);
	oldpid = read_c0_entryhi();
	page &= (PAGE_MASK << 1);
	write_c0_entryhi(page);
	mtc0_tlbw_hazard();
	tlb_probe();
	tlb_probe_hazard();
	idx = read_c0_index();
	write_c0_entrylo0(0);
	write_c0_entrylo1(0);
	if (idx >= 0) {
		/* Make sure all entries differ. */
		write_c0_entryhi(UNIQUE_ENTRYHI(idx));
		mtc0_tlbw_hazard();
		tlb_write_indexed();
		tlbw_use_hazard();
	}
	write_c0_entryhi(oldpid);
	FLUSH_ITLB;
	EXIT_CRITICAL(flags);
}

/*
 * We will need multiple versions of update_mmu_cache(), one that just
 * updates the TLB with the new pte(s), and another which also checks
 * for the R4k "end of page" hardware bug and does the needy.
 */
void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
{
	unsigned long flags;
	pgd_t *pgdp;
	pud_t *pudp;
	pmd_t *pmdp;
	pte_t *ptep;
	int idx, pid;

	/*
	 * Handle debugger faulting in for debugee.
	 */
	if (current->active_mm != vma->vm_mm)
		return;

	ENTER_CRITICAL(flags);

	pid = read_c0_entryhi() & ASID_MASK;
	address &= (PAGE_MASK << 1);
	write_c0_entryhi(address | pid);
	pgdp = pgd_offset(vma->vm_mm, address);
	mtc0_tlbw_hazard();
	tlb_probe();
	tlb_probe_hazard();
	pudp = pud_offset(pgdp, address);
	pmdp = pmd_offset(pudp, address);
	idx = read_c0_index();
#ifdef CONFIG_HUGETLB_PAGE
	/* this could be a huge page  */
	if (pmd_huge(*pmdp)) {
		unsigned long lo;
		write_c0_pagemask(PM_HUGE_MASK);
		ptep = (pte_t *)pmdp;
		lo = pte_to_entrylo(pte_val(*ptep));
		write_c0_entrylo0(lo);
		write_c0_entrylo1(lo + (HPAGE_SIZE >> 7));

		mtc0_tlbw_hazard();
		if (idx < 0)
			tlb_write_random();
		else
			tlb_write_indexed();
		tlbw_use_hazard();
		write_c0_pagemask(PM_DEFAULT_MASK);
	} else
#endif
	{
		ptep = pte_offset_map(pmdp, address);

#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
		write_c0_entrylo0(ptep->pte_high);
		ptep++;
		write_c0_entrylo1(ptep->pte_high);
#else
		write_c0_entrylo0(pte_to_entrylo(pte_val(*ptep++)));
		write_c0_entrylo1(pte_to_entrylo(pte_val(*ptep)));
#endif
		mtc0_tlbw_hazard();
		if (idx < 0)
			tlb_write_random();
		else
			tlb_write_indexed();
	}
	tlbw_use_hazard();
	FLUSH_ITLB_VM(vma);
	EXIT_CRITICAL(flags);
}

void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
		     unsigned long entryhi, unsigned long pagemask)
{
	unsigned long flags;
	unsigned long wired;
	unsigned long old_pagemask;
	unsigned long old_ctx;

	ENTER_CRITICAL(flags);
	/* Save old context and create impossible VPN2 value */
	old_ctx = read_c0_entryhi();
	old_pagemask = read_c0_pagemask();
	wired = read_c0_wired();
	write_c0_wired(wired + 1);
	write_c0_index(wired);
	tlbw_use_hazard();	/* What is the hazard here? */
	write_c0_pagemask(pagemask);
	write_c0_entryhi(entryhi);
	write_c0_entrylo0(entrylo0);
	write_c0_entrylo1(entrylo1);
	mtc0_tlbw_hazard();
	tlb_write_indexed();
	tlbw_use_hazard();

	write_c0_entryhi(old_ctx);
	tlbw_use_hazard();	/* What is the hazard here? */
	write_c0_pagemask(old_pagemask);
	local_flush_tlb_all();
	EXIT_CRITICAL(flags);
}

static int __cpuinitdata ntlb;
static int __init set_ntlb(char *str)
{
	get_option(&str, &ntlb);
	return 1;
}

__setup("ntlb=", set_ntlb);

void __cpuinit tlb_init(void)
{
	/*
	 * You should never change this register:
	 *   - On R4600 1.7 the tlbp never hits for pages smaller than
	 *     the value in the c0_pagemask register.
	 *   - The entire mm handling assumes the c0_pagemask register to
	 *     be set to fixed-size pages.
	 */
	write_c0_pagemask(PM_DEFAULT_MASK);
	write_c0_wired(0);
	if (current_cpu_type() == CPU_R10000 ||
	    current_cpu_type() == CPU_R12000 ||
	    current_cpu_type() == CPU_R14000)
		write_c0_framemask(0);

	if (cpu_has_rixi) {
		/*
		 * Enable the no read, no exec bits, and enable large virtual
		 * address.
		 */
		u32 pg = PG_RIE | PG_XIE;
#ifdef CONFIG_64BIT
		pg |= PG_ELPA;
#endif
		write_c0_pagegrain(pg);
	}

        /* From this point on the ARC firmware is dead.  */
	local_flush_tlb_all();

	/* Did I tell you that ARC SUCKS?  */

	if (ntlb) {
		if (ntlb > 1 && ntlb <= current_cpu_data.tlbsize) {
			int wired = current_cpu_data.tlbsize - ntlb;
			write_c0_wired(wired);
			write_c0_index(wired-1);
			printk("Restricting TLB to %d entries\n", ntlb);
		} else
			printk("Ignoring invalid argument ntlb=%d\n", ntlb);
	}

	build_tlb_refill_handler();
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
79add627	6	* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
1da177e4 LT	7	* Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org
	8	* Carsten Langgaard, carstenl@mips.com
	9	* Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
	10	*/
1da177e4 LT	11	#include <linux/init.h>
1da177e4 LT	12	#include <linux/sched.h>
631330f5	13	#include <linux/smp.h>
1da177e4	14	#include <linux/mm.h>
fd062c84	15	#include <linux/hugetlb.h>
1da177e4 LT	16
	17	#include <asm/cpu.h>
	18	#include <asm/bootinfo.h>
	19	#include <asm/mmu_context.h>
	20	#include <asm/pgtable.h>
3d18c983	21	#include <asm/tlbmisc.h>
1da177e4 LT	22
	23	extern void build_tlb_refill_handler(void);
	24
172546bf TS	25	/*
	26	* Make sure all entries differ. If they're not different
	27	* MIPS32 will take revenge ...
	28	*/
	29	#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
	30
41c594ab RB	31	/* Atomicity and interruptability */
	32	#ifdef CONFIG_MIPS_MT_SMTC
	33
	34	#include <asm/smtc.h>
	35	#include <asm/mipsmtregs.h>
	36
	37	#define ENTER_CRITICAL(flags) \
	38	{ \
	39	unsigned int mvpflags; \
	40	local_irq_save(flags);\
	41	mvpflags = dvpe()
	42	#define EXIT_CRITICAL(flags) \
	43	evpe(mvpflags); \
	44	local_irq_restore(flags); \
	45	}
	46	#else
	47
	48	#define ENTER_CRITICAL(flags) local_irq_save(flags)
	49	#define EXIT_CRITICAL(flags) local_irq_restore(flags)
	50
	51	#endif /* CONFIG_MIPS_MT_SMTC */
	52
2a21c730 FZ	53	#if defined(CONFIG_CPU_LOONGSON2)
	54	/*
	55	* LOONGSON2 has a 4 entry itlb which is a subset of dtlb,
	56	* unfortrunately, itlb is not totally transparent to software.
	57	*/
	58	#define FLUSH_ITLB write_c0_diag(4);
	59
	60	#define FLUSH_ITLB_VM(vma) { if ((vma)->vm_flags & VM_EXEC) write_c0_diag(4); }
	61
	62	#else
	63
	64	#define FLUSH_ITLB
	65	#define FLUSH_ITLB_VM(vma)
	66
	67	#endif
	68
1da177e4 LT	69	void local_flush_tlb_all(void)
	70	{
	71	unsigned long flags;
	72	unsigned long old_ctx;
	73	int entry;
	74
41c594ab	75	ENTER_CRITICAL(flags);
1da177e4 LT	76	/* Save old context and create impossible VPN2 value */
	77	old_ctx = read_c0_entryhi();
	78	write_c0_entrylo0(0);
	79	write_c0_entrylo1(0);
	80
	81	entry = read_c0_wired();
	82
	83	/* Blast 'em all away. */
	84	while (entry < current_cpu_data.tlbsize) {
172546bf TS	85	/* Make sure all entries differ. */
172546bf TS	86	write_c0_entryhi(UNIQUE_ENTRYHI(entry));
1da177e4 LT	87	write_c0_index(entry);
	88	mtc0_tlbw_hazard();
	89	tlb_write_indexed();
	90	entry++;
	91	}
	92	tlbw_use_hazard();
	93	write_c0_entryhi(old_ctx);
2a21c730	94	FLUSH_ITLB;
41c594ab	95	EXIT_CRITICAL(flags);
1da177e4 LT	96	}
1da177e4 LT	97
172546bf TS	98	/* All entries common to a mm share an asid. To effectively flush
172546bf TS	99	these entries, we just bump the asid. */
1da177e4 LT	100	void local_flush_tlb_mm(struct mm_struct *mm)
1da177e4 LT	101	{
172546bf TS	102	int cpu;
	103
	104	preempt_disable();
1da177e4	105
172546bf TS	106	cpu = smp_processor_id();
	107
	108	if (cpu_context(cpu, mm) != 0) {
	109	drop_mmu_context(mm, cpu);
	110	}
	111
	112	preempt_enable();
1da177e4 LT	113	}
	114
	115	void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
	116	unsigned long end)
	117	{
	118	struct mm_struct *mm = vma->vm_mm;
	119	int cpu = smp_processor_id();
	120
	121	if (cpu_context(cpu, mm) != 0) {
a5e696e5	122	unsigned long size, flags;
1da177e4	123
41c594ab	124	ENTER_CRITICAL(flags);
ac53c4fc DD	125	start = round_down(start, PAGE_SIZE << 1);
	126	end = round_up(end, PAGE_SIZE << 1);
	127	size = (end - start) >> (PAGE_SHIFT + 1);
1da177e4 LT	128	if (size <= current_cpu_data.tlbsize/2) {
	129	int oldpid = read_c0_entryhi();
	130	int newpid = cpu_asid(cpu, mm);
	131
1da177e4 LT	132	while (start < end) {
	133	int idx;
	134
	135	write_c0_entryhi(start \| newpid);
ac53c4fc	136	start += (PAGE_SIZE << 1);
1da177e4 LT	137	mtc0_tlbw_hazard();
1da177e4 LT	138	tlb_probe();
432bef2a	139	tlb_probe_hazard();
1da177e4 LT	140	idx = read_c0_index();
	141	write_c0_entrylo0(0);
	142	write_c0_entrylo1(0);
	143	if (idx < 0)
	144	continue;
	145	/* Make sure all entries differ. */
172546bf	146	write_c0_entryhi(UNIQUE_ENTRYHI(idx));
1da177e4 LT	147	mtc0_tlbw_hazard();
	148	tlb_write_indexed();
	149	}
	150	tlbw_use_hazard();
	151	write_c0_entryhi(oldpid);
	152	} else {
	153	drop_mmu_context(mm, cpu);
	154	}
2a21c730	155	FLUSH_ITLB;
41c594ab	156	EXIT_CRITICAL(flags);
1da177e4 LT	157	}
	158	}
	159
	160	void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
	161	{
a5e696e5	162	unsigned long size, flags;
1da177e4	163
41c594ab	164	ENTER_CRITICAL(flags);
1da177e4 LT	165	size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
	166	size = (size + 1) >> 1;
	167	if (size <= current_cpu_data.tlbsize / 2) {
	168	int pid = read_c0_entryhi();
	169
	170	start &= (PAGE_MASK << 1);
	171	end += ((PAGE_SIZE << 1) - 1);
	172	end &= (PAGE_MASK << 1);
	173
	174	while (start < end) {
	175	int idx;
	176
	177	write_c0_entryhi(start);
	178	start += (PAGE_SIZE << 1);
	179	mtc0_tlbw_hazard();
	180	tlb_probe();
432bef2a	181	tlb_probe_hazard();
1da177e4 LT	182	idx = read_c0_index();
	183	write_c0_entrylo0(0);
	184	write_c0_entrylo1(0);
	185	if (idx < 0)
	186	continue;
	187	/* Make sure all entries differ. */
172546bf	188	write_c0_entryhi(UNIQUE_ENTRYHI(idx));
1da177e4 LT	189	mtc0_tlbw_hazard();
	190	tlb_write_indexed();
	191	}
	192	tlbw_use_hazard();
	193	write_c0_entryhi(pid);
	194	} else {
	195	local_flush_tlb_all();
	196	}
2a21c730	197	FLUSH_ITLB;
41c594ab	198	EXIT_CRITICAL(flags);
1da177e4 LT	199	}
	200
	201	void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
	202	{
	203	int cpu = smp_processor_id();
	204
	205	if (cpu_context(cpu, vma->vm_mm) != 0) {
	206	unsigned long flags;
	207	int oldpid, newpid, idx;
	208
	209	newpid = cpu_asid(cpu, vma->vm_mm);
	210	page &= (PAGE_MASK << 1);
41c594ab	211	ENTER_CRITICAL(flags);
1da177e4 LT	212	oldpid = read_c0_entryhi();
	213	write_c0_entryhi(page \| newpid);
	214	mtc0_tlbw_hazard();
	215	tlb_probe();
432bef2a	216	tlb_probe_hazard();
1da177e4 LT	217	idx = read_c0_index();
	218	write_c0_entrylo0(0);
	219	write_c0_entrylo1(0);
	220	if (idx < 0)
	221	goto finish;
	222	/* Make sure all entries differ. */
172546bf	223	write_c0_entryhi(UNIQUE_ENTRYHI(idx));
1da177e4 LT	224	mtc0_tlbw_hazard();
	225	tlb_write_indexed();
	226	tlbw_use_hazard();
	227
	228	finish:
	229	write_c0_entryhi(oldpid);
2a21c730	230	FLUSH_ITLB_VM(vma);
41c594ab	231	EXIT_CRITICAL(flags);
1da177e4 LT	232	}
	233	}
	234
	235	/*
	236	* This one is only used for pages with the global bit set so we don't care
	237	* much about the ASID.
	238	*/
	239	void local_flush_tlb_one(unsigned long page)
	240	{
	241	unsigned long flags;
	242	int oldpid, idx;
	243
41c594ab	244	ENTER_CRITICAL(flags);
1da177e4	245	oldpid = read_c0_entryhi();
172546bf	246	page &= (PAGE_MASK << 1);
1da177e4 LT	247	write_c0_entryhi(page);
	248	mtc0_tlbw_hazard();
	249	tlb_probe();
432bef2a	250	tlb_probe_hazard();
1da177e4 LT	251	idx = read_c0_index();
	252	write_c0_entrylo0(0);
	253	write_c0_entrylo1(0);
	254	if (idx >= 0) {
	255	/* Make sure all entries differ. */
172546bf	256	write_c0_entryhi(UNIQUE_ENTRYHI(idx));
1da177e4 LT	257	mtc0_tlbw_hazard();
	258	tlb_write_indexed();
	259	tlbw_use_hazard();
	260	}
	261	write_c0_entryhi(oldpid);
2a21c730	262	FLUSH_ITLB;
41c594ab	263	EXIT_CRITICAL(flags);
1da177e4 LT	264	}
	265
	266	/*
	267	* We will need multiple versions of update_mmu_cache(), one that just
	268	* updates the TLB with the new pte(s), and another which also checks
	269	* for the R4k "end of page" hardware bug and does the needy.
	270	*/
	271	void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
	272	{
	273	unsigned long flags;
	274	pgd_t *pgdp;
c6e8b587	275	pud_t *pudp;
1da177e4 LT	276	pmd_t *pmdp;
	277	pte_t *ptep;
	278	int idx, pid;
	279
	280	/*
	281	* Handle debugger faulting in for debugee.
	282	*/
	283	if (current->active_mm != vma->vm_mm)
	284	return;
	285
41c594ab	286	ENTER_CRITICAL(flags);
172546bf TS	287
172546bf TS	288	pid = read_c0_entryhi() & ASID_MASK;
1da177e4 LT	289	address &= (PAGE_MASK << 1);
	290	write_c0_entryhi(address \| pid);
	291	pgdp = pgd_offset(vma->vm_mm, address);
	292	mtc0_tlbw_hazard();
	293	tlb_probe();
432bef2a	294	tlb_probe_hazard();
c6e8b587 RB	295	pudp = pud_offset(pgdp, address);
c6e8b587 RB	296	pmdp = pmd_offset(pudp, address);
1da177e4	297	idx = read_c0_index();
fd062c84 DD	298	#ifdef CONFIG_HUGETLB_PAGE
	299	/* this could be a huge page */
	300	if (pmd_huge(*pmdp)) {
	301	unsigned long lo;
	302	write_c0_pagemask(PM_HUGE_MASK);
	303	ptep = (pte_t *)pmdp;
6dd9344c	304	lo = pte_to_entrylo(pte_val(*ptep));
fd062c84 DD	305	write_c0_entrylo0(lo);
	306	write_c0_entrylo1(lo + (HPAGE_SIZE >> 7));
	307
	308	mtc0_tlbw_hazard();
	309	if (idx < 0)
	310	tlb_write_random();
	311	else
	312	tlb_write_indexed();
fb944c9b	313	tlbw_use_hazard();
fd062c84 DD	314	write_c0_pagemask(PM_DEFAULT_MASK);
	315	} else
	316	#endif
	317	{
	318	ptep = pte_offset_map(pmdp, address);
1da177e4	319
962f480e	320	#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
fd062c84 DD	321	write_c0_entrylo0(ptep->pte_high);
	322	ptep++;
	323	write_c0_entrylo1(ptep->pte_high);
1da177e4	324	#else
6dd9344c DD	325	write_c0_entrylo0(pte_to_entrylo(pte_val(*ptep++)));
6dd9344c DD	326	write_c0_entrylo1(pte_to_entrylo(pte_val(*ptep)));
1da177e4	327	#endif
fd062c84 DD	328	mtc0_tlbw_hazard();
	329	if (idx < 0)
	330	tlb_write_random();
	331	else
	332	tlb_write_indexed();
	333	}
1da177e4	334	tlbw_use_hazard();
2a21c730	335	FLUSH_ITLB_VM(vma);
41c594ab	336	EXIT_CRITICAL(flags);
1da177e4 LT	337	}
1da177e4 LT	338
694b8c35 ML	339	void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
694b8c35 ML	340	unsigned long entryhi, unsigned long pagemask)
1da177e4 LT	341	{
	342	unsigned long flags;
	343	unsigned long wired;
	344	unsigned long old_pagemask;
	345	unsigned long old_ctx;
	346
41c594ab	347	ENTER_CRITICAL(flags);
1da177e4 LT	348	/* Save old context and create impossible VPN2 value */
	349	old_ctx = read_c0_entryhi();
	350	old_pagemask = read_c0_pagemask();
	351	wired = read_c0_wired();
	352	write_c0_wired(wired + 1);
	353	write_c0_index(wired);
432bef2a	354	tlbw_use_hazard(); /* What is the hazard here? */
1da177e4 LT	355	write_c0_pagemask(pagemask);
	356	write_c0_entryhi(entryhi);
	357	write_c0_entrylo0(entrylo0);
	358	write_c0_entrylo1(entrylo1);
	359	mtc0_tlbw_hazard();
	360	tlb_write_indexed();
	361	tlbw_use_hazard();
	362
	363	write_c0_entryhi(old_ctx);
432bef2a	364	tlbw_use_hazard(); /* What is the hazard here? */
1da177e4 LT	365	write_c0_pagemask(old_pagemask);
1da177e4 LT	366	local_flush_tlb_all();
41c594ab	367	EXIT_CRITICAL(flags);
1da177e4 LT	368	}
1da177e4 LT	369
982f6ffe	370	static int __cpuinitdata ntlb;
41c594ab RB	371	static int __init set_ntlb(char *str)
	372	{
	373	get_option(&str, &ntlb);
	374	return 1;
	375	}
	376
	377	__setup("ntlb=", set_ntlb);
	378
234fcd14	379	void __cpuinit tlb_init(void)
1da177e4	380	{
1da177e4 LT	381	/*
	382	* You should never change this register:
	383	* - On R4600 1.7 the tlbp never hits for pages smaller than
	384	* the value in the c0_pagemask register.
	385	* - The entire mm handling assumes the c0_pagemask register to
a7c2996e	386	* be set to fixed-size pages.
1da177e4	387	*/
1da177e4 LT	388	write_c0_pagemask(PM_DEFAULT_MASK);
1da177e4 LT	389	write_c0_wired(0);
cde15b59 RB	390	if (current_cpu_type() == CPU_R10000 \|\|
	391	current_cpu_type() == CPU_R12000 \|\|
	392	current_cpu_type() == CPU_R14000)
	393	write_c0_framemask(0);
6dd9344c	394
05857c64	395	if (cpu_has_rixi) {
6dd9344c DD	396	/*
	397	* Enable the no read, no exec bits, and enable large virtual
	398	* address.
	399	*/
	400	u32 pg = PG_RIE \| PG_XIE;
	401	#ifdef CONFIG_64BIT
	402	pg \|= PG_ELPA;
	403	#endif
	404	write_c0_pagegrain(pg);
	405	}
	406
c6281edb	407	/* From this point on the ARC firmware is dead. */
1da177e4 LT	408	local_flush_tlb_all();
1da177e4 LT	409
c6281edb TS	410	/* Did I tell you that ARC SUCKS? */
c6281edb TS	411
41c594ab RB	412	if (ntlb) {
	413	if (ntlb > 1 && ntlb <= current_cpu_data.tlbsize) {
	414	int wired = current_cpu_data.tlbsize - ntlb;
	415	write_c0_wired(wired);
	416	write_c0_index(wired-1);
49a89efb	417	printk("Restricting TLB to %d entries\n", ntlb);
41c594ab RB	418	} else
	419	printk("Ignoring invalid argument ntlb=%d\n", ntlb);
	420	}
	421
1da177e4 LT	422	build_tlb_refill_handler();
1da177e4 LT	423	}