[deliverable/linux.git] / arch / mips / mm / tlb-r4k.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
 * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org
 * Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2002 MIPS Technologies, Inc.  All rights reserved.
 */
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/mm.h>
#include <linux/hugetlb.h>
#include <linux/module.h>

#include <asm/cpu.h>
#include <asm/bootinfo.h>
#include <asm/mmu_context.h>
#include <asm/pgtable.h>
#include <asm/tlbmisc.h>

extern void build_tlb_refill_handler(void);

/*
 * Make sure all entries differ.  If they're not different
 * MIPS32 will take revenge ...
 */
#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))

/* Atomicity and interruptability */
#ifdef CONFIG_MIPS_MT_SMTC

#include <asm/smtc.h>
#include <asm/mipsmtregs.h>

#define ENTER_CRITICAL(flags) \
	{ \
	unsigned int mvpflags; \
	local_irq_save(flags);\
	mvpflags = dvpe()
#define EXIT_CRITICAL(flags) \
	evpe(mvpflags); \
	local_irq_restore(flags); \
	}
#else

#define ENTER_CRITICAL(flags) local_irq_save(flags)
#define EXIT_CRITICAL(flags) local_irq_restore(flags)

#endif /* CONFIG_MIPS_MT_SMTC */

#if defined(CONFIG_CPU_LOONGSON2)
/*
 * LOONGSON2 has a 4 entry itlb which is a subset of dtlb,
 * unfortrunately, itlb is not totally transparent to software.
 */
#define FLUSH_ITLB write_c0_diag(4);

#define FLUSH_ITLB_VM(vma) { if ((vma)->vm_flags & VM_EXEC)  write_c0_diag(4); }

#else

#define FLUSH_ITLB
#define FLUSH_ITLB_VM(vma)

#endif

void local_flush_tlb_all(void)
{
	unsigned long flags;
	unsigned long old_ctx;
	int entry;

	ENTER_CRITICAL(flags);
	/* Save old context and create impossible VPN2 value */
	old_ctx = read_c0_entryhi();
	write_c0_entrylo0(0);
	write_c0_entrylo1(0);

	entry = read_c0_wired();

	/* Blast 'em all away. */
	while (entry < current_cpu_data.tlbsize) {
		/* Make sure all entries differ. */
		write_c0_entryhi(UNIQUE_ENTRYHI(entry));
		write_c0_index(entry);
		mtc0_tlbw_hazard();
		tlb_write_indexed();
		entry++;
	}
	tlbw_use_hazard();
	write_c0_entryhi(old_ctx);
	FLUSH_ITLB;
	EXIT_CRITICAL(flags);
}
EXPORT_SYMBOL(local_flush_tlb_all);

/* All entries common to a mm share an asid.  To effectively flush
   these entries, we just bump the asid. */
void local_flush_tlb_mm(struct mm_struct *mm)
{
	int cpu;

	preempt_disable();

	cpu = smp_processor_id();

	if (cpu_context(cpu, mm) != 0) {
		drop_mmu_context(mm, cpu);
	}

	preempt_enable();
}

void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
	unsigned long end)
{
	struct mm_struct *mm = vma->vm_mm;
	int cpu = smp_processor_id();

	if (cpu_context(cpu, mm) != 0) {
		unsigned long size, flags;

		ENTER_CRITICAL(flags);
		start = round_down(start, PAGE_SIZE << 1);
		end = round_up(end, PAGE_SIZE << 1);
		size = (end - start) >> (PAGE_SHIFT + 1);
		if (size <= current_cpu_data.tlbsize/2) {
			int oldpid = read_c0_entryhi();
			int newpid = cpu_asid(cpu, mm);

			while (start < end) {
				int idx;

				write_c0_entryhi(start | newpid);
				start += (PAGE_SIZE << 1);
				mtc0_tlbw_hazard();
				tlb_probe();
				tlb_probe_hazard();
				idx = read_c0_index();
				write_c0_entrylo0(0);
				write_c0_entrylo1(0);
				if (idx < 0)
					continue;
				/* Make sure all entries differ. */
				write_c0_entryhi(UNIQUE_ENTRYHI(idx));
				mtc0_tlbw_hazard();
				tlb_write_indexed();
			}
			tlbw_use_hazard();
			write_c0_entryhi(oldpid);
		} else {
			drop_mmu_context(mm, cpu);
		}
		FLUSH_ITLB;
		EXIT_CRITICAL(flags);
	}
}

void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
{
	unsigned long size, flags;

	ENTER_CRITICAL(flags);
	size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
	size = (size + 1) >> 1;
	if (size <= current_cpu_data.tlbsize / 2) {
		int pid = read_c0_entryhi();

		start &= (PAGE_MASK << 1);
		end += ((PAGE_SIZE << 1) - 1);
		end &= (PAGE_MASK << 1);

		while (start < end) {
			int idx;

			write_c0_entryhi(start);
			start += (PAGE_SIZE << 1);
			mtc0_tlbw_hazard();
			tlb_probe();
			tlb_probe_hazard();
			idx = read_c0_index();
			write_c0_entrylo0(0);
			write_c0_entrylo1(0);
			if (idx < 0)
				continue;
			/* Make sure all entries differ. */
			write_c0_entryhi(UNIQUE_ENTRYHI(idx));
			mtc0_tlbw_hazard();
			tlb_write_indexed();
		}
		tlbw_use_hazard();
		write_c0_entryhi(pid);
	} else {
		local_flush_tlb_all();
	}
	FLUSH_ITLB;
	EXIT_CRITICAL(flags);
}

void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
{
	int cpu = smp_processor_id();

	if (cpu_context(cpu, vma->vm_mm) != 0) {
		unsigned long flags;
		int oldpid, newpid, idx;

		newpid = cpu_asid(cpu, vma->vm_mm);
		page &= (PAGE_MASK << 1);
		ENTER_CRITICAL(flags);
		oldpid = read_c0_entryhi();
		write_c0_entryhi(page | newpid);
		mtc0_tlbw_hazard();
		tlb_probe();
		tlb_probe_hazard();
		idx = read_c0_index();
		write_c0_entrylo0(0);
		write_c0_entrylo1(0);
		if (idx < 0)
			goto finish;
		/* Make sure all entries differ. */
		write_c0_entryhi(UNIQUE_ENTRYHI(idx));
		mtc0_tlbw_hazard();
		tlb_write_indexed();
		tlbw_use_hazard();

	finish:
		write_c0_entryhi(oldpid);
		FLUSH_ITLB_VM(vma);
		EXIT_CRITICAL(flags);
	}
}

/*
 * This one is only used for pages with the global bit set so we don't care
 * much about the ASID.
 */
void local_flush_tlb_one(unsigned long page)
{
	unsigned long flags;
	int oldpid, idx;

	ENTER_CRITICAL(flags);
	oldpid = read_c0_entryhi();
	page &= (PAGE_MASK << 1);
	write_c0_entryhi(page);
	mtc0_tlbw_hazard();
	tlb_probe();
	tlb_probe_hazard();
	idx = read_c0_index();
	write_c0_entrylo0(0);
	write_c0_entrylo1(0);
	if (idx >= 0) {
		/* Make sure all entries differ. */
		write_c0_entryhi(UNIQUE_ENTRYHI(idx));
		mtc0_tlbw_hazard();
		tlb_write_indexed();
		tlbw_use_hazard();
	}
	write_c0_entryhi(oldpid);
	FLUSH_ITLB;
	EXIT_CRITICAL(flags);
}

/*
 * We will need multiple versions of update_mmu_cache(), one that just
 * updates the TLB with the new pte(s), and another which also checks
 * for the R4k "end of page" hardware bug and does the needy.
 */
void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
{
	unsigned long flags;
	pgd_t *pgdp;
	pud_t *pudp;
	pmd_t *pmdp;
	pte_t *ptep;
	int idx, pid;

	/*
	 * Handle debugger faulting in for debugee.
	 */
	if (current->active_mm != vma->vm_mm)
		return;

	ENTER_CRITICAL(flags);

	pid = read_c0_entryhi() & ASID_MASK;
	address &= (PAGE_MASK << 1);
	write_c0_entryhi(address | pid);
	pgdp = pgd_offset(vma->vm_mm, address);
	mtc0_tlbw_hazard();
	tlb_probe();
	tlb_probe_hazard();
	pudp = pud_offset(pgdp, address);
	pmdp = pmd_offset(pudp, address);
	idx = read_c0_index();
#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
	/* this could be a huge page  */
	if (pmd_huge(*pmdp)) {
		unsigned long lo;
		write_c0_pagemask(PM_HUGE_MASK);
		ptep = (pte_t *)pmdp;
		lo = pte_to_entrylo(pte_val(*ptep));
		write_c0_entrylo0(lo);
		write_c0_entrylo1(lo + (HPAGE_SIZE >> 7));

		mtc0_tlbw_hazard();
		if (idx < 0)
			tlb_write_random();
		else
			tlb_write_indexed();
		tlbw_use_hazard();
		write_c0_pagemask(PM_DEFAULT_MASK);
	} else
#endif
	{
		ptep = pte_offset_map(pmdp, address);

#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
		write_c0_entrylo0(ptep->pte_high);
		ptep++;
		write_c0_entrylo1(ptep->pte_high);
#else
		write_c0_entrylo0(pte_to_entrylo(pte_val(*ptep++)));
		write_c0_entrylo1(pte_to_entrylo(pte_val(*ptep)));
#endif
		mtc0_tlbw_hazard();
		if (idx < 0)
			tlb_write_random();
		else
			tlb_write_indexed();
	}
	tlbw_use_hazard();
	FLUSH_ITLB_VM(vma);
	EXIT_CRITICAL(flags);
}

void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
		     unsigned long entryhi, unsigned long pagemask)
{
	unsigned long flags;
	unsigned long wired;
	unsigned long old_pagemask;
	unsigned long old_ctx;

	ENTER_CRITICAL(flags);
	/* Save old context and create impossible VPN2 value */
	old_ctx = read_c0_entryhi();
	old_pagemask = read_c0_pagemask();
	wired = read_c0_wired();
	write_c0_wired(wired + 1);
	write_c0_index(wired);
	tlbw_use_hazard();	/* What is the hazard here? */
	write_c0_pagemask(pagemask);
	write_c0_entryhi(entryhi);
	write_c0_entrylo0(entrylo0);
	write_c0_entrylo1(entrylo1);
	mtc0_tlbw_hazard();
	tlb_write_indexed();
	tlbw_use_hazard();

	write_c0_entryhi(old_ctx);
	tlbw_use_hazard();	/* What is the hazard here? */
	write_c0_pagemask(old_pagemask);
	local_flush_tlb_all();
	EXIT_CRITICAL(flags);
}

#ifdef CONFIG_TRANSPARENT_HUGEPAGE

int __init has_transparent_hugepage(void)
{
	unsigned int mask;
	unsigned long flags;

	ENTER_CRITICAL(flags);
	write_c0_pagemask(PM_HUGE_MASK);
	back_to_back_c0_hazard();
	mask = read_c0_pagemask();
	write_c0_pagemask(PM_DEFAULT_MASK);

	EXIT_CRITICAL(flags);

	return mask == PM_HUGE_MASK;
}

#endif /* CONFIG_TRANSPARENT_HUGEPAGE  */

static int ntlb;
static int __init set_ntlb(char *str)
{
	get_option(&str, &ntlb);
	return 1;
}

__setup("ntlb=", set_ntlb);

void tlb_init(void)
{
	/*
	 * You should never change this register:
	 *   - On R4600 1.7 the tlbp never hits for pages smaller than
	 *     the value in the c0_pagemask register.
	 *   - The entire mm handling assumes the c0_pagemask register to
	 *     be set to fixed-size pages.
	 */
	write_c0_pagemask(PM_DEFAULT_MASK);
	write_c0_wired(0);
	if (current_cpu_type() == CPU_R10000 ||
	    current_cpu_type() == CPU_R12000 ||
	    current_cpu_type() == CPU_R14000)
		write_c0_framemask(0);

	if (cpu_has_rixi) {
		/*
		 * Enable the no read, no exec bits, and enable large virtual
		 * address.
		 */
		u32 pg = PG_RIE | PG_XIE;
#ifdef CONFIG_64BIT
		pg |= PG_ELPA;
#endif
		write_c0_pagegrain(pg);
	}

	/* From this point on the ARC firmware is dead.	 */
	local_flush_tlb_all();

	/* Did I tell you that ARC SUCKS?  */

	if (ntlb) {
		if (ntlb > 1 && ntlb <= current_cpu_data.tlbsize) {
			int wired = current_cpu_data.tlbsize - ntlb;
			write_c0_wired(wired);
			write_c0_index(wired-1);
			printk("Restricting TLB to %d entries\n", ntlb);
		} else
			printk("Ignoring invalid argument ntlb=%d\n", ntlb);
	}

	build_tlb_refill_handler();
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
79add627	6	* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
1da177e4 LT	7	* Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org
	8	* Carsten Langgaard, carstenl@mips.com
	9	* Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
	10	*/
1da177e4 LT	11	#include <linux/init.h>
1da177e4 LT	12	#include <linux/sched.h>
631330f5	13	#include <linux/smp.h>
1da177e4	14	#include <linux/mm.h>
fd062c84	15	#include <linux/hugetlb.h>
f2e3656d	16	#include <linux/module.h>
1da177e4 LT	17
	18	#include <asm/cpu.h>
	19	#include <asm/bootinfo.h>
	20	#include <asm/mmu_context.h>
	21	#include <asm/pgtable.h>
3d18c983	22	#include <asm/tlbmisc.h>
1da177e4 LT	23
	24	extern void build_tlb_refill_handler(void);
	25
172546bf TS	26	/*
	27	* Make sure all entries differ. If they're not different
	28	* MIPS32 will take revenge ...
	29	*/
	30	#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
	31
41c594ab RB	32	/* Atomicity and interruptability */
	33	#ifdef CONFIG_MIPS_MT_SMTC
	34
	35	#include <asm/smtc.h>
	36	#include <asm/mipsmtregs.h>
	37
	38	#define ENTER_CRITICAL(flags) \
	39	{ \
	40	unsigned int mvpflags; \
	41	local_irq_save(flags);\
	42	mvpflags = dvpe()
	43	#define EXIT_CRITICAL(flags) \
	44	evpe(mvpflags); \
	45	local_irq_restore(flags); \
	46	}
	47	#else
	48
	49	#define ENTER_CRITICAL(flags) local_irq_save(flags)
	50	#define EXIT_CRITICAL(flags) local_irq_restore(flags)
	51
	52	#endif /* CONFIG_MIPS_MT_SMTC */
	53
2a21c730 FZ	54	#if defined(CONFIG_CPU_LOONGSON2)
	55	/*
	56	* LOONGSON2 has a 4 entry itlb which is a subset of dtlb,
	57	* unfortrunately, itlb is not totally transparent to software.
	58	*/
	59	#define FLUSH_ITLB write_c0_diag(4);
	60
	61	#define FLUSH_ITLB_VM(vma) { if ((vma)->vm_flags & VM_EXEC) write_c0_diag(4); }
	62
	63	#else
	64
	65	#define FLUSH_ITLB
	66	#define FLUSH_ITLB_VM(vma)
	67
	68	#endif
	69
1da177e4 LT	70	void local_flush_tlb_all(void)
	71	{
	72	unsigned long flags;
	73	unsigned long old_ctx;
	74	int entry;
	75
41c594ab	76	ENTER_CRITICAL(flags);
1da177e4 LT	77	/* Save old context and create impossible VPN2 value */
	78	old_ctx = read_c0_entryhi();
	79	write_c0_entrylo0(0);
	80	write_c0_entrylo1(0);
	81
	82	entry = read_c0_wired();
	83
	84	/* Blast 'em all away. */
	85	while (entry < current_cpu_data.tlbsize) {
172546bf TS	86	/* Make sure all entries differ. */
172546bf TS	87	write_c0_entryhi(UNIQUE_ENTRYHI(entry));
1da177e4 LT	88	write_c0_index(entry);
	89	mtc0_tlbw_hazard();
	90	tlb_write_indexed();
	91	entry++;
	92	}
	93	tlbw_use_hazard();
	94	write_c0_entryhi(old_ctx);
2a21c730	95	FLUSH_ITLB;
41c594ab	96	EXIT_CRITICAL(flags);
1da177e4	97	}
f2e3656d	98	EXPORT_SYMBOL(local_flush_tlb_all);
1da177e4	99
172546bf TS	100	/* All entries common to a mm share an asid. To effectively flush
172546bf TS	101	these entries, we just bump the asid. */
1da177e4 LT	102	void local_flush_tlb_mm(struct mm_struct *mm)
1da177e4 LT	103	{
172546bf TS	104	int cpu;
	105
	106	preempt_disable();
1da177e4	107
172546bf TS	108	cpu = smp_processor_id();
	109
	110	if (cpu_context(cpu, mm) != 0) {
	111	drop_mmu_context(mm, cpu);
	112	}
	113
	114	preempt_enable();
1da177e4 LT	115	}
	116
	117	void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
	118	unsigned long end)
	119	{
	120	struct mm_struct *mm = vma->vm_mm;
	121	int cpu = smp_processor_id();
	122
	123	if (cpu_context(cpu, mm) != 0) {
a5e696e5	124	unsigned long size, flags;
1da177e4	125
41c594ab	126	ENTER_CRITICAL(flags);
ac53c4fc DD	127	start = round_down(start, PAGE_SIZE << 1);
	128	end = round_up(end, PAGE_SIZE << 1);
	129	size = (end - start) >> (PAGE_SHIFT + 1);
1da177e4 LT	130	if (size <= current_cpu_data.tlbsize/2) {
	131	int oldpid = read_c0_entryhi();
	132	int newpid = cpu_asid(cpu, mm);
	133
1da177e4 LT	134	while (start < end) {
	135	int idx;
	136
	137	write_c0_entryhi(start \| newpid);
ac53c4fc	138	start += (PAGE_SIZE << 1);
1da177e4 LT	139	mtc0_tlbw_hazard();
1da177e4 LT	140	tlb_probe();
432bef2a	141	tlb_probe_hazard();
1da177e4 LT	142	idx = read_c0_index();
	143	write_c0_entrylo0(0);
	144	write_c0_entrylo1(0);
	145	if (idx < 0)
	146	continue;
	147	/* Make sure all entries differ. */
172546bf	148	write_c0_entryhi(UNIQUE_ENTRYHI(idx));
1da177e4 LT	149	mtc0_tlbw_hazard();
	150	tlb_write_indexed();
	151	}
	152	tlbw_use_hazard();
	153	write_c0_entryhi(oldpid);
	154	} else {
	155	drop_mmu_context(mm, cpu);
	156	}
2a21c730	157	FLUSH_ITLB;
41c594ab	158	EXIT_CRITICAL(flags);
1da177e4 LT	159	}
	160	}
	161
	162	void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
	163	{
a5e696e5	164	unsigned long size, flags;
1da177e4	165
41c594ab	166	ENTER_CRITICAL(flags);
1da177e4 LT	167	size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
	168	size = (size + 1) >> 1;
	169	if (size <= current_cpu_data.tlbsize / 2) {
	170	int pid = read_c0_entryhi();
	171
	172	start &= (PAGE_MASK << 1);
	173	end += ((PAGE_SIZE << 1) - 1);
	174	end &= (PAGE_MASK << 1);
	175
	176	while (start < end) {
	177	int idx;
	178
	179	write_c0_entryhi(start);
	180	start += (PAGE_SIZE << 1);
	181	mtc0_tlbw_hazard();
	182	tlb_probe();
432bef2a	183	tlb_probe_hazard();
1da177e4 LT	184	idx = read_c0_index();
	185	write_c0_entrylo0(0);
	186	write_c0_entrylo1(0);
	187	if (idx < 0)
	188	continue;
	189	/* Make sure all entries differ. */
172546bf	190	write_c0_entryhi(UNIQUE_ENTRYHI(idx));
1da177e4 LT	191	mtc0_tlbw_hazard();
	192	tlb_write_indexed();
	193	}
	194	tlbw_use_hazard();
	195	write_c0_entryhi(pid);
	196	} else {
	197	local_flush_tlb_all();
	198	}
2a21c730	199	FLUSH_ITLB;
41c594ab	200	EXIT_CRITICAL(flags);
1da177e4 LT	201	}
	202
	203	void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
	204	{
	205	int cpu = smp_processor_id();
	206
	207	if (cpu_context(cpu, vma->vm_mm) != 0) {
	208	unsigned long flags;
	209	int oldpid, newpid, idx;
	210
	211	newpid = cpu_asid(cpu, vma->vm_mm);
	212	page &= (PAGE_MASK << 1);
41c594ab	213	ENTER_CRITICAL(flags);
1da177e4 LT	214	oldpid = read_c0_entryhi();
	215	write_c0_entryhi(page \| newpid);
	216	mtc0_tlbw_hazard();
	217	tlb_probe();
432bef2a	218	tlb_probe_hazard();
1da177e4 LT	219	idx = read_c0_index();
	220	write_c0_entrylo0(0);
	221	write_c0_entrylo1(0);
	222	if (idx < 0)
	223	goto finish;
	224	/* Make sure all entries differ. */
172546bf	225	write_c0_entryhi(UNIQUE_ENTRYHI(idx));
1da177e4 LT	226	mtc0_tlbw_hazard();
	227	tlb_write_indexed();
	228	tlbw_use_hazard();
	229
	230	finish:
	231	write_c0_entryhi(oldpid);
2a21c730	232	FLUSH_ITLB_VM(vma);
41c594ab	233	EXIT_CRITICAL(flags);
1da177e4 LT	234	}
	235	}
	236
	237	/*
	238	* This one is only used for pages with the global bit set so we don't care
	239	* much about the ASID.
	240	*/
	241	void local_flush_tlb_one(unsigned long page)
	242	{
	243	unsigned long flags;
	244	int oldpid, idx;
	245
41c594ab	246	ENTER_CRITICAL(flags);
1da177e4	247	oldpid = read_c0_entryhi();
172546bf	248	page &= (PAGE_MASK << 1);
1da177e4 LT	249	write_c0_entryhi(page);
	250	mtc0_tlbw_hazard();
	251	tlb_probe();
432bef2a	252	tlb_probe_hazard();
1da177e4 LT	253	idx = read_c0_index();
	254	write_c0_entrylo0(0);
	255	write_c0_entrylo1(0);
	256	if (idx >= 0) {
	257	/* Make sure all entries differ. */
172546bf	258	write_c0_entryhi(UNIQUE_ENTRYHI(idx));
1da177e4 LT	259	mtc0_tlbw_hazard();
	260	tlb_write_indexed();
	261	tlbw_use_hazard();
	262	}
	263	write_c0_entryhi(oldpid);
2a21c730	264	FLUSH_ITLB;
41c594ab	265	EXIT_CRITICAL(flags);
1da177e4 LT	266	}
	267
	268	/*
	269	* We will need multiple versions of update_mmu_cache(), one that just
	270	* updates the TLB with the new pte(s), and another which also checks
	271	* for the R4k "end of page" hardware bug and does the needy.
	272	*/
	273	void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
	274	{
	275	unsigned long flags;
	276	pgd_t *pgdp;
c6e8b587	277	pud_t *pudp;
1da177e4 LT	278	pmd_t *pmdp;
	279	pte_t *ptep;
	280	int idx, pid;
	281
	282	/*
	283	* Handle debugger faulting in for debugee.
	284	*/
	285	if (current->active_mm != vma->vm_mm)
	286	return;
	287
41c594ab	288	ENTER_CRITICAL(flags);
172546bf	289
48c4ac97	290	pid = read_c0_entryhi() & ASID_MASK;
1da177e4 LT	291	address &= (PAGE_MASK << 1);
	292	write_c0_entryhi(address \| pid);
	293	pgdp = pgd_offset(vma->vm_mm, address);
	294	mtc0_tlbw_hazard();
	295	tlb_probe();
432bef2a	296	tlb_probe_hazard();
c6e8b587 RB	297	pudp = pud_offset(pgdp, address);
c6e8b587 RB	298	pmdp = pmd_offset(pudp, address);
1da177e4	299	idx = read_c0_index();
aa1762f4	300	#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
fd062c84 DD	301	/* this could be a huge page */
	302	if (pmd_huge(*pmdp)) {
	303	unsigned long lo;
	304	write_c0_pagemask(PM_HUGE_MASK);
	305	ptep = (pte_t *)pmdp;
6dd9344c	306	lo = pte_to_entrylo(pte_val(*ptep));
fd062c84 DD	307	write_c0_entrylo0(lo);
	308	write_c0_entrylo1(lo + (HPAGE_SIZE >> 7));
	309
	310	mtc0_tlbw_hazard();
	311	if (idx < 0)
	312	tlb_write_random();
	313	else
	314	tlb_write_indexed();
fb944c9b	315	tlbw_use_hazard();
fd062c84 DD	316	write_c0_pagemask(PM_DEFAULT_MASK);
	317	} else
	318	#endif
	319	{
	320	ptep = pte_offset_map(pmdp, address);
1da177e4	321
962f480e	322	#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
fd062c84 DD	323	write_c0_entrylo0(ptep->pte_high);
	324	ptep++;
	325	write_c0_entrylo1(ptep->pte_high);
1da177e4	326	#else
6dd9344c DD	327	write_c0_entrylo0(pte_to_entrylo(pte_val(*ptep++)));
6dd9344c DD	328	write_c0_entrylo1(pte_to_entrylo(pte_val(*ptep)));
1da177e4	329	#endif
fd062c84 DD	330	mtc0_tlbw_hazard();
	331	if (idx < 0)
	332	tlb_write_random();
	333	else
	334	tlb_write_indexed();
	335	}
1da177e4	336	tlbw_use_hazard();
2a21c730	337	FLUSH_ITLB_VM(vma);
41c594ab	338	EXIT_CRITICAL(flags);
1da177e4 LT	339	}
1da177e4 LT	340
694b8c35 ML	341	void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
694b8c35 ML	342	unsigned long entryhi, unsigned long pagemask)
1da177e4 LT	343	{
	344	unsigned long flags;
	345	unsigned long wired;
	346	unsigned long old_pagemask;
	347	unsigned long old_ctx;
	348
41c594ab	349	ENTER_CRITICAL(flags);
1da177e4 LT	350	/* Save old context and create impossible VPN2 value */
	351	old_ctx = read_c0_entryhi();
	352	old_pagemask = read_c0_pagemask();
	353	wired = read_c0_wired();
	354	write_c0_wired(wired + 1);
	355	write_c0_index(wired);
432bef2a	356	tlbw_use_hazard(); /* What is the hazard here? */
1da177e4 LT	357	write_c0_pagemask(pagemask);
	358	write_c0_entryhi(entryhi);
	359	write_c0_entrylo0(entrylo0);
	360	write_c0_entrylo1(entrylo1);
	361	mtc0_tlbw_hazard();
	362	tlb_write_indexed();
	363	tlbw_use_hazard();
	364
	365	write_c0_entryhi(old_ctx);
432bef2a	366	tlbw_use_hazard(); /* What is the hazard here? */
1da177e4 LT	367	write_c0_pagemask(old_pagemask);
1da177e4 LT	368	local_flush_tlb_all();
41c594ab	369	EXIT_CRITICAL(flags);
1da177e4 LT	370	}
1da177e4 LT	371
970d032f RB	372	#ifdef CONFIG_TRANSPARENT_HUGEPAGE
	373
	374	int __init has_transparent_hugepage(void)
	375	{
	376	unsigned int mask;
	377	unsigned long flags;
	378
	379	ENTER_CRITICAL(flags);
	380	write_c0_pagemask(PM_HUGE_MASK);
	381	back_to_back_c0_hazard();
	382	mask = read_c0_pagemask();
	383	write_c0_pagemask(PM_DEFAULT_MASK);
	384
	385	EXIT_CRITICAL(flags);
	386
	387	return mask == PM_HUGE_MASK;
	388	}
	389
	390	#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
	391
078a55fc	392	static int ntlb;
41c594ab RB	393	static int __init set_ntlb(char *str)
	394	{
	395	get_option(&str, &ntlb);
	396	return 1;
	397	}
	398
	399	__setup("ntlb=", set_ntlb);
	400
078a55fc	401	void tlb_init(void)
1da177e4	402	{
1da177e4 LT	403	/*
	404	* You should never change this register:
	405	* - On R4600 1.7 the tlbp never hits for pages smaller than
	406	* the value in the c0_pagemask register.
	407	* - The entire mm handling assumes the c0_pagemask register to
a7c2996e	408	* be set to fixed-size pages.
1da177e4	409	*/
1da177e4 LT	410	write_c0_pagemask(PM_DEFAULT_MASK);
1da177e4 LT	411	write_c0_wired(0);
cde15b59 RB	412	if (current_cpu_type() == CPU_R10000 \|\|
	413	current_cpu_type() == CPU_R12000 \|\|
	414	current_cpu_type() == CPU_R14000)
	415	write_c0_framemask(0);
6dd9344c	416
05857c64	417	if (cpu_has_rixi) {
6dd9344c DD	418	/*
	419	* Enable the no read, no exec bits, and enable large virtual
	420	* address.
	421	*/
	422	u32 pg = PG_RIE \| PG_XIE;
	423	#ifdef CONFIG_64BIT
	424	pg \|= PG_ELPA;
	425	#endif
	426	write_c0_pagegrain(pg);
	427	}
	428
70342287	429	/* From this point on the ARC firmware is dead. */
1da177e4 LT	430	local_flush_tlb_all();
1da177e4 LT	431
c6281edb TS	432	/* Did I tell you that ARC SUCKS? */
c6281edb TS	433
41c594ab RB	434	if (ntlb) {
	435	if (ntlb > 1 && ntlb <= current_cpu_data.tlbsize) {
	436	int wired = current_cpu_data.tlbsize - ntlb;
	437	write_c0_wired(wired);
	438	write_c0_index(wired-1);
49a89efb	439	printk("Restricting TLB to %d entries\n", ntlb);
41c594ab RB	440	} else
	441	printk("Ignoring invalid argument ntlb=%d\n", ntlb);
	442	}
	443
1da177e4 LT	444	build_tlb_refill_handler();
1da177e4 LT	445	}