[deliverable/linux.git] / arch / mips / mm / tlb-r4k.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
 * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org
 * Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2002 MIPS Technologies, Inc.  All rights reserved.
 */
#include <linux/cpu_pm.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/mm.h>
#include <linux/hugetlb.h>
#include <linux/module.h>

#include <asm/cpu.h>
#include <asm/cpu-type.h>
#include <asm/bootinfo.h>
#include <asm/mmu_context.h>
#include <asm/pgtable.h>
#include <asm/tlb.h>
#include <asm/tlbmisc.h>

extern void build_tlb_refill_handler(void);

/*
 * LOONGSON2/3 has a 4 entry itlb which is a subset of dtlb,
 * unfortunately, itlb is not totally transparent to software.
 */
static inline void flush_itlb(void)
{
	switch (current_cpu_type()) {
	case CPU_LOONGSON2:
	case CPU_LOONGSON3:
		write_c0_diag(4);
		break;
	default:
		break;
	}
}

static inline void flush_itlb_vm(struct vm_area_struct *vma)
{
	if (vma->vm_flags & VM_EXEC)
		flush_itlb();
}

void local_flush_tlb_all(void)
{
	unsigned long flags;
	unsigned long old_ctx;
	int entry, ftlbhighset;

	local_irq_save(flags);
	/* Save old context and create impossible VPN2 value */
	old_ctx = read_c0_entryhi();
	htw_stop();
	write_c0_entrylo0(0);
	write_c0_entrylo1(0);

	entry = read_c0_wired();

	/* Blast 'em all away. */
	if (cpu_has_tlbinv) {
		if (current_cpu_data.tlbsizevtlb) {
			write_c0_index(0);
			mtc0_tlbw_hazard();
			tlbinvf();  /* invalidate VTLB */
		}
		ftlbhighset = current_cpu_data.tlbsizevtlb +
			current_cpu_data.tlbsizeftlbsets;
		for (entry = current_cpu_data.tlbsizevtlb;
		     entry < ftlbhighset;
		     entry++) {
			write_c0_index(entry);
			mtc0_tlbw_hazard();
			tlbinvf();  /* invalidate one FTLB set */
		}
	} else {
		while (entry < current_cpu_data.tlbsize) {
			/* Make sure all entries differ. */
			write_c0_entryhi(UNIQUE_ENTRYHI(entry));
			write_c0_index(entry);
			mtc0_tlbw_hazard();
			tlb_write_indexed();
			entry++;
		}
	}
	tlbw_use_hazard();
	write_c0_entryhi(old_ctx);
	htw_start();
	flush_itlb();
	local_irq_restore(flags);
}
EXPORT_SYMBOL(local_flush_tlb_all);

/* All entries common to a mm share an asid.  To effectively flush
   these entries, we just bump the asid. */
void local_flush_tlb_mm(struct mm_struct *mm)
{
	int cpu;

	preempt_disable();

	cpu = smp_processor_id();

	if (cpu_context(cpu, mm) != 0) {
		drop_mmu_context(mm, cpu);
	}

	preempt_enable();
}

void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
	unsigned long end)
{
	struct mm_struct *mm = vma->vm_mm;
	int cpu = smp_processor_id();

	if (cpu_context(cpu, mm) != 0) {
		unsigned long size, flags;

		local_irq_save(flags);
		start = round_down(start, PAGE_SIZE << 1);
		end = round_up(end, PAGE_SIZE << 1);
		size = (end - start) >> (PAGE_SHIFT + 1);
		if (size <= (current_cpu_data.tlbsizeftlbsets ?
			     current_cpu_data.tlbsize / 8 :
			     current_cpu_data.tlbsize / 2)) {
			int oldpid = read_c0_entryhi();
			int newpid = cpu_asid(cpu, mm);

			htw_stop();
			while (start < end) {
				int idx;

				write_c0_entryhi(start | newpid);
				start += (PAGE_SIZE << 1);
				mtc0_tlbw_hazard();
				tlb_probe();
				tlb_probe_hazard();
				idx = read_c0_index();
				write_c0_entrylo0(0);
				write_c0_entrylo1(0);
				if (idx < 0)
					continue;
				/* Make sure all entries differ. */
				write_c0_entryhi(UNIQUE_ENTRYHI(idx));
				mtc0_tlbw_hazard();
				tlb_write_indexed();
			}
			tlbw_use_hazard();
			write_c0_entryhi(oldpid);
			htw_start();
		} else {
			drop_mmu_context(mm, cpu);
		}
		flush_itlb();
		local_irq_restore(flags);
	}
}

void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
{
	unsigned long size, flags;

	local_irq_save(flags);
	size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
	size = (size + 1) >> 1;
	if (size <= (current_cpu_data.tlbsizeftlbsets ?
		     current_cpu_data.tlbsize / 8 :
		     current_cpu_data.tlbsize / 2)) {
		int pid = read_c0_entryhi();

		start &= (PAGE_MASK << 1);
		end += ((PAGE_SIZE << 1) - 1);
		end &= (PAGE_MASK << 1);
		htw_stop();

		while (start < end) {
			int idx;

			write_c0_entryhi(start);
			start += (PAGE_SIZE << 1);
			mtc0_tlbw_hazard();
			tlb_probe();
			tlb_probe_hazard();
			idx = read_c0_index();
			write_c0_entrylo0(0);
			write_c0_entrylo1(0);
			if (idx < 0)
				continue;
			/* Make sure all entries differ. */
			write_c0_entryhi(UNIQUE_ENTRYHI(idx));
			mtc0_tlbw_hazard();
			tlb_write_indexed();
		}
		tlbw_use_hazard();
		write_c0_entryhi(pid);
		htw_start();
	} else {
		local_flush_tlb_all();
	}
	flush_itlb();
	local_irq_restore(flags);
}

void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
{
	int cpu = smp_processor_id();

	if (cpu_context(cpu, vma->vm_mm) != 0) {
		unsigned long flags;
		int oldpid, newpid, idx;

		newpid = cpu_asid(cpu, vma->vm_mm);
		page &= (PAGE_MASK << 1);
		local_irq_save(flags);
		oldpid = read_c0_entryhi();
		htw_stop();
		write_c0_entryhi(page | newpid);
		mtc0_tlbw_hazard();
		tlb_probe();
		tlb_probe_hazard();
		idx = read_c0_index();
		write_c0_entrylo0(0);
		write_c0_entrylo1(0);
		if (idx < 0)
			goto finish;
		/* Make sure all entries differ. */
		write_c0_entryhi(UNIQUE_ENTRYHI(idx));
		mtc0_tlbw_hazard();
		tlb_write_indexed();
		tlbw_use_hazard();

	finish:
		write_c0_entryhi(oldpid);
		htw_start();
		flush_itlb_vm(vma);
		local_irq_restore(flags);
	}
}

/*
 * This one is only used for pages with the global bit set so we don't care
 * much about the ASID.
 */
void local_flush_tlb_one(unsigned long page)
{
	unsigned long flags;
	int oldpid, idx;

	local_irq_save(flags);
	oldpid = read_c0_entryhi();
	htw_stop();
	page &= (PAGE_MASK << 1);
	write_c0_entryhi(page);
	mtc0_tlbw_hazard();
	tlb_probe();
	tlb_probe_hazard();
	idx = read_c0_index();
	write_c0_entrylo0(0);
	write_c0_entrylo1(0);
	if (idx >= 0) {
		/* Make sure all entries differ. */
		write_c0_entryhi(UNIQUE_ENTRYHI(idx));
		mtc0_tlbw_hazard();
		tlb_write_indexed();
		tlbw_use_hazard();
	}
	write_c0_entryhi(oldpid);
	htw_start();
	flush_itlb();
	local_irq_restore(flags);
}

/*
 * We will need multiple versions of update_mmu_cache(), one that just
 * updates the TLB with the new pte(s), and another which also checks
 * for the R4k "end of page" hardware bug and does the needy.
 */
void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
{
	unsigned long flags;
	pgd_t *pgdp;
	pud_t *pudp;
	pmd_t *pmdp;
	pte_t *ptep;
	int idx, pid;

	/*
	 * Handle debugger faulting in for debugee.
	 */
	if (current->active_mm != vma->vm_mm)
		return;

	local_irq_save(flags);

	htw_stop();
	pid = read_c0_entryhi() & ASID_MASK;
	address &= (PAGE_MASK << 1);
	write_c0_entryhi(address | pid);
	pgdp = pgd_offset(vma->vm_mm, address);
	mtc0_tlbw_hazard();
	tlb_probe();
	tlb_probe_hazard();
	pudp = pud_offset(pgdp, address);
	pmdp = pmd_offset(pudp, address);
	idx = read_c0_index();
#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
	/* this could be a huge page  */
	if (pmd_huge(*pmdp)) {
		unsigned long lo;
		write_c0_pagemask(PM_HUGE_MASK);
		ptep = (pte_t *)pmdp;
		lo = pte_to_entrylo(pte_val(*ptep));
		write_c0_entrylo0(lo);
		write_c0_entrylo1(lo + (HPAGE_SIZE >> 7));

		mtc0_tlbw_hazard();
		if (idx < 0)
			tlb_write_random();
		else
			tlb_write_indexed();
		tlbw_use_hazard();
		write_c0_pagemask(PM_DEFAULT_MASK);
	} else
#endif
	{
		ptep = pte_offset_map(pmdp, address);

#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
#ifdef CONFIG_XPA
		write_c0_entrylo0(pte_to_entrylo(ptep->pte_high));
		writex_c0_entrylo0(ptep->pte_low & _PFNX_MASK);
		ptep++;
		write_c0_entrylo1(pte_to_entrylo(ptep->pte_high));
		writex_c0_entrylo1(ptep->pte_low & _PFNX_MASK);
#else
		write_c0_entrylo0(ptep->pte_high);
		ptep++;
		write_c0_entrylo1(ptep->pte_high);
#endif
#else
		write_c0_entrylo0(pte_to_entrylo(pte_val(*ptep++)));
		write_c0_entrylo1(pte_to_entrylo(pte_val(*ptep)));
#endif
		mtc0_tlbw_hazard();
		if (idx < 0)
			tlb_write_random();
		else
			tlb_write_indexed();
	}
	tlbw_use_hazard();
	htw_start();
	flush_itlb_vm(vma);
	local_irq_restore(flags);
}

void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
		     unsigned long entryhi, unsigned long pagemask)
{
#ifdef CONFIG_XPA
	panic("Broken for XPA kernels");
#else
	unsigned long flags;
	unsigned long wired;
	unsigned long old_pagemask;
	unsigned long old_ctx;

	local_irq_save(flags);
	/* Save old context and create impossible VPN2 value */
	old_ctx = read_c0_entryhi();
	htw_stop();
	old_pagemask = read_c0_pagemask();
	wired = read_c0_wired();
	write_c0_wired(wired + 1);
	write_c0_index(wired);
	tlbw_use_hazard();	/* What is the hazard here? */
	write_c0_pagemask(pagemask);
	write_c0_entryhi(entryhi);
	write_c0_entrylo0(entrylo0);
	write_c0_entrylo1(entrylo1);
	mtc0_tlbw_hazard();
	tlb_write_indexed();
	tlbw_use_hazard();

	write_c0_entryhi(old_ctx);
	tlbw_use_hazard();	/* What is the hazard here? */
	htw_start();
	write_c0_pagemask(old_pagemask);
	local_flush_tlb_all();
	local_irq_restore(flags);
#endif
}

#ifdef CONFIG_TRANSPARENT_HUGEPAGE

int __init has_transparent_hugepage(void)
{
	unsigned int mask;
	unsigned long flags;

	local_irq_save(flags);
	write_c0_pagemask(PM_HUGE_MASK);
	back_to_back_c0_hazard();
	mask = read_c0_pagemask();
	write_c0_pagemask(PM_DEFAULT_MASK);

	local_irq_restore(flags);

	return mask == PM_HUGE_MASK;
}

#endif /* CONFIG_TRANSPARENT_HUGEPAGE  */

/*
 * Used for loading TLB entries before trap_init() has started, when we
 * don't actually want to add a wired entry which remains throughout the
 * lifetime of the system
 */

int temp_tlb_entry __cpuinitdata;

__init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
			       unsigned long entryhi, unsigned long pagemask)
{
	int ret = 0;
	unsigned long flags;
	unsigned long wired;
	unsigned long old_pagemask;
	unsigned long old_ctx;

	local_irq_save(flags);
	/* Save old context and create impossible VPN2 value */
	htw_stop();
	old_ctx = read_c0_entryhi();
	old_pagemask = read_c0_pagemask();
	wired = read_c0_wired();
	if (--temp_tlb_entry < wired) {
		printk(KERN_WARNING
		       "No TLB space left for add_temporary_entry\n");
		ret = -ENOSPC;
		goto out;
	}

	write_c0_index(temp_tlb_entry);
	write_c0_pagemask(pagemask);
	write_c0_entryhi(entryhi);
	write_c0_entrylo0(entrylo0);
	write_c0_entrylo1(entrylo1);
	mtc0_tlbw_hazard();
	tlb_write_indexed();
	tlbw_use_hazard();

	write_c0_entryhi(old_ctx);
	write_c0_pagemask(old_pagemask);
	htw_start();
out:
	local_irq_restore(flags);
	return ret;
}

static int ntlb;
static int __init set_ntlb(char *str)
{
	get_option(&str, &ntlb);
	return 1;
}

__setup("ntlb=", set_ntlb);

/*
 * Configure TLB (for init or after a CPU has been powered off).
 */
static void r4k_tlb_configure(void)
{
	/*
	 * You should never change this register:
	 *   - On R4600 1.7 the tlbp never hits for pages smaller than
	 *     the value in the c0_pagemask register.
	 *   - The entire mm handling assumes the c0_pagemask register to
	 *     be set to fixed-size pages.
	 */
	write_c0_pagemask(PM_DEFAULT_MASK);
	write_c0_wired(0);
	if (current_cpu_type() == CPU_R10000 ||
	    current_cpu_type() == CPU_R12000 ||
	    current_cpu_type() == CPU_R14000)
		write_c0_framemask(0);

	if (cpu_has_rixi) {
		/*
		 * Enable the no read, no exec bits, and enable large virtual
		 * address.
		 */
#ifdef CONFIG_64BIT
		set_c0_pagegrain(PG_RIE | PG_XIE | PG_ELPA);
#else
		set_c0_pagegrain(PG_RIE | PG_XIE);
#endif
	}

	temp_tlb_entry = current_cpu_data.tlbsize - 1;

	/* From this point on the ARC firmware is dead.	 */
	local_flush_tlb_all();

	/* Did I tell you that ARC SUCKS?  */
}

void tlb_init(void)
{
	r4k_tlb_configure();

	if (ntlb) {
		if (ntlb > 1 && ntlb <= current_cpu_data.tlbsize) {
			int wired = current_cpu_data.tlbsize - ntlb;
			write_c0_wired(wired);
			write_c0_index(wired-1);
			printk("Restricting TLB to %d entries\n", ntlb);
		} else
			printk("Ignoring invalid argument ntlb=%d\n", ntlb);
	}

	build_tlb_refill_handler();
}

static int r4k_tlb_pm_notifier(struct notifier_block *self, unsigned long cmd,
			       void *v)
{
	switch (cmd) {
	case CPU_PM_ENTER_FAILED:
	case CPU_PM_EXIT:
		r4k_tlb_configure();
		break;
	}

	return NOTIFY_OK;
}

static struct notifier_block r4k_tlb_pm_notifier_block = {
	.notifier_call = r4k_tlb_pm_notifier,
};

static int __init r4k_tlb_init_pm(void)
{
	return cpu_pm_register_notifier(&r4k_tlb_pm_notifier_block);
}
arch_initcall(r4k_tlb_init_pm);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
79add627	6	* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
1da177e4 LT	7	* Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org
	8	* Carsten Langgaard, carstenl@mips.com
	9	* Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
	10	*/
eaa38d63	11	#include <linux/cpu_pm.h>
1da177e4 LT	12	#include <linux/init.h>
1da177e4 LT	13	#include <linux/sched.h>
631330f5	14	#include <linux/smp.h>
1da177e4	15	#include <linux/mm.h>
fd062c84	16	#include <linux/hugetlb.h>
f2e3656d	17	#include <linux/module.h>
1da177e4 LT	18
1da177e4 LT	19	#include <asm/cpu.h>
69f24d17	20	#include <asm/cpu-type.h>
1da177e4 LT	21	#include <asm/bootinfo.h>
	22	#include <asm/mmu_context.h>
	23	#include <asm/pgtable.h>
c01905ee	24	#include <asm/tlb.h>
3d18c983	25	#include <asm/tlbmisc.h>
1da177e4 LT	26
	27	extern void build_tlb_refill_handler(void);
	28
2a21c730	29	/*
c579d310 HC	30	* LOONGSON2/3 has a 4 entry itlb which is a subset of dtlb,
c579d310 HC	31	* unfortunately, itlb is not totally transparent to software.
2a21c730	32	*/
14bd8c08 RB	33	static inline void flush_itlb(void)
	34	{
	35	switch (current_cpu_type()) {
	36	case CPU_LOONGSON2:
c579d310	37	case CPU_LOONGSON3:
14bd8c08 RB	38	write_c0_diag(4);
	39	break;
	40	default:
	41	break;
	42	}
	43	}
2a21c730	44
14bd8c08 RB	45	static inline void flush_itlb_vm(struct vm_area_struct *vma)
	46	{
	47	if (vma->vm_flags & VM_EXEC)
	48	flush_itlb();
	49	}
2a21c730	50
1da177e4 LT	51	void local_flush_tlb_all(void)
	52	{
	53	unsigned long flags;
	54	unsigned long old_ctx;
75b5b5e0	55	int entry, ftlbhighset;
1da177e4	56
b633648c	57	local_irq_save(flags);
1da177e4 LT	58	/* Save old context and create impossible VPN2 value */
1da177e4 LT	59	old_ctx = read_c0_entryhi();
f1014d1b	60	htw_stop();
1da177e4 LT	61	write_c0_entrylo0(0);
	62	write_c0_entrylo1(0);
	63
	64	entry = read_c0_wired();
	65
	66	/* Blast 'em all away. */
75b5b5e0 LY	67	if (cpu_has_tlbinv) {
	68	if (current_cpu_data.tlbsizevtlb) {
	69	write_c0_index(0);
	70	mtc0_tlbw_hazard();
	71	tlbinvf(); /* invalidate VTLB */
	72	}
	73	ftlbhighset = current_cpu_data.tlbsizevtlb +
	74	current_cpu_data.tlbsizeftlbsets;
	75	for (entry = current_cpu_data.tlbsizevtlb;
	76	entry < ftlbhighset;
	77	entry++) {
	78	write_c0_index(entry);
	79	mtc0_tlbw_hazard();
	80	tlbinvf(); /* invalidate one FTLB set */
	81	}
601cfa7b LY	82	} else {
	83	while (entry < current_cpu_data.tlbsize) {
	84	/* Make sure all entries differ. */
	85	write_c0_entryhi(UNIQUE_ENTRYHI(entry));
	86	write_c0_index(entry);
	87	mtc0_tlbw_hazard();
	88	tlb_write_indexed();
	89	entry++;
	90	}
1da177e4 LT	91	}
	92	tlbw_use_hazard();
	93	write_c0_entryhi(old_ctx);
f1014d1b	94	htw_start();
14bd8c08	95	flush_itlb();
b633648c	96	local_irq_restore(flags);
1da177e4	97	}
f2e3656d	98	EXPORT_SYMBOL(local_flush_tlb_all);
1da177e4	99
172546bf TS	100	/* All entries common to a mm share an asid. To effectively flush
172546bf TS	101	these entries, we just bump the asid. */
1da177e4 LT	102	void local_flush_tlb_mm(struct mm_struct *mm)
1da177e4 LT	103	{
172546bf TS	104	int cpu;
	105
	106	preempt_disable();
1da177e4	107
172546bf TS	108	cpu = smp_processor_id();
	109
	110	if (cpu_context(cpu, mm) != 0) {
	111	drop_mmu_context(mm, cpu);
	112	}
	113
	114	preempt_enable();
1da177e4 LT	115	}
	116
	117	void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
	118	unsigned long end)
	119	{
	120	struct mm_struct *mm = vma->vm_mm;
	121	int cpu = smp_processor_id();
	122
	123	if (cpu_context(cpu, mm) != 0) {
a5e696e5	124	unsigned long size, flags;
1da177e4	125
b633648c	126	local_irq_save(flags);
ac53c4fc DD	127	start = round_down(start, PAGE_SIZE << 1);
	128	end = round_up(end, PAGE_SIZE << 1);
	129	size = (end - start) >> (PAGE_SHIFT + 1);
75b5b5e0 LY	130	if (size <= (current_cpu_data.tlbsizeftlbsets ?
	131	current_cpu_data.tlbsize / 8 :
	132	current_cpu_data.tlbsize / 2)) {
1da177e4 LT	133	int oldpid = read_c0_entryhi();
	134	int newpid = cpu_asid(cpu, mm);
	135
f1014d1b	136	htw_stop();
1da177e4 LT	137	while (start < end) {
	138	int idx;
	139
	140	write_c0_entryhi(start \| newpid);
ac53c4fc	141	start += (PAGE_SIZE << 1);
1da177e4 LT	142	mtc0_tlbw_hazard();
1da177e4 LT	143	tlb_probe();
432bef2a	144	tlb_probe_hazard();
1da177e4 LT	145	idx = read_c0_index();
	146	write_c0_entrylo0(0);
	147	write_c0_entrylo1(0);
	148	if (idx < 0)
	149	continue;
	150	/* Make sure all entries differ. */
172546bf	151	write_c0_entryhi(UNIQUE_ENTRYHI(idx));
1da177e4 LT	152	mtc0_tlbw_hazard();
	153	tlb_write_indexed();
	154	}
	155	tlbw_use_hazard();
	156	write_c0_entryhi(oldpid);
f1014d1b	157	htw_start();
1da177e4 LT	158	} else {
	159	drop_mmu_context(mm, cpu);
	160	}
14bd8c08	161	flush_itlb();
b633648c	162	local_irq_restore(flags);
1da177e4 LT	163	}
	164	}
	165
	166	void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
	167	{
a5e696e5	168	unsigned long size, flags;
1da177e4	169
b633648c	170	local_irq_save(flags);
1da177e4 LT	171	size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
1da177e4 LT	172	size = (size + 1) >> 1;
75b5b5e0 LY	173	if (size <= (current_cpu_data.tlbsizeftlbsets ?
	174	current_cpu_data.tlbsize / 8 :
	175	current_cpu_data.tlbsize / 2)) {
1da177e4 LT	176	int pid = read_c0_entryhi();
	177
	178	start &= (PAGE_MASK << 1);
	179	end += ((PAGE_SIZE << 1) - 1);
	180	end &= (PAGE_MASK << 1);
f1014d1b	181	htw_stop();
1da177e4 LT	182
	183	while (start < end) {
	184	int idx;
	185
	186	write_c0_entryhi(start);
	187	start += (PAGE_SIZE << 1);
	188	mtc0_tlbw_hazard();
	189	tlb_probe();
432bef2a	190	tlb_probe_hazard();
1da177e4 LT	191	idx = read_c0_index();
	192	write_c0_entrylo0(0);
	193	write_c0_entrylo1(0);
	194	if (idx < 0)
	195	continue;
	196	/* Make sure all entries differ. */
172546bf	197	write_c0_entryhi(UNIQUE_ENTRYHI(idx));
1da177e4 LT	198	mtc0_tlbw_hazard();
	199	tlb_write_indexed();
	200	}
	201	tlbw_use_hazard();
	202	write_c0_entryhi(pid);
f1014d1b	203	htw_start();
1da177e4 LT	204	} else {
	205	local_flush_tlb_all();
	206	}
14bd8c08	207	flush_itlb();
b633648c	208	local_irq_restore(flags);
1da177e4 LT	209	}
	210
	211	void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
	212	{
	213	int cpu = smp_processor_id();
	214
	215	if (cpu_context(cpu, vma->vm_mm) != 0) {
	216	unsigned long flags;
	217	int oldpid, newpid, idx;
	218
	219	newpid = cpu_asid(cpu, vma->vm_mm);
	220	page &= (PAGE_MASK << 1);
b633648c	221	local_irq_save(flags);
1da177e4	222	oldpid = read_c0_entryhi();
f1014d1b	223	htw_stop();
1da177e4 LT	224	write_c0_entryhi(page \| newpid);
	225	mtc0_tlbw_hazard();
	226	tlb_probe();
432bef2a	227	tlb_probe_hazard();
1da177e4 LT	228	idx = read_c0_index();
	229	write_c0_entrylo0(0);
	230	write_c0_entrylo1(0);
	231	if (idx < 0)
	232	goto finish;
	233	/* Make sure all entries differ. */
172546bf	234	write_c0_entryhi(UNIQUE_ENTRYHI(idx));
1da177e4 LT	235	mtc0_tlbw_hazard();
	236	tlb_write_indexed();
	237	tlbw_use_hazard();
	238
	239	finish:
	240	write_c0_entryhi(oldpid);
f1014d1b	241	htw_start();
14bd8c08	242	flush_itlb_vm(vma);
b633648c	243	local_irq_restore(flags);
1da177e4 LT	244	}
	245	}
	246
	247	/*
	248	* This one is only used for pages with the global bit set so we don't care
	249	* much about the ASID.
	250	*/
	251	void local_flush_tlb_one(unsigned long page)
	252	{
	253	unsigned long flags;
	254	int oldpid, idx;
	255
b633648c	256	local_irq_save(flags);
1da177e4	257	oldpid = read_c0_entryhi();
f1014d1b	258	htw_stop();
172546bf	259	page &= (PAGE_MASK << 1);
1da177e4 LT	260	write_c0_entryhi(page);
	261	mtc0_tlbw_hazard();
	262	tlb_probe();
432bef2a	263	tlb_probe_hazard();
1da177e4 LT	264	idx = read_c0_index();
	265	write_c0_entrylo0(0);
	266	write_c0_entrylo1(0);
	267	if (idx >= 0) {
	268	/* Make sure all entries differ. */
172546bf	269	write_c0_entryhi(UNIQUE_ENTRYHI(idx));
1da177e4 LT	270	mtc0_tlbw_hazard();
	271	tlb_write_indexed();
	272	tlbw_use_hazard();
	273	}
	274	write_c0_entryhi(oldpid);
f1014d1b	275	htw_start();
14bd8c08	276	flush_itlb();
b633648c	277	local_irq_restore(flags);
1da177e4 LT	278	}
	279
	280	/*
	281	* We will need multiple versions of update_mmu_cache(), one that just
	282	* updates the TLB with the new pte(s), and another which also checks
	283	* for the R4k "end of page" hardware bug and does the needy.
	284	*/
	285	void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
	286	{
	287	unsigned long flags;
	288	pgd_t *pgdp;
c6e8b587	289	pud_t *pudp;
1da177e4 LT	290	pmd_t *pmdp;
	291	pte_t *ptep;
	292	int idx, pid;
	293
	294	/*
	295	* Handle debugger faulting in for debugee.
	296	*/
	297	if (current->active_mm != vma->vm_mm)
	298	return;
	299
b633648c	300	local_irq_save(flags);
172546bf	301
6a8dff6a	302	htw_stop();
48c4ac97	303	pid = read_c0_entryhi() & ASID_MASK;
1da177e4 LT	304	address &= (PAGE_MASK << 1);
	305	write_c0_entryhi(address \| pid);
	306	pgdp = pgd_offset(vma->vm_mm, address);
	307	mtc0_tlbw_hazard();
	308	tlb_probe();
432bef2a	309	tlb_probe_hazard();
c6e8b587 RB	310	pudp = pud_offset(pgdp, address);
c6e8b587 RB	311	pmdp = pmd_offset(pudp, address);
1da177e4	312	idx = read_c0_index();
aa1762f4	313	#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
fd062c84 DD	314	/* this could be a huge page */
	315	if (pmd_huge(*pmdp)) {
	316	unsigned long lo;
	317	write_c0_pagemask(PM_HUGE_MASK);
	318	ptep = (pte_t *)pmdp;
6dd9344c	319	lo = pte_to_entrylo(pte_val(*ptep));
fd062c84 DD	320	write_c0_entrylo0(lo);
	321	write_c0_entrylo1(lo + (HPAGE_SIZE >> 7));
	322
	323	mtc0_tlbw_hazard();
	324	if (idx < 0)
	325	tlb_write_random();
	326	else
	327	tlb_write_indexed();
fb944c9b	328	tlbw_use_hazard();
fd062c84 DD	329	write_c0_pagemask(PM_DEFAULT_MASK);
	330	} else
	331	#endif
	332	{
	333	ptep = pte_offset_map(pmdp, address);
1da177e4	334
34adb28d	335	#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
c5b36783 SH	336	#ifdef CONFIG_XPA
	337	write_c0_entrylo0(pte_to_entrylo(ptep->pte_high));
	338	writex_c0_entrylo0(ptep->pte_low & _PFNX_MASK);
	339	ptep++;
	340	write_c0_entrylo1(pte_to_entrylo(ptep->pte_high));
	341	writex_c0_entrylo1(ptep->pte_low & _PFNX_MASK);
	342	#else
fd062c84 DD	343	write_c0_entrylo0(ptep->pte_high);
	344	ptep++;
	345	write_c0_entrylo1(ptep->pte_high);
c5b36783	346	#endif
1da177e4	347	#else
6dd9344c DD	348	write_c0_entrylo0(pte_to_entrylo(pte_val(*ptep++)));
6dd9344c DD	349	write_c0_entrylo1(pte_to_entrylo(pte_val(*ptep)));
1da177e4	350	#endif
fd062c84 DD	351	mtc0_tlbw_hazard();
	352	if (idx < 0)
	353	tlb_write_random();
	354	else
	355	tlb_write_indexed();
	356	}
1da177e4	357	tlbw_use_hazard();
6a8dff6a	358	htw_start();
14bd8c08	359	flush_itlb_vm(vma);
b633648c	360	local_irq_restore(flags);
1da177e4 LT	361	}
1da177e4 LT	362
694b8c35 ML	363	void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
694b8c35 ML	364	unsigned long entryhi, unsigned long pagemask)
1da177e4	365	{
c5b36783 SH	366	#ifdef CONFIG_XPA
	367	panic("Broken for XPA kernels");
	368	#else
1da177e4 LT	369	unsigned long flags;
	370	unsigned long wired;
	371	unsigned long old_pagemask;
	372	unsigned long old_ctx;
	373
b633648c	374	local_irq_save(flags);
1da177e4 LT	375	/* Save old context and create impossible VPN2 value */
1da177e4 LT	376	old_ctx = read_c0_entryhi();
f1014d1b	377	htw_stop();
1da177e4 LT	378	old_pagemask = read_c0_pagemask();
	379	wired = read_c0_wired();
	380	write_c0_wired(wired + 1);
	381	write_c0_index(wired);
432bef2a	382	tlbw_use_hazard(); /* What is the hazard here? */
1da177e4 LT	383	write_c0_pagemask(pagemask);
	384	write_c0_entryhi(entryhi);
	385	write_c0_entrylo0(entrylo0);
	386	write_c0_entrylo1(entrylo1);
	387	mtc0_tlbw_hazard();
	388	tlb_write_indexed();
	389	tlbw_use_hazard();
	390
	391	write_c0_entryhi(old_ctx);
432bef2a	392	tlbw_use_hazard(); /* What is the hazard here? */
f1014d1b	393	htw_start();
1da177e4 LT	394	write_c0_pagemask(old_pagemask);
1da177e4 LT	395	local_flush_tlb_all();
b633648c	396	local_irq_restore(flags);
c5b36783	397	#endif
1da177e4 LT	398	}
1da177e4 LT	399
970d032f RB	400	#ifdef CONFIG_TRANSPARENT_HUGEPAGE
	401
	402	int __init has_transparent_hugepage(void)
	403	{
	404	unsigned int mask;
	405	unsigned long flags;
	406
b633648c	407	local_irq_save(flags);
970d032f RB	408	write_c0_pagemask(PM_HUGE_MASK);
	409	back_to_back_c0_hazard();
	410	mask = read_c0_pagemask();
	411	write_c0_pagemask(PM_DEFAULT_MASK);
	412
b633648c	413	local_irq_restore(flags);
970d032f RB	414
	415	return mask == PM_HUGE_MASK;
	416	}
	417
	418	#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
	419
d377732c RM	420	/*
	421	* Used for loading TLB entries before trap_init() has started, when we
	422	* don't actually want to add a wired entry which remains throughout the
	423	* lifetime of the system
	424	*/
	425
6ee1d934	426	int temp_tlb_entry __cpuinitdata;
d377732c RM	427
	428	__init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
	429	unsigned long entryhi, unsigned long pagemask)
	430	{
	431	int ret = 0;
	432	unsigned long flags;
	433	unsigned long wired;
	434	unsigned long old_pagemask;
	435	unsigned long old_ctx;
	436
	437	local_irq_save(flags);
	438	/* Save old context and create impossible VPN2 value */
6a8dff6a	439	htw_stop();
d377732c RM	440	old_ctx = read_c0_entryhi();
	441	old_pagemask = read_c0_pagemask();
	442	wired = read_c0_wired();
	443	if (--temp_tlb_entry < wired) {
	444	printk(KERN_WARNING
	445	"No TLB space left for add_temporary_entry\n");
	446	ret = -ENOSPC;
	447	goto out;
	448	}
	449
	450	write_c0_index(temp_tlb_entry);
	451	write_c0_pagemask(pagemask);
	452	write_c0_entryhi(entryhi);
	453	write_c0_entrylo0(entrylo0);
	454	write_c0_entrylo1(entrylo1);
	455	mtc0_tlbw_hazard();
	456	tlb_write_indexed();
	457	tlbw_use_hazard();
	458
	459	write_c0_entryhi(old_ctx);
	460	write_c0_pagemask(old_pagemask);
6a8dff6a	461	htw_start();
d377732c RM	462	out:
	463	local_irq_restore(flags);
	464	return ret;
	465	}
	466
078a55fc	467	static int ntlb;
41c594ab RB	468	static int __init set_ntlb(char *str)
	469	{
	470	get_option(&str, &ntlb);
	471	return 1;
	472	}
	473
	474	__setup("ntlb=", set_ntlb);
	475
eaa38d63 JH	476	/*
	477	* Configure TLB (for init or after a CPU has been powered off).
	478	*/
	479	static void r4k_tlb_configure(void)
1da177e4	480	{
1da177e4 LT	481	/*
	482	* You should never change this register:
	483	* - On R4600 1.7 the tlbp never hits for pages smaller than
	484	* the value in the c0_pagemask register.
	485	* - The entire mm handling assumes the c0_pagemask register to
a7c2996e	486	* be set to fixed-size pages.
1da177e4	487	*/
1da177e4 LT	488	write_c0_pagemask(PM_DEFAULT_MASK);
1da177e4 LT	489	write_c0_wired(0);
cde15b59 RB	490	if (current_cpu_type() == CPU_R10000 \|\|
	491	current_cpu_type() == CPU_R12000 \|\|
	492	current_cpu_type() == CPU_R14000)
	493	write_c0_framemask(0);
6dd9344c	494
05857c64	495	if (cpu_has_rixi) {
6dd9344c DD	496	/*
	497	* Enable the no read, no exec bits, and enable large virtual
	498	* address.
	499	*/
6dd9344c	500	#ifdef CONFIG_64BIT
a5770df0 SH	501	set_c0_pagegrain(PG_RIE \| PG_XIE \| PG_ELPA);
	502	#else
	503	set_c0_pagegrain(PG_RIE \| PG_XIE);
6dd9344c	504	#endif
6dd9344c DD	505	}
6dd9344c DD	506
d377732c RM	507	temp_tlb_entry = current_cpu_data.tlbsize - 1;
d377732c RM	508
70342287	509	/* From this point on the ARC firmware is dead. */
1da177e4 LT	510	local_flush_tlb_all();
1da177e4 LT	511
c6281edb	512	/* Did I tell you that ARC SUCKS? */
eaa38d63 JH	513	}
	514
	515	void tlb_init(void)
	516	{
	517	r4k_tlb_configure();
c6281edb	518
41c594ab RB	519	if (ntlb) {
	520	if (ntlb > 1 && ntlb <= current_cpu_data.tlbsize) {
	521	int wired = current_cpu_data.tlbsize - ntlb;
	522	write_c0_wired(wired);
	523	write_c0_index(wired-1);
49a89efb	524	printk("Restricting TLB to %d entries\n", ntlb);
41c594ab RB	525	} else
	526	printk("Ignoring invalid argument ntlb=%d\n", ntlb);
	527	}
	528
1da177e4 LT	529	build_tlb_refill_handler();
1da177e4 LT	530	}
eaa38d63 JH	531
	532	static int r4k_tlb_pm_notifier(struct notifier_block *self, unsigned long cmd,
	533	void *v)
	534	{
	535	switch (cmd) {
	536	case CPU_PM_ENTER_FAILED:
	537	case CPU_PM_EXIT:
	538	r4k_tlb_configure();
	539	break;
	540	}
	541
	542	return NOTIFY_OK;
	543	}
	544
	545	static struct notifier_block r4k_tlb_pm_notifier_block = {
	546	.notifier_call = r4k_tlb_pm_notifier,
	547	};
	548
	549	static int __init r4k_tlb_init_pm(void)
	550	{
	551	return cpu_pm_register_notifier(&r4k_tlb_pm_notifier_block);
	552	}
	553	arch_initcall(r4k_tlb_init_pm);