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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Synthesize TLB refill handlers at runtime. | |
7 | * | |
e30ec452 | 8 | * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer |
95affdda | 9 | * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki |
41c594ab | 10 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) |
fd062c84 | 11 | * Copyright (C) 2008, 2009 Cavium Networks, Inc. |
41c594ab RB |
12 | * |
13 | * ... and the days got worse and worse and now you see | |
14 | * I've gone completly out of my mind. | |
15 | * | |
16 | * They're coming to take me a away haha | |
17 | * they're coming to take me a away hoho hihi haha | |
18 | * to the funny farm where code is beautiful all the time ... | |
19 | * | |
20 | * (Condolences to Napoleon XIV) | |
1da177e4 LT |
21 | */ |
22 | ||
95affdda | 23 | #include <linux/bug.h> |
1da177e4 LT |
24 | #include <linux/kernel.h> |
25 | #include <linux/types.h> | |
631330f5 | 26 | #include <linux/smp.h> |
1da177e4 LT |
27 | #include <linux/string.h> |
28 | #include <linux/init.h> | |
29 | ||
1da177e4 | 30 | #include <asm/mmu_context.h> |
1da177e4 LT |
31 | #include <asm/war.h> |
32 | ||
e30ec452 TS |
33 | #include "uasm.h" |
34 | ||
aeffdbba | 35 | static inline int r45k_bvahwbug(void) |
1da177e4 LT |
36 | { |
37 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
38 | return 0; | |
39 | } | |
40 | ||
aeffdbba | 41 | static inline int r4k_250MHZhwbug(void) |
1da177e4 LT |
42 | { |
43 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
44 | return 0; | |
45 | } | |
46 | ||
aeffdbba | 47 | static inline int __maybe_unused bcm1250_m3_war(void) |
1da177e4 LT |
48 | { |
49 | return BCM1250_M3_WAR; | |
50 | } | |
51 | ||
aeffdbba | 52 | static inline int __maybe_unused r10000_llsc_war(void) |
1da177e4 LT |
53 | { |
54 | return R10000_LLSC_WAR; | |
55 | } | |
56 | ||
8df5beac MR |
57 | /* |
58 | * Found by experiment: At least some revisions of the 4kc throw under | |
59 | * some circumstances a machine check exception, triggered by invalid | |
60 | * values in the index register. Delaying the tlbp instruction until | |
61 | * after the next branch, plus adding an additional nop in front of | |
62 | * tlbwi/tlbwr avoids the invalid index register values. Nobody knows | |
63 | * why; it's not an issue caused by the core RTL. | |
64 | * | |
65 | */ | |
234fcd14 | 66 | static int __cpuinit m4kc_tlbp_war(void) |
8df5beac MR |
67 | { |
68 | return (current_cpu_data.processor_id & 0xffff00) == | |
69 | (PRID_COMP_MIPS | PRID_IMP_4KC); | |
70 | } | |
71 | ||
e30ec452 | 72 | /* Handle labels (which must be positive integers). */ |
1da177e4 | 73 | enum label_id { |
e30ec452 | 74 | label_second_part = 1, |
1da177e4 | 75 | label_leave, |
656be92f AN |
76 | #ifdef MODULE_START |
77 | label_module_alloc, | |
78 | #endif | |
1da177e4 LT |
79 | label_vmalloc, |
80 | label_vmalloc_done, | |
81 | label_tlbw_hazard, | |
82 | label_split, | |
83 | label_nopage_tlbl, | |
84 | label_nopage_tlbs, | |
85 | label_nopage_tlbm, | |
86 | label_smp_pgtable_change, | |
87 | label_r3000_write_probe_fail, | |
fd062c84 DD |
88 | #ifdef CONFIG_HUGETLB_PAGE |
89 | label_tlb_huge_update, | |
90 | #endif | |
1da177e4 LT |
91 | }; |
92 | ||
e30ec452 TS |
93 | UASM_L_LA(_second_part) |
94 | UASM_L_LA(_leave) | |
656be92f | 95 | #ifdef MODULE_START |
e30ec452 | 96 | UASM_L_LA(_module_alloc) |
619b6e18 | 97 | #endif |
e30ec452 TS |
98 | UASM_L_LA(_vmalloc) |
99 | UASM_L_LA(_vmalloc_done) | |
100 | UASM_L_LA(_tlbw_hazard) | |
101 | UASM_L_LA(_split) | |
102 | UASM_L_LA(_nopage_tlbl) | |
103 | UASM_L_LA(_nopage_tlbs) | |
104 | UASM_L_LA(_nopage_tlbm) | |
105 | UASM_L_LA(_smp_pgtable_change) | |
106 | UASM_L_LA(_r3000_write_probe_fail) | |
fd062c84 DD |
107 | #ifdef CONFIG_HUGETLB_PAGE |
108 | UASM_L_LA(_tlb_huge_update) | |
109 | #endif | |
656be92f | 110 | |
92b1e6a6 FBH |
111 | /* |
112 | * For debug purposes. | |
113 | */ | |
114 | static inline void dump_handler(const u32 *handler, int count) | |
115 | { | |
116 | int i; | |
117 | ||
118 | pr_debug("\t.set push\n"); | |
119 | pr_debug("\t.set noreorder\n"); | |
120 | ||
121 | for (i = 0; i < count; i++) | |
122 | pr_debug("\t%p\t.word 0x%08x\n", &handler[i], handler[i]); | |
123 | ||
124 | pr_debug("\t.set pop\n"); | |
125 | } | |
126 | ||
1da177e4 LT |
127 | /* The only general purpose registers allowed in TLB handlers. */ |
128 | #define K0 26 | |
129 | #define K1 27 | |
130 | ||
131 | /* Some CP0 registers */ | |
41c594ab RB |
132 | #define C0_INDEX 0, 0 |
133 | #define C0_ENTRYLO0 2, 0 | |
134 | #define C0_TCBIND 2, 2 | |
135 | #define C0_ENTRYLO1 3, 0 | |
136 | #define C0_CONTEXT 4, 0 | |
fd062c84 | 137 | #define C0_PAGEMASK 5, 0 |
41c594ab RB |
138 | #define C0_BADVADDR 8, 0 |
139 | #define C0_ENTRYHI 10, 0 | |
140 | #define C0_EPC 14, 0 | |
141 | #define C0_XCONTEXT 20, 0 | |
1da177e4 | 142 | |
875d43e7 | 143 | #ifdef CONFIG_64BIT |
e30ec452 | 144 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT) |
1da177e4 | 145 | #else |
e30ec452 | 146 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT) |
1da177e4 LT |
147 | #endif |
148 | ||
149 | /* The worst case length of the handler is around 18 instructions for | |
150 | * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. | |
151 | * Maximum space available is 32 instructions for R3000 and 64 | |
152 | * instructions for R4000. | |
153 | * | |
154 | * We deliberately chose a buffer size of 128, so we won't scribble | |
155 | * over anything important on overflow before we panic. | |
156 | */ | |
234fcd14 | 157 | static u32 tlb_handler[128] __cpuinitdata; |
1da177e4 LT |
158 | |
159 | /* simply assume worst case size for labels and relocs */ | |
234fcd14 RB |
160 | static struct uasm_label labels[128] __cpuinitdata; |
161 | static struct uasm_reloc relocs[128] __cpuinitdata; | |
1da177e4 LT |
162 | |
163 | /* | |
164 | * The R3000 TLB handler is simple. | |
165 | */ | |
234fcd14 | 166 | static void __cpuinit build_r3000_tlb_refill_handler(void) |
1da177e4 LT |
167 | { |
168 | long pgdc = (long)pgd_current; | |
169 | u32 *p; | |
170 | ||
171 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
172 | p = tlb_handler; | |
173 | ||
e30ec452 TS |
174 | uasm_i_mfc0(&p, K0, C0_BADVADDR); |
175 | uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */ | |
176 | uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1); | |
177 | uasm_i_srl(&p, K0, K0, 22); /* load delay */ | |
178 | uasm_i_sll(&p, K0, K0, 2); | |
179 | uasm_i_addu(&p, K1, K1, K0); | |
180 | uasm_i_mfc0(&p, K0, C0_CONTEXT); | |
181 | uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */ | |
182 | uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */ | |
183 | uasm_i_addu(&p, K1, K1, K0); | |
184 | uasm_i_lw(&p, K0, 0, K1); | |
185 | uasm_i_nop(&p); /* load delay */ | |
186 | uasm_i_mtc0(&p, K0, C0_ENTRYLO0); | |
187 | uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ | |
188 | uasm_i_tlbwr(&p); /* cp0 delay */ | |
189 | uasm_i_jr(&p, K1); | |
190 | uasm_i_rfe(&p); /* branch delay */ | |
1da177e4 LT |
191 | |
192 | if (p > tlb_handler + 32) | |
193 | panic("TLB refill handler space exceeded"); | |
194 | ||
e30ec452 TS |
195 | pr_debug("Wrote TLB refill handler (%u instructions).\n", |
196 | (unsigned int)(p - tlb_handler)); | |
1da177e4 | 197 | |
91b05e67 | 198 | memcpy((void *)ebase, tlb_handler, 0x80); |
92b1e6a6 FBH |
199 | |
200 | dump_handler((u32 *)ebase, 32); | |
1da177e4 LT |
201 | } |
202 | ||
203 | /* | |
204 | * The R4000 TLB handler is much more complicated. We have two | |
205 | * consecutive handler areas with 32 instructions space each. | |
206 | * Since they aren't used at the same time, we can overflow in the | |
207 | * other one.To keep things simple, we first assume linear space, | |
208 | * then we relocate it to the final handler layout as needed. | |
209 | */ | |
234fcd14 | 210 | static u32 final_handler[64] __cpuinitdata; |
1da177e4 LT |
211 | |
212 | /* | |
213 | * Hazards | |
214 | * | |
215 | * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: | |
216 | * 2. A timing hazard exists for the TLBP instruction. | |
217 | * | |
218 | * stalling_instruction | |
219 | * TLBP | |
220 | * | |
221 | * The JTLB is being read for the TLBP throughout the stall generated by the | |
222 | * previous instruction. This is not really correct as the stalling instruction | |
223 | * can modify the address used to access the JTLB. The failure symptom is that | |
224 | * the TLBP instruction will use an address created for the stalling instruction | |
225 | * and not the address held in C0_ENHI and thus report the wrong results. | |
226 | * | |
227 | * The software work-around is to not allow the instruction preceding the TLBP | |
228 | * to stall - make it an NOP or some other instruction guaranteed not to stall. | |
229 | * | |
230 | * Errata 2 will not be fixed. This errata is also on the R5000. | |
231 | * | |
232 | * As if we MIPS hackers wouldn't know how to nop pipelines happy ... | |
233 | */ | |
234fcd14 | 234 | static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p) |
1da177e4 | 235 | { |
10cc3529 | 236 | switch (current_cpu_type()) { |
326e2e1a | 237 | /* Found by experiment: R4600 v2.0/R4700 needs this, too. */ |
f5b4d956 | 238 | case CPU_R4600: |
326e2e1a | 239 | case CPU_R4700: |
1da177e4 LT |
240 | case CPU_R5000: |
241 | case CPU_R5000A: | |
242 | case CPU_NEVADA: | |
e30ec452 TS |
243 | uasm_i_nop(p); |
244 | uasm_i_tlbp(p); | |
1da177e4 LT |
245 | break; |
246 | ||
247 | default: | |
e30ec452 | 248 | uasm_i_tlbp(p); |
1da177e4 LT |
249 | break; |
250 | } | |
251 | } | |
252 | ||
253 | /* | |
254 | * Write random or indexed TLB entry, and care about the hazards from | |
255 | * the preceeding mtc0 and for the following eret. | |
256 | */ | |
257 | enum tlb_write_entry { tlb_random, tlb_indexed }; | |
258 | ||
234fcd14 | 259 | static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, |
e30ec452 | 260 | struct uasm_reloc **r, |
1da177e4 LT |
261 | enum tlb_write_entry wmode) |
262 | { | |
263 | void(*tlbw)(u32 **) = NULL; | |
264 | ||
265 | switch (wmode) { | |
e30ec452 TS |
266 | case tlb_random: tlbw = uasm_i_tlbwr; break; |
267 | case tlb_indexed: tlbw = uasm_i_tlbwi; break; | |
1da177e4 LT |
268 | } |
269 | ||
161548bf | 270 | if (cpu_has_mips_r2) { |
41f0e4d0 DD |
271 | if (cpu_has_mips_r2_exec_hazard) |
272 | uasm_i_ehb(p); | |
161548bf RB |
273 | tlbw(p); |
274 | return; | |
275 | } | |
276 | ||
10cc3529 | 277 | switch (current_cpu_type()) { |
1da177e4 LT |
278 | case CPU_R4000PC: |
279 | case CPU_R4000SC: | |
280 | case CPU_R4000MC: | |
281 | case CPU_R4400PC: | |
282 | case CPU_R4400SC: | |
283 | case CPU_R4400MC: | |
284 | /* | |
285 | * This branch uses up a mtc0 hazard nop slot and saves | |
286 | * two nops after the tlbw instruction. | |
287 | */ | |
e30ec452 | 288 | uasm_il_bgezl(p, r, 0, label_tlbw_hazard); |
1da177e4 | 289 | tlbw(p); |
e30ec452 TS |
290 | uasm_l_tlbw_hazard(l, *p); |
291 | uasm_i_nop(p); | |
1da177e4 LT |
292 | break; |
293 | ||
294 | case CPU_R4600: | |
295 | case CPU_R4700: | |
296 | case CPU_R5000: | |
297 | case CPU_R5000A: | |
e30ec452 | 298 | uasm_i_nop(p); |
2c93e12c | 299 | tlbw(p); |
e30ec452 | 300 | uasm_i_nop(p); |
2c93e12c MR |
301 | break; |
302 | ||
303 | case CPU_R4300: | |
1da177e4 LT |
304 | case CPU_5KC: |
305 | case CPU_TX49XX: | |
bdf21b18 | 306 | case CPU_PR4450: |
e30ec452 | 307 | uasm_i_nop(p); |
1da177e4 LT |
308 | tlbw(p); |
309 | break; | |
310 | ||
311 | case CPU_R10000: | |
312 | case CPU_R12000: | |
44d921b2 | 313 | case CPU_R14000: |
1da177e4 | 314 | case CPU_4KC: |
b1ec4c8e | 315 | case CPU_4KEC: |
1da177e4 | 316 | case CPU_SB1: |
93ce2f52 | 317 | case CPU_SB1A: |
1da177e4 LT |
318 | case CPU_4KSC: |
319 | case CPU_20KC: | |
320 | case CPU_25KF: | |
1c0c13eb AJ |
321 | case CPU_BCM3302: |
322 | case CPU_BCM4710: | |
2a21c730 | 323 | case CPU_LOONGSON2: |
a644b277 | 324 | case CPU_R5500: |
8df5beac | 325 | if (m4kc_tlbp_war()) |
e30ec452 | 326 | uasm_i_nop(p); |
2f794d09 | 327 | case CPU_ALCHEMY: |
1da177e4 LT |
328 | tlbw(p); |
329 | break; | |
330 | ||
331 | case CPU_NEVADA: | |
e30ec452 | 332 | uasm_i_nop(p); /* QED specifies 2 nops hazard */ |
1da177e4 LT |
333 | /* |
334 | * This branch uses up a mtc0 hazard nop slot and saves | |
335 | * a nop after the tlbw instruction. | |
336 | */ | |
e30ec452 | 337 | uasm_il_bgezl(p, r, 0, label_tlbw_hazard); |
1da177e4 | 338 | tlbw(p); |
e30ec452 | 339 | uasm_l_tlbw_hazard(l, *p); |
1da177e4 LT |
340 | break; |
341 | ||
342 | case CPU_RM7000: | |
e30ec452 TS |
343 | uasm_i_nop(p); |
344 | uasm_i_nop(p); | |
345 | uasm_i_nop(p); | |
346 | uasm_i_nop(p); | |
1da177e4 LT |
347 | tlbw(p); |
348 | break; | |
349 | ||
1da177e4 LT |
350 | case CPU_RM9000: |
351 | /* | |
352 | * When the JTLB is updated by tlbwi or tlbwr, a subsequent | |
353 | * use of the JTLB for instructions should not occur for 4 | |
354 | * cpu cycles and use for data translations should not occur | |
355 | * for 3 cpu cycles. | |
356 | */ | |
e30ec452 TS |
357 | uasm_i_ssnop(p); |
358 | uasm_i_ssnop(p); | |
359 | uasm_i_ssnop(p); | |
360 | uasm_i_ssnop(p); | |
1da177e4 | 361 | tlbw(p); |
e30ec452 TS |
362 | uasm_i_ssnop(p); |
363 | uasm_i_ssnop(p); | |
364 | uasm_i_ssnop(p); | |
365 | uasm_i_ssnop(p); | |
1da177e4 LT |
366 | break; |
367 | ||
368 | case CPU_VR4111: | |
369 | case CPU_VR4121: | |
370 | case CPU_VR4122: | |
371 | case CPU_VR4181: | |
372 | case CPU_VR4181A: | |
e30ec452 TS |
373 | uasm_i_nop(p); |
374 | uasm_i_nop(p); | |
1da177e4 | 375 | tlbw(p); |
e30ec452 TS |
376 | uasm_i_nop(p); |
377 | uasm_i_nop(p); | |
1da177e4 LT |
378 | break; |
379 | ||
380 | case CPU_VR4131: | |
381 | case CPU_VR4133: | |
7623debf | 382 | case CPU_R5432: |
e30ec452 TS |
383 | uasm_i_nop(p); |
384 | uasm_i_nop(p); | |
1da177e4 LT |
385 | tlbw(p); |
386 | break; | |
387 | ||
388 | default: | |
389 | panic("No TLB refill handler yet (CPU type: %d)", | |
390 | current_cpu_data.cputype); | |
391 | break; | |
392 | } | |
393 | } | |
394 | ||
fd062c84 DD |
395 | #ifdef CONFIG_HUGETLB_PAGE |
396 | static __cpuinit void build_huge_tlb_write_entry(u32 **p, | |
397 | struct uasm_label **l, | |
398 | struct uasm_reloc **r, | |
399 | unsigned int tmp, | |
400 | enum tlb_write_entry wmode) | |
401 | { | |
402 | /* Set huge page tlb entry size */ | |
403 | uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16); | |
404 | uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff); | |
405 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
406 | ||
407 | build_tlb_write_entry(p, l, r, wmode); | |
408 | ||
409 | /* Reset default page size */ | |
410 | if (PM_DEFAULT_MASK >> 16) { | |
411 | uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); | |
412 | uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); | |
413 | uasm_il_b(p, r, label_leave); | |
414 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
415 | } else if (PM_DEFAULT_MASK) { | |
416 | uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); | |
417 | uasm_il_b(p, r, label_leave); | |
418 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
419 | } else { | |
420 | uasm_il_b(p, r, label_leave); | |
421 | uasm_i_mtc0(p, 0, C0_PAGEMASK); | |
422 | } | |
423 | } | |
424 | ||
425 | /* | |
426 | * Check if Huge PTE is present, if so then jump to LABEL. | |
427 | */ | |
428 | static void __cpuinit | |
429 | build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp, | |
430 | unsigned int pmd, int lid) | |
431 | { | |
432 | UASM_i_LW(p, tmp, 0, pmd); | |
433 | uasm_i_andi(p, tmp, tmp, _PAGE_HUGE); | |
434 | uasm_il_bnez(p, r, tmp, lid); | |
435 | } | |
436 | ||
437 | static __cpuinit void build_huge_update_entries(u32 **p, | |
438 | unsigned int pte, | |
439 | unsigned int tmp) | |
440 | { | |
441 | int small_sequence; | |
442 | ||
443 | /* | |
444 | * A huge PTE describes an area the size of the | |
445 | * configured huge page size. This is twice the | |
446 | * of the large TLB entry size we intend to use. | |
447 | * A TLB entry half the size of the configured | |
448 | * huge page size is configured into entrylo0 | |
449 | * and entrylo1 to cover the contiguous huge PTE | |
450 | * address space. | |
451 | */ | |
452 | small_sequence = (HPAGE_SIZE >> 7) < 0x10000; | |
453 | ||
454 | /* We can clobber tmp. It isn't used after this.*/ | |
455 | if (!small_sequence) | |
456 | uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16)); | |
457 | ||
458 | UASM_i_SRL(p, pte, pte, 6); /* convert to entrylo */ | |
459 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* load it */ | |
460 | /* convert to entrylo1 */ | |
461 | if (small_sequence) | |
462 | UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7); | |
463 | else | |
464 | UASM_i_ADDU(p, pte, pte, tmp); | |
465 | ||
466 | uasm_i_mtc0(p, pte, C0_ENTRYLO1); /* load it */ | |
467 | } | |
468 | ||
469 | static __cpuinit void build_huge_handler_tail(u32 **p, | |
470 | struct uasm_reloc **r, | |
471 | struct uasm_label **l, | |
472 | unsigned int pte, | |
473 | unsigned int ptr) | |
474 | { | |
475 | #ifdef CONFIG_SMP | |
476 | UASM_i_SC(p, pte, 0, ptr); | |
477 | uasm_il_beqz(p, r, pte, label_tlb_huge_update); | |
478 | UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */ | |
479 | #else | |
480 | UASM_i_SW(p, pte, 0, ptr); | |
481 | #endif | |
482 | build_huge_update_entries(p, pte, ptr); | |
483 | build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed); | |
484 | } | |
485 | #endif /* CONFIG_HUGETLB_PAGE */ | |
486 | ||
875d43e7 | 487 | #ifdef CONFIG_64BIT |
1da177e4 LT |
488 | /* |
489 | * TMP and PTR are scratch. | |
490 | * TMP will be clobbered, PTR will hold the pmd entry. | |
491 | */ | |
234fcd14 | 492 | static void __cpuinit |
e30ec452 | 493 | build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
1da177e4 LT |
494 | unsigned int tmp, unsigned int ptr) |
495 | { | |
496 | long pgdc = (long)pgd_current; | |
497 | ||
498 | /* | |
499 | * The vmalloc handling is not in the hotpath. | |
500 | */ | |
e30ec452 | 501 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); |
656be92f | 502 | #ifdef MODULE_START |
e30ec452 | 503 | uasm_il_bltz(p, r, tmp, label_module_alloc); |
656be92f | 504 | #else |
e30ec452 | 505 | uasm_il_bltz(p, r, tmp, label_vmalloc); |
656be92f | 506 | #endif |
e30ec452 | 507 | /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ |
1da177e4 LT |
508 | |
509 | #ifdef CONFIG_SMP | |
41c594ab RB |
510 | # ifdef CONFIG_MIPS_MT_SMTC |
511 | /* | |
512 | * SMTC uses TCBind value as "CPU" index | |
513 | */ | |
e30ec452 TS |
514 | uasm_i_mfc0(p, ptr, C0_TCBIND); |
515 | uasm_i_dsrl(p, ptr, ptr, 19); | |
41c594ab | 516 | # else |
1da177e4 | 517 | /* |
1b3a6e97 | 518 | * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 |
1da177e4 LT |
519 | * stored in CONTEXT. |
520 | */ | |
e30ec452 TS |
521 | uasm_i_dmfc0(p, ptr, C0_CONTEXT); |
522 | uasm_i_dsrl(p, ptr, ptr, 23); | |
41c594ab | 523 | #endif |
e30ec452 TS |
524 | UASM_i_LA_mostly(p, tmp, pgdc); |
525 | uasm_i_daddu(p, ptr, ptr, tmp); | |
526 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); | |
527 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1da177e4 | 528 | #else |
e30ec452 TS |
529 | UASM_i_LA_mostly(p, ptr, pgdc); |
530 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1da177e4 LT |
531 | #endif |
532 | ||
e30ec452 | 533 | uasm_l_vmalloc_done(l, *p); |
242954b5 RB |
534 | |
535 | if (PGDIR_SHIFT - 3 < 32) /* get pgd offset in bytes */ | |
e30ec452 | 536 | uasm_i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3); |
242954b5 | 537 | else |
e30ec452 TS |
538 | uasm_i_dsrl32(p, tmp, tmp, PGDIR_SHIFT - 3 - 32); |
539 | ||
540 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); | |
541 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
542 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ | |
543 | uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ | |
544 | uasm_i_dsrl(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ | |
545 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); | |
546 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ | |
1da177e4 LT |
547 | } |
548 | ||
549 | /* | |
550 | * BVADDR is the faulting address, PTR is scratch. | |
551 | * PTR will hold the pgd for vmalloc. | |
552 | */ | |
234fcd14 | 553 | static void __cpuinit |
e30ec452 | 554 | build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
1da177e4 LT |
555 | unsigned int bvaddr, unsigned int ptr) |
556 | { | |
557 | long swpd = (long)swapper_pg_dir; | |
558 | ||
656be92f AN |
559 | #ifdef MODULE_START |
560 | long modd = (long)module_pg_dir; | |
561 | ||
e30ec452 | 562 | uasm_l_module_alloc(l, *p); |
656be92f AN |
563 | /* |
564 | * Assumption: | |
565 | * VMALLOC_START >= 0xc000000000000000UL | |
566 | * MODULE_START >= 0xe000000000000000UL | |
567 | */ | |
e30ec452 TS |
568 | UASM_i_SLL(p, ptr, bvaddr, 2); |
569 | uasm_il_bgez(p, r, ptr, label_vmalloc); | |
656be92f | 570 | |
e30ec452 TS |
571 | if (uasm_in_compat_space_p(MODULE_START) && |
572 | !uasm_rel_lo(MODULE_START)) { | |
573 | uasm_i_lui(p, ptr, uasm_rel_hi(MODULE_START)); /* delay slot */ | |
656be92f AN |
574 | } else { |
575 | /* unlikely configuration */ | |
e30ec452 TS |
576 | uasm_i_nop(p); /* delay slot */ |
577 | UASM_i_LA(p, ptr, MODULE_START); | |
656be92f | 578 | } |
e30ec452 | 579 | uasm_i_dsubu(p, bvaddr, bvaddr, ptr); |
656be92f | 580 | |
e30ec452 TS |
581 | if (uasm_in_compat_space_p(modd) && !uasm_rel_lo(modd)) { |
582 | uasm_il_b(p, r, label_vmalloc_done); | |
583 | uasm_i_lui(p, ptr, uasm_rel_hi(modd)); | |
656be92f | 584 | } else { |
e30ec452 TS |
585 | UASM_i_LA_mostly(p, ptr, modd); |
586 | uasm_il_b(p, r, label_vmalloc_done); | |
587 | if (uasm_in_compat_space_p(modd)) | |
588 | uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(modd)); | |
619b6e18 | 589 | else |
e30ec452 | 590 | uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(modd)); |
656be92f AN |
591 | } |
592 | ||
e30ec452 TS |
593 | uasm_l_vmalloc(l, *p); |
594 | if (uasm_in_compat_space_p(MODULE_START) && | |
595 | !uasm_rel_lo(MODULE_START) && | |
656be92f | 596 | MODULE_START << 32 == VMALLOC_START) |
e30ec452 | 597 | uasm_i_dsll32(p, ptr, ptr, 0); /* typical case */ |
656be92f | 598 | else |
e30ec452 | 599 | UASM_i_LA(p, ptr, VMALLOC_START); |
656be92f | 600 | #else |
e30ec452 TS |
601 | uasm_l_vmalloc(l, *p); |
602 | UASM_i_LA(p, ptr, VMALLOC_START); | |
656be92f | 603 | #endif |
e30ec452 | 604 | uasm_i_dsubu(p, bvaddr, bvaddr, ptr); |
1da177e4 | 605 | |
e30ec452 TS |
606 | if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) { |
607 | uasm_il_b(p, r, label_vmalloc_done); | |
608 | uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); | |
1da177e4 | 609 | } else { |
e30ec452 TS |
610 | UASM_i_LA_mostly(p, ptr, swpd); |
611 | uasm_il_b(p, r, label_vmalloc_done); | |
612 | if (uasm_in_compat_space_p(swpd)) | |
613 | uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd)); | |
619b6e18 | 614 | else |
e30ec452 | 615 | uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); |
1da177e4 LT |
616 | } |
617 | } | |
618 | ||
875d43e7 | 619 | #else /* !CONFIG_64BIT */ |
1da177e4 LT |
620 | |
621 | /* | |
622 | * TMP and PTR are scratch. | |
623 | * TMP will be clobbered, PTR will hold the pgd entry. | |
624 | */ | |
234fcd14 | 625 | static void __cpuinit __maybe_unused |
1da177e4 LT |
626 | build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) |
627 | { | |
628 | long pgdc = (long)pgd_current; | |
629 | ||
630 | /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ | |
631 | #ifdef CONFIG_SMP | |
41c594ab RB |
632 | #ifdef CONFIG_MIPS_MT_SMTC |
633 | /* | |
634 | * SMTC uses TCBind value as "CPU" index | |
635 | */ | |
e30ec452 TS |
636 | uasm_i_mfc0(p, ptr, C0_TCBIND); |
637 | UASM_i_LA_mostly(p, tmp, pgdc); | |
638 | uasm_i_srl(p, ptr, ptr, 19); | |
41c594ab RB |
639 | #else |
640 | /* | |
641 | * smp_processor_id() << 3 is stored in CONTEXT. | |
642 | */ | |
e30ec452 TS |
643 | uasm_i_mfc0(p, ptr, C0_CONTEXT); |
644 | UASM_i_LA_mostly(p, tmp, pgdc); | |
645 | uasm_i_srl(p, ptr, ptr, 23); | |
41c594ab | 646 | #endif |
e30ec452 | 647 | uasm_i_addu(p, ptr, tmp, ptr); |
1da177e4 | 648 | #else |
e30ec452 | 649 | UASM_i_LA_mostly(p, ptr, pgdc); |
1da177e4 | 650 | #endif |
e30ec452 TS |
651 | uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ |
652 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); | |
653 | uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ | |
654 | uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); | |
655 | uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
1da177e4 LT |
656 | } |
657 | ||
875d43e7 | 658 | #endif /* !CONFIG_64BIT */ |
1da177e4 | 659 | |
234fcd14 | 660 | static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx) |
1da177e4 | 661 | { |
242954b5 | 662 | unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; |
1da177e4 LT |
663 | unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); |
664 | ||
10cc3529 | 665 | switch (current_cpu_type()) { |
1da177e4 LT |
666 | case CPU_VR41XX: |
667 | case CPU_VR4111: | |
668 | case CPU_VR4121: | |
669 | case CPU_VR4122: | |
670 | case CPU_VR4131: | |
671 | case CPU_VR4181: | |
672 | case CPU_VR4181A: | |
673 | case CPU_VR4133: | |
674 | shift += 2; | |
675 | break; | |
676 | ||
677 | default: | |
678 | break; | |
679 | } | |
680 | ||
681 | if (shift) | |
e30ec452 TS |
682 | UASM_i_SRL(p, ctx, ctx, shift); |
683 | uasm_i_andi(p, ctx, ctx, mask); | |
1da177e4 LT |
684 | } |
685 | ||
234fcd14 | 686 | static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) |
1da177e4 LT |
687 | { |
688 | /* | |
689 | * Bug workaround for the Nevada. It seems as if under certain | |
690 | * circumstances the move from cp0_context might produce a | |
691 | * bogus result when the mfc0 instruction and its consumer are | |
692 | * in a different cacheline or a load instruction, probably any | |
693 | * memory reference, is between them. | |
694 | */ | |
10cc3529 | 695 | switch (current_cpu_type()) { |
1da177e4 | 696 | case CPU_NEVADA: |
e30ec452 | 697 | UASM_i_LW(p, ptr, 0, ptr); |
1da177e4 LT |
698 | GET_CONTEXT(p, tmp); /* get context reg */ |
699 | break; | |
700 | ||
701 | default: | |
702 | GET_CONTEXT(p, tmp); /* get context reg */ | |
e30ec452 | 703 | UASM_i_LW(p, ptr, 0, ptr); |
1da177e4 LT |
704 | break; |
705 | } | |
706 | ||
707 | build_adjust_context(p, tmp); | |
e30ec452 | 708 | UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ |
1da177e4 LT |
709 | } |
710 | ||
234fcd14 | 711 | static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, |
1da177e4 LT |
712 | unsigned int ptep) |
713 | { | |
714 | /* | |
715 | * 64bit address support (36bit on a 32bit CPU) in a 32bit | |
716 | * Kernel is a special case. Only a few CPUs use it. | |
717 | */ | |
718 | #ifdef CONFIG_64BIT_PHYS_ADDR | |
719 | if (cpu_has_64bits) { | |
e30ec452 TS |
720 | uasm_i_ld(p, tmp, 0, ptep); /* get even pte */ |
721 | uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ | |
722 | uasm_i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */ | |
723 | uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ | |
724 | uasm_i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */ | |
725 | uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ | |
1da177e4 LT |
726 | } else { |
727 | int pte_off_even = sizeof(pte_t) / 2; | |
728 | int pte_off_odd = pte_off_even + sizeof(pte_t); | |
729 | ||
730 | /* The pte entries are pre-shifted */ | |
e30ec452 TS |
731 | uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */ |
732 | uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ | |
733 | uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */ | |
734 | uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ | |
1da177e4 LT |
735 | } |
736 | #else | |
e30ec452 TS |
737 | UASM_i_LW(p, tmp, 0, ptep); /* get even pte */ |
738 | UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ | |
1da177e4 LT |
739 | if (r45k_bvahwbug()) |
740 | build_tlb_probe_entry(p); | |
e30ec452 | 741 | UASM_i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */ |
1da177e4 | 742 | if (r4k_250MHZhwbug()) |
e30ec452 TS |
743 | uasm_i_mtc0(p, 0, C0_ENTRYLO0); |
744 | uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ | |
745 | UASM_i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */ | |
1da177e4 | 746 | if (r45k_bvahwbug()) |
e30ec452 | 747 | uasm_i_mfc0(p, tmp, C0_INDEX); |
1da177e4 | 748 | if (r4k_250MHZhwbug()) |
e30ec452 TS |
749 | uasm_i_mtc0(p, 0, C0_ENTRYLO1); |
750 | uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ | |
1da177e4 LT |
751 | #endif |
752 | } | |
753 | ||
e6f72d3a DD |
754 | /* |
755 | * For a 64-bit kernel, we are using the 64-bit XTLB refill exception | |
756 | * because EXL == 0. If we wrap, we can also use the 32 instruction | |
757 | * slots before the XTLB refill exception handler which belong to the | |
758 | * unused TLB refill exception. | |
759 | */ | |
760 | #define MIPS64_REFILL_INSNS 32 | |
761 | ||
234fcd14 | 762 | static void __cpuinit build_r4000_tlb_refill_handler(void) |
1da177e4 LT |
763 | { |
764 | u32 *p = tlb_handler; | |
e30ec452 TS |
765 | struct uasm_label *l = labels; |
766 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
767 | u32 *f; |
768 | unsigned int final_len; | |
769 | ||
770 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
771 | memset(labels, 0, sizeof(labels)); | |
772 | memset(relocs, 0, sizeof(relocs)); | |
773 | memset(final_handler, 0, sizeof(final_handler)); | |
774 | ||
775 | /* | |
776 | * create the plain linear handler | |
777 | */ | |
778 | if (bcm1250_m3_war()) { | |
e30ec452 TS |
779 | UASM_i_MFC0(&p, K0, C0_BADVADDR); |
780 | UASM_i_MFC0(&p, K1, C0_ENTRYHI); | |
781 | uasm_i_xor(&p, K0, K0, K1); | |
782 | UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1); | |
783 | uasm_il_bnez(&p, &r, K0, label_leave); | |
784 | /* No need for uasm_i_nop */ | |
1da177e4 LT |
785 | } |
786 | ||
875d43e7 | 787 | #ifdef CONFIG_64BIT |
1da177e4 LT |
788 | build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ |
789 | #else | |
790 | build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ | |
791 | #endif | |
792 | ||
fd062c84 DD |
793 | #ifdef CONFIG_HUGETLB_PAGE |
794 | build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update); | |
795 | #endif | |
796 | ||
1da177e4 LT |
797 | build_get_ptep(&p, K0, K1); |
798 | build_update_entries(&p, K0, K1); | |
799 | build_tlb_write_entry(&p, &l, &r, tlb_random); | |
e30ec452 TS |
800 | uasm_l_leave(&l, p); |
801 | uasm_i_eret(&p); /* return from trap */ | |
1da177e4 | 802 | |
fd062c84 DD |
803 | #ifdef CONFIG_HUGETLB_PAGE |
804 | uasm_l_tlb_huge_update(&l, p); | |
805 | UASM_i_LW(&p, K0, 0, K1); | |
806 | build_huge_update_entries(&p, K0, K1); | |
807 | build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random); | |
808 | #endif | |
809 | ||
875d43e7 | 810 | #ifdef CONFIG_64BIT |
1da177e4 LT |
811 | build_get_pgd_vmalloc64(&p, &l, &r, K0, K1); |
812 | #endif | |
813 | ||
814 | /* | |
815 | * Overflow check: For the 64bit handler, we need at least one | |
816 | * free instruction slot for the wrap-around branch. In worst | |
817 | * case, if the intended insertion point is a delay slot, we | |
4b3f686d | 818 | * need three, with the second nop'ed and the third being |
1da177e4 LT |
819 | * unused. |
820 | */ | |
2a21c730 FZ |
821 | /* Loongson2 ebase is different than r4k, we have more space */ |
822 | #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) | |
1da177e4 LT |
823 | if ((p - tlb_handler) > 64) |
824 | panic("TLB refill handler space exceeded"); | |
825 | #else | |
e6f72d3a DD |
826 | if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1) |
827 | || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3) | |
828 | && uasm_insn_has_bdelay(relocs, | |
829 | tlb_handler + MIPS64_REFILL_INSNS - 3))) | |
1da177e4 LT |
830 | panic("TLB refill handler space exceeded"); |
831 | #endif | |
832 | ||
833 | /* | |
834 | * Now fold the handler in the TLB refill handler space. | |
835 | */ | |
2a21c730 | 836 | #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) |
1da177e4 LT |
837 | f = final_handler; |
838 | /* Simplest case, just copy the handler. */ | |
e30ec452 | 839 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); |
1da177e4 | 840 | final_len = p - tlb_handler; |
875d43e7 | 841 | #else /* CONFIG_64BIT */ |
e6f72d3a DD |
842 | f = final_handler + MIPS64_REFILL_INSNS; |
843 | if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) { | |
1da177e4 | 844 | /* Just copy the handler. */ |
e30ec452 | 845 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); |
1da177e4 LT |
846 | final_len = p - tlb_handler; |
847 | } else { | |
fd062c84 DD |
848 | #if defined(CONFIG_HUGETLB_PAGE) |
849 | const enum label_id ls = label_tlb_huge_update; | |
850 | #elif defined(MODULE_START) | |
95affdda DD |
851 | const enum label_id ls = label_module_alloc; |
852 | #else | |
853 | const enum label_id ls = label_vmalloc; | |
854 | #endif | |
855 | u32 *split; | |
856 | int ov = 0; | |
857 | int i; | |
858 | ||
859 | for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++) | |
860 | ; | |
861 | BUG_ON(i == ARRAY_SIZE(labels)); | |
862 | split = labels[i].addr; | |
1da177e4 LT |
863 | |
864 | /* | |
95affdda | 865 | * See if we have overflown one way or the other. |
1da177e4 | 866 | */ |
95affdda DD |
867 | if (split > tlb_handler + MIPS64_REFILL_INSNS || |
868 | split < p - MIPS64_REFILL_INSNS) | |
869 | ov = 1; | |
870 | ||
871 | if (ov) { | |
872 | /* | |
873 | * Split two instructions before the end. One | |
874 | * for the branch and one for the instruction | |
875 | * in the delay slot. | |
876 | */ | |
877 | split = tlb_handler + MIPS64_REFILL_INSNS - 2; | |
878 | ||
879 | /* | |
880 | * If the branch would fall in a delay slot, | |
881 | * we must back up an additional instruction | |
882 | * so that it is no longer in a delay slot. | |
883 | */ | |
884 | if (uasm_insn_has_bdelay(relocs, split - 1)) | |
885 | split--; | |
886 | } | |
1da177e4 | 887 | /* Copy first part of the handler. */ |
e30ec452 | 888 | uasm_copy_handler(relocs, labels, tlb_handler, split, f); |
1da177e4 LT |
889 | f += split - tlb_handler; |
890 | ||
95affdda DD |
891 | if (ov) { |
892 | /* Insert branch. */ | |
893 | uasm_l_split(&l, final_handler); | |
894 | uasm_il_b(&f, &r, label_split); | |
895 | if (uasm_insn_has_bdelay(relocs, split)) | |
896 | uasm_i_nop(&f); | |
897 | else { | |
898 | uasm_copy_handler(relocs, labels, | |
899 | split, split + 1, f); | |
900 | uasm_move_labels(labels, f, f + 1, -1); | |
901 | f++; | |
902 | split++; | |
903 | } | |
1da177e4 LT |
904 | } |
905 | ||
906 | /* Copy the rest of the handler. */ | |
e30ec452 | 907 | uasm_copy_handler(relocs, labels, split, p, final_handler); |
e6f72d3a DD |
908 | final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) + |
909 | (p - split); | |
1da177e4 | 910 | } |
875d43e7 | 911 | #endif /* CONFIG_64BIT */ |
1da177e4 | 912 | |
e30ec452 TS |
913 | uasm_resolve_relocs(relocs, labels); |
914 | pr_debug("Wrote TLB refill handler (%u instructions).\n", | |
915 | final_len); | |
1da177e4 | 916 | |
91b05e67 | 917 | memcpy((void *)ebase, final_handler, 0x100); |
92b1e6a6 FBH |
918 | |
919 | dump_handler((u32 *)ebase, 64); | |
1da177e4 LT |
920 | } |
921 | ||
922 | /* | |
923 | * TLB load/store/modify handlers. | |
924 | * | |
925 | * Only the fastpath gets synthesized at runtime, the slowpath for | |
926 | * do_page_fault remains normal asm. | |
927 | */ | |
928 | extern void tlb_do_page_fault_0(void); | |
929 | extern void tlb_do_page_fault_1(void); | |
930 | ||
1da177e4 LT |
931 | /* |
932 | * 128 instructions for the fastpath handler is generous and should | |
933 | * never be exceeded. | |
934 | */ | |
935 | #define FASTPATH_SIZE 128 | |
936 | ||
cbdbe07f FBH |
937 | u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned; |
938 | u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned; | |
939 | u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned; | |
1da177e4 | 940 | |
234fcd14 | 941 | static void __cpuinit |
bd1437e4 | 942 | iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) |
1da177e4 LT |
943 | { |
944 | #ifdef CONFIG_SMP | |
945 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
946 | if (cpu_has_64bits) | |
e30ec452 | 947 | uasm_i_lld(p, pte, 0, ptr); |
1da177e4 LT |
948 | else |
949 | # endif | |
e30ec452 | 950 | UASM_i_LL(p, pte, 0, ptr); |
1da177e4 LT |
951 | #else |
952 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
953 | if (cpu_has_64bits) | |
e30ec452 | 954 | uasm_i_ld(p, pte, 0, ptr); |
1da177e4 LT |
955 | else |
956 | # endif | |
e30ec452 | 957 | UASM_i_LW(p, pte, 0, ptr); |
1da177e4 LT |
958 | #endif |
959 | } | |
960 | ||
234fcd14 | 961 | static void __cpuinit |
e30ec452 | 962 | iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, |
63b2d2f4 | 963 | unsigned int mode) |
1da177e4 | 964 | { |
63b2d2f4 TS |
965 | #ifdef CONFIG_64BIT_PHYS_ADDR |
966 | unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); | |
967 | #endif | |
968 | ||
e30ec452 | 969 | uasm_i_ori(p, pte, pte, mode); |
1da177e4 LT |
970 | #ifdef CONFIG_SMP |
971 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
972 | if (cpu_has_64bits) | |
e30ec452 | 973 | uasm_i_scd(p, pte, 0, ptr); |
1da177e4 LT |
974 | else |
975 | # endif | |
e30ec452 | 976 | UASM_i_SC(p, pte, 0, ptr); |
1da177e4 LT |
977 | |
978 | if (r10000_llsc_war()) | |
e30ec452 | 979 | uasm_il_beqzl(p, r, pte, label_smp_pgtable_change); |
1da177e4 | 980 | else |
e30ec452 | 981 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); |
1da177e4 LT |
982 | |
983 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
984 | if (!cpu_has_64bits) { | |
e30ec452 TS |
985 | /* no uasm_i_nop needed */ |
986 | uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr); | |
987 | uasm_i_ori(p, pte, pte, hwmode); | |
988 | uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr); | |
989 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); | |
990 | /* no uasm_i_nop needed */ | |
991 | uasm_i_lw(p, pte, 0, ptr); | |
1da177e4 | 992 | } else |
e30ec452 | 993 | uasm_i_nop(p); |
1da177e4 | 994 | # else |
e30ec452 | 995 | uasm_i_nop(p); |
1da177e4 LT |
996 | # endif |
997 | #else | |
998 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
999 | if (cpu_has_64bits) | |
e30ec452 | 1000 | uasm_i_sd(p, pte, 0, ptr); |
1da177e4 LT |
1001 | else |
1002 | # endif | |
e30ec452 | 1003 | UASM_i_SW(p, pte, 0, ptr); |
1da177e4 LT |
1004 | |
1005 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1006 | if (!cpu_has_64bits) { | |
e30ec452 TS |
1007 | uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr); |
1008 | uasm_i_ori(p, pte, pte, hwmode); | |
1009 | uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr); | |
1010 | uasm_i_lw(p, pte, 0, ptr); | |
1da177e4 LT |
1011 | } |
1012 | # endif | |
1013 | #endif | |
1014 | } | |
1015 | ||
1016 | /* | |
1017 | * Check if PTE is present, if not then jump to LABEL. PTR points to | |
1018 | * the page table where this PTE is located, PTE will be re-loaded | |
1019 | * with it's original value. | |
1020 | */ | |
234fcd14 | 1021 | static void __cpuinit |
bd1437e4 | 1022 | build_pte_present(u32 **p, struct uasm_reloc **r, |
1da177e4 LT |
1023 | unsigned int pte, unsigned int ptr, enum label_id lid) |
1024 | { | |
e30ec452 TS |
1025 | uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); |
1026 | uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); | |
1027 | uasm_il_bnez(p, r, pte, lid); | |
bd1437e4 | 1028 | iPTE_LW(p, pte, ptr); |
1da177e4 LT |
1029 | } |
1030 | ||
1031 | /* Make PTE valid, store result in PTR. */ | |
234fcd14 | 1032 | static void __cpuinit |
e30ec452 | 1033 | build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte, |
1da177e4 LT |
1034 | unsigned int ptr) |
1035 | { | |
63b2d2f4 TS |
1036 | unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; |
1037 | ||
1038 | iPTE_SW(p, r, pte, ptr, mode); | |
1da177e4 LT |
1039 | } |
1040 | ||
1041 | /* | |
1042 | * Check if PTE can be written to, if not branch to LABEL. Regardless | |
1043 | * restore PTE with value from PTR when done. | |
1044 | */ | |
234fcd14 | 1045 | static void __cpuinit |
bd1437e4 | 1046 | build_pte_writable(u32 **p, struct uasm_reloc **r, |
1da177e4 LT |
1047 | unsigned int pte, unsigned int ptr, enum label_id lid) |
1048 | { | |
e30ec452 TS |
1049 | uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); |
1050 | uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); | |
1051 | uasm_il_bnez(p, r, pte, lid); | |
bd1437e4 | 1052 | iPTE_LW(p, pte, ptr); |
1da177e4 LT |
1053 | } |
1054 | ||
1055 | /* Make PTE writable, update software status bits as well, then store | |
1056 | * at PTR. | |
1057 | */ | |
234fcd14 | 1058 | static void __cpuinit |
e30ec452 | 1059 | build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte, |
1da177e4 LT |
1060 | unsigned int ptr) |
1061 | { | |
63b2d2f4 TS |
1062 | unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID |
1063 | | _PAGE_DIRTY); | |
1064 | ||
1065 | iPTE_SW(p, r, pte, ptr, mode); | |
1da177e4 LT |
1066 | } |
1067 | ||
1068 | /* | |
1069 | * Check if PTE can be modified, if not branch to LABEL. Regardless | |
1070 | * restore PTE with value from PTR when done. | |
1071 | */ | |
234fcd14 | 1072 | static void __cpuinit |
bd1437e4 | 1073 | build_pte_modifiable(u32 **p, struct uasm_reloc **r, |
1da177e4 LT |
1074 | unsigned int pte, unsigned int ptr, enum label_id lid) |
1075 | { | |
e30ec452 TS |
1076 | uasm_i_andi(p, pte, pte, _PAGE_WRITE); |
1077 | uasm_il_beqz(p, r, pte, lid); | |
bd1437e4 | 1078 | iPTE_LW(p, pte, ptr); |
1da177e4 LT |
1079 | } |
1080 | ||
1081 | /* | |
1082 | * R3000 style TLB load/store/modify handlers. | |
1083 | */ | |
1084 | ||
fded2e50 MR |
1085 | /* |
1086 | * This places the pte into ENTRYLO0 and writes it with tlbwi. | |
1087 | * Then it returns. | |
1088 | */ | |
234fcd14 | 1089 | static void __cpuinit |
fded2e50 | 1090 | build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) |
1da177e4 | 1091 | { |
e30ec452 TS |
1092 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ |
1093 | uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ | |
1094 | uasm_i_tlbwi(p); | |
1095 | uasm_i_jr(p, tmp); | |
1096 | uasm_i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1097 | } |
1098 | ||
1099 | /* | |
fded2e50 MR |
1100 | * This places the pte into ENTRYLO0 and writes it with tlbwi |
1101 | * or tlbwr as appropriate. This is because the index register | |
1102 | * may have the probe fail bit set as a result of a trap on a | |
1103 | * kseg2 access, i.e. without refill. Then it returns. | |
1da177e4 | 1104 | */ |
234fcd14 | 1105 | static void __cpuinit |
e30ec452 TS |
1106 | build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l, |
1107 | struct uasm_reloc **r, unsigned int pte, | |
1108 | unsigned int tmp) | |
1109 | { | |
1110 | uasm_i_mfc0(p, tmp, C0_INDEX); | |
1111 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ | |
1112 | uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ | |
1113 | uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */ | |
1114 | uasm_i_tlbwi(p); /* cp0 delay */ | |
1115 | uasm_i_jr(p, tmp); | |
1116 | uasm_i_rfe(p); /* branch delay */ | |
1117 | uasm_l_r3000_write_probe_fail(l, *p); | |
1118 | uasm_i_tlbwr(p); /* cp0 delay */ | |
1119 | uasm_i_jr(p, tmp); | |
1120 | uasm_i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1121 | } |
1122 | ||
234fcd14 | 1123 | static void __cpuinit |
1da177e4 LT |
1124 | build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, |
1125 | unsigned int ptr) | |
1126 | { | |
1127 | long pgdc = (long)pgd_current; | |
1128 | ||
e30ec452 TS |
1129 | uasm_i_mfc0(p, pte, C0_BADVADDR); |
1130 | uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */ | |
1131 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1132 | uasm_i_srl(p, pte, pte, 22); /* load delay */ | |
1133 | uasm_i_sll(p, pte, pte, 2); | |
1134 | uasm_i_addu(p, ptr, ptr, pte); | |
1135 | uasm_i_mfc0(p, pte, C0_CONTEXT); | |
1136 | uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */ | |
1137 | uasm_i_andi(p, pte, pte, 0xffc); /* load delay */ | |
1138 | uasm_i_addu(p, ptr, ptr, pte); | |
1139 | uasm_i_lw(p, pte, 0, ptr); | |
1140 | uasm_i_tlbp(p); /* load delay */ | |
1da177e4 LT |
1141 | } |
1142 | ||
234fcd14 | 1143 | static void __cpuinit build_r3000_tlb_load_handler(void) |
1da177e4 LT |
1144 | { |
1145 | u32 *p = handle_tlbl; | |
e30ec452 TS |
1146 | struct uasm_label *l = labels; |
1147 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1148 | |
1149 | memset(handle_tlbl, 0, sizeof(handle_tlbl)); | |
1150 | memset(labels, 0, sizeof(labels)); | |
1151 | memset(relocs, 0, sizeof(relocs)); | |
1152 | ||
1153 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
bd1437e4 | 1154 | build_pte_present(&p, &r, K0, K1, label_nopage_tlbl); |
e30ec452 | 1155 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1156 | build_make_valid(&p, &r, K0, K1); |
fded2e50 | 1157 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 | 1158 | |
e30ec452 TS |
1159 | uasm_l_nopage_tlbl(&l, p); |
1160 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); | |
1161 | uasm_i_nop(&p); | |
1da177e4 LT |
1162 | |
1163 | if ((p - handle_tlbl) > FASTPATH_SIZE) | |
1164 | panic("TLB load handler fastpath space exceeded"); | |
1165 | ||
e30ec452 TS |
1166 | uasm_resolve_relocs(relocs, labels); |
1167 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", | |
1168 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 1169 | |
92b1e6a6 | 1170 | dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl)); |
1da177e4 LT |
1171 | } |
1172 | ||
234fcd14 | 1173 | static void __cpuinit build_r3000_tlb_store_handler(void) |
1da177e4 LT |
1174 | { |
1175 | u32 *p = handle_tlbs; | |
e30ec452 TS |
1176 | struct uasm_label *l = labels; |
1177 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1178 | |
1179 | memset(handle_tlbs, 0, sizeof(handle_tlbs)); | |
1180 | memset(labels, 0, sizeof(labels)); | |
1181 | memset(relocs, 0, sizeof(relocs)); | |
1182 | ||
1183 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
bd1437e4 | 1184 | build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs); |
e30ec452 | 1185 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1186 | build_make_write(&p, &r, K0, K1); |
fded2e50 | 1187 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 | 1188 | |
e30ec452 TS |
1189 | uasm_l_nopage_tlbs(&l, p); |
1190 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1191 | uasm_i_nop(&p); | |
1da177e4 LT |
1192 | |
1193 | if ((p - handle_tlbs) > FASTPATH_SIZE) | |
1194 | panic("TLB store handler fastpath space exceeded"); | |
1195 | ||
e30ec452 TS |
1196 | uasm_resolve_relocs(relocs, labels); |
1197 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", | |
1198 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 1199 | |
92b1e6a6 | 1200 | dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs)); |
1da177e4 LT |
1201 | } |
1202 | ||
234fcd14 | 1203 | static void __cpuinit build_r3000_tlb_modify_handler(void) |
1da177e4 LT |
1204 | { |
1205 | u32 *p = handle_tlbm; | |
e30ec452 TS |
1206 | struct uasm_label *l = labels; |
1207 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1208 | |
1209 | memset(handle_tlbm, 0, sizeof(handle_tlbm)); | |
1210 | memset(labels, 0, sizeof(labels)); | |
1211 | memset(relocs, 0, sizeof(relocs)); | |
1212 | ||
1213 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
bd1437e4 | 1214 | build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm); |
e30ec452 | 1215 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1216 | build_make_write(&p, &r, K0, K1); |
fded2e50 | 1217 | build_r3000_pte_reload_tlbwi(&p, K0, K1); |
1da177e4 | 1218 | |
e30ec452 TS |
1219 | uasm_l_nopage_tlbm(&l, p); |
1220 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1221 | uasm_i_nop(&p); | |
1da177e4 LT |
1222 | |
1223 | if ((p - handle_tlbm) > FASTPATH_SIZE) | |
1224 | panic("TLB modify handler fastpath space exceeded"); | |
1225 | ||
e30ec452 TS |
1226 | uasm_resolve_relocs(relocs, labels); |
1227 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", | |
1228 | (unsigned int)(p - handle_tlbm)); | |
1da177e4 | 1229 | |
92b1e6a6 | 1230 | dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm)); |
1da177e4 LT |
1231 | } |
1232 | ||
1233 | /* | |
1234 | * R4000 style TLB load/store/modify handlers. | |
1235 | */ | |
234fcd14 | 1236 | static void __cpuinit |
e30ec452 TS |
1237 | build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l, |
1238 | struct uasm_reloc **r, unsigned int pte, | |
1da177e4 LT |
1239 | unsigned int ptr) |
1240 | { | |
875d43e7 | 1241 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1242 | build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */ |
1243 | #else | |
1244 | build_get_pgde32(p, pte, ptr); /* get pgd in ptr */ | |
1245 | #endif | |
1246 | ||
fd062c84 DD |
1247 | #ifdef CONFIG_HUGETLB_PAGE |
1248 | /* | |
1249 | * For huge tlb entries, pmd doesn't contain an address but | |
1250 | * instead contains the tlb pte. Check the PAGE_HUGE bit and | |
1251 | * see if we need to jump to huge tlb processing. | |
1252 | */ | |
1253 | build_is_huge_pte(p, r, pte, ptr, label_tlb_huge_update); | |
1254 | #endif | |
1255 | ||
e30ec452 TS |
1256 | UASM_i_MFC0(p, pte, C0_BADVADDR); |
1257 | UASM_i_LW(p, ptr, 0, ptr); | |
1258 | UASM_i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); | |
1259 | uasm_i_andi(p, pte, pte, (PTRS_PER_PTE - 1) << PTE_T_LOG2); | |
1260 | UASM_i_ADDU(p, ptr, ptr, pte); | |
1da177e4 LT |
1261 | |
1262 | #ifdef CONFIG_SMP | |
e30ec452 TS |
1263 | uasm_l_smp_pgtable_change(l, *p); |
1264 | #endif | |
bd1437e4 | 1265 | iPTE_LW(p, pte, ptr); /* get even pte */ |
8df5beac MR |
1266 | if (!m4kc_tlbp_war()) |
1267 | build_tlb_probe_entry(p); | |
1da177e4 LT |
1268 | } |
1269 | ||
234fcd14 | 1270 | static void __cpuinit |
e30ec452 TS |
1271 | build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, |
1272 | struct uasm_reloc **r, unsigned int tmp, | |
1da177e4 LT |
1273 | unsigned int ptr) |
1274 | { | |
e30ec452 TS |
1275 | uasm_i_ori(p, ptr, ptr, sizeof(pte_t)); |
1276 | uasm_i_xori(p, ptr, ptr, sizeof(pte_t)); | |
1da177e4 LT |
1277 | build_update_entries(p, tmp, ptr); |
1278 | build_tlb_write_entry(p, l, r, tlb_indexed); | |
e30ec452 TS |
1279 | uasm_l_leave(l, *p); |
1280 | uasm_i_eret(p); /* return from trap */ | |
1da177e4 | 1281 | |
875d43e7 | 1282 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1283 | build_get_pgd_vmalloc64(p, l, r, tmp, ptr); |
1284 | #endif | |
1285 | } | |
1286 | ||
234fcd14 | 1287 | static void __cpuinit build_r4000_tlb_load_handler(void) |
1da177e4 LT |
1288 | { |
1289 | u32 *p = handle_tlbl; | |
e30ec452 TS |
1290 | struct uasm_label *l = labels; |
1291 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1292 | |
1293 | memset(handle_tlbl, 0, sizeof(handle_tlbl)); | |
1294 | memset(labels, 0, sizeof(labels)); | |
1295 | memset(relocs, 0, sizeof(relocs)); | |
1296 | ||
1297 | if (bcm1250_m3_war()) { | |
e30ec452 TS |
1298 | UASM_i_MFC0(&p, K0, C0_BADVADDR); |
1299 | UASM_i_MFC0(&p, K1, C0_ENTRYHI); | |
1300 | uasm_i_xor(&p, K0, K0, K1); | |
1301 | UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1); | |
1302 | uasm_il_bnez(&p, &r, K0, label_leave); | |
1303 | /* No need for uasm_i_nop */ | |
1da177e4 LT |
1304 | } |
1305 | ||
1306 | build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); | |
bd1437e4 | 1307 | build_pte_present(&p, &r, K0, K1, label_nopage_tlbl); |
8df5beac MR |
1308 | if (m4kc_tlbp_war()) |
1309 | build_tlb_probe_entry(&p); | |
1da177e4 LT |
1310 | build_make_valid(&p, &r, K0, K1); |
1311 | build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); | |
1312 | ||
fd062c84 DD |
1313 | #ifdef CONFIG_HUGETLB_PAGE |
1314 | /* | |
1315 | * This is the entry point when build_r4000_tlbchange_handler_head | |
1316 | * spots a huge page. | |
1317 | */ | |
1318 | uasm_l_tlb_huge_update(&l, p); | |
1319 | iPTE_LW(&p, K0, K1); | |
1320 | build_pte_present(&p, &r, K0, K1, label_nopage_tlbl); | |
1321 | build_tlb_probe_entry(&p); | |
1322 | uasm_i_ori(&p, K0, K0, (_PAGE_ACCESSED | _PAGE_VALID)); | |
1323 | build_huge_handler_tail(&p, &r, &l, K0, K1); | |
1324 | #endif | |
1325 | ||
e30ec452 TS |
1326 | uasm_l_nopage_tlbl(&l, p); |
1327 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); | |
1328 | uasm_i_nop(&p); | |
1da177e4 LT |
1329 | |
1330 | if ((p - handle_tlbl) > FASTPATH_SIZE) | |
1331 | panic("TLB load handler fastpath space exceeded"); | |
1332 | ||
e30ec452 TS |
1333 | uasm_resolve_relocs(relocs, labels); |
1334 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", | |
1335 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 1336 | |
92b1e6a6 | 1337 | dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl)); |
1da177e4 LT |
1338 | } |
1339 | ||
234fcd14 | 1340 | static void __cpuinit build_r4000_tlb_store_handler(void) |
1da177e4 LT |
1341 | { |
1342 | u32 *p = handle_tlbs; | |
e30ec452 TS |
1343 | struct uasm_label *l = labels; |
1344 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1345 | |
1346 | memset(handle_tlbs, 0, sizeof(handle_tlbs)); | |
1347 | memset(labels, 0, sizeof(labels)); | |
1348 | memset(relocs, 0, sizeof(relocs)); | |
1349 | ||
1350 | build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); | |
bd1437e4 | 1351 | build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs); |
8df5beac MR |
1352 | if (m4kc_tlbp_war()) |
1353 | build_tlb_probe_entry(&p); | |
1da177e4 LT |
1354 | build_make_write(&p, &r, K0, K1); |
1355 | build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); | |
1356 | ||
fd062c84 DD |
1357 | #ifdef CONFIG_HUGETLB_PAGE |
1358 | /* | |
1359 | * This is the entry point when | |
1360 | * build_r4000_tlbchange_handler_head spots a huge page. | |
1361 | */ | |
1362 | uasm_l_tlb_huge_update(&l, p); | |
1363 | iPTE_LW(&p, K0, K1); | |
1364 | build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs); | |
1365 | build_tlb_probe_entry(&p); | |
1366 | uasm_i_ori(&p, K0, K0, | |
1367 | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); | |
1368 | build_huge_handler_tail(&p, &r, &l, K0, K1); | |
1369 | #endif | |
1370 | ||
e30ec452 TS |
1371 | uasm_l_nopage_tlbs(&l, p); |
1372 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1373 | uasm_i_nop(&p); | |
1da177e4 LT |
1374 | |
1375 | if ((p - handle_tlbs) > FASTPATH_SIZE) | |
1376 | panic("TLB store handler fastpath space exceeded"); | |
1377 | ||
e30ec452 TS |
1378 | uasm_resolve_relocs(relocs, labels); |
1379 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", | |
1380 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 1381 | |
92b1e6a6 | 1382 | dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs)); |
1da177e4 LT |
1383 | } |
1384 | ||
234fcd14 | 1385 | static void __cpuinit build_r4000_tlb_modify_handler(void) |
1da177e4 LT |
1386 | { |
1387 | u32 *p = handle_tlbm; | |
e30ec452 TS |
1388 | struct uasm_label *l = labels; |
1389 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1390 | |
1391 | memset(handle_tlbm, 0, sizeof(handle_tlbm)); | |
1392 | memset(labels, 0, sizeof(labels)); | |
1393 | memset(relocs, 0, sizeof(relocs)); | |
1394 | ||
1395 | build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); | |
bd1437e4 | 1396 | build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm); |
8df5beac MR |
1397 | if (m4kc_tlbp_war()) |
1398 | build_tlb_probe_entry(&p); | |
1da177e4 LT |
1399 | /* Present and writable bits set, set accessed and dirty bits. */ |
1400 | build_make_write(&p, &r, K0, K1); | |
1401 | build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); | |
1402 | ||
fd062c84 DD |
1403 | #ifdef CONFIG_HUGETLB_PAGE |
1404 | /* | |
1405 | * This is the entry point when | |
1406 | * build_r4000_tlbchange_handler_head spots a huge page. | |
1407 | */ | |
1408 | uasm_l_tlb_huge_update(&l, p); | |
1409 | iPTE_LW(&p, K0, K1); | |
1410 | build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm); | |
1411 | build_tlb_probe_entry(&p); | |
1412 | uasm_i_ori(&p, K0, K0, | |
1413 | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); | |
1414 | build_huge_handler_tail(&p, &r, &l, K0, K1); | |
1415 | #endif | |
1416 | ||
e30ec452 TS |
1417 | uasm_l_nopage_tlbm(&l, p); |
1418 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1419 | uasm_i_nop(&p); | |
1da177e4 LT |
1420 | |
1421 | if ((p - handle_tlbm) > FASTPATH_SIZE) | |
1422 | panic("TLB modify handler fastpath space exceeded"); | |
1423 | ||
e30ec452 TS |
1424 | uasm_resolve_relocs(relocs, labels); |
1425 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", | |
1426 | (unsigned int)(p - handle_tlbm)); | |
115f2a44 | 1427 | |
92b1e6a6 | 1428 | dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm)); |
1da177e4 LT |
1429 | } |
1430 | ||
234fcd14 | 1431 | void __cpuinit build_tlb_refill_handler(void) |
1da177e4 LT |
1432 | { |
1433 | /* | |
1434 | * The refill handler is generated per-CPU, multi-node systems | |
1435 | * may have local storage for it. The other handlers are only | |
1436 | * needed once. | |
1437 | */ | |
1438 | static int run_once = 0; | |
1439 | ||
10cc3529 | 1440 | switch (current_cpu_type()) { |
1da177e4 LT |
1441 | case CPU_R2000: |
1442 | case CPU_R3000: | |
1443 | case CPU_R3000A: | |
1444 | case CPU_R3081E: | |
1445 | case CPU_TX3912: | |
1446 | case CPU_TX3922: | |
1447 | case CPU_TX3927: | |
1448 | build_r3000_tlb_refill_handler(); | |
1449 | if (!run_once) { | |
1450 | build_r3000_tlb_load_handler(); | |
1451 | build_r3000_tlb_store_handler(); | |
1452 | build_r3000_tlb_modify_handler(); | |
1453 | run_once++; | |
1454 | } | |
1455 | break; | |
1456 | ||
1457 | case CPU_R6000: | |
1458 | case CPU_R6000A: | |
1459 | panic("No R6000 TLB refill handler yet"); | |
1460 | break; | |
1461 | ||
1462 | case CPU_R8000: | |
1463 | panic("No R8000 TLB refill handler yet"); | |
1464 | break; | |
1465 | ||
1466 | default: | |
1467 | build_r4000_tlb_refill_handler(); | |
1468 | if (!run_once) { | |
1469 | build_r4000_tlb_load_handler(); | |
1470 | build_r4000_tlb_store_handler(); | |
1471 | build_r4000_tlb_modify_handler(); | |
1472 | run_once++; | |
1473 | } | |
1474 | } | |
1475 | } | |
1d40cfcd | 1476 | |
234fcd14 | 1477 | void __cpuinit flush_tlb_handlers(void) |
1d40cfcd | 1478 | { |
e0cee3ee | 1479 | local_flush_icache_range((unsigned long)handle_tlbl, |
1d40cfcd | 1480 | (unsigned long)handle_tlbl + sizeof(handle_tlbl)); |
e0cee3ee | 1481 | local_flush_icache_range((unsigned long)handle_tlbs, |
1d40cfcd | 1482 | (unsigned long)handle_tlbs + sizeof(handle_tlbs)); |
e0cee3ee | 1483 | local_flush_icache_range((unsigned long)handle_tlbm, |
1d40cfcd RB |
1484 | (unsigned long)handle_tlbm + sizeof(handle_tlbm)); |
1485 | } |