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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Synthesize TLB refill handlers at runtime. | |
7 | * | |
70342287 RB |
8 | * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer |
9 | * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki | |
41c594ab | 10 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) |
fd062c84 | 11 | * Copyright (C) 2008, 2009 Cavium Networks, Inc. |
113c62d9 | 12 | * Copyright (C) 2011 MIPS Technologies, Inc. |
41c594ab RB |
13 | * |
14 | * ... and the days got worse and worse and now you see | |
15 | * I've gone completly out of my mind. | |
16 | * | |
17 | * They're coming to take me a away haha | |
18 | * they're coming to take me a away hoho hihi haha | |
19 | * to the funny farm where code is beautiful all the time ... | |
20 | * | |
21 | * (Condolences to Napoleon XIV) | |
1da177e4 LT |
22 | */ |
23 | ||
95affdda | 24 | #include <linux/bug.h> |
1da177e4 LT |
25 | #include <linux/kernel.h> |
26 | #include <linux/types.h> | |
631330f5 | 27 | #include <linux/smp.h> |
1da177e4 LT |
28 | #include <linux/string.h> |
29 | #include <linux/init.h> | |
3d8bfdd0 | 30 | #include <linux/cache.h> |
1da177e4 | 31 | |
3d8bfdd0 DD |
32 | #include <asm/cacheflush.h> |
33 | #include <asm/pgtable.h> | |
1da177e4 | 34 | #include <asm/war.h> |
3482d713 | 35 | #include <asm/uasm.h> |
b81947c6 | 36 | #include <asm/setup.h> |
e30ec452 | 37 | |
1ec56329 DD |
38 | /* |
39 | * TLB load/store/modify handlers. | |
40 | * | |
41 | * Only the fastpath gets synthesized at runtime, the slowpath for | |
42 | * do_page_fault remains normal asm. | |
43 | */ | |
44 | extern void tlb_do_page_fault_0(void); | |
45 | extern void tlb_do_page_fault_1(void); | |
46 | ||
bf28607f DD |
47 | struct work_registers { |
48 | int r1; | |
49 | int r2; | |
50 | int r3; | |
51 | }; | |
52 | ||
53 | struct tlb_reg_save { | |
54 | unsigned long a; | |
55 | unsigned long b; | |
56 | } ____cacheline_aligned_in_smp; | |
57 | ||
58 | static struct tlb_reg_save handler_reg_save[NR_CPUS]; | |
1ec56329 | 59 | |
aeffdbba | 60 | static inline int r45k_bvahwbug(void) |
1da177e4 LT |
61 | { |
62 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
63 | return 0; | |
64 | } | |
65 | ||
aeffdbba | 66 | static inline int r4k_250MHZhwbug(void) |
1da177e4 LT |
67 | { |
68 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
69 | return 0; | |
70 | } | |
71 | ||
aeffdbba | 72 | static inline int __maybe_unused bcm1250_m3_war(void) |
1da177e4 LT |
73 | { |
74 | return BCM1250_M3_WAR; | |
75 | } | |
76 | ||
aeffdbba | 77 | static inline int __maybe_unused r10000_llsc_war(void) |
1da177e4 LT |
78 | { |
79 | return R10000_LLSC_WAR; | |
80 | } | |
81 | ||
cc33ae43 DD |
82 | static int use_bbit_insns(void) |
83 | { | |
84 | switch (current_cpu_type()) { | |
85 | case CPU_CAVIUM_OCTEON: | |
86 | case CPU_CAVIUM_OCTEON_PLUS: | |
87 | case CPU_CAVIUM_OCTEON2: | |
88 | return 1; | |
89 | default: | |
90 | return 0; | |
91 | } | |
92 | } | |
93 | ||
2c8c53e2 DD |
94 | static int use_lwx_insns(void) |
95 | { | |
96 | switch (current_cpu_type()) { | |
97 | case CPU_CAVIUM_OCTEON2: | |
98 | return 1; | |
99 | default: | |
100 | return 0; | |
101 | } | |
102 | } | |
103 | #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \ | |
104 | CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 | |
105 | static bool scratchpad_available(void) | |
106 | { | |
107 | return true; | |
108 | } | |
109 | static int scratchpad_offset(int i) | |
110 | { | |
111 | /* | |
112 | * CVMSEG starts at address -32768 and extends for | |
113 | * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines. | |
114 | */ | |
115 | i += 1; /* Kernel use starts at the top and works down. */ | |
116 | return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768; | |
117 | } | |
118 | #else | |
119 | static bool scratchpad_available(void) | |
120 | { | |
121 | return false; | |
122 | } | |
123 | static int scratchpad_offset(int i) | |
124 | { | |
125 | BUG(); | |
e1c87d2a DD |
126 | /* Really unreachable, but evidently some GCC want this. */ |
127 | return 0; | |
2c8c53e2 DD |
128 | } |
129 | #endif | |
8df5beac MR |
130 | /* |
131 | * Found by experiment: At least some revisions of the 4kc throw under | |
132 | * some circumstances a machine check exception, triggered by invalid | |
133 | * values in the index register. Delaying the tlbp instruction until | |
134 | * after the next branch, plus adding an additional nop in front of | |
135 | * tlbwi/tlbwr avoids the invalid index register values. Nobody knows | |
136 | * why; it's not an issue caused by the core RTL. | |
137 | * | |
138 | */ | |
234fcd14 | 139 | static int __cpuinit m4kc_tlbp_war(void) |
8df5beac MR |
140 | { |
141 | return (current_cpu_data.processor_id & 0xffff00) == | |
142 | (PRID_COMP_MIPS | PRID_IMP_4KC); | |
143 | } | |
144 | ||
e30ec452 | 145 | /* Handle labels (which must be positive integers). */ |
1da177e4 | 146 | enum label_id { |
e30ec452 | 147 | label_second_part = 1, |
1da177e4 LT |
148 | label_leave, |
149 | label_vmalloc, | |
150 | label_vmalloc_done, | |
02a54177 RB |
151 | label_tlbw_hazard_0, |
152 | label_split = label_tlbw_hazard_0 + 8, | |
6dd9344c DD |
153 | label_tlbl_goaround1, |
154 | label_tlbl_goaround2, | |
1da177e4 LT |
155 | label_nopage_tlbl, |
156 | label_nopage_tlbs, | |
157 | label_nopage_tlbm, | |
158 | label_smp_pgtable_change, | |
159 | label_r3000_write_probe_fail, | |
1ec56329 | 160 | label_large_segbits_fault, |
aa1762f4 | 161 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
162 | label_tlb_huge_update, |
163 | #endif | |
1da177e4 LT |
164 | }; |
165 | ||
e30ec452 TS |
166 | UASM_L_LA(_second_part) |
167 | UASM_L_LA(_leave) | |
e30ec452 TS |
168 | UASM_L_LA(_vmalloc) |
169 | UASM_L_LA(_vmalloc_done) | |
02a54177 | 170 | /* _tlbw_hazard_x is handled differently. */ |
e30ec452 | 171 | UASM_L_LA(_split) |
6dd9344c DD |
172 | UASM_L_LA(_tlbl_goaround1) |
173 | UASM_L_LA(_tlbl_goaround2) | |
e30ec452 TS |
174 | UASM_L_LA(_nopage_tlbl) |
175 | UASM_L_LA(_nopage_tlbs) | |
176 | UASM_L_LA(_nopage_tlbm) | |
177 | UASM_L_LA(_smp_pgtable_change) | |
178 | UASM_L_LA(_r3000_write_probe_fail) | |
1ec56329 | 179 | UASM_L_LA(_large_segbits_fault) |
aa1762f4 | 180 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
181 | UASM_L_LA(_tlb_huge_update) |
182 | #endif | |
656be92f | 183 | |
02a54177 RB |
184 | static int __cpuinitdata hazard_instance; |
185 | ||
f151f3b9 KC |
186 | static void __cpuinit uasm_bgezl_hazard(u32 **p, |
187 | struct uasm_reloc **r, | |
188 | int instance) | |
02a54177 RB |
189 | { |
190 | switch (instance) { | |
191 | case 0 ... 7: | |
192 | uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance); | |
193 | return; | |
194 | default: | |
195 | BUG(); | |
196 | } | |
197 | } | |
198 | ||
f151f3b9 KC |
199 | static void __cpuinit uasm_bgezl_label(struct uasm_label **l, |
200 | u32 **p, | |
201 | int instance) | |
02a54177 RB |
202 | { |
203 | switch (instance) { | |
204 | case 0 ... 7: | |
205 | uasm_build_label(l, *p, label_tlbw_hazard_0 + instance); | |
206 | break; | |
207 | default: | |
208 | BUG(); | |
209 | } | |
210 | } | |
211 | ||
92b1e6a6 | 212 | /* |
a2c763e0 RB |
213 | * pgtable bits are assigned dynamically depending on processor feature |
214 | * and statically based on kernel configuration. This spits out the actual | |
70342287 | 215 | * values the kernel is using. Required to make sense from disassembled |
a2c763e0 | 216 | * TLB exception handlers. |
92b1e6a6 | 217 | */ |
a2c763e0 RB |
218 | static void output_pgtable_bits_defines(void) |
219 | { | |
220 | #define pr_define(fmt, ...) \ | |
221 | pr_debug("#define " fmt, ##__VA_ARGS__) | |
222 | ||
223 | pr_debug("#include <asm/asm.h>\n"); | |
224 | pr_debug("#include <asm/regdef.h>\n"); | |
225 | pr_debug("\n"); | |
226 | ||
227 | pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT); | |
228 | pr_define("_PAGE_READ_SHIFT %d\n", _PAGE_READ_SHIFT); | |
229 | pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT); | |
230 | pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT); | |
231 | pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT); | |
970d032f | 232 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
a2c763e0 | 233 | pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT); |
970d032f | 234 | pr_define("_PAGE_SPLITTING_SHIFT %d\n", _PAGE_SPLITTING_SHIFT); |
a2c763e0 RB |
235 | #endif |
236 | if (cpu_has_rixi) { | |
237 | #ifdef _PAGE_NO_EXEC_SHIFT | |
238 | pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT); | |
239 | #endif | |
240 | #ifdef _PAGE_NO_READ_SHIFT | |
241 | pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT); | |
242 | #endif | |
243 | } | |
244 | pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT); | |
245 | pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT); | |
246 | pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT); | |
247 | pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT); | |
248 | pr_debug("\n"); | |
249 | } | |
250 | ||
251 | static inline void dump_handler(const char *symbol, const u32 *handler, int count) | |
92b1e6a6 FBH |
252 | { |
253 | int i; | |
254 | ||
a2c763e0 RB |
255 | pr_debug("LEAF(%s)\n", symbol); |
256 | ||
92b1e6a6 FBH |
257 | pr_debug("\t.set push\n"); |
258 | pr_debug("\t.set noreorder\n"); | |
259 | ||
260 | for (i = 0; i < count; i++) | |
a2c763e0 | 261 | pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]); |
92b1e6a6 | 262 | |
a2c763e0 RB |
263 | pr_debug("\t.set\tpop\n"); |
264 | ||
265 | pr_debug("\tEND(%s)\n", symbol); | |
92b1e6a6 FBH |
266 | } |
267 | ||
1da177e4 LT |
268 | /* The only general purpose registers allowed in TLB handlers. */ |
269 | #define K0 26 | |
270 | #define K1 27 | |
271 | ||
272 | /* Some CP0 registers */ | |
41c594ab RB |
273 | #define C0_INDEX 0, 0 |
274 | #define C0_ENTRYLO0 2, 0 | |
275 | #define C0_TCBIND 2, 2 | |
276 | #define C0_ENTRYLO1 3, 0 | |
277 | #define C0_CONTEXT 4, 0 | |
fd062c84 | 278 | #define C0_PAGEMASK 5, 0 |
41c594ab RB |
279 | #define C0_BADVADDR 8, 0 |
280 | #define C0_ENTRYHI 10, 0 | |
281 | #define C0_EPC 14, 0 | |
282 | #define C0_XCONTEXT 20, 0 | |
1da177e4 | 283 | |
875d43e7 | 284 | #ifdef CONFIG_64BIT |
e30ec452 | 285 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT) |
1da177e4 | 286 | #else |
e30ec452 | 287 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT) |
1da177e4 LT |
288 | #endif |
289 | ||
290 | /* The worst case length of the handler is around 18 instructions for | |
291 | * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. | |
292 | * Maximum space available is 32 instructions for R3000 and 64 | |
293 | * instructions for R4000. | |
294 | * | |
295 | * We deliberately chose a buffer size of 128, so we won't scribble | |
296 | * over anything important on overflow before we panic. | |
297 | */ | |
234fcd14 | 298 | static u32 tlb_handler[128] __cpuinitdata; |
1da177e4 LT |
299 | |
300 | /* simply assume worst case size for labels and relocs */ | |
234fcd14 RB |
301 | static struct uasm_label labels[128] __cpuinitdata; |
302 | static struct uasm_reloc relocs[128] __cpuinitdata; | |
1da177e4 | 303 | |
2c8c53e2 | 304 | static int check_for_high_segbits __cpuinitdata; |
3d8bfdd0 DD |
305 | |
306 | static unsigned int kscratch_used_mask __cpuinitdata; | |
307 | ||
7777b939 J |
308 | static inline int __maybe_unused c0_kscratch(void) |
309 | { | |
310 | switch (current_cpu_type()) { | |
311 | case CPU_XLP: | |
312 | case CPU_XLR: | |
313 | return 22; | |
314 | default: | |
315 | return 31; | |
316 | } | |
317 | } | |
318 | ||
3d8bfdd0 DD |
319 | static int __cpuinit allocate_kscratch(void) |
320 | { | |
321 | int r; | |
322 | unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask; | |
323 | ||
324 | r = ffs(a); | |
325 | ||
326 | if (r == 0) | |
327 | return -1; | |
328 | ||
329 | r--; /* make it zero based */ | |
330 | ||
331 | kscratch_used_mask |= (1 << r); | |
332 | ||
333 | return r; | |
334 | } | |
335 | ||
2c8c53e2 | 336 | static int scratch_reg __cpuinitdata; |
3d8bfdd0 | 337 | static int pgd_reg __cpuinitdata; |
2c8c53e2 DD |
338 | enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch}; |
339 | ||
bf28607f DD |
340 | static struct work_registers __cpuinit build_get_work_registers(u32 **p) |
341 | { | |
342 | struct work_registers r; | |
343 | ||
344 | int smp_processor_id_reg; | |
345 | int smp_processor_id_sel; | |
346 | int smp_processor_id_shift; | |
347 | ||
0e6ecc1a | 348 | if (scratch_reg >= 0) { |
bf28607f | 349 | /* Save in CPU local C0_KScratch? */ |
7777b939 | 350 | UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg); |
bf28607f DD |
351 | r.r1 = K0; |
352 | r.r2 = K1; | |
353 | r.r3 = 1; | |
354 | return r; | |
355 | } | |
356 | ||
357 | if (num_possible_cpus() > 1) { | |
358 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT | |
359 | smp_processor_id_shift = 51; | |
360 | smp_processor_id_reg = 20; /* XContext */ | |
361 | smp_processor_id_sel = 0; | |
362 | #else | |
363 | # ifdef CONFIG_32BIT | |
364 | smp_processor_id_shift = 25; | |
365 | smp_processor_id_reg = 4; /* Context */ | |
366 | smp_processor_id_sel = 0; | |
367 | # endif | |
368 | # ifdef CONFIG_64BIT | |
369 | smp_processor_id_shift = 26; | |
370 | smp_processor_id_reg = 4; /* Context */ | |
371 | smp_processor_id_sel = 0; | |
372 | # endif | |
373 | #endif | |
374 | /* Get smp_processor_id */ | |
375 | UASM_i_MFC0(p, K0, smp_processor_id_reg, smp_processor_id_sel); | |
376 | UASM_i_SRL_SAFE(p, K0, K0, smp_processor_id_shift); | |
377 | ||
378 | /* handler_reg_save index in K0 */ | |
379 | UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save))); | |
380 | ||
381 | UASM_i_LA(p, K1, (long)&handler_reg_save); | |
382 | UASM_i_ADDU(p, K0, K0, K1); | |
383 | } else { | |
384 | UASM_i_LA(p, K0, (long)&handler_reg_save); | |
385 | } | |
386 | /* K0 now points to save area, save $1 and $2 */ | |
387 | UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0); | |
388 | UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0); | |
389 | ||
390 | r.r1 = K1; | |
391 | r.r2 = 1; | |
392 | r.r3 = 2; | |
393 | return r; | |
394 | } | |
395 | ||
396 | static void __cpuinit build_restore_work_registers(u32 **p) | |
397 | { | |
0e6ecc1a | 398 | if (scratch_reg >= 0) { |
7777b939 | 399 | UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); |
bf28607f DD |
400 | return; |
401 | } | |
402 | /* K0 already points to save area, restore $1 and $2 */ | |
403 | UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0); | |
404 | UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0); | |
405 | } | |
406 | ||
2c8c53e2 | 407 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
3d8bfdd0 | 408 | |
82622284 DD |
409 | /* |
410 | * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current, | |
411 | * we cannot do r3000 under these circumstances. | |
3d8bfdd0 DD |
412 | * |
413 | * Declare pgd_current here instead of including mmu_context.h to avoid type | |
414 | * conflicts for tlbmiss_handler_setup_pgd | |
82622284 | 415 | */ |
3d8bfdd0 | 416 | extern unsigned long pgd_current[]; |
82622284 | 417 | |
1da177e4 LT |
418 | /* |
419 | * The R3000 TLB handler is simple. | |
420 | */ | |
234fcd14 | 421 | static void __cpuinit build_r3000_tlb_refill_handler(void) |
1da177e4 LT |
422 | { |
423 | long pgdc = (long)pgd_current; | |
424 | u32 *p; | |
425 | ||
426 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
427 | p = tlb_handler; | |
428 | ||
e30ec452 TS |
429 | uasm_i_mfc0(&p, K0, C0_BADVADDR); |
430 | uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */ | |
431 | uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1); | |
432 | uasm_i_srl(&p, K0, K0, 22); /* load delay */ | |
433 | uasm_i_sll(&p, K0, K0, 2); | |
434 | uasm_i_addu(&p, K1, K1, K0); | |
435 | uasm_i_mfc0(&p, K0, C0_CONTEXT); | |
436 | uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */ | |
437 | uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */ | |
438 | uasm_i_addu(&p, K1, K1, K0); | |
439 | uasm_i_lw(&p, K0, 0, K1); | |
440 | uasm_i_nop(&p); /* load delay */ | |
441 | uasm_i_mtc0(&p, K0, C0_ENTRYLO0); | |
442 | uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ | |
443 | uasm_i_tlbwr(&p); /* cp0 delay */ | |
444 | uasm_i_jr(&p, K1); | |
445 | uasm_i_rfe(&p); /* branch delay */ | |
1da177e4 LT |
446 | |
447 | if (p > tlb_handler + 32) | |
448 | panic("TLB refill handler space exceeded"); | |
449 | ||
e30ec452 TS |
450 | pr_debug("Wrote TLB refill handler (%u instructions).\n", |
451 | (unsigned int)(p - tlb_handler)); | |
1da177e4 | 452 | |
91b05e67 | 453 | memcpy((void *)ebase, tlb_handler, 0x80); |
92b1e6a6 | 454 | |
a2c763e0 | 455 | dump_handler("r3000_tlb_refill", (u32 *)ebase, 32); |
1da177e4 | 456 | } |
82622284 | 457 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ |
1da177e4 LT |
458 | |
459 | /* | |
460 | * The R4000 TLB handler is much more complicated. We have two | |
461 | * consecutive handler areas with 32 instructions space each. | |
462 | * Since they aren't used at the same time, we can overflow in the | |
463 | * other one.To keep things simple, we first assume linear space, | |
464 | * then we relocate it to the final handler layout as needed. | |
465 | */ | |
234fcd14 | 466 | static u32 final_handler[64] __cpuinitdata; |
1da177e4 LT |
467 | |
468 | /* | |
469 | * Hazards | |
470 | * | |
471 | * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: | |
472 | * 2. A timing hazard exists for the TLBP instruction. | |
473 | * | |
70342287 RB |
474 | * stalling_instruction |
475 | * TLBP | |
1da177e4 LT |
476 | * |
477 | * The JTLB is being read for the TLBP throughout the stall generated by the | |
478 | * previous instruction. This is not really correct as the stalling instruction | |
479 | * can modify the address used to access the JTLB. The failure symptom is that | |
480 | * the TLBP instruction will use an address created for the stalling instruction | |
481 | * and not the address held in C0_ENHI and thus report the wrong results. | |
482 | * | |
483 | * The software work-around is to not allow the instruction preceding the TLBP | |
484 | * to stall - make it an NOP or some other instruction guaranteed not to stall. | |
485 | * | |
70342287 | 486 | * Errata 2 will not be fixed. This errata is also on the R5000. |
1da177e4 LT |
487 | * |
488 | * As if we MIPS hackers wouldn't know how to nop pipelines happy ... | |
489 | */ | |
234fcd14 | 490 | static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p) |
1da177e4 | 491 | { |
10cc3529 | 492 | switch (current_cpu_type()) { |
326e2e1a | 493 | /* Found by experiment: R4600 v2.0/R4700 needs this, too. */ |
f5b4d956 | 494 | case CPU_R4600: |
326e2e1a | 495 | case CPU_R4700: |
1da177e4 | 496 | case CPU_R5000: |
1da177e4 | 497 | case CPU_NEVADA: |
e30ec452 TS |
498 | uasm_i_nop(p); |
499 | uasm_i_tlbp(p); | |
1da177e4 LT |
500 | break; |
501 | ||
502 | default: | |
e30ec452 | 503 | uasm_i_tlbp(p); |
1da177e4 LT |
504 | break; |
505 | } | |
506 | } | |
507 | ||
508 | /* | |
509 | * Write random or indexed TLB entry, and care about the hazards from | |
25985edc | 510 | * the preceding mtc0 and for the following eret. |
1da177e4 LT |
511 | */ |
512 | enum tlb_write_entry { tlb_random, tlb_indexed }; | |
513 | ||
234fcd14 | 514 | static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, |
e30ec452 | 515 | struct uasm_reloc **r, |
1da177e4 LT |
516 | enum tlb_write_entry wmode) |
517 | { | |
518 | void(*tlbw)(u32 **) = NULL; | |
519 | ||
520 | switch (wmode) { | |
e30ec452 TS |
521 | case tlb_random: tlbw = uasm_i_tlbwr; break; |
522 | case tlb_indexed: tlbw = uasm_i_tlbwi; break; | |
1da177e4 LT |
523 | } |
524 | ||
161548bf | 525 | if (cpu_has_mips_r2) { |
625c0a21 SH |
526 | /* |
527 | * The architecture spec says an ehb is required here, | |
528 | * but a number of cores do not have the hazard and | |
529 | * using an ehb causes an expensive pipeline stall. | |
530 | */ | |
531 | switch (current_cpu_type()) { | |
532 | case CPU_M14KC: | |
533 | case CPU_74K: | |
534 | break; | |
535 | ||
536 | default: | |
41f0e4d0 | 537 | uasm_i_ehb(p); |
625c0a21 SH |
538 | break; |
539 | } | |
161548bf RB |
540 | tlbw(p); |
541 | return; | |
542 | } | |
543 | ||
10cc3529 | 544 | switch (current_cpu_type()) { |
1da177e4 LT |
545 | case CPU_R4000PC: |
546 | case CPU_R4000SC: | |
547 | case CPU_R4000MC: | |
548 | case CPU_R4400PC: | |
549 | case CPU_R4400SC: | |
550 | case CPU_R4400MC: | |
551 | /* | |
552 | * This branch uses up a mtc0 hazard nop slot and saves | |
553 | * two nops after the tlbw instruction. | |
554 | */ | |
02a54177 | 555 | uasm_bgezl_hazard(p, r, hazard_instance); |
1da177e4 | 556 | tlbw(p); |
02a54177 RB |
557 | uasm_bgezl_label(l, p, hazard_instance); |
558 | hazard_instance++; | |
e30ec452 | 559 | uasm_i_nop(p); |
1da177e4 LT |
560 | break; |
561 | ||
562 | case CPU_R4600: | |
563 | case CPU_R4700: | |
e30ec452 | 564 | uasm_i_nop(p); |
2c93e12c | 565 | tlbw(p); |
e30ec452 | 566 | uasm_i_nop(p); |
2c93e12c MR |
567 | break; |
568 | ||
359187d6 | 569 | case CPU_R5000: |
359187d6 RB |
570 | case CPU_NEVADA: |
571 | uasm_i_nop(p); /* QED specifies 2 nops hazard */ | |
572 | uasm_i_nop(p); /* QED specifies 2 nops hazard */ | |
573 | tlbw(p); | |
574 | break; | |
575 | ||
2c93e12c | 576 | case CPU_R4300: |
1da177e4 LT |
577 | case CPU_5KC: |
578 | case CPU_TX49XX: | |
bdf21b18 | 579 | case CPU_PR4450: |
efa0f81c | 580 | case CPU_XLR: |
e30ec452 | 581 | uasm_i_nop(p); |
1da177e4 LT |
582 | tlbw(p); |
583 | break; | |
584 | ||
585 | case CPU_R10000: | |
586 | case CPU_R12000: | |
44d921b2 | 587 | case CPU_R14000: |
1da177e4 | 588 | case CPU_4KC: |
b1ec4c8e | 589 | case CPU_4KEC: |
113c62d9 | 590 | case CPU_M14KC: |
f8fa4811 | 591 | case CPU_M14KEC: |
1da177e4 | 592 | case CPU_SB1: |
93ce2f52 | 593 | case CPU_SB1A: |
1da177e4 LT |
594 | case CPU_4KSC: |
595 | case CPU_20KC: | |
596 | case CPU_25KF: | |
602977b0 KC |
597 | case CPU_BMIPS32: |
598 | case CPU_BMIPS3300: | |
599 | case CPU_BMIPS4350: | |
600 | case CPU_BMIPS4380: | |
601 | case CPU_BMIPS5000: | |
2a21c730 | 602 | case CPU_LOONGSON2: |
a644b277 | 603 | case CPU_R5500: |
8df5beac | 604 | if (m4kc_tlbp_war()) |
e30ec452 | 605 | uasm_i_nop(p); |
2f794d09 | 606 | case CPU_ALCHEMY: |
1da177e4 LT |
607 | tlbw(p); |
608 | break; | |
609 | ||
1da177e4 | 610 | case CPU_RM7000: |
e30ec452 TS |
611 | uasm_i_nop(p); |
612 | uasm_i_nop(p); | |
613 | uasm_i_nop(p); | |
614 | uasm_i_nop(p); | |
1da177e4 LT |
615 | tlbw(p); |
616 | break; | |
617 | ||
1da177e4 LT |
618 | case CPU_VR4111: |
619 | case CPU_VR4121: | |
620 | case CPU_VR4122: | |
621 | case CPU_VR4181: | |
622 | case CPU_VR4181A: | |
e30ec452 TS |
623 | uasm_i_nop(p); |
624 | uasm_i_nop(p); | |
1da177e4 | 625 | tlbw(p); |
e30ec452 TS |
626 | uasm_i_nop(p); |
627 | uasm_i_nop(p); | |
1da177e4 LT |
628 | break; |
629 | ||
630 | case CPU_VR4131: | |
631 | case CPU_VR4133: | |
7623debf | 632 | case CPU_R5432: |
e30ec452 TS |
633 | uasm_i_nop(p); |
634 | uasm_i_nop(p); | |
1da177e4 LT |
635 | tlbw(p); |
636 | break; | |
637 | ||
83ccf69d LPC |
638 | case CPU_JZRISC: |
639 | tlbw(p); | |
640 | uasm_i_nop(p); | |
641 | break; | |
642 | ||
1da177e4 LT |
643 | default: |
644 | panic("No TLB refill handler yet (CPU type: %d)", | |
645 | current_cpu_data.cputype); | |
646 | break; | |
647 | } | |
648 | } | |
649 | ||
6dd9344c DD |
650 | static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p, |
651 | unsigned int reg) | |
fd062c84 | 652 | { |
05857c64 | 653 | if (cpu_has_rixi) { |
748e787e | 654 | UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL)); |
6dd9344c DD |
655 | } else { |
656 | #ifdef CONFIG_64BIT_PHYS_ADDR | |
3be6022c | 657 | uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL)); |
6dd9344c DD |
658 | #else |
659 | UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL)); | |
660 | #endif | |
661 | } | |
662 | } | |
fd062c84 | 663 | |
aa1762f4 | 664 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 | 665 | |
6dd9344c DD |
666 | static __cpuinit void build_restore_pagemask(u32 **p, |
667 | struct uasm_reloc **r, | |
668 | unsigned int tmp, | |
2c8c53e2 DD |
669 | enum label_id lid, |
670 | int restore_scratch) | |
6dd9344c | 671 | { |
2c8c53e2 DD |
672 | if (restore_scratch) { |
673 | /* Reset default page size */ | |
674 | if (PM_DEFAULT_MASK >> 16) { | |
675 | uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); | |
676 | uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); | |
677 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
678 | uasm_il_b(p, r, lid); | |
679 | } else if (PM_DEFAULT_MASK) { | |
680 | uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); | |
681 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
682 | uasm_il_b(p, r, lid); | |
683 | } else { | |
684 | uasm_i_mtc0(p, 0, C0_PAGEMASK); | |
685 | uasm_il_b(p, r, lid); | |
686 | } | |
0e6ecc1a | 687 | if (scratch_reg >= 0) |
7777b939 | 688 | UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); |
2c8c53e2 DD |
689 | else |
690 | UASM_i_LW(p, 1, scratchpad_offset(0), 0); | |
fd062c84 | 691 | } else { |
2c8c53e2 DD |
692 | /* Reset default page size */ |
693 | if (PM_DEFAULT_MASK >> 16) { | |
694 | uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); | |
695 | uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); | |
696 | uasm_il_b(p, r, lid); | |
697 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
698 | } else if (PM_DEFAULT_MASK) { | |
699 | uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); | |
700 | uasm_il_b(p, r, lid); | |
701 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
702 | } else { | |
703 | uasm_il_b(p, r, lid); | |
704 | uasm_i_mtc0(p, 0, C0_PAGEMASK); | |
705 | } | |
fd062c84 DD |
706 | } |
707 | } | |
708 | ||
6dd9344c DD |
709 | static __cpuinit void build_huge_tlb_write_entry(u32 **p, |
710 | struct uasm_label **l, | |
711 | struct uasm_reloc **r, | |
712 | unsigned int tmp, | |
2c8c53e2 DD |
713 | enum tlb_write_entry wmode, |
714 | int restore_scratch) | |
6dd9344c DD |
715 | { |
716 | /* Set huge page tlb entry size */ | |
717 | uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16); | |
718 | uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff); | |
719 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
720 | ||
721 | build_tlb_write_entry(p, l, r, wmode); | |
722 | ||
2c8c53e2 | 723 | build_restore_pagemask(p, r, tmp, label_leave, restore_scratch); |
6dd9344c DD |
724 | } |
725 | ||
fd062c84 DD |
726 | /* |
727 | * Check if Huge PTE is present, if so then jump to LABEL. | |
728 | */ | |
729 | static void __cpuinit | |
730 | build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp, | |
731 | unsigned int pmd, int lid) | |
732 | { | |
733 | UASM_i_LW(p, tmp, 0, pmd); | |
cc33ae43 DD |
734 | if (use_bbit_insns()) { |
735 | uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid); | |
736 | } else { | |
737 | uasm_i_andi(p, tmp, tmp, _PAGE_HUGE); | |
738 | uasm_il_bnez(p, r, tmp, lid); | |
739 | } | |
fd062c84 DD |
740 | } |
741 | ||
742 | static __cpuinit void build_huge_update_entries(u32 **p, | |
743 | unsigned int pte, | |
744 | unsigned int tmp) | |
745 | { | |
746 | int small_sequence; | |
747 | ||
748 | /* | |
749 | * A huge PTE describes an area the size of the | |
750 | * configured huge page size. This is twice the | |
751 | * of the large TLB entry size we intend to use. | |
752 | * A TLB entry half the size of the configured | |
753 | * huge page size is configured into entrylo0 | |
754 | * and entrylo1 to cover the contiguous huge PTE | |
755 | * address space. | |
756 | */ | |
757 | small_sequence = (HPAGE_SIZE >> 7) < 0x10000; | |
758 | ||
70342287 | 759 | /* We can clobber tmp. It isn't used after this.*/ |
fd062c84 DD |
760 | if (!small_sequence) |
761 | uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16)); | |
762 | ||
6dd9344c | 763 | build_convert_pte_to_entrylo(p, pte); |
9b8c3891 | 764 | UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */ |
fd062c84 DD |
765 | /* convert to entrylo1 */ |
766 | if (small_sequence) | |
767 | UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7); | |
768 | else | |
769 | UASM_i_ADDU(p, pte, pte, tmp); | |
770 | ||
9b8c3891 | 771 | UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */ |
fd062c84 DD |
772 | } |
773 | ||
774 | static __cpuinit void build_huge_handler_tail(u32 **p, | |
775 | struct uasm_reloc **r, | |
776 | struct uasm_label **l, | |
777 | unsigned int pte, | |
778 | unsigned int ptr) | |
779 | { | |
780 | #ifdef CONFIG_SMP | |
781 | UASM_i_SC(p, pte, 0, ptr); | |
782 | uasm_il_beqz(p, r, pte, label_tlb_huge_update); | |
783 | UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */ | |
784 | #else | |
785 | UASM_i_SW(p, pte, 0, ptr); | |
786 | #endif | |
787 | build_huge_update_entries(p, pte, ptr); | |
2c8c53e2 | 788 | build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0); |
fd062c84 | 789 | } |
aa1762f4 | 790 | #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ |
fd062c84 | 791 | |
875d43e7 | 792 | #ifdef CONFIG_64BIT |
1da177e4 LT |
793 | /* |
794 | * TMP and PTR are scratch. | |
795 | * TMP will be clobbered, PTR will hold the pmd entry. | |
796 | */ | |
234fcd14 | 797 | static void __cpuinit |
e30ec452 | 798 | build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
1da177e4 LT |
799 | unsigned int tmp, unsigned int ptr) |
800 | { | |
82622284 | 801 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
1da177e4 | 802 | long pgdc = (long)pgd_current; |
82622284 | 803 | #endif |
1da177e4 LT |
804 | /* |
805 | * The vmalloc handling is not in the hotpath. | |
806 | */ | |
e30ec452 | 807 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); |
1ec56329 DD |
808 | |
809 | if (check_for_high_segbits) { | |
810 | /* | |
811 | * The kernel currently implicitely assumes that the | |
812 | * MIPS SEGBITS parameter for the processor is | |
813 | * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never | |
814 | * allocate virtual addresses outside the maximum | |
815 | * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But | |
816 | * that doesn't prevent user code from accessing the | |
817 | * higher xuseg addresses. Here, we make sure that | |
818 | * everything but the lower xuseg addresses goes down | |
819 | * the module_alloc/vmalloc path. | |
820 | */ | |
821 | uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); | |
822 | uasm_il_bnez(p, r, ptr, label_vmalloc); | |
823 | } else { | |
824 | uasm_il_bltz(p, r, tmp, label_vmalloc); | |
825 | } | |
e30ec452 | 826 | /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ |
1da177e4 | 827 | |
82622284 | 828 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
3d8bfdd0 DD |
829 | if (pgd_reg != -1) { |
830 | /* pgd is in pgd_reg */ | |
7777b939 | 831 | UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); |
3d8bfdd0 DD |
832 | } else { |
833 | /* | |
834 | * &pgd << 11 stored in CONTEXT [23..63]. | |
835 | */ | |
836 | UASM_i_MFC0(p, ptr, C0_CONTEXT); | |
837 | ||
838 | /* Clear lower 23 bits of context. */ | |
839 | uasm_i_dins(p, ptr, 0, 0, 23); | |
840 | ||
70342287 | 841 | /* 1 0 1 0 1 << 6 xkphys cached */ |
3d8bfdd0 DD |
842 | uasm_i_ori(p, ptr, ptr, 0x540); |
843 | uasm_i_drotr(p, ptr, ptr, 11); | |
844 | } | |
82622284 | 845 | #elif defined(CONFIG_SMP) |
70342287 | 846 | # ifdef CONFIG_MIPS_MT_SMTC |
41c594ab RB |
847 | /* |
848 | * SMTC uses TCBind value as "CPU" index | |
849 | */ | |
e30ec452 | 850 | uasm_i_mfc0(p, ptr, C0_TCBIND); |
3be6022c | 851 | uasm_i_dsrl_safe(p, ptr, ptr, 19); |
41c594ab | 852 | # else |
1da177e4 | 853 | /* |
1b3a6e97 | 854 | * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 |
1da177e4 LT |
855 | * stored in CONTEXT. |
856 | */ | |
e30ec452 | 857 | uasm_i_dmfc0(p, ptr, C0_CONTEXT); |
3be6022c | 858 | uasm_i_dsrl_safe(p, ptr, ptr, 23); |
82622284 | 859 | # endif |
e30ec452 TS |
860 | UASM_i_LA_mostly(p, tmp, pgdc); |
861 | uasm_i_daddu(p, ptr, ptr, tmp); | |
862 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); | |
863 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1da177e4 | 864 | #else |
e30ec452 TS |
865 | UASM_i_LA_mostly(p, ptr, pgdc); |
866 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1da177e4 LT |
867 | #endif |
868 | ||
e30ec452 | 869 | uasm_l_vmalloc_done(l, *p); |
242954b5 | 870 | |
3be6022c DD |
871 | /* get pgd offset in bytes */ |
872 | uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3); | |
e30ec452 TS |
873 | |
874 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); | |
875 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
325f8a0a | 876 | #ifndef __PAGETABLE_PMD_FOLDED |
e30ec452 TS |
877 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ |
878 | uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ | |
3be6022c | 879 | uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ |
e30ec452 TS |
880 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); |
881 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ | |
325f8a0a | 882 | #endif |
1da177e4 LT |
883 | } |
884 | ||
885 | /* | |
886 | * BVADDR is the faulting address, PTR is scratch. | |
887 | * PTR will hold the pgd for vmalloc. | |
888 | */ | |
234fcd14 | 889 | static void __cpuinit |
e30ec452 | 890 | build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
1ec56329 DD |
891 | unsigned int bvaddr, unsigned int ptr, |
892 | enum vmalloc64_mode mode) | |
1da177e4 LT |
893 | { |
894 | long swpd = (long)swapper_pg_dir; | |
1ec56329 DD |
895 | int single_insn_swpd; |
896 | int did_vmalloc_branch = 0; | |
897 | ||
898 | single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd); | |
1da177e4 | 899 | |
e30ec452 | 900 | uasm_l_vmalloc(l, *p); |
1da177e4 | 901 | |
2c8c53e2 | 902 | if (mode != not_refill && check_for_high_segbits) { |
1ec56329 DD |
903 | if (single_insn_swpd) { |
904 | uasm_il_bltz(p, r, bvaddr, label_vmalloc_done); | |
905 | uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); | |
906 | did_vmalloc_branch = 1; | |
907 | /* fall through */ | |
908 | } else { | |
909 | uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault); | |
910 | } | |
911 | } | |
912 | if (!did_vmalloc_branch) { | |
913 | if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) { | |
914 | uasm_il_b(p, r, label_vmalloc_done); | |
915 | uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); | |
916 | } else { | |
917 | UASM_i_LA_mostly(p, ptr, swpd); | |
918 | uasm_il_b(p, r, label_vmalloc_done); | |
919 | if (uasm_in_compat_space_p(swpd)) | |
920 | uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd)); | |
921 | else | |
922 | uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); | |
923 | } | |
924 | } | |
2c8c53e2 | 925 | if (mode != not_refill && check_for_high_segbits) { |
1ec56329 DD |
926 | uasm_l_large_segbits_fault(l, *p); |
927 | /* | |
928 | * We get here if we are an xsseg address, or if we are | |
929 | * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary. | |
930 | * | |
931 | * Ignoring xsseg (assume disabled so would generate | |
932 | * (address errors?), the only remaining possibility | |
933 | * is the upper xuseg addresses. On processors with | |
934 | * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these | |
935 | * addresses would have taken an address error. We try | |
936 | * to mimic that here by taking a load/istream page | |
937 | * fault. | |
938 | */ | |
939 | UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0); | |
940 | uasm_i_jr(p, ptr); | |
2c8c53e2 DD |
941 | |
942 | if (mode == refill_scratch) { | |
0e6ecc1a | 943 | if (scratch_reg >= 0) |
7777b939 | 944 | UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); |
2c8c53e2 DD |
945 | else |
946 | UASM_i_LW(p, 1, scratchpad_offset(0), 0); | |
947 | } else { | |
948 | uasm_i_nop(p); | |
949 | } | |
1da177e4 LT |
950 | } |
951 | } | |
952 | ||
875d43e7 | 953 | #else /* !CONFIG_64BIT */ |
1da177e4 LT |
954 | |
955 | /* | |
956 | * TMP and PTR are scratch. | |
957 | * TMP will be clobbered, PTR will hold the pgd entry. | |
958 | */ | |
234fcd14 | 959 | static void __cpuinit __maybe_unused |
1da177e4 LT |
960 | build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) |
961 | { | |
962 | long pgdc = (long)pgd_current; | |
963 | ||
964 | /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ | |
965 | #ifdef CONFIG_SMP | |
70342287 | 966 | #ifdef CONFIG_MIPS_MT_SMTC |
41c594ab RB |
967 | /* |
968 | * SMTC uses TCBind value as "CPU" index | |
969 | */ | |
e30ec452 TS |
970 | uasm_i_mfc0(p, ptr, C0_TCBIND); |
971 | UASM_i_LA_mostly(p, tmp, pgdc); | |
972 | uasm_i_srl(p, ptr, ptr, 19); | |
41c594ab RB |
973 | #else |
974 | /* | |
975 | * smp_processor_id() << 3 is stored in CONTEXT. | |
70342287 | 976 | */ |
e30ec452 TS |
977 | uasm_i_mfc0(p, ptr, C0_CONTEXT); |
978 | UASM_i_LA_mostly(p, tmp, pgdc); | |
979 | uasm_i_srl(p, ptr, ptr, 23); | |
41c594ab | 980 | #endif |
e30ec452 | 981 | uasm_i_addu(p, ptr, tmp, ptr); |
1da177e4 | 982 | #else |
e30ec452 | 983 | UASM_i_LA_mostly(p, ptr, pgdc); |
1da177e4 | 984 | #endif |
e30ec452 TS |
985 | uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ |
986 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); | |
987 | uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ | |
988 | uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); | |
989 | uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
1da177e4 LT |
990 | } |
991 | ||
875d43e7 | 992 | #endif /* !CONFIG_64BIT */ |
1da177e4 | 993 | |
234fcd14 | 994 | static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx) |
1da177e4 | 995 | { |
242954b5 | 996 | unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; |
1da177e4 LT |
997 | unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); |
998 | ||
10cc3529 | 999 | switch (current_cpu_type()) { |
1da177e4 LT |
1000 | case CPU_VR41XX: |
1001 | case CPU_VR4111: | |
1002 | case CPU_VR4121: | |
1003 | case CPU_VR4122: | |
1004 | case CPU_VR4131: | |
1005 | case CPU_VR4181: | |
1006 | case CPU_VR4181A: | |
1007 | case CPU_VR4133: | |
1008 | shift += 2; | |
1009 | break; | |
1010 | ||
1011 | default: | |
1012 | break; | |
1013 | } | |
1014 | ||
1015 | if (shift) | |
e30ec452 TS |
1016 | UASM_i_SRL(p, ctx, ctx, shift); |
1017 | uasm_i_andi(p, ctx, ctx, mask); | |
1da177e4 LT |
1018 | } |
1019 | ||
234fcd14 | 1020 | static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) |
1da177e4 LT |
1021 | { |
1022 | /* | |
1023 | * Bug workaround for the Nevada. It seems as if under certain | |
1024 | * circumstances the move from cp0_context might produce a | |
1025 | * bogus result when the mfc0 instruction and its consumer are | |
1026 | * in a different cacheline or a load instruction, probably any | |
1027 | * memory reference, is between them. | |
1028 | */ | |
10cc3529 | 1029 | switch (current_cpu_type()) { |
1da177e4 | 1030 | case CPU_NEVADA: |
e30ec452 | 1031 | UASM_i_LW(p, ptr, 0, ptr); |
1da177e4 LT |
1032 | GET_CONTEXT(p, tmp); /* get context reg */ |
1033 | break; | |
1034 | ||
1035 | default: | |
1036 | GET_CONTEXT(p, tmp); /* get context reg */ | |
e30ec452 | 1037 | UASM_i_LW(p, ptr, 0, ptr); |
1da177e4 LT |
1038 | break; |
1039 | } | |
1040 | ||
1041 | build_adjust_context(p, tmp); | |
e30ec452 | 1042 | UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ |
1da177e4 LT |
1043 | } |
1044 | ||
234fcd14 | 1045 | static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, |
1da177e4 LT |
1046 | unsigned int ptep) |
1047 | { | |
1048 | /* | |
1049 | * 64bit address support (36bit on a 32bit CPU) in a 32bit | |
1050 | * Kernel is a special case. Only a few CPUs use it. | |
1051 | */ | |
1052 | #ifdef CONFIG_64BIT_PHYS_ADDR | |
1053 | if (cpu_has_64bits) { | |
e30ec452 TS |
1054 | uasm_i_ld(p, tmp, 0, ptep); /* get even pte */ |
1055 | uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ | |
05857c64 | 1056 | if (cpu_has_rixi) { |
748e787e | 1057 | UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); |
6dd9344c | 1058 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ |
748e787e | 1059 | UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); |
6dd9344c | 1060 | } else { |
3be6022c | 1061 | uasm_i_dsrl_safe(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */ |
6dd9344c | 1062 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ |
3be6022c | 1063 | uasm_i_dsrl_safe(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */ |
6dd9344c | 1064 | } |
9b8c3891 | 1065 | UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ |
1da177e4 LT |
1066 | } else { |
1067 | int pte_off_even = sizeof(pte_t) / 2; | |
1068 | int pte_off_odd = pte_off_even + sizeof(pte_t); | |
1069 | ||
1070 | /* The pte entries are pre-shifted */ | |
e30ec452 | 1071 | uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */ |
9b8c3891 | 1072 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ |
e30ec452 | 1073 | uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */ |
9b8c3891 | 1074 | UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ |
1da177e4 LT |
1075 | } |
1076 | #else | |
e30ec452 TS |
1077 | UASM_i_LW(p, tmp, 0, ptep); /* get even pte */ |
1078 | UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ | |
1da177e4 LT |
1079 | if (r45k_bvahwbug()) |
1080 | build_tlb_probe_entry(p); | |
05857c64 | 1081 | if (cpu_has_rixi) { |
748e787e | 1082 | UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); |
6dd9344c DD |
1083 | if (r4k_250MHZhwbug()) |
1084 | UASM_i_MTC0(p, 0, C0_ENTRYLO0); | |
1085 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ | |
748e787e | 1086 | UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); |
6dd9344c DD |
1087 | } else { |
1088 | UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */ | |
1089 | if (r4k_250MHZhwbug()) | |
1090 | UASM_i_MTC0(p, 0, C0_ENTRYLO0); | |
1091 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ | |
1092 | UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */ | |
1093 | if (r45k_bvahwbug()) | |
1094 | uasm_i_mfc0(p, tmp, C0_INDEX); | |
1095 | } | |
1da177e4 | 1096 | if (r4k_250MHZhwbug()) |
9b8c3891 DD |
1097 | UASM_i_MTC0(p, 0, C0_ENTRYLO1); |
1098 | UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ | |
1da177e4 LT |
1099 | #endif |
1100 | } | |
1101 | ||
2c8c53e2 DD |
1102 | struct mips_huge_tlb_info { |
1103 | int huge_pte; | |
1104 | int restore_scratch; | |
1105 | }; | |
1106 | ||
1107 | static struct mips_huge_tlb_info __cpuinit | |
1108 | build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, | |
1109 | struct uasm_reloc **r, unsigned int tmp, | |
7777b939 | 1110 | unsigned int ptr, int c0_scratch_reg) |
2c8c53e2 DD |
1111 | { |
1112 | struct mips_huge_tlb_info rv; | |
1113 | unsigned int even, odd; | |
1114 | int vmalloc_branch_delay_filled = 0; | |
1115 | const int scratch = 1; /* Our extra working register */ | |
1116 | ||
1117 | rv.huge_pte = scratch; | |
1118 | rv.restore_scratch = 0; | |
1119 | ||
1120 | if (check_for_high_segbits) { | |
1121 | UASM_i_MFC0(p, tmp, C0_BADVADDR); | |
1122 | ||
1123 | if (pgd_reg != -1) | |
7777b939 | 1124 | UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); |
2c8c53e2 DD |
1125 | else |
1126 | UASM_i_MFC0(p, ptr, C0_CONTEXT); | |
1127 | ||
7777b939 J |
1128 | if (c0_scratch_reg >= 0) |
1129 | UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); | |
2c8c53e2 DD |
1130 | else |
1131 | UASM_i_SW(p, scratch, scratchpad_offset(0), 0); | |
1132 | ||
1133 | uasm_i_dsrl_safe(p, scratch, tmp, | |
1134 | PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); | |
1135 | uasm_il_bnez(p, r, scratch, label_vmalloc); | |
1136 | ||
1137 | if (pgd_reg == -1) { | |
1138 | vmalloc_branch_delay_filled = 1; | |
1139 | /* Clear lower 23 bits of context. */ | |
1140 | uasm_i_dins(p, ptr, 0, 0, 23); | |
1141 | } | |
1142 | } else { | |
1143 | if (pgd_reg != -1) | |
7777b939 | 1144 | UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); |
2c8c53e2 DD |
1145 | else |
1146 | UASM_i_MFC0(p, ptr, C0_CONTEXT); | |
1147 | ||
1148 | UASM_i_MFC0(p, tmp, C0_BADVADDR); | |
1149 | ||
7777b939 J |
1150 | if (c0_scratch_reg >= 0) |
1151 | UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); | |
2c8c53e2 DD |
1152 | else |
1153 | UASM_i_SW(p, scratch, scratchpad_offset(0), 0); | |
1154 | ||
1155 | if (pgd_reg == -1) | |
1156 | /* Clear lower 23 bits of context. */ | |
1157 | uasm_i_dins(p, ptr, 0, 0, 23); | |
1158 | ||
1159 | uasm_il_bltz(p, r, tmp, label_vmalloc); | |
1160 | } | |
1161 | ||
1162 | if (pgd_reg == -1) { | |
1163 | vmalloc_branch_delay_filled = 1; | |
70342287 | 1164 | /* 1 0 1 0 1 << 6 xkphys cached */ |
2c8c53e2 DD |
1165 | uasm_i_ori(p, ptr, ptr, 0x540); |
1166 | uasm_i_drotr(p, ptr, ptr, 11); | |
1167 | } | |
1168 | ||
1169 | #ifdef __PAGETABLE_PMD_FOLDED | |
1170 | #define LOC_PTEP scratch | |
1171 | #else | |
1172 | #define LOC_PTEP ptr | |
1173 | #endif | |
1174 | ||
1175 | if (!vmalloc_branch_delay_filled) | |
1176 | /* get pgd offset in bytes */ | |
1177 | uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); | |
1178 | ||
1179 | uasm_l_vmalloc_done(l, *p); | |
1180 | ||
1181 | /* | |
70342287 RB |
1182 | * tmp ptr |
1183 | * fall-through case = badvaddr *pgd_current | |
1184 | * vmalloc case = badvaddr swapper_pg_dir | |
2c8c53e2 DD |
1185 | */ |
1186 | ||
1187 | if (vmalloc_branch_delay_filled) | |
1188 | /* get pgd offset in bytes */ | |
1189 | uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); | |
1190 | ||
1191 | #ifdef __PAGETABLE_PMD_FOLDED | |
1192 | GET_CONTEXT(p, tmp); /* get context reg */ | |
1193 | #endif | |
1194 | uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3); | |
1195 | ||
1196 | if (use_lwx_insns()) { | |
1197 | UASM_i_LWX(p, LOC_PTEP, scratch, ptr); | |
1198 | } else { | |
1199 | uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */ | |
1200 | uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */ | |
1201 | } | |
1202 | ||
1203 | #ifndef __PAGETABLE_PMD_FOLDED | |
1204 | /* get pmd offset in bytes */ | |
1205 | uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3); | |
1206 | uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3); | |
1207 | GET_CONTEXT(p, tmp); /* get context reg */ | |
1208 | ||
1209 | if (use_lwx_insns()) { | |
1210 | UASM_i_LWX(p, scratch, scratch, ptr); | |
1211 | } else { | |
1212 | uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */ | |
1213 | UASM_i_LW(p, scratch, 0, ptr); | |
1214 | } | |
1215 | #endif | |
1216 | /* Adjust the context during the load latency. */ | |
1217 | build_adjust_context(p, tmp); | |
1218 | ||
aa1762f4 | 1219 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
2c8c53e2 DD |
1220 | uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update); |
1221 | /* | |
1222 | * The in the LWX case we don't want to do the load in the | |
70342287 | 1223 | * delay slot. It cannot issue in the same cycle and may be |
2c8c53e2 DD |
1224 | * speculative and unneeded. |
1225 | */ | |
1226 | if (use_lwx_insns()) | |
1227 | uasm_i_nop(p); | |
aa1762f4 | 1228 | #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ |
2c8c53e2 DD |
1229 | |
1230 | ||
1231 | /* build_update_entries */ | |
1232 | if (use_lwx_insns()) { | |
1233 | even = ptr; | |
1234 | odd = tmp; | |
1235 | UASM_i_LWX(p, even, scratch, tmp); | |
1236 | UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t)); | |
1237 | UASM_i_LWX(p, odd, scratch, tmp); | |
1238 | } else { | |
1239 | UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */ | |
1240 | even = tmp; | |
1241 | odd = ptr; | |
1242 | UASM_i_LW(p, even, 0, ptr); /* get even pte */ | |
1243 | UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */ | |
1244 | } | |
05857c64 | 1245 | if (cpu_has_rixi) { |
748e787e | 1246 | uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL)); |
2c8c53e2 | 1247 | UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ |
748e787e | 1248 | uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL)); |
2c8c53e2 DD |
1249 | } else { |
1250 | uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL)); | |
1251 | UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ | |
1252 | uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL)); | |
1253 | } | |
1254 | UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */ | |
1255 | ||
7777b939 J |
1256 | if (c0_scratch_reg >= 0) { |
1257 | UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg); | |
2c8c53e2 DD |
1258 | build_tlb_write_entry(p, l, r, tlb_random); |
1259 | uasm_l_leave(l, *p); | |
1260 | rv.restore_scratch = 1; | |
1261 | } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) { | |
1262 | build_tlb_write_entry(p, l, r, tlb_random); | |
1263 | uasm_l_leave(l, *p); | |
1264 | UASM_i_LW(p, scratch, scratchpad_offset(0), 0); | |
1265 | } else { | |
1266 | UASM_i_LW(p, scratch, scratchpad_offset(0), 0); | |
1267 | build_tlb_write_entry(p, l, r, tlb_random); | |
1268 | uasm_l_leave(l, *p); | |
1269 | rv.restore_scratch = 1; | |
1270 | } | |
1271 | ||
1272 | uasm_i_eret(p); /* return from trap */ | |
1273 | ||
1274 | return rv; | |
1275 | } | |
1276 | ||
e6f72d3a DD |
1277 | /* |
1278 | * For a 64-bit kernel, we are using the 64-bit XTLB refill exception | |
1279 | * because EXL == 0. If we wrap, we can also use the 32 instruction | |
1280 | * slots before the XTLB refill exception handler which belong to the | |
1281 | * unused TLB refill exception. | |
1282 | */ | |
1283 | #define MIPS64_REFILL_INSNS 32 | |
1284 | ||
234fcd14 | 1285 | static void __cpuinit build_r4000_tlb_refill_handler(void) |
1da177e4 LT |
1286 | { |
1287 | u32 *p = tlb_handler; | |
e30ec452 TS |
1288 | struct uasm_label *l = labels; |
1289 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1290 | u32 *f; |
1291 | unsigned int final_len; | |
4a9040f4 RB |
1292 | struct mips_huge_tlb_info htlb_info __maybe_unused; |
1293 | enum vmalloc64_mode vmalloc_mode __maybe_unused; | |
1da177e4 LT |
1294 | |
1295 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
1296 | memset(labels, 0, sizeof(labels)); | |
1297 | memset(relocs, 0, sizeof(relocs)); | |
1298 | memset(final_handler, 0, sizeof(final_handler)); | |
1299 | ||
0e6ecc1a | 1300 | if ((scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) { |
2c8c53e2 DD |
1301 | htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1, |
1302 | scratch_reg); | |
1303 | vmalloc_mode = refill_scratch; | |
1304 | } else { | |
1305 | htlb_info.huge_pte = K0; | |
1306 | htlb_info.restore_scratch = 0; | |
1307 | vmalloc_mode = refill_noscratch; | |
1308 | /* | |
1309 | * create the plain linear handler | |
1310 | */ | |
1311 | if (bcm1250_m3_war()) { | |
1312 | unsigned int segbits = 44; | |
1313 | ||
1314 | uasm_i_dmfc0(&p, K0, C0_BADVADDR); | |
1315 | uasm_i_dmfc0(&p, K1, C0_ENTRYHI); | |
1316 | uasm_i_xor(&p, K0, K0, K1); | |
1317 | uasm_i_dsrl_safe(&p, K1, K0, 62); | |
1318 | uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); | |
1319 | uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); | |
1320 | uasm_i_or(&p, K0, K0, K1); | |
1321 | uasm_il_bnez(&p, &r, K0, label_leave); | |
1322 | /* No need for uasm_i_nop */ | |
1323 | } | |
1da177e4 | 1324 | |
875d43e7 | 1325 | #ifdef CONFIG_64BIT |
2c8c53e2 | 1326 | build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ |
1da177e4 | 1327 | #else |
2c8c53e2 | 1328 | build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ |
1da177e4 LT |
1329 | #endif |
1330 | ||
aa1762f4 | 1331 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
2c8c53e2 | 1332 | build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update); |
fd062c84 DD |
1333 | #endif |
1334 | ||
2c8c53e2 DD |
1335 | build_get_ptep(&p, K0, K1); |
1336 | build_update_entries(&p, K0, K1); | |
1337 | build_tlb_write_entry(&p, &l, &r, tlb_random); | |
1338 | uasm_l_leave(&l, p); | |
1339 | uasm_i_eret(&p); /* return from trap */ | |
1340 | } | |
aa1762f4 | 1341 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 | 1342 | uasm_l_tlb_huge_update(&l, p); |
2c8c53e2 DD |
1343 | build_huge_update_entries(&p, htlb_info.huge_pte, K1); |
1344 | build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random, | |
1345 | htlb_info.restore_scratch); | |
fd062c84 DD |
1346 | #endif |
1347 | ||
875d43e7 | 1348 | #ifdef CONFIG_64BIT |
2c8c53e2 | 1349 | build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode); |
1da177e4 LT |
1350 | #endif |
1351 | ||
1352 | /* | |
1353 | * Overflow check: For the 64bit handler, we need at least one | |
1354 | * free instruction slot for the wrap-around branch. In worst | |
1355 | * case, if the intended insertion point is a delay slot, we | |
4b3f686d | 1356 | * need three, with the second nop'ed and the third being |
1da177e4 LT |
1357 | * unused. |
1358 | */ | |
2a21c730 FZ |
1359 | /* Loongson2 ebase is different than r4k, we have more space */ |
1360 | #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) | |
1da177e4 LT |
1361 | if ((p - tlb_handler) > 64) |
1362 | panic("TLB refill handler space exceeded"); | |
1363 | #else | |
e6f72d3a DD |
1364 | if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1) |
1365 | || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3) | |
1366 | && uasm_insn_has_bdelay(relocs, | |
1367 | tlb_handler + MIPS64_REFILL_INSNS - 3))) | |
1da177e4 LT |
1368 | panic("TLB refill handler space exceeded"); |
1369 | #endif | |
1370 | ||
1371 | /* | |
1372 | * Now fold the handler in the TLB refill handler space. | |
1373 | */ | |
2a21c730 | 1374 | #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) |
1da177e4 LT |
1375 | f = final_handler; |
1376 | /* Simplest case, just copy the handler. */ | |
e30ec452 | 1377 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); |
1da177e4 | 1378 | final_len = p - tlb_handler; |
875d43e7 | 1379 | #else /* CONFIG_64BIT */ |
e6f72d3a DD |
1380 | f = final_handler + MIPS64_REFILL_INSNS; |
1381 | if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) { | |
1da177e4 | 1382 | /* Just copy the handler. */ |
e30ec452 | 1383 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); |
1da177e4 LT |
1384 | final_len = p - tlb_handler; |
1385 | } else { | |
aa1762f4 | 1386 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 | 1387 | const enum label_id ls = label_tlb_huge_update; |
95affdda DD |
1388 | #else |
1389 | const enum label_id ls = label_vmalloc; | |
1390 | #endif | |
1391 | u32 *split; | |
1392 | int ov = 0; | |
1393 | int i; | |
1394 | ||
1395 | for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++) | |
1396 | ; | |
1397 | BUG_ON(i == ARRAY_SIZE(labels)); | |
1398 | split = labels[i].addr; | |
1da177e4 LT |
1399 | |
1400 | /* | |
95affdda | 1401 | * See if we have overflown one way or the other. |
1da177e4 | 1402 | */ |
95affdda DD |
1403 | if (split > tlb_handler + MIPS64_REFILL_INSNS || |
1404 | split < p - MIPS64_REFILL_INSNS) | |
1405 | ov = 1; | |
1406 | ||
1407 | if (ov) { | |
1408 | /* | |
1409 | * Split two instructions before the end. One | |
1410 | * for the branch and one for the instruction | |
1411 | * in the delay slot. | |
1412 | */ | |
1413 | split = tlb_handler + MIPS64_REFILL_INSNS - 2; | |
1414 | ||
1415 | /* | |
1416 | * If the branch would fall in a delay slot, | |
1417 | * we must back up an additional instruction | |
1418 | * so that it is no longer in a delay slot. | |
1419 | */ | |
1420 | if (uasm_insn_has_bdelay(relocs, split - 1)) | |
1421 | split--; | |
1422 | } | |
1da177e4 | 1423 | /* Copy first part of the handler. */ |
e30ec452 | 1424 | uasm_copy_handler(relocs, labels, tlb_handler, split, f); |
1da177e4 LT |
1425 | f += split - tlb_handler; |
1426 | ||
95affdda DD |
1427 | if (ov) { |
1428 | /* Insert branch. */ | |
1429 | uasm_l_split(&l, final_handler); | |
1430 | uasm_il_b(&f, &r, label_split); | |
1431 | if (uasm_insn_has_bdelay(relocs, split)) | |
1432 | uasm_i_nop(&f); | |
1433 | else { | |
1434 | uasm_copy_handler(relocs, labels, | |
1435 | split, split + 1, f); | |
1436 | uasm_move_labels(labels, f, f + 1, -1); | |
1437 | f++; | |
1438 | split++; | |
1439 | } | |
1da177e4 LT |
1440 | } |
1441 | ||
1442 | /* Copy the rest of the handler. */ | |
e30ec452 | 1443 | uasm_copy_handler(relocs, labels, split, p, final_handler); |
e6f72d3a DD |
1444 | final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) + |
1445 | (p - split); | |
1da177e4 | 1446 | } |
875d43e7 | 1447 | #endif /* CONFIG_64BIT */ |
1da177e4 | 1448 | |
e30ec452 TS |
1449 | uasm_resolve_relocs(relocs, labels); |
1450 | pr_debug("Wrote TLB refill handler (%u instructions).\n", | |
1451 | final_len); | |
1da177e4 | 1452 | |
91b05e67 | 1453 | memcpy((void *)ebase, final_handler, 0x100); |
92b1e6a6 | 1454 | |
a2c763e0 | 1455 | dump_handler("r4000_tlb_refill", (u32 *)ebase, 64); |
1da177e4 LT |
1456 | } |
1457 | ||
1da177e4 LT |
1458 | /* |
1459 | * 128 instructions for the fastpath handler is generous and should | |
1460 | * never be exceeded. | |
1461 | */ | |
1462 | #define FASTPATH_SIZE 128 | |
1463 | ||
cbdbe07f FBH |
1464 | u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned; |
1465 | u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned; | |
1466 | u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned; | |
3d8bfdd0 | 1467 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
0bfbf6a2 | 1468 | u32 tlbmiss_handler_setup_pgd_array[16] __cacheline_aligned; |
3d8bfdd0 DD |
1469 | |
1470 | static void __cpuinit build_r4000_setup_pgd(void) | |
1471 | { | |
1472 | const int a0 = 4; | |
1473 | const int a1 = 5; | |
0bfbf6a2 | 1474 | u32 *p = tlbmiss_handler_setup_pgd_array; |
3d8bfdd0 DD |
1475 | struct uasm_label *l = labels; |
1476 | struct uasm_reloc *r = relocs; | |
1477 | ||
0bfbf6a2 | 1478 | memset(tlbmiss_handler_setup_pgd_array, 0, sizeof(tlbmiss_handler_setup_pgd_array)); |
3d8bfdd0 DD |
1479 | memset(labels, 0, sizeof(labels)); |
1480 | memset(relocs, 0, sizeof(relocs)); | |
1481 | ||
1482 | pgd_reg = allocate_kscratch(); | |
1483 | ||
1484 | if (pgd_reg == -1) { | |
1485 | /* PGD << 11 in c0_Context */ | |
1486 | /* | |
1487 | * If it is a ckseg0 address, convert to a physical | |
1488 | * address. Shifting right by 29 and adding 4 will | |
1489 | * result in zero for these addresses. | |
1490 | * | |
1491 | */ | |
1492 | UASM_i_SRA(&p, a1, a0, 29); | |
1493 | UASM_i_ADDIU(&p, a1, a1, 4); | |
1494 | uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1); | |
1495 | uasm_i_nop(&p); | |
1496 | uasm_i_dinsm(&p, a0, 0, 29, 64 - 29); | |
1497 | uasm_l_tlbl_goaround1(&l, p); | |
1498 | UASM_i_SLL(&p, a0, a0, 11); | |
1499 | uasm_i_jr(&p, 31); | |
1500 | UASM_i_MTC0(&p, a0, C0_CONTEXT); | |
1501 | } else { | |
1502 | /* PGD in c0_KScratch */ | |
1503 | uasm_i_jr(&p, 31); | |
7777b939 | 1504 | UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); |
3d8bfdd0 | 1505 | } |
0bfbf6a2 RB |
1506 | if (p - tlbmiss_handler_setup_pgd_array > ARRAY_SIZE(tlbmiss_handler_setup_pgd_array)) |
1507 | panic("tlbmiss_handler_setup_pgd_array space exceeded"); | |
3d8bfdd0 | 1508 | uasm_resolve_relocs(relocs, labels); |
0bfbf6a2 RB |
1509 | pr_debug("Wrote tlbmiss_handler_setup_pgd_array (%u instructions).\n", |
1510 | (unsigned int)(p - tlbmiss_handler_setup_pgd_array)); | |
3d8bfdd0 | 1511 | |
a2c763e0 | 1512 | dump_handler("tlbmiss_handler", |
0bfbf6a2 RB |
1513 | tlbmiss_handler_setup_pgd_array, |
1514 | ARRAY_SIZE(tlbmiss_handler_setup_pgd_array)); | |
3d8bfdd0 DD |
1515 | } |
1516 | #endif | |
1da177e4 | 1517 | |
234fcd14 | 1518 | static void __cpuinit |
bd1437e4 | 1519 | iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) |
1da177e4 LT |
1520 | { |
1521 | #ifdef CONFIG_SMP | |
1522 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1523 | if (cpu_has_64bits) | |
e30ec452 | 1524 | uasm_i_lld(p, pte, 0, ptr); |
1da177e4 LT |
1525 | else |
1526 | # endif | |
e30ec452 | 1527 | UASM_i_LL(p, pte, 0, ptr); |
1da177e4 LT |
1528 | #else |
1529 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1530 | if (cpu_has_64bits) | |
e30ec452 | 1531 | uasm_i_ld(p, pte, 0, ptr); |
1da177e4 LT |
1532 | else |
1533 | # endif | |
e30ec452 | 1534 | UASM_i_LW(p, pte, 0, ptr); |
1da177e4 LT |
1535 | #endif |
1536 | } | |
1537 | ||
234fcd14 | 1538 | static void __cpuinit |
e30ec452 | 1539 | iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, |
63b2d2f4 | 1540 | unsigned int mode) |
1da177e4 | 1541 | { |
63b2d2f4 TS |
1542 | #ifdef CONFIG_64BIT_PHYS_ADDR |
1543 | unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); | |
1544 | #endif | |
1545 | ||
e30ec452 | 1546 | uasm_i_ori(p, pte, pte, mode); |
1da177e4 LT |
1547 | #ifdef CONFIG_SMP |
1548 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1549 | if (cpu_has_64bits) | |
e30ec452 | 1550 | uasm_i_scd(p, pte, 0, ptr); |
1da177e4 LT |
1551 | else |
1552 | # endif | |
e30ec452 | 1553 | UASM_i_SC(p, pte, 0, ptr); |
1da177e4 LT |
1554 | |
1555 | if (r10000_llsc_war()) | |
e30ec452 | 1556 | uasm_il_beqzl(p, r, pte, label_smp_pgtable_change); |
1da177e4 | 1557 | else |
e30ec452 | 1558 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); |
1da177e4 LT |
1559 | |
1560 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1561 | if (!cpu_has_64bits) { | |
e30ec452 TS |
1562 | /* no uasm_i_nop needed */ |
1563 | uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr); | |
1564 | uasm_i_ori(p, pte, pte, hwmode); | |
1565 | uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr); | |
1566 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); | |
1567 | /* no uasm_i_nop needed */ | |
1568 | uasm_i_lw(p, pte, 0, ptr); | |
1da177e4 | 1569 | } else |
e30ec452 | 1570 | uasm_i_nop(p); |
1da177e4 | 1571 | # else |
e30ec452 | 1572 | uasm_i_nop(p); |
1da177e4 LT |
1573 | # endif |
1574 | #else | |
1575 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1576 | if (cpu_has_64bits) | |
e30ec452 | 1577 | uasm_i_sd(p, pte, 0, ptr); |
1da177e4 LT |
1578 | else |
1579 | # endif | |
e30ec452 | 1580 | UASM_i_SW(p, pte, 0, ptr); |
1da177e4 LT |
1581 | |
1582 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1583 | if (!cpu_has_64bits) { | |
e30ec452 TS |
1584 | uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr); |
1585 | uasm_i_ori(p, pte, pte, hwmode); | |
1586 | uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr); | |
1587 | uasm_i_lw(p, pte, 0, ptr); | |
1da177e4 LT |
1588 | } |
1589 | # endif | |
1590 | #endif | |
1591 | } | |
1592 | ||
1593 | /* | |
1594 | * Check if PTE is present, if not then jump to LABEL. PTR points to | |
1595 | * the page table where this PTE is located, PTE will be re-loaded | |
1596 | * with it's original value. | |
1597 | */ | |
234fcd14 | 1598 | static void __cpuinit |
bd1437e4 | 1599 | build_pte_present(u32 **p, struct uasm_reloc **r, |
bf28607f | 1600 | int pte, int ptr, int scratch, enum label_id lid) |
1da177e4 | 1601 | { |
bf28607f DD |
1602 | int t = scratch >= 0 ? scratch : pte; |
1603 | ||
05857c64 | 1604 | if (cpu_has_rixi) { |
cc33ae43 DD |
1605 | if (use_bbit_insns()) { |
1606 | uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); | |
1607 | uasm_i_nop(p); | |
1608 | } else { | |
bf28607f DD |
1609 | uasm_i_andi(p, t, pte, _PAGE_PRESENT); |
1610 | uasm_il_beqz(p, r, t, lid); | |
1611 | if (pte == t) | |
1612 | /* You lose the SMP race :-(*/ | |
1613 | iPTE_LW(p, pte, ptr); | |
cc33ae43 | 1614 | } |
6dd9344c | 1615 | } else { |
bf28607f DD |
1616 | uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_READ); |
1617 | uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_READ); | |
1618 | uasm_il_bnez(p, r, t, lid); | |
1619 | if (pte == t) | |
1620 | /* You lose the SMP race :-(*/ | |
1621 | iPTE_LW(p, pte, ptr); | |
6dd9344c | 1622 | } |
1da177e4 LT |
1623 | } |
1624 | ||
1625 | /* Make PTE valid, store result in PTR. */ | |
234fcd14 | 1626 | static void __cpuinit |
e30ec452 | 1627 | build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte, |
1da177e4 LT |
1628 | unsigned int ptr) |
1629 | { | |
63b2d2f4 TS |
1630 | unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; |
1631 | ||
1632 | iPTE_SW(p, r, pte, ptr, mode); | |
1da177e4 LT |
1633 | } |
1634 | ||
1635 | /* | |
1636 | * Check if PTE can be written to, if not branch to LABEL. Regardless | |
1637 | * restore PTE with value from PTR when done. | |
1638 | */ | |
234fcd14 | 1639 | static void __cpuinit |
bd1437e4 | 1640 | build_pte_writable(u32 **p, struct uasm_reloc **r, |
bf28607f DD |
1641 | unsigned int pte, unsigned int ptr, int scratch, |
1642 | enum label_id lid) | |
1da177e4 | 1643 | { |
bf28607f DD |
1644 | int t = scratch >= 0 ? scratch : pte; |
1645 | ||
1646 | uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_WRITE); | |
1647 | uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_WRITE); | |
1648 | uasm_il_bnez(p, r, t, lid); | |
1649 | if (pte == t) | |
1650 | /* You lose the SMP race :-(*/ | |
cc33ae43 | 1651 | iPTE_LW(p, pte, ptr); |
bf28607f DD |
1652 | else |
1653 | uasm_i_nop(p); | |
1da177e4 LT |
1654 | } |
1655 | ||
1656 | /* Make PTE writable, update software status bits as well, then store | |
1657 | * at PTR. | |
1658 | */ | |
234fcd14 | 1659 | static void __cpuinit |
e30ec452 | 1660 | build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte, |
1da177e4 LT |
1661 | unsigned int ptr) |
1662 | { | |
63b2d2f4 TS |
1663 | unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID |
1664 | | _PAGE_DIRTY); | |
1665 | ||
1666 | iPTE_SW(p, r, pte, ptr, mode); | |
1da177e4 LT |
1667 | } |
1668 | ||
1669 | /* | |
1670 | * Check if PTE can be modified, if not branch to LABEL. Regardless | |
1671 | * restore PTE with value from PTR when done. | |
1672 | */ | |
234fcd14 | 1673 | static void __cpuinit |
bd1437e4 | 1674 | build_pte_modifiable(u32 **p, struct uasm_reloc **r, |
bf28607f DD |
1675 | unsigned int pte, unsigned int ptr, int scratch, |
1676 | enum label_id lid) | |
1da177e4 | 1677 | { |
cc33ae43 DD |
1678 | if (use_bbit_insns()) { |
1679 | uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid); | |
1680 | uasm_i_nop(p); | |
1681 | } else { | |
bf28607f DD |
1682 | int t = scratch >= 0 ? scratch : pte; |
1683 | uasm_i_andi(p, t, pte, _PAGE_WRITE); | |
1684 | uasm_il_beqz(p, r, t, lid); | |
1685 | if (pte == t) | |
1686 | /* You lose the SMP race :-(*/ | |
1687 | iPTE_LW(p, pte, ptr); | |
cc33ae43 | 1688 | } |
1da177e4 LT |
1689 | } |
1690 | ||
82622284 | 1691 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
3d8bfdd0 DD |
1692 | |
1693 | ||
1da177e4 LT |
1694 | /* |
1695 | * R3000 style TLB load/store/modify handlers. | |
1696 | */ | |
1697 | ||
fded2e50 MR |
1698 | /* |
1699 | * This places the pte into ENTRYLO0 and writes it with tlbwi. | |
1700 | * Then it returns. | |
1701 | */ | |
234fcd14 | 1702 | static void __cpuinit |
fded2e50 | 1703 | build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) |
1da177e4 | 1704 | { |
e30ec452 TS |
1705 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ |
1706 | uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ | |
1707 | uasm_i_tlbwi(p); | |
1708 | uasm_i_jr(p, tmp); | |
1709 | uasm_i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1710 | } |
1711 | ||
1712 | /* | |
fded2e50 MR |
1713 | * This places the pte into ENTRYLO0 and writes it with tlbwi |
1714 | * or tlbwr as appropriate. This is because the index register | |
1715 | * may have the probe fail bit set as a result of a trap on a | |
1716 | * kseg2 access, i.e. without refill. Then it returns. | |
1da177e4 | 1717 | */ |
234fcd14 | 1718 | static void __cpuinit |
e30ec452 TS |
1719 | build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l, |
1720 | struct uasm_reloc **r, unsigned int pte, | |
1721 | unsigned int tmp) | |
1722 | { | |
1723 | uasm_i_mfc0(p, tmp, C0_INDEX); | |
1724 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ | |
1725 | uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ | |
1726 | uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */ | |
1727 | uasm_i_tlbwi(p); /* cp0 delay */ | |
1728 | uasm_i_jr(p, tmp); | |
1729 | uasm_i_rfe(p); /* branch delay */ | |
1730 | uasm_l_r3000_write_probe_fail(l, *p); | |
1731 | uasm_i_tlbwr(p); /* cp0 delay */ | |
1732 | uasm_i_jr(p, tmp); | |
1733 | uasm_i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1734 | } |
1735 | ||
234fcd14 | 1736 | static void __cpuinit |
1da177e4 LT |
1737 | build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, |
1738 | unsigned int ptr) | |
1739 | { | |
1740 | long pgdc = (long)pgd_current; | |
1741 | ||
e30ec452 TS |
1742 | uasm_i_mfc0(p, pte, C0_BADVADDR); |
1743 | uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */ | |
1744 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1745 | uasm_i_srl(p, pte, pte, 22); /* load delay */ | |
1746 | uasm_i_sll(p, pte, pte, 2); | |
1747 | uasm_i_addu(p, ptr, ptr, pte); | |
1748 | uasm_i_mfc0(p, pte, C0_CONTEXT); | |
1749 | uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */ | |
1750 | uasm_i_andi(p, pte, pte, 0xffc); /* load delay */ | |
1751 | uasm_i_addu(p, ptr, ptr, pte); | |
1752 | uasm_i_lw(p, pte, 0, ptr); | |
1753 | uasm_i_tlbp(p); /* load delay */ | |
1da177e4 LT |
1754 | } |
1755 | ||
234fcd14 | 1756 | static void __cpuinit build_r3000_tlb_load_handler(void) |
1da177e4 LT |
1757 | { |
1758 | u32 *p = handle_tlbl; | |
e30ec452 TS |
1759 | struct uasm_label *l = labels; |
1760 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1761 | |
1762 | memset(handle_tlbl, 0, sizeof(handle_tlbl)); | |
1763 | memset(labels, 0, sizeof(labels)); | |
1764 | memset(relocs, 0, sizeof(relocs)); | |
1765 | ||
1766 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
bf28607f | 1767 | build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl); |
e30ec452 | 1768 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1769 | build_make_valid(&p, &r, K0, K1); |
fded2e50 | 1770 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 | 1771 | |
e30ec452 TS |
1772 | uasm_l_nopage_tlbl(&l, p); |
1773 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); | |
1774 | uasm_i_nop(&p); | |
1da177e4 LT |
1775 | |
1776 | if ((p - handle_tlbl) > FASTPATH_SIZE) | |
1777 | panic("TLB load handler fastpath space exceeded"); | |
1778 | ||
e30ec452 TS |
1779 | uasm_resolve_relocs(relocs, labels); |
1780 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", | |
1781 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 1782 | |
a2c763e0 | 1783 | dump_handler("r3000_tlb_load", handle_tlbl, ARRAY_SIZE(handle_tlbl)); |
1da177e4 LT |
1784 | } |
1785 | ||
234fcd14 | 1786 | static void __cpuinit build_r3000_tlb_store_handler(void) |
1da177e4 LT |
1787 | { |
1788 | u32 *p = handle_tlbs; | |
e30ec452 TS |
1789 | struct uasm_label *l = labels; |
1790 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1791 | |
1792 | memset(handle_tlbs, 0, sizeof(handle_tlbs)); | |
1793 | memset(labels, 0, sizeof(labels)); | |
1794 | memset(relocs, 0, sizeof(relocs)); | |
1795 | ||
1796 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
bf28607f | 1797 | build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs); |
e30ec452 | 1798 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1799 | build_make_write(&p, &r, K0, K1); |
fded2e50 | 1800 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 | 1801 | |
e30ec452 TS |
1802 | uasm_l_nopage_tlbs(&l, p); |
1803 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1804 | uasm_i_nop(&p); | |
1da177e4 LT |
1805 | |
1806 | if ((p - handle_tlbs) > FASTPATH_SIZE) | |
1807 | panic("TLB store handler fastpath space exceeded"); | |
1808 | ||
e30ec452 TS |
1809 | uasm_resolve_relocs(relocs, labels); |
1810 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", | |
1811 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 1812 | |
a2c763e0 | 1813 | dump_handler("r3000_tlb_store", handle_tlbs, ARRAY_SIZE(handle_tlbs)); |
1da177e4 LT |
1814 | } |
1815 | ||
234fcd14 | 1816 | static void __cpuinit build_r3000_tlb_modify_handler(void) |
1da177e4 LT |
1817 | { |
1818 | u32 *p = handle_tlbm; | |
e30ec452 TS |
1819 | struct uasm_label *l = labels; |
1820 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1821 | |
1822 | memset(handle_tlbm, 0, sizeof(handle_tlbm)); | |
1823 | memset(labels, 0, sizeof(labels)); | |
1824 | memset(relocs, 0, sizeof(relocs)); | |
1825 | ||
1826 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
d954ffe3 | 1827 | build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm); |
e30ec452 | 1828 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1829 | build_make_write(&p, &r, K0, K1); |
fded2e50 | 1830 | build_r3000_pte_reload_tlbwi(&p, K0, K1); |
1da177e4 | 1831 | |
e30ec452 TS |
1832 | uasm_l_nopage_tlbm(&l, p); |
1833 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1834 | uasm_i_nop(&p); | |
1da177e4 LT |
1835 | |
1836 | if ((p - handle_tlbm) > FASTPATH_SIZE) | |
1837 | panic("TLB modify handler fastpath space exceeded"); | |
1838 | ||
e30ec452 TS |
1839 | uasm_resolve_relocs(relocs, labels); |
1840 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", | |
1841 | (unsigned int)(p - handle_tlbm)); | |
1da177e4 | 1842 | |
a2c763e0 | 1843 | dump_handler("r3000_tlb_modify", handle_tlbm, ARRAY_SIZE(handle_tlbm)); |
1da177e4 | 1844 | } |
82622284 | 1845 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ |
1da177e4 LT |
1846 | |
1847 | /* | |
1848 | * R4000 style TLB load/store/modify handlers. | |
1849 | */ | |
bf28607f | 1850 | static struct work_registers __cpuinit |
e30ec452 | 1851 | build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l, |
bf28607f | 1852 | struct uasm_reloc **r) |
1da177e4 | 1853 | { |
bf28607f DD |
1854 | struct work_registers wr = build_get_work_registers(p); |
1855 | ||
875d43e7 | 1856 | #ifdef CONFIG_64BIT |
bf28607f | 1857 | build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */ |
1da177e4 | 1858 | #else |
bf28607f | 1859 | build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */ |
1da177e4 LT |
1860 | #endif |
1861 | ||
aa1762f4 | 1862 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
1863 | /* |
1864 | * For huge tlb entries, pmd doesn't contain an address but | |
1865 | * instead contains the tlb pte. Check the PAGE_HUGE bit and | |
1866 | * see if we need to jump to huge tlb processing. | |
1867 | */ | |
bf28607f | 1868 | build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update); |
fd062c84 DD |
1869 | #endif |
1870 | ||
bf28607f DD |
1871 | UASM_i_MFC0(p, wr.r1, C0_BADVADDR); |
1872 | UASM_i_LW(p, wr.r2, 0, wr.r2); | |
1873 | UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); | |
1874 | uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2); | |
1875 | UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1); | |
1da177e4 LT |
1876 | |
1877 | #ifdef CONFIG_SMP | |
e30ec452 TS |
1878 | uasm_l_smp_pgtable_change(l, *p); |
1879 | #endif | |
bf28607f | 1880 | iPTE_LW(p, wr.r1, wr.r2); /* get even pte */ |
8df5beac MR |
1881 | if (!m4kc_tlbp_war()) |
1882 | build_tlb_probe_entry(p); | |
bf28607f | 1883 | return wr; |
1da177e4 LT |
1884 | } |
1885 | ||
234fcd14 | 1886 | static void __cpuinit |
e30ec452 TS |
1887 | build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, |
1888 | struct uasm_reloc **r, unsigned int tmp, | |
1da177e4 LT |
1889 | unsigned int ptr) |
1890 | { | |
e30ec452 TS |
1891 | uasm_i_ori(p, ptr, ptr, sizeof(pte_t)); |
1892 | uasm_i_xori(p, ptr, ptr, sizeof(pte_t)); | |
1da177e4 LT |
1893 | build_update_entries(p, tmp, ptr); |
1894 | build_tlb_write_entry(p, l, r, tlb_indexed); | |
e30ec452 | 1895 | uasm_l_leave(l, *p); |
bf28607f | 1896 | build_restore_work_registers(p); |
e30ec452 | 1897 | uasm_i_eret(p); /* return from trap */ |
1da177e4 | 1898 | |
875d43e7 | 1899 | #ifdef CONFIG_64BIT |
1ec56329 | 1900 | build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill); |
1da177e4 LT |
1901 | #endif |
1902 | } | |
1903 | ||
234fcd14 | 1904 | static void __cpuinit build_r4000_tlb_load_handler(void) |
1da177e4 LT |
1905 | { |
1906 | u32 *p = handle_tlbl; | |
e30ec452 TS |
1907 | struct uasm_label *l = labels; |
1908 | struct uasm_reloc *r = relocs; | |
bf28607f | 1909 | struct work_registers wr; |
1da177e4 LT |
1910 | |
1911 | memset(handle_tlbl, 0, sizeof(handle_tlbl)); | |
1912 | memset(labels, 0, sizeof(labels)); | |
1913 | memset(relocs, 0, sizeof(relocs)); | |
1914 | ||
1915 | if (bcm1250_m3_war()) { | |
3d45285d RB |
1916 | unsigned int segbits = 44; |
1917 | ||
1918 | uasm_i_dmfc0(&p, K0, C0_BADVADDR); | |
1919 | uasm_i_dmfc0(&p, K1, C0_ENTRYHI); | |
e30ec452 | 1920 | uasm_i_xor(&p, K0, K0, K1); |
3be6022c DD |
1921 | uasm_i_dsrl_safe(&p, K1, K0, 62); |
1922 | uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); | |
1923 | uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); | |
3d45285d | 1924 | uasm_i_or(&p, K0, K0, K1); |
e30ec452 TS |
1925 | uasm_il_bnez(&p, &r, K0, label_leave); |
1926 | /* No need for uasm_i_nop */ | |
1da177e4 LT |
1927 | } |
1928 | ||
bf28607f DD |
1929 | wr = build_r4000_tlbchange_handler_head(&p, &l, &r); |
1930 | build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); | |
8df5beac MR |
1931 | if (m4kc_tlbp_war()) |
1932 | build_tlb_probe_entry(&p); | |
6dd9344c | 1933 | |
05857c64 | 1934 | if (cpu_has_rixi) { |
6dd9344c DD |
1935 | /* |
1936 | * If the page is not _PAGE_VALID, RI or XI could not | |
1937 | * have triggered it. Skip the expensive test.. | |
1938 | */ | |
cc33ae43 | 1939 | if (use_bbit_insns()) { |
bf28607f | 1940 | uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), |
cc33ae43 DD |
1941 | label_tlbl_goaround1); |
1942 | } else { | |
bf28607f DD |
1943 | uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); |
1944 | uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1); | |
cc33ae43 | 1945 | } |
6dd9344c DD |
1946 | uasm_i_nop(&p); |
1947 | ||
1948 | uasm_i_tlbr(&p); | |
1949 | /* Examine entrylo 0 or 1 based on ptr. */ | |
cc33ae43 | 1950 | if (use_bbit_insns()) { |
bf28607f | 1951 | uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); |
cc33ae43 | 1952 | } else { |
bf28607f DD |
1953 | uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); |
1954 | uasm_i_beqz(&p, wr.r3, 8); | |
cc33ae43 | 1955 | } |
bf28607f DD |
1956 | /* load it in the delay slot*/ |
1957 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); | |
1958 | /* load it if ptr is odd */ | |
1959 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); | |
6dd9344c | 1960 | /* |
bf28607f | 1961 | * If the entryLo (now in wr.r3) is valid (bit 1), RI or |
6dd9344c DD |
1962 | * XI must have triggered it. |
1963 | */ | |
cc33ae43 | 1964 | if (use_bbit_insns()) { |
bf28607f DD |
1965 | uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl); |
1966 | uasm_i_nop(&p); | |
cc33ae43 DD |
1967 | uasm_l_tlbl_goaround1(&l, p); |
1968 | } else { | |
bf28607f DD |
1969 | uasm_i_andi(&p, wr.r3, wr.r3, 2); |
1970 | uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl); | |
1971 | uasm_i_nop(&p); | |
cc33ae43 | 1972 | } |
bf28607f | 1973 | uasm_l_tlbl_goaround1(&l, p); |
6dd9344c | 1974 | } |
bf28607f DD |
1975 | build_make_valid(&p, &r, wr.r1, wr.r2); |
1976 | build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); | |
1da177e4 | 1977 | |
aa1762f4 | 1978 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
1979 | /* |
1980 | * This is the entry point when build_r4000_tlbchange_handler_head | |
1981 | * spots a huge page. | |
1982 | */ | |
1983 | uasm_l_tlb_huge_update(&l, p); | |
bf28607f DD |
1984 | iPTE_LW(&p, wr.r1, wr.r2); |
1985 | build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); | |
fd062c84 | 1986 | build_tlb_probe_entry(&p); |
6dd9344c | 1987 | |
05857c64 | 1988 | if (cpu_has_rixi) { |
6dd9344c DD |
1989 | /* |
1990 | * If the page is not _PAGE_VALID, RI or XI could not | |
1991 | * have triggered it. Skip the expensive test.. | |
1992 | */ | |
cc33ae43 | 1993 | if (use_bbit_insns()) { |
bf28607f | 1994 | uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), |
cc33ae43 DD |
1995 | label_tlbl_goaround2); |
1996 | } else { | |
bf28607f DD |
1997 | uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); |
1998 | uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); | |
cc33ae43 | 1999 | } |
6dd9344c DD |
2000 | uasm_i_nop(&p); |
2001 | ||
2002 | uasm_i_tlbr(&p); | |
2003 | /* Examine entrylo 0 or 1 based on ptr. */ | |
cc33ae43 | 2004 | if (use_bbit_insns()) { |
bf28607f | 2005 | uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); |
cc33ae43 | 2006 | } else { |
bf28607f DD |
2007 | uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); |
2008 | uasm_i_beqz(&p, wr.r3, 8); | |
cc33ae43 | 2009 | } |
bf28607f DD |
2010 | /* load it in the delay slot*/ |
2011 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); | |
2012 | /* load it if ptr is odd */ | |
2013 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); | |
6dd9344c | 2014 | /* |
bf28607f | 2015 | * If the entryLo (now in wr.r3) is valid (bit 1), RI or |
6dd9344c DD |
2016 | * XI must have triggered it. |
2017 | */ | |
cc33ae43 | 2018 | if (use_bbit_insns()) { |
bf28607f | 2019 | uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2); |
cc33ae43 | 2020 | } else { |
bf28607f DD |
2021 | uasm_i_andi(&p, wr.r3, wr.r3, 2); |
2022 | uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); | |
cc33ae43 | 2023 | } |
0f4ccbc8 DD |
2024 | if (PM_DEFAULT_MASK == 0) |
2025 | uasm_i_nop(&p); | |
6dd9344c DD |
2026 | /* |
2027 | * We clobbered C0_PAGEMASK, restore it. On the other branch | |
2028 | * it is restored in build_huge_tlb_write_entry. | |
2029 | */ | |
bf28607f | 2030 | build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0); |
6dd9344c DD |
2031 | |
2032 | uasm_l_tlbl_goaround2(&l, p); | |
2033 | } | |
bf28607f DD |
2034 | uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID)); |
2035 | build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2); | |
fd062c84 DD |
2036 | #endif |
2037 | ||
e30ec452 | 2038 | uasm_l_nopage_tlbl(&l, p); |
bf28607f | 2039 | build_restore_work_registers(&p); |
2a0b24f5 SH |
2040 | #ifdef CONFIG_CPU_MICROMIPS |
2041 | if ((unsigned long)tlb_do_page_fault_0 & 1) { | |
2042 | uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0)); | |
2043 | uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0)); | |
2044 | uasm_i_jr(&p, K0); | |
2045 | } else | |
2046 | #endif | |
e30ec452 TS |
2047 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); |
2048 | uasm_i_nop(&p); | |
1da177e4 LT |
2049 | |
2050 | if ((p - handle_tlbl) > FASTPATH_SIZE) | |
2051 | panic("TLB load handler fastpath space exceeded"); | |
2052 | ||
e30ec452 TS |
2053 | uasm_resolve_relocs(relocs, labels); |
2054 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", | |
2055 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 2056 | |
a2c763e0 | 2057 | dump_handler("r4000_tlb_load", handle_tlbl, ARRAY_SIZE(handle_tlbl)); |
1da177e4 LT |
2058 | } |
2059 | ||
234fcd14 | 2060 | static void __cpuinit build_r4000_tlb_store_handler(void) |
1da177e4 LT |
2061 | { |
2062 | u32 *p = handle_tlbs; | |
e30ec452 TS |
2063 | struct uasm_label *l = labels; |
2064 | struct uasm_reloc *r = relocs; | |
bf28607f | 2065 | struct work_registers wr; |
1da177e4 LT |
2066 | |
2067 | memset(handle_tlbs, 0, sizeof(handle_tlbs)); | |
2068 | memset(labels, 0, sizeof(labels)); | |
2069 | memset(relocs, 0, sizeof(relocs)); | |
2070 | ||
bf28607f DD |
2071 | wr = build_r4000_tlbchange_handler_head(&p, &l, &r); |
2072 | build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); | |
8df5beac MR |
2073 | if (m4kc_tlbp_war()) |
2074 | build_tlb_probe_entry(&p); | |
bf28607f DD |
2075 | build_make_write(&p, &r, wr.r1, wr.r2); |
2076 | build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); | |
1da177e4 | 2077 | |
aa1762f4 | 2078 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
2079 | /* |
2080 | * This is the entry point when | |
2081 | * build_r4000_tlbchange_handler_head spots a huge page. | |
2082 | */ | |
2083 | uasm_l_tlb_huge_update(&l, p); | |
bf28607f DD |
2084 | iPTE_LW(&p, wr.r1, wr.r2); |
2085 | build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); | |
fd062c84 | 2086 | build_tlb_probe_entry(&p); |
bf28607f | 2087 | uasm_i_ori(&p, wr.r1, wr.r1, |
fd062c84 | 2088 | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); |
bf28607f | 2089 | build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2); |
fd062c84 DD |
2090 | #endif |
2091 | ||
e30ec452 | 2092 | uasm_l_nopage_tlbs(&l, p); |
bf28607f | 2093 | build_restore_work_registers(&p); |
2a0b24f5 SH |
2094 | #ifdef CONFIG_CPU_MICROMIPS |
2095 | if ((unsigned long)tlb_do_page_fault_1 & 1) { | |
2096 | uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); | |
2097 | uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); | |
2098 | uasm_i_jr(&p, K0); | |
2099 | } else | |
2100 | #endif | |
e30ec452 TS |
2101 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); |
2102 | uasm_i_nop(&p); | |
1da177e4 LT |
2103 | |
2104 | if ((p - handle_tlbs) > FASTPATH_SIZE) | |
2105 | panic("TLB store handler fastpath space exceeded"); | |
2106 | ||
e30ec452 TS |
2107 | uasm_resolve_relocs(relocs, labels); |
2108 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", | |
2109 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 2110 | |
a2c763e0 | 2111 | dump_handler("r4000_tlb_store", handle_tlbs, ARRAY_SIZE(handle_tlbs)); |
1da177e4 LT |
2112 | } |
2113 | ||
234fcd14 | 2114 | static void __cpuinit build_r4000_tlb_modify_handler(void) |
1da177e4 LT |
2115 | { |
2116 | u32 *p = handle_tlbm; | |
e30ec452 TS |
2117 | struct uasm_label *l = labels; |
2118 | struct uasm_reloc *r = relocs; | |
bf28607f | 2119 | struct work_registers wr; |
1da177e4 LT |
2120 | |
2121 | memset(handle_tlbm, 0, sizeof(handle_tlbm)); | |
2122 | memset(labels, 0, sizeof(labels)); | |
2123 | memset(relocs, 0, sizeof(relocs)); | |
2124 | ||
bf28607f DD |
2125 | wr = build_r4000_tlbchange_handler_head(&p, &l, &r); |
2126 | build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); | |
8df5beac MR |
2127 | if (m4kc_tlbp_war()) |
2128 | build_tlb_probe_entry(&p); | |
1da177e4 | 2129 | /* Present and writable bits set, set accessed and dirty bits. */ |
bf28607f DD |
2130 | build_make_write(&p, &r, wr.r1, wr.r2); |
2131 | build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); | |
1da177e4 | 2132 | |
aa1762f4 | 2133 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
2134 | /* |
2135 | * This is the entry point when | |
2136 | * build_r4000_tlbchange_handler_head spots a huge page. | |
2137 | */ | |
2138 | uasm_l_tlb_huge_update(&l, p); | |
bf28607f DD |
2139 | iPTE_LW(&p, wr.r1, wr.r2); |
2140 | build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); | |
fd062c84 | 2141 | build_tlb_probe_entry(&p); |
bf28607f | 2142 | uasm_i_ori(&p, wr.r1, wr.r1, |
fd062c84 | 2143 | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); |
bf28607f | 2144 | build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2); |
fd062c84 DD |
2145 | #endif |
2146 | ||
e30ec452 | 2147 | uasm_l_nopage_tlbm(&l, p); |
bf28607f | 2148 | build_restore_work_registers(&p); |
2a0b24f5 SH |
2149 | #ifdef CONFIG_CPU_MICROMIPS |
2150 | if ((unsigned long)tlb_do_page_fault_1 & 1) { | |
2151 | uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); | |
2152 | uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); | |
2153 | uasm_i_jr(&p, K0); | |
2154 | } else | |
2155 | #endif | |
e30ec452 TS |
2156 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); |
2157 | uasm_i_nop(&p); | |
1da177e4 LT |
2158 | |
2159 | if ((p - handle_tlbm) > FASTPATH_SIZE) | |
2160 | panic("TLB modify handler fastpath space exceeded"); | |
2161 | ||
e30ec452 TS |
2162 | uasm_resolve_relocs(relocs, labels); |
2163 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", | |
2164 | (unsigned int)(p - handle_tlbm)); | |
115f2a44 | 2165 | |
a2c763e0 | 2166 | dump_handler("r4000_tlb_modify", handle_tlbm, ARRAY_SIZE(handle_tlbm)); |
1da177e4 LT |
2167 | } |
2168 | ||
234fcd14 | 2169 | void __cpuinit build_tlb_refill_handler(void) |
1da177e4 LT |
2170 | { |
2171 | /* | |
2172 | * The refill handler is generated per-CPU, multi-node systems | |
2173 | * may have local storage for it. The other handlers are only | |
2174 | * needed once. | |
2175 | */ | |
2176 | static int run_once = 0; | |
2177 | ||
a2c763e0 RB |
2178 | output_pgtable_bits_defines(); |
2179 | ||
1ec56329 DD |
2180 | #ifdef CONFIG_64BIT |
2181 | check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); | |
2182 | #endif | |
2183 | ||
10cc3529 | 2184 | switch (current_cpu_type()) { |
1da177e4 LT |
2185 | case CPU_R2000: |
2186 | case CPU_R3000: | |
2187 | case CPU_R3000A: | |
2188 | case CPU_R3081E: | |
2189 | case CPU_TX3912: | |
2190 | case CPU_TX3922: | |
2191 | case CPU_TX3927: | |
82622284 | 2192 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
8759934e HC |
2193 | if (cpu_has_local_ebase) |
2194 | build_r3000_tlb_refill_handler(); | |
1da177e4 | 2195 | if (!run_once) { |
8759934e HC |
2196 | if (!cpu_has_local_ebase) |
2197 | build_r3000_tlb_refill_handler(); | |
1da177e4 LT |
2198 | build_r3000_tlb_load_handler(); |
2199 | build_r3000_tlb_store_handler(); | |
2200 | build_r3000_tlb_modify_handler(); | |
2201 | run_once++; | |
2202 | } | |
82622284 DD |
2203 | #else |
2204 | panic("No R3000 TLB refill handler"); | |
2205 | #endif | |
1da177e4 LT |
2206 | break; |
2207 | ||
2208 | case CPU_R6000: | |
2209 | case CPU_R6000A: | |
2210 | panic("No R6000 TLB refill handler yet"); | |
2211 | break; | |
2212 | ||
2213 | case CPU_R8000: | |
2214 | panic("No R8000 TLB refill handler yet"); | |
2215 | break; | |
2216 | ||
2217 | default: | |
1da177e4 | 2218 | if (!run_once) { |
bf28607f | 2219 | scratch_reg = allocate_kscratch(); |
3d8bfdd0 DD |
2220 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
2221 | build_r4000_setup_pgd(); | |
2222 | #endif | |
1da177e4 LT |
2223 | build_r4000_tlb_load_handler(); |
2224 | build_r4000_tlb_store_handler(); | |
2225 | build_r4000_tlb_modify_handler(); | |
8759934e HC |
2226 | if (!cpu_has_local_ebase) |
2227 | build_r4000_tlb_refill_handler(); | |
1da177e4 LT |
2228 | run_once++; |
2229 | } | |
8759934e HC |
2230 | if (cpu_has_local_ebase) |
2231 | build_r4000_tlb_refill_handler(); | |
1da177e4 LT |
2232 | } |
2233 | } | |
1d40cfcd | 2234 | |
234fcd14 | 2235 | void __cpuinit flush_tlb_handlers(void) |
1d40cfcd | 2236 | { |
e0cee3ee | 2237 | local_flush_icache_range((unsigned long)handle_tlbl, |
1d40cfcd | 2238 | (unsigned long)handle_tlbl + sizeof(handle_tlbl)); |
e0cee3ee | 2239 | local_flush_icache_range((unsigned long)handle_tlbs, |
1d40cfcd | 2240 | (unsigned long)handle_tlbs + sizeof(handle_tlbs)); |
e0cee3ee | 2241 | local_flush_icache_range((unsigned long)handle_tlbm, |
1d40cfcd | 2242 | (unsigned long)handle_tlbm + sizeof(handle_tlbm)); |
3d8bfdd0 | 2243 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
0bfbf6a2 RB |
2244 | local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd_array, |
2245 | (unsigned long)tlbmiss_handler_setup_pgd_array + sizeof(handle_tlbm)); | |
3d8bfdd0 | 2246 | #endif |
1d40cfcd | 2247 | } |