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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Synthesize TLB refill handlers at runtime. | |
7 | * | |
70342287 RB |
8 | * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer |
9 | * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki | |
41c594ab | 10 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) |
fd062c84 | 11 | * Copyright (C) 2008, 2009 Cavium Networks, Inc. |
113c62d9 | 12 | * Copyright (C) 2011 MIPS Technologies, Inc. |
41c594ab RB |
13 | * |
14 | * ... and the days got worse and worse and now you see | |
15 | * I've gone completly out of my mind. | |
16 | * | |
17 | * They're coming to take me a away haha | |
18 | * they're coming to take me a away hoho hihi haha | |
19 | * to the funny farm where code is beautiful all the time ... | |
20 | * | |
21 | * (Condolences to Napoleon XIV) | |
1da177e4 LT |
22 | */ |
23 | ||
95affdda | 24 | #include <linux/bug.h> |
1da177e4 LT |
25 | #include <linux/kernel.h> |
26 | #include <linux/types.h> | |
631330f5 | 27 | #include <linux/smp.h> |
1da177e4 | 28 | #include <linux/string.h> |
3d8bfdd0 | 29 | #include <linux/cache.h> |
1da177e4 | 30 | |
3d8bfdd0 | 31 | #include <asm/cacheflush.h> |
69f24d17 | 32 | #include <asm/cpu-type.h> |
3d8bfdd0 | 33 | #include <asm/pgtable.h> |
1da177e4 | 34 | #include <asm/war.h> |
3482d713 | 35 | #include <asm/uasm.h> |
b81947c6 | 36 | #include <asm/setup.h> |
e30ec452 | 37 | |
a2d25e63 | 38 | static int mips_xpa_disabled; |
c5b36783 SH |
39 | |
40 | static int __init xpa_disable(char *s) | |
41 | { | |
42 | mips_xpa_disabled = 1; | |
43 | ||
44 | return 1; | |
45 | } | |
46 | ||
47 | __setup("noxpa", xpa_disable); | |
48 | ||
1ec56329 DD |
49 | /* |
50 | * TLB load/store/modify handlers. | |
51 | * | |
52 | * Only the fastpath gets synthesized at runtime, the slowpath for | |
53 | * do_page_fault remains normal asm. | |
54 | */ | |
55 | extern void tlb_do_page_fault_0(void); | |
56 | extern void tlb_do_page_fault_1(void); | |
57 | ||
bf28607f DD |
58 | struct work_registers { |
59 | int r1; | |
60 | int r2; | |
61 | int r3; | |
62 | }; | |
63 | ||
64 | struct tlb_reg_save { | |
65 | unsigned long a; | |
66 | unsigned long b; | |
67 | } ____cacheline_aligned_in_smp; | |
68 | ||
69 | static struct tlb_reg_save handler_reg_save[NR_CPUS]; | |
1ec56329 | 70 | |
aeffdbba | 71 | static inline int r45k_bvahwbug(void) |
1da177e4 LT |
72 | { |
73 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
74 | return 0; | |
75 | } | |
76 | ||
aeffdbba | 77 | static inline int r4k_250MHZhwbug(void) |
1da177e4 LT |
78 | { |
79 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
80 | return 0; | |
81 | } | |
82 | ||
aeffdbba | 83 | static inline int __maybe_unused bcm1250_m3_war(void) |
1da177e4 LT |
84 | { |
85 | return BCM1250_M3_WAR; | |
86 | } | |
87 | ||
aeffdbba | 88 | static inline int __maybe_unused r10000_llsc_war(void) |
1da177e4 LT |
89 | { |
90 | return R10000_LLSC_WAR; | |
91 | } | |
92 | ||
cc33ae43 DD |
93 | static int use_bbit_insns(void) |
94 | { | |
95 | switch (current_cpu_type()) { | |
96 | case CPU_CAVIUM_OCTEON: | |
97 | case CPU_CAVIUM_OCTEON_PLUS: | |
98 | case CPU_CAVIUM_OCTEON2: | |
4723b20a | 99 | case CPU_CAVIUM_OCTEON3: |
cc33ae43 DD |
100 | return 1; |
101 | default: | |
102 | return 0; | |
103 | } | |
104 | } | |
105 | ||
2c8c53e2 DD |
106 | static int use_lwx_insns(void) |
107 | { | |
108 | switch (current_cpu_type()) { | |
109 | case CPU_CAVIUM_OCTEON2: | |
4723b20a | 110 | case CPU_CAVIUM_OCTEON3: |
2c8c53e2 DD |
111 | return 1; |
112 | default: | |
113 | return 0; | |
114 | } | |
115 | } | |
116 | #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \ | |
117 | CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 | |
118 | static bool scratchpad_available(void) | |
119 | { | |
120 | return true; | |
121 | } | |
122 | static int scratchpad_offset(int i) | |
123 | { | |
124 | /* | |
125 | * CVMSEG starts at address -32768 and extends for | |
126 | * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines. | |
127 | */ | |
128 | i += 1; /* Kernel use starts at the top and works down. */ | |
129 | return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768; | |
130 | } | |
131 | #else | |
132 | static bool scratchpad_available(void) | |
133 | { | |
134 | return false; | |
135 | } | |
136 | static int scratchpad_offset(int i) | |
137 | { | |
138 | BUG(); | |
e1c87d2a DD |
139 | /* Really unreachable, but evidently some GCC want this. */ |
140 | return 0; | |
2c8c53e2 DD |
141 | } |
142 | #endif | |
8df5beac MR |
143 | /* |
144 | * Found by experiment: At least some revisions of the 4kc throw under | |
145 | * some circumstances a machine check exception, triggered by invalid | |
146 | * values in the index register. Delaying the tlbp instruction until | |
147 | * after the next branch, plus adding an additional nop in front of | |
148 | * tlbwi/tlbwr avoids the invalid index register values. Nobody knows | |
149 | * why; it's not an issue caused by the core RTL. | |
150 | * | |
151 | */ | |
078a55fc | 152 | static int m4kc_tlbp_war(void) |
8df5beac MR |
153 | { |
154 | return (current_cpu_data.processor_id & 0xffff00) == | |
155 | (PRID_COMP_MIPS | PRID_IMP_4KC); | |
156 | } | |
157 | ||
e30ec452 | 158 | /* Handle labels (which must be positive integers). */ |
1da177e4 | 159 | enum label_id { |
e30ec452 | 160 | label_second_part = 1, |
1da177e4 LT |
161 | label_leave, |
162 | label_vmalloc, | |
163 | label_vmalloc_done, | |
02a54177 RB |
164 | label_tlbw_hazard_0, |
165 | label_split = label_tlbw_hazard_0 + 8, | |
6dd9344c DD |
166 | label_tlbl_goaround1, |
167 | label_tlbl_goaround2, | |
1da177e4 LT |
168 | label_nopage_tlbl, |
169 | label_nopage_tlbs, | |
170 | label_nopage_tlbm, | |
171 | label_smp_pgtable_change, | |
172 | label_r3000_write_probe_fail, | |
1ec56329 | 173 | label_large_segbits_fault, |
aa1762f4 | 174 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
175 | label_tlb_huge_update, |
176 | #endif | |
1da177e4 LT |
177 | }; |
178 | ||
e30ec452 TS |
179 | UASM_L_LA(_second_part) |
180 | UASM_L_LA(_leave) | |
e30ec452 TS |
181 | UASM_L_LA(_vmalloc) |
182 | UASM_L_LA(_vmalloc_done) | |
02a54177 | 183 | /* _tlbw_hazard_x is handled differently. */ |
e30ec452 | 184 | UASM_L_LA(_split) |
6dd9344c DD |
185 | UASM_L_LA(_tlbl_goaround1) |
186 | UASM_L_LA(_tlbl_goaround2) | |
e30ec452 TS |
187 | UASM_L_LA(_nopage_tlbl) |
188 | UASM_L_LA(_nopage_tlbs) | |
189 | UASM_L_LA(_nopage_tlbm) | |
190 | UASM_L_LA(_smp_pgtable_change) | |
191 | UASM_L_LA(_r3000_write_probe_fail) | |
1ec56329 | 192 | UASM_L_LA(_large_segbits_fault) |
aa1762f4 | 193 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
194 | UASM_L_LA(_tlb_huge_update) |
195 | #endif | |
656be92f | 196 | |
078a55fc | 197 | static int hazard_instance; |
02a54177 | 198 | |
078a55fc | 199 | static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance) |
02a54177 RB |
200 | { |
201 | switch (instance) { | |
202 | case 0 ... 7: | |
203 | uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance); | |
204 | return; | |
205 | default: | |
206 | BUG(); | |
207 | } | |
208 | } | |
209 | ||
078a55fc | 210 | static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance) |
02a54177 RB |
211 | { |
212 | switch (instance) { | |
213 | case 0 ... 7: | |
214 | uasm_build_label(l, *p, label_tlbw_hazard_0 + instance); | |
215 | break; | |
216 | default: | |
217 | BUG(); | |
218 | } | |
219 | } | |
220 | ||
92b1e6a6 | 221 | /* |
a2c763e0 RB |
222 | * pgtable bits are assigned dynamically depending on processor feature |
223 | * and statically based on kernel configuration. This spits out the actual | |
70342287 | 224 | * values the kernel is using. Required to make sense from disassembled |
a2c763e0 | 225 | * TLB exception handlers. |
92b1e6a6 | 226 | */ |
a2c763e0 RB |
227 | static void output_pgtable_bits_defines(void) |
228 | { | |
229 | #define pr_define(fmt, ...) \ | |
230 | pr_debug("#define " fmt, ##__VA_ARGS__) | |
231 | ||
232 | pr_debug("#include <asm/asm.h>\n"); | |
233 | pr_debug("#include <asm/regdef.h>\n"); | |
234 | pr_debug("\n"); | |
235 | ||
236 | pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT); | |
237 | pr_define("_PAGE_READ_SHIFT %d\n", _PAGE_READ_SHIFT); | |
238 | pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT); | |
239 | pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT); | |
240 | pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT); | |
970d032f | 241 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
a2c763e0 | 242 | pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT); |
970d032f | 243 | pr_define("_PAGE_SPLITTING_SHIFT %d\n", _PAGE_SPLITTING_SHIFT); |
a2c763e0 | 244 | #endif |
be0c37c9 | 245 | #ifdef CONFIG_CPU_MIPSR2 |
a2c763e0 RB |
246 | if (cpu_has_rixi) { |
247 | #ifdef _PAGE_NO_EXEC_SHIFT | |
248 | pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT); | |
a2c763e0 RB |
249 | pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT); |
250 | #endif | |
251 | } | |
be0c37c9 | 252 | #endif |
a2c763e0 RB |
253 | pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT); |
254 | pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT); | |
255 | pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT); | |
256 | pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT); | |
257 | pr_debug("\n"); | |
258 | } | |
259 | ||
260 | static inline void dump_handler(const char *symbol, const u32 *handler, int count) | |
92b1e6a6 FBH |
261 | { |
262 | int i; | |
263 | ||
a2c763e0 RB |
264 | pr_debug("LEAF(%s)\n", symbol); |
265 | ||
92b1e6a6 FBH |
266 | pr_debug("\t.set push\n"); |
267 | pr_debug("\t.set noreorder\n"); | |
268 | ||
269 | for (i = 0; i < count; i++) | |
a2c763e0 | 270 | pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]); |
92b1e6a6 | 271 | |
a2c763e0 RB |
272 | pr_debug("\t.set\tpop\n"); |
273 | ||
274 | pr_debug("\tEND(%s)\n", symbol); | |
92b1e6a6 FBH |
275 | } |
276 | ||
1da177e4 LT |
277 | /* The only general purpose registers allowed in TLB handlers. */ |
278 | #define K0 26 | |
279 | #define K1 27 | |
280 | ||
281 | /* Some CP0 registers */ | |
41c594ab RB |
282 | #define C0_INDEX 0, 0 |
283 | #define C0_ENTRYLO0 2, 0 | |
284 | #define C0_TCBIND 2, 2 | |
285 | #define C0_ENTRYLO1 3, 0 | |
286 | #define C0_CONTEXT 4, 0 | |
fd062c84 | 287 | #define C0_PAGEMASK 5, 0 |
41c594ab RB |
288 | #define C0_BADVADDR 8, 0 |
289 | #define C0_ENTRYHI 10, 0 | |
290 | #define C0_EPC 14, 0 | |
291 | #define C0_XCONTEXT 20, 0 | |
1da177e4 | 292 | |
875d43e7 | 293 | #ifdef CONFIG_64BIT |
e30ec452 | 294 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT) |
1da177e4 | 295 | #else |
e30ec452 | 296 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT) |
1da177e4 LT |
297 | #endif |
298 | ||
299 | /* The worst case length of the handler is around 18 instructions for | |
300 | * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. | |
301 | * Maximum space available is 32 instructions for R3000 and 64 | |
302 | * instructions for R4000. | |
303 | * | |
304 | * We deliberately chose a buffer size of 128, so we won't scribble | |
305 | * over anything important on overflow before we panic. | |
306 | */ | |
078a55fc | 307 | static u32 tlb_handler[128]; |
1da177e4 LT |
308 | |
309 | /* simply assume worst case size for labels and relocs */ | |
078a55fc PG |
310 | static struct uasm_label labels[128]; |
311 | static struct uasm_reloc relocs[128]; | |
1da177e4 | 312 | |
078a55fc | 313 | static int check_for_high_segbits; |
3d8bfdd0 | 314 | |
078a55fc | 315 | static unsigned int kscratch_used_mask; |
3d8bfdd0 | 316 | |
7777b939 J |
317 | static inline int __maybe_unused c0_kscratch(void) |
318 | { | |
319 | switch (current_cpu_type()) { | |
320 | case CPU_XLP: | |
321 | case CPU_XLR: | |
322 | return 22; | |
323 | default: | |
324 | return 31; | |
325 | } | |
326 | } | |
327 | ||
078a55fc | 328 | static int allocate_kscratch(void) |
3d8bfdd0 DD |
329 | { |
330 | int r; | |
331 | unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask; | |
332 | ||
333 | r = ffs(a); | |
334 | ||
335 | if (r == 0) | |
336 | return -1; | |
337 | ||
338 | r--; /* make it zero based */ | |
339 | ||
340 | kscratch_used_mask |= (1 << r); | |
341 | ||
342 | return r; | |
343 | } | |
344 | ||
078a55fc PG |
345 | static int scratch_reg; |
346 | static int pgd_reg; | |
2c8c53e2 DD |
347 | enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch}; |
348 | ||
078a55fc | 349 | static struct work_registers build_get_work_registers(u32 **p) |
bf28607f DD |
350 | { |
351 | struct work_registers r; | |
352 | ||
0e6ecc1a | 353 | if (scratch_reg >= 0) { |
bf28607f | 354 | /* Save in CPU local C0_KScratch? */ |
7777b939 | 355 | UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg); |
bf28607f DD |
356 | r.r1 = K0; |
357 | r.r2 = K1; | |
358 | r.r3 = 1; | |
359 | return r; | |
360 | } | |
361 | ||
362 | if (num_possible_cpus() > 1) { | |
bf28607f | 363 | /* Get smp_processor_id */ |
c2377a42 J |
364 | UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG); |
365 | UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT); | |
bf28607f DD |
366 | |
367 | /* handler_reg_save index in K0 */ | |
368 | UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save))); | |
369 | ||
370 | UASM_i_LA(p, K1, (long)&handler_reg_save); | |
371 | UASM_i_ADDU(p, K0, K0, K1); | |
372 | } else { | |
373 | UASM_i_LA(p, K0, (long)&handler_reg_save); | |
374 | } | |
375 | /* K0 now points to save area, save $1 and $2 */ | |
376 | UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0); | |
377 | UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0); | |
378 | ||
379 | r.r1 = K1; | |
380 | r.r2 = 1; | |
381 | r.r3 = 2; | |
382 | return r; | |
383 | } | |
384 | ||
078a55fc | 385 | static void build_restore_work_registers(u32 **p) |
bf28607f | 386 | { |
0e6ecc1a | 387 | if (scratch_reg >= 0) { |
7777b939 | 388 | UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); |
bf28607f DD |
389 | return; |
390 | } | |
391 | /* K0 already points to save area, restore $1 and $2 */ | |
392 | UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0); | |
393 | UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0); | |
394 | } | |
395 | ||
2c8c53e2 | 396 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
3d8bfdd0 | 397 | |
82622284 DD |
398 | /* |
399 | * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current, | |
400 | * we cannot do r3000 under these circumstances. | |
3d8bfdd0 DD |
401 | * |
402 | * Declare pgd_current here instead of including mmu_context.h to avoid type | |
403 | * conflicts for tlbmiss_handler_setup_pgd | |
82622284 | 404 | */ |
3d8bfdd0 | 405 | extern unsigned long pgd_current[]; |
82622284 | 406 | |
1da177e4 LT |
407 | /* |
408 | * The R3000 TLB handler is simple. | |
409 | */ | |
078a55fc | 410 | static void build_r3000_tlb_refill_handler(void) |
1da177e4 LT |
411 | { |
412 | long pgdc = (long)pgd_current; | |
413 | u32 *p; | |
414 | ||
415 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
416 | p = tlb_handler; | |
417 | ||
e30ec452 TS |
418 | uasm_i_mfc0(&p, K0, C0_BADVADDR); |
419 | uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */ | |
420 | uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1); | |
421 | uasm_i_srl(&p, K0, K0, 22); /* load delay */ | |
422 | uasm_i_sll(&p, K0, K0, 2); | |
423 | uasm_i_addu(&p, K1, K1, K0); | |
424 | uasm_i_mfc0(&p, K0, C0_CONTEXT); | |
425 | uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */ | |
426 | uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */ | |
427 | uasm_i_addu(&p, K1, K1, K0); | |
428 | uasm_i_lw(&p, K0, 0, K1); | |
429 | uasm_i_nop(&p); /* load delay */ | |
430 | uasm_i_mtc0(&p, K0, C0_ENTRYLO0); | |
431 | uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ | |
432 | uasm_i_tlbwr(&p); /* cp0 delay */ | |
433 | uasm_i_jr(&p, K1); | |
434 | uasm_i_rfe(&p); /* branch delay */ | |
1da177e4 LT |
435 | |
436 | if (p > tlb_handler + 32) | |
437 | panic("TLB refill handler space exceeded"); | |
438 | ||
e30ec452 TS |
439 | pr_debug("Wrote TLB refill handler (%u instructions).\n", |
440 | (unsigned int)(p - tlb_handler)); | |
1da177e4 | 441 | |
91b05e67 | 442 | memcpy((void *)ebase, tlb_handler, 0x80); |
1062080a | 443 | local_flush_icache_range(ebase, ebase + 0x80); |
92b1e6a6 | 444 | |
a2c763e0 | 445 | dump_handler("r3000_tlb_refill", (u32 *)ebase, 32); |
1da177e4 | 446 | } |
82622284 | 447 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ |
1da177e4 LT |
448 | |
449 | /* | |
450 | * The R4000 TLB handler is much more complicated. We have two | |
451 | * consecutive handler areas with 32 instructions space each. | |
452 | * Since they aren't used at the same time, we can overflow in the | |
453 | * other one.To keep things simple, we first assume linear space, | |
454 | * then we relocate it to the final handler layout as needed. | |
455 | */ | |
078a55fc | 456 | static u32 final_handler[64]; |
1da177e4 LT |
457 | |
458 | /* | |
459 | * Hazards | |
460 | * | |
461 | * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: | |
462 | * 2. A timing hazard exists for the TLBP instruction. | |
463 | * | |
70342287 RB |
464 | * stalling_instruction |
465 | * TLBP | |
1da177e4 LT |
466 | * |
467 | * The JTLB is being read for the TLBP throughout the stall generated by the | |
468 | * previous instruction. This is not really correct as the stalling instruction | |
469 | * can modify the address used to access the JTLB. The failure symptom is that | |
470 | * the TLBP instruction will use an address created for the stalling instruction | |
471 | * and not the address held in C0_ENHI and thus report the wrong results. | |
472 | * | |
473 | * The software work-around is to not allow the instruction preceding the TLBP | |
474 | * to stall - make it an NOP or some other instruction guaranteed not to stall. | |
475 | * | |
70342287 | 476 | * Errata 2 will not be fixed. This errata is also on the R5000. |
1da177e4 LT |
477 | * |
478 | * As if we MIPS hackers wouldn't know how to nop pipelines happy ... | |
479 | */ | |
078a55fc | 480 | static void __maybe_unused build_tlb_probe_entry(u32 **p) |
1da177e4 | 481 | { |
10cc3529 | 482 | switch (current_cpu_type()) { |
326e2e1a | 483 | /* Found by experiment: R4600 v2.0/R4700 needs this, too. */ |
f5b4d956 | 484 | case CPU_R4600: |
326e2e1a | 485 | case CPU_R4700: |
1da177e4 | 486 | case CPU_R5000: |
1da177e4 | 487 | case CPU_NEVADA: |
e30ec452 TS |
488 | uasm_i_nop(p); |
489 | uasm_i_tlbp(p); | |
1da177e4 LT |
490 | break; |
491 | ||
492 | default: | |
e30ec452 | 493 | uasm_i_tlbp(p); |
1da177e4 LT |
494 | break; |
495 | } | |
496 | } | |
497 | ||
498 | /* | |
499 | * Write random or indexed TLB entry, and care about the hazards from | |
25985edc | 500 | * the preceding mtc0 and for the following eret. |
1da177e4 LT |
501 | */ |
502 | enum tlb_write_entry { tlb_random, tlb_indexed }; | |
503 | ||
078a55fc PG |
504 | static void build_tlb_write_entry(u32 **p, struct uasm_label **l, |
505 | struct uasm_reloc **r, | |
506 | enum tlb_write_entry wmode) | |
1da177e4 LT |
507 | { |
508 | void(*tlbw)(u32 **) = NULL; | |
509 | ||
510 | switch (wmode) { | |
e30ec452 TS |
511 | case tlb_random: tlbw = uasm_i_tlbwr; break; |
512 | case tlb_indexed: tlbw = uasm_i_tlbwi; break; | |
1da177e4 LT |
513 | } |
514 | ||
9eaffa84 RB |
515 | if (cpu_has_mips_r2_r6) { |
516 | if (cpu_has_mips_r2_exec_hazard) | |
41f0e4d0 | 517 | uasm_i_ehb(p); |
161548bf RB |
518 | tlbw(p); |
519 | return; | |
520 | } | |
521 | ||
10cc3529 | 522 | switch (current_cpu_type()) { |
1da177e4 LT |
523 | case CPU_R4000PC: |
524 | case CPU_R4000SC: | |
525 | case CPU_R4000MC: | |
526 | case CPU_R4400PC: | |
527 | case CPU_R4400SC: | |
528 | case CPU_R4400MC: | |
529 | /* | |
530 | * This branch uses up a mtc0 hazard nop slot and saves | |
531 | * two nops after the tlbw instruction. | |
532 | */ | |
02a54177 | 533 | uasm_bgezl_hazard(p, r, hazard_instance); |
1da177e4 | 534 | tlbw(p); |
02a54177 RB |
535 | uasm_bgezl_label(l, p, hazard_instance); |
536 | hazard_instance++; | |
e30ec452 | 537 | uasm_i_nop(p); |
1da177e4 LT |
538 | break; |
539 | ||
540 | case CPU_R4600: | |
541 | case CPU_R4700: | |
e30ec452 | 542 | uasm_i_nop(p); |
2c93e12c | 543 | tlbw(p); |
e30ec452 | 544 | uasm_i_nop(p); |
2c93e12c MR |
545 | break; |
546 | ||
359187d6 | 547 | case CPU_R5000: |
359187d6 RB |
548 | case CPU_NEVADA: |
549 | uasm_i_nop(p); /* QED specifies 2 nops hazard */ | |
550 | uasm_i_nop(p); /* QED specifies 2 nops hazard */ | |
551 | tlbw(p); | |
552 | break; | |
553 | ||
2c93e12c | 554 | case CPU_R4300: |
1da177e4 LT |
555 | case CPU_5KC: |
556 | case CPU_TX49XX: | |
bdf21b18 | 557 | case CPU_PR4450: |
efa0f81c | 558 | case CPU_XLR: |
e30ec452 | 559 | uasm_i_nop(p); |
1da177e4 LT |
560 | tlbw(p); |
561 | break; | |
562 | ||
563 | case CPU_R10000: | |
564 | case CPU_R12000: | |
44d921b2 | 565 | case CPU_R14000: |
30577391 | 566 | case CPU_R16000: |
1da177e4 | 567 | case CPU_4KC: |
b1ec4c8e | 568 | case CPU_4KEC: |
113c62d9 | 569 | case CPU_M14KC: |
f8fa4811 | 570 | case CPU_M14KEC: |
1da177e4 | 571 | case CPU_SB1: |
93ce2f52 | 572 | case CPU_SB1A: |
1da177e4 LT |
573 | case CPU_4KSC: |
574 | case CPU_20KC: | |
575 | case CPU_25KF: | |
602977b0 KC |
576 | case CPU_BMIPS32: |
577 | case CPU_BMIPS3300: | |
578 | case CPU_BMIPS4350: | |
579 | case CPU_BMIPS4380: | |
580 | case CPU_BMIPS5000: | |
2a21c730 | 581 | case CPU_LOONGSON2: |
c579d310 | 582 | case CPU_LOONGSON3: |
a644b277 | 583 | case CPU_R5500: |
8df5beac | 584 | if (m4kc_tlbp_war()) |
e30ec452 | 585 | uasm_i_nop(p); |
2f794d09 | 586 | case CPU_ALCHEMY: |
1da177e4 LT |
587 | tlbw(p); |
588 | break; | |
589 | ||
1da177e4 | 590 | case CPU_RM7000: |
e30ec452 TS |
591 | uasm_i_nop(p); |
592 | uasm_i_nop(p); | |
593 | uasm_i_nop(p); | |
594 | uasm_i_nop(p); | |
1da177e4 LT |
595 | tlbw(p); |
596 | break; | |
597 | ||
1da177e4 LT |
598 | case CPU_VR4111: |
599 | case CPU_VR4121: | |
600 | case CPU_VR4122: | |
601 | case CPU_VR4181: | |
602 | case CPU_VR4181A: | |
e30ec452 TS |
603 | uasm_i_nop(p); |
604 | uasm_i_nop(p); | |
1da177e4 | 605 | tlbw(p); |
e30ec452 TS |
606 | uasm_i_nop(p); |
607 | uasm_i_nop(p); | |
1da177e4 LT |
608 | break; |
609 | ||
610 | case CPU_VR4131: | |
611 | case CPU_VR4133: | |
7623debf | 612 | case CPU_R5432: |
e30ec452 TS |
613 | uasm_i_nop(p); |
614 | uasm_i_nop(p); | |
1da177e4 LT |
615 | tlbw(p); |
616 | break; | |
617 | ||
83ccf69d LPC |
618 | case CPU_JZRISC: |
619 | tlbw(p); | |
620 | uasm_i_nop(p); | |
621 | break; | |
622 | ||
1da177e4 LT |
623 | default: |
624 | panic("No TLB refill handler yet (CPU type: %d)", | |
d7b12056 | 625 | current_cpu_type()); |
1da177e4 LT |
626 | break; |
627 | } | |
628 | } | |
629 | ||
078a55fc PG |
630 | static __maybe_unused void build_convert_pte_to_entrylo(u32 **p, |
631 | unsigned int reg) | |
fd062c84 | 632 | { |
05857c64 | 633 | if (cpu_has_rixi) { |
748e787e | 634 | UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL)); |
6dd9344c | 635 | } else { |
34adb28d | 636 | #ifdef CONFIG_PHYS_ADDR_T_64BIT |
3be6022c | 637 | uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL)); |
6dd9344c DD |
638 | #else |
639 | UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL)); | |
640 | #endif | |
641 | } | |
642 | } | |
fd062c84 | 643 | |
aa1762f4 | 644 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 | 645 | |
078a55fc PG |
646 | static void build_restore_pagemask(u32 **p, struct uasm_reloc **r, |
647 | unsigned int tmp, enum label_id lid, | |
648 | int restore_scratch) | |
6dd9344c | 649 | { |
2c8c53e2 DD |
650 | if (restore_scratch) { |
651 | /* Reset default page size */ | |
652 | if (PM_DEFAULT_MASK >> 16) { | |
653 | uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); | |
654 | uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); | |
655 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
656 | uasm_il_b(p, r, lid); | |
657 | } else if (PM_DEFAULT_MASK) { | |
658 | uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); | |
659 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
660 | uasm_il_b(p, r, lid); | |
661 | } else { | |
662 | uasm_i_mtc0(p, 0, C0_PAGEMASK); | |
663 | uasm_il_b(p, r, lid); | |
664 | } | |
0e6ecc1a | 665 | if (scratch_reg >= 0) |
7777b939 | 666 | UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); |
2c8c53e2 DD |
667 | else |
668 | UASM_i_LW(p, 1, scratchpad_offset(0), 0); | |
fd062c84 | 669 | } else { |
2c8c53e2 DD |
670 | /* Reset default page size */ |
671 | if (PM_DEFAULT_MASK >> 16) { | |
672 | uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); | |
673 | uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); | |
674 | uasm_il_b(p, r, lid); | |
675 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
676 | } else if (PM_DEFAULT_MASK) { | |
677 | uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); | |
678 | uasm_il_b(p, r, lid); | |
679 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
680 | } else { | |
681 | uasm_il_b(p, r, lid); | |
682 | uasm_i_mtc0(p, 0, C0_PAGEMASK); | |
683 | } | |
fd062c84 DD |
684 | } |
685 | } | |
686 | ||
078a55fc PG |
687 | static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l, |
688 | struct uasm_reloc **r, | |
689 | unsigned int tmp, | |
690 | enum tlb_write_entry wmode, | |
691 | int restore_scratch) | |
6dd9344c DD |
692 | { |
693 | /* Set huge page tlb entry size */ | |
694 | uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16); | |
695 | uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff); | |
696 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
697 | ||
698 | build_tlb_write_entry(p, l, r, wmode); | |
699 | ||
2c8c53e2 | 700 | build_restore_pagemask(p, r, tmp, label_leave, restore_scratch); |
6dd9344c DD |
701 | } |
702 | ||
fd062c84 DD |
703 | /* |
704 | * Check if Huge PTE is present, if so then jump to LABEL. | |
705 | */ | |
078a55fc | 706 | static void |
fd062c84 | 707 | build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp, |
078a55fc | 708 | unsigned int pmd, int lid) |
fd062c84 DD |
709 | { |
710 | UASM_i_LW(p, tmp, 0, pmd); | |
cc33ae43 DD |
711 | if (use_bbit_insns()) { |
712 | uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid); | |
713 | } else { | |
714 | uasm_i_andi(p, tmp, tmp, _PAGE_HUGE); | |
715 | uasm_il_bnez(p, r, tmp, lid); | |
716 | } | |
fd062c84 DD |
717 | } |
718 | ||
078a55fc PG |
719 | static void build_huge_update_entries(u32 **p, unsigned int pte, |
720 | unsigned int tmp) | |
fd062c84 DD |
721 | { |
722 | int small_sequence; | |
723 | ||
724 | /* | |
725 | * A huge PTE describes an area the size of the | |
726 | * configured huge page size. This is twice the | |
727 | * of the large TLB entry size we intend to use. | |
728 | * A TLB entry half the size of the configured | |
729 | * huge page size is configured into entrylo0 | |
730 | * and entrylo1 to cover the contiguous huge PTE | |
731 | * address space. | |
732 | */ | |
733 | small_sequence = (HPAGE_SIZE >> 7) < 0x10000; | |
734 | ||
70342287 | 735 | /* We can clobber tmp. It isn't used after this.*/ |
fd062c84 DD |
736 | if (!small_sequence) |
737 | uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16)); | |
738 | ||
6dd9344c | 739 | build_convert_pte_to_entrylo(p, pte); |
9b8c3891 | 740 | UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */ |
fd062c84 DD |
741 | /* convert to entrylo1 */ |
742 | if (small_sequence) | |
743 | UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7); | |
744 | else | |
745 | UASM_i_ADDU(p, pte, pte, tmp); | |
746 | ||
9b8c3891 | 747 | UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */ |
fd062c84 DD |
748 | } |
749 | ||
078a55fc PG |
750 | static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r, |
751 | struct uasm_label **l, | |
752 | unsigned int pte, | |
753 | unsigned int ptr) | |
fd062c84 DD |
754 | { |
755 | #ifdef CONFIG_SMP | |
756 | UASM_i_SC(p, pte, 0, ptr); | |
757 | uasm_il_beqz(p, r, pte, label_tlb_huge_update); | |
758 | UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */ | |
759 | #else | |
760 | UASM_i_SW(p, pte, 0, ptr); | |
761 | #endif | |
762 | build_huge_update_entries(p, pte, ptr); | |
2c8c53e2 | 763 | build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0); |
fd062c84 | 764 | } |
aa1762f4 | 765 | #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ |
fd062c84 | 766 | |
875d43e7 | 767 | #ifdef CONFIG_64BIT |
1da177e4 LT |
768 | /* |
769 | * TMP and PTR are scratch. | |
770 | * TMP will be clobbered, PTR will hold the pmd entry. | |
771 | */ | |
078a55fc | 772 | static void |
e30ec452 | 773 | build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
1da177e4 LT |
774 | unsigned int tmp, unsigned int ptr) |
775 | { | |
82622284 | 776 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
1da177e4 | 777 | long pgdc = (long)pgd_current; |
82622284 | 778 | #endif |
1da177e4 LT |
779 | /* |
780 | * The vmalloc handling is not in the hotpath. | |
781 | */ | |
e30ec452 | 782 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); |
1ec56329 DD |
783 | |
784 | if (check_for_high_segbits) { | |
785 | /* | |
786 | * The kernel currently implicitely assumes that the | |
787 | * MIPS SEGBITS parameter for the processor is | |
788 | * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never | |
789 | * allocate virtual addresses outside the maximum | |
790 | * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But | |
791 | * that doesn't prevent user code from accessing the | |
792 | * higher xuseg addresses. Here, we make sure that | |
793 | * everything but the lower xuseg addresses goes down | |
794 | * the module_alloc/vmalloc path. | |
795 | */ | |
796 | uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); | |
797 | uasm_il_bnez(p, r, ptr, label_vmalloc); | |
798 | } else { | |
799 | uasm_il_bltz(p, r, tmp, label_vmalloc); | |
800 | } | |
e30ec452 | 801 | /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ |
1da177e4 | 802 | |
3d8bfdd0 DD |
803 | if (pgd_reg != -1) { |
804 | /* pgd is in pgd_reg */ | |
7777b939 | 805 | UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); |
3d8bfdd0 | 806 | } else { |
f4ae17aa | 807 | #if defined(CONFIG_MIPS_PGD_C0_CONTEXT) |
3d8bfdd0 DD |
808 | /* |
809 | * &pgd << 11 stored in CONTEXT [23..63]. | |
810 | */ | |
811 | UASM_i_MFC0(p, ptr, C0_CONTEXT); | |
812 | ||
813 | /* Clear lower 23 bits of context. */ | |
814 | uasm_i_dins(p, ptr, 0, 0, 23); | |
815 | ||
70342287 | 816 | /* 1 0 1 0 1 << 6 xkphys cached */ |
3d8bfdd0 DD |
817 | uasm_i_ori(p, ptr, ptr, 0x540); |
818 | uasm_i_drotr(p, ptr, ptr, 11); | |
82622284 | 819 | #elif defined(CONFIG_SMP) |
f4ae17aa J |
820 | UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG); |
821 | uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT); | |
822 | UASM_i_LA_mostly(p, tmp, pgdc); | |
823 | uasm_i_daddu(p, ptr, ptr, tmp); | |
824 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); | |
825 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1da177e4 | 826 | #else |
f4ae17aa J |
827 | UASM_i_LA_mostly(p, ptr, pgdc); |
828 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1da177e4 | 829 | #endif |
f4ae17aa | 830 | } |
1da177e4 | 831 | |
e30ec452 | 832 | uasm_l_vmalloc_done(l, *p); |
242954b5 | 833 | |
3be6022c DD |
834 | /* get pgd offset in bytes */ |
835 | uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3); | |
e30ec452 TS |
836 | |
837 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); | |
838 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
325f8a0a | 839 | #ifndef __PAGETABLE_PMD_FOLDED |
e30ec452 TS |
840 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ |
841 | uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ | |
3be6022c | 842 | uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ |
e30ec452 TS |
843 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); |
844 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ | |
325f8a0a | 845 | #endif |
1da177e4 LT |
846 | } |
847 | ||
848 | /* | |
849 | * BVADDR is the faulting address, PTR is scratch. | |
850 | * PTR will hold the pgd for vmalloc. | |
851 | */ | |
078a55fc | 852 | static void |
e30ec452 | 853 | build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
1ec56329 DD |
854 | unsigned int bvaddr, unsigned int ptr, |
855 | enum vmalloc64_mode mode) | |
1da177e4 LT |
856 | { |
857 | long swpd = (long)swapper_pg_dir; | |
1ec56329 DD |
858 | int single_insn_swpd; |
859 | int did_vmalloc_branch = 0; | |
860 | ||
861 | single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd); | |
1da177e4 | 862 | |
e30ec452 | 863 | uasm_l_vmalloc(l, *p); |
1da177e4 | 864 | |
2c8c53e2 | 865 | if (mode != not_refill && check_for_high_segbits) { |
1ec56329 DD |
866 | if (single_insn_swpd) { |
867 | uasm_il_bltz(p, r, bvaddr, label_vmalloc_done); | |
868 | uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); | |
869 | did_vmalloc_branch = 1; | |
870 | /* fall through */ | |
871 | } else { | |
872 | uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault); | |
873 | } | |
874 | } | |
875 | if (!did_vmalloc_branch) { | |
876 | if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) { | |
877 | uasm_il_b(p, r, label_vmalloc_done); | |
878 | uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); | |
879 | } else { | |
880 | UASM_i_LA_mostly(p, ptr, swpd); | |
881 | uasm_il_b(p, r, label_vmalloc_done); | |
882 | if (uasm_in_compat_space_p(swpd)) | |
883 | uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd)); | |
884 | else | |
885 | uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); | |
886 | } | |
887 | } | |
2c8c53e2 | 888 | if (mode != not_refill && check_for_high_segbits) { |
1ec56329 DD |
889 | uasm_l_large_segbits_fault(l, *p); |
890 | /* | |
891 | * We get here if we are an xsseg address, or if we are | |
892 | * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary. | |
893 | * | |
894 | * Ignoring xsseg (assume disabled so would generate | |
895 | * (address errors?), the only remaining possibility | |
896 | * is the upper xuseg addresses. On processors with | |
897 | * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these | |
898 | * addresses would have taken an address error. We try | |
899 | * to mimic that here by taking a load/istream page | |
900 | * fault. | |
901 | */ | |
902 | UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0); | |
903 | uasm_i_jr(p, ptr); | |
2c8c53e2 DD |
904 | |
905 | if (mode == refill_scratch) { | |
0e6ecc1a | 906 | if (scratch_reg >= 0) |
7777b939 | 907 | UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); |
2c8c53e2 DD |
908 | else |
909 | UASM_i_LW(p, 1, scratchpad_offset(0), 0); | |
910 | } else { | |
911 | uasm_i_nop(p); | |
912 | } | |
1da177e4 LT |
913 | } |
914 | } | |
915 | ||
875d43e7 | 916 | #else /* !CONFIG_64BIT */ |
1da177e4 LT |
917 | |
918 | /* | |
919 | * TMP and PTR are scratch. | |
920 | * TMP will be clobbered, PTR will hold the pgd entry. | |
921 | */ | |
078a55fc | 922 | static void __maybe_unused |
1da177e4 LT |
923 | build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) |
924 | { | |
f4ae17aa J |
925 | if (pgd_reg != -1) { |
926 | /* pgd is in pgd_reg */ | |
927 | uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg); | |
928 | uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ | |
929 | } else { | |
930 | long pgdc = (long)pgd_current; | |
1da177e4 | 931 | |
f4ae17aa | 932 | /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ |
1da177e4 | 933 | #ifdef CONFIG_SMP |
f4ae17aa J |
934 | uasm_i_mfc0(p, ptr, SMP_CPUID_REG); |
935 | UASM_i_LA_mostly(p, tmp, pgdc); | |
936 | uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT); | |
937 | uasm_i_addu(p, ptr, tmp, ptr); | |
1da177e4 | 938 | #else |
f4ae17aa | 939 | UASM_i_LA_mostly(p, ptr, pgdc); |
1da177e4 | 940 | #endif |
f4ae17aa J |
941 | uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ |
942 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); | |
943 | } | |
e30ec452 TS |
944 | uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ |
945 | uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); | |
946 | uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
1da177e4 LT |
947 | } |
948 | ||
875d43e7 | 949 | #endif /* !CONFIG_64BIT */ |
1da177e4 | 950 | |
078a55fc | 951 | static void build_adjust_context(u32 **p, unsigned int ctx) |
1da177e4 | 952 | { |
242954b5 | 953 | unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; |
1da177e4 LT |
954 | unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); |
955 | ||
10cc3529 | 956 | switch (current_cpu_type()) { |
1da177e4 LT |
957 | case CPU_VR41XX: |
958 | case CPU_VR4111: | |
959 | case CPU_VR4121: | |
960 | case CPU_VR4122: | |
961 | case CPU_VR4131: | |
962 | case CPU_VR4181: | |
963 | case CPU_VR4181A: | |
964 | case CPU_VR4133: | |
965 | shift += 2; | |
966 | break; | |
967 | ||
968 | default: | |
969 | break; | |
970 | } | |
971 | ||
972 | if (shift) | |
e30ec452 TS |
973 | UASM_i_SRL(p, ctx, ctx, shift); |
974 | uasm_i_andi(p, ctx, ctx, mask); | |
1da177e4 LT |
975 | } |
976 | ||
078a55fc | 977 | static void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) |
1da177e4 LT |
978 | { |
979 | /* | |
980 | * Bug workaround for the Nevada. It seems as if under certain | |
981 | * circumstances the move from cp0_context might produce a | |
982 | * bogus result when the mfc0 instruction and its consumer are | |
983 | * in a different cacheline or a load instruction, probably any | |
984 | * memory reference, is between them. | |
985 | */ | |
10cc3529 | 986 | switch (current_cpu_type()) { |
1da177e4 | 987 | case CPU_NEVADA: |
e30ec452 | 988 | UASM_i_LW(p, ptr, 0, ptr); |
1da177e4 LT |
989 | GET_CONTEXT(p, tmp); /* get context reg */ |
990 | break; | |
991 | ||
992 | default: | |
993 | GET_CONTEXT(p, tmp); /* get context reg */ | |
e30ec452 | 994 | UASM_i_LW(p, ptr, 0, ptr); |
1da177e4 LT |
995 | break; |
996 | } | |
997 | ||
998 | build_adjust_context(p, tmp); | |
e30ec452 | 999 | UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ |
1da177e4 LT |
1000 | } |
1001 | ||
078a55fc | 1002 | static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep) |
1da177e4 LT |
1003 | { |
1004 | /* | |
1005 | * 64bit address support (36bit on a 32bit CPU) in a 32bit | |
1006 | * Kernel is a special case. Only a few CPUs use it. | |
1007 | */ | |
34adb28d | 1008 | #ifdef CONFIG_PHYS_ADDR_T_64BIT |
1da177e4 | 1009 | if (cpu_has_64bits) { |
e30ec452 TS |
1010 | uasm_i_ld(p, tmp, 0, ptep); /* get even pte */ |
1011 | uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ | |
05857c64 | 1012 | if (cpu_has_rixi) { |
748e787e | 1013 | UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); |
6dd9344c | 1014 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ |
748e787e | 1015 | UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); |
6dd9344c | 1016 | } else { |
3be6022c | 1017 | uasm_i_dsrl_safe(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */ |
6dd9344c | 1018 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ |
3be6022c | 1019 | uasm_i_dsrl_safe(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */ |
6dd9344c | 1020 | } |
9b8c3891 | 1021 | UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ |
1da177e4 LT |
1022 | } else { |
1023 | int pte_off_even = sizeof(pte_t) / 2; | |
1024 | int pte_off_odd = pte_off_even + sizeof(pte_t); | |
c5b36783 SH |
1025 | #ifdef CONFIG_XPA |
1026 | const int scratch = 1; /* Our extra working register */ | |
1da177e4 | 1027 | |
c5b36783 SH |
1028 | uasm_i_addu(p, scratch, 0, ptep); |
1029 | #endif | |
1030 | uasm_i_lw(p, tmp, pte_off_even, ptep); /* even pte */ | |
1031 | uasm_i_lw(p, ptep, pte_off_odd, ptep); /* odd pte */ | |
1032 | UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); | |
1033 | UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); | |
1034 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); | |
1035 | UASM_i_MTC0(p, ptep, C0_ENTRYLO1); | |
1036 | #ifdef CONFIG_XPA | |
1037 | uasm_i_lw(p, tmp, 0, scratch); | |
1038 | uasm_i_lw(p, ptep, sizeof(pte_t), scratch); | |
1039 | uasm_i_lui(p, scratch, 0xff); | |
1040 | uasm_i_ori(p, scratch, scratch, 0xffff); | |
1041 | uasm_i_and(p, tmp, scratch, tmp); | |
1042 | uasm_i_and(p, ptep, scratch, ptep); | |
1043 | uasm_i_mthc0(p, tmp, C0_ENTRYLO0); | |
1044 | uasm_i_mthc0(p, ptep, C0_ENTRYLO1); | |
1045 | #endif | |
1da177e4 LT |
1046 | } |
1047 | #else | |
e30ec452 TS |
1048 | UASM_i_LW(p, tmp, 0, ptep); /* get even pte */ |
1049 | UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ | |
1da177e4 LT |
1050 | if (r45k_bvahwbug()) |
1051 | build_tlb_probe_entry(p); | |
05857c64 | 1052 | if (cpu_has_rixi) { |
748e787e | 1053 | UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); |
6dd9344c DD |
1054 | if (r4k_250MHZhwbug()) |
1055 | UASM_i_MTC0(p, 0, C0_ENTRYLO0); | |
1056 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ | |
748e787e | 1057 | UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); |
6dd9344c DD |
1058 | } else { |
1059 | UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */ | |
1060 | if (r4k_250MHZhwbug()) | |
1061 | UASM_i_MTC0(p, 0, C0_ENTRYLO0); | |
1062 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ | |
1063 | UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */ | |
1064 | if (r45k_bvahwbug()) | |
1065 | uasm_i_mfc0(p, tmp, C0_INDEX); | |
1066 | } | |
1da177e4 | 1067 | if (r4k_250MHZhwbug()) |
9b8c3891 DD |
1068 | UASM_i_MTC0(p, 0, C0_ENTRYLO1); |
1069 | UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ | |
1da177e4 LT |
1070 | #endif |
1071 | } | |
1072 | ||
2c8c53e2 DD |
1073 | struct mips_huge_tlb_info { |
1074 | int huge_pte; | |
1075 | int restore_scratch; | |
9e0f162a | 1076 | bool need_reload_pte; |
2c8c53e2 DD |
1077 | }; |
1078 | ||
078a55fc | 1079 | static struct mips_huge_tlb_info |
2c8c53e2 DD |
1080 | build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, |
1081 | struct uasm_reloc **r, unsigned int tmp, | |
7777b939 | 1082 | unsigned int ptr, int c0_scratch_reg) |
2c8c53e2 DD |
1083 | { |
1084 | struct mips_huge_tlb_info rv; | |
1085 | unsigned int even, odd; | |
1086 | int vmalloc_branch_delay_filled = 0; | |
1087 | const int scratch = 1; /* Our extra working register */ | |
1088 | ||
1089 | rv.huge_pte = scratch; | |
1090 | rv.restore_scratch = 0; | |
9e0f162a | 1091 | rv.need_reload_pte = false; |
2c8c53e2 DD |
1092 | |
1093 | if (check_for_high_segbits) { | |
1094 | UASM_i_MFC0(p, tmp, C0_BADVADDR); | |
1095 | ||
1096 | if (pgd_reg != -1) | |
7777b939 | 1097 | UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); |
2c8c53e2 DD |
1098 | else |
1099 | UASM_i_MFC0(p, ptr, C0_CONTEXT); | |
1100 | ||
7777b939 J |
1101 | if (c0_scratch_reg >= 0) |
1102 | UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); | |
2c8c53e2 DD |
1103 | else |
1104 | UASM_i_SW(p, scratch, scratchpad_offset(0), 0); | |
1105 | ||
1106 | uasm_i_dsrl_safe(p, scratch, tmp, | |
1107 | PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); | |
1108 | uasm_il_bnez(p, r, scratch, label_vmalloc); | |
1109 | ||
1110 | if (pgd_reg == -1) { | |
1111 | vmalloc_branch_delay_filled = 1; | |
1112 | /* Clear lower 23 bits of context. */ | |
1113 | uasm_i_dins(p, ptr, 0, 0, 23); | |
1114 | } | |
1115 | } else { | |
1116 | if (pgd_reg != -1) | |
7777b939 | 1117 | UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); |
2c8c53e2 DD |
1118 | else |
1119 | UASM_i_MFC0(p, ptr, C0_CONTEXT); | |
1120 | ||
1121 | UASM_i_MFC0(p, tmp, C0_BADVADDR); | |
1122 | ||
7777b939 J |
1123 | if (c0_scratch_reg >= 0) |
1124 | UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); | |
2c8c53e2 DD |
1125 | else |
1126 | UASM_i_SW(p, scratch, scratchpad_offset(0), 0); | |
1127 | ||
1128 | if (pgd_reg == -1) | |
1129 | /* Clear lower 23 bits of context. */ | |
1130 | uasm_i_dins(p, ptr, 0, 0, 23); | |
1131 | ||
1132 | uasm_il_bltz(p, r, tmp, label_vmalloc); | |
1133 | } | |
1134 | ||
1135 | if (pgd_reg == -1) { | |
1136 | vmalloc_branch_delay_filled = 1; | |
70342287 | 1137 | /* 1 0 1 0 1 << 6 xkphys cached */ |
2c8c53e2 DD |
1138 | uasm_i_ori(p, ptr, ptr, 0x540); |
1139 | uasm_i_drotr(p, ptr, ptr, 11); | |
1140 | } | |
1141 | ||
1142 | #ifdef __PAGETABLE_PMD_FOLDED | |
1143 | #define LOC_PTEP scratch | |
1144 | #else | |
1145 | #define LOC_PTEP ptr | |
1146 | #endif | |
1147 | ||
1148 | if (!vmalloc_branch_delay_filled) | |
1149 | /* get pgd offset in bytes */ | |
1150 | uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); | |
1151 | ||
1152 | uasm_l_vmalloc_done(l, *p); | |
1153 | ||
1154 | /* | |
70342287 RB |
1155 | * tmp ptr |
1156 | * fall-through case = badvaddr *pgd_current | |
1157 | * vmalloc case = badvaddr swapper_pg_dir | |
2c8c53e2 DD |
1158 | */ |
1159 | ||
1160 | if (vmalloc_branch_delay_filled) | |
1161 | /* get pgd offset in bytes */ | |
1162 | uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); | |
1163 | ||
1164 | #ifdef __PAGETABLE_PMD_FOLDED | |
1165 | GET_CONTEXT(p, tmp); /* get context reg */ | |
1166 | #endif | |
1167 | uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3); | |
1168 | ||
1169 | if (use_lwx_insns()) { | |
1170 | UASM_i_LWX(p, LOC_PTEP, scratch, ptr); | |
1171 | } else { | |
1172 | uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */ | |
1173 | uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */ | |
1174 | } | |
1175 | ||
1176 | #ifndef __PAGETABLE_PMD_FOLDED | |
1177 | /* get pmd offset in bytes */ | |
1178 | uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3); | |
1179 | uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3); | |
1180 | GET_CONTEXT(p, tmp); /* get context reg */ | |
1181 | ||
1182 | if (use_lwx_insns()) { | |
1183 | UASM_i_LWX(p, scratch, scratch, ptr); | |
1184 | } else { | |
1185 | uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */ | |
1186 | UASM_i_LW(p, scratch, 0, ptr); | |
1187 | } | |
1188 | #endif | |
1189 | /* Adjust the context during the load latency. */ | |
1190 | build_adjust_context(p, tmp); | |
1191 | ||
aa1762f4 | 1192 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
2c8c53e2 DD |
1193 | uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update); |
1194 | /* | |
1195 | * The in the LWX case we don't want to do the load in the | |
70342287 | 1196 | * delay slot. It cannot issue in the same cycle and may be |
2c8c53e2 DD |
1197 | * speculative and unneeded. |
1198 | */ | |
1199 | if (use_lwx_insns()) | |
1200 | uasm_i_nop(p); | |
aa1762f4 | 1201 | #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ |
2c8c53e2 DD |
1202 | |
1203 | ||
1204 | /* build_update_entries */ | |
1205 | if (use_lwx_insns()) { | |
1206 | even = ptr; | |
1207 | odd = tmp; | |
1208 | UASM_i_LWX(p, even, scratch, tmp); | |
1209 | UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t)); | |
1210 | UASM_i_LWX(p, odd, scratch, tmp); | |
1211 | } else { | |
1212 | UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */ | |
1213 | even = tmp; | |
1214 | odd = ptr; | |
1215 | UASM_i_LW(p, even, 0, ptr); /* get even pte */ | |
1216 | UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */ | |
1217 | } | |
05857c64 | 1218 | if (cpu_has_rixi) { |
748e787e | 1219 | uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL)); |
2c8c53e2 | 1220 | UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ |
748e787e | 1221 | uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL)); |
2c8c53e2 DD |
1222 | } else { |
1223 | uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL)); | |
1224 | UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ | |
1225 | uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL)); | |
1226 | } | |
1227 | UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */ | |
1228 | ||
7777b939 J |
1229 | if (c0_scratch_reg >= 0) { |
1230 | UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg); | |
2c8c53e2 DD |
1231 | build_tlb_write_entry(p, l, r, tlb_random); |
1232 | uasm_l_leave(l, *p); | |
1233 | rv.restore_scratch = 1; | |
1234 | } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) { | |
1235 | build_tlb_write_entry(p, l, r, tlb_random); | |
1236 | uasm_l_leave(l, *p); | |
1237 | UASM_i_LW(p, scratch, scratchpad_offset(0), 0); | |
1238 | } else { | |
1239 | UASM_i_LW(p, scratch, scratchpad_offset(0), 0); | |
1240 | build_tlb_write_entry(p, l, r, tlb_random); | |
1241 | uasm_l_leave(l, *p); | |
1242 | rv.restore_scratch = 1; | |
1243 | } | |
1244 | ||
1245 | uasm_i_eret(p); /* return from trap */ | |
1246 | ||
1247 | return rv; | |
1248 | } | |
1249 | ||
e6f72d3a DD |
1250 | /* |
1251 | * For a 64-bit kernel, we are using the 64-bit XTLB refill exception | |
1252 | * because EXL == 0. If we wrap, we can also use the 32 instruction | |
1253 | * slots before the XTLB refill exception handler which belong to the | |
1254 | * unused TLB refill exception. | |
1255 | */ | |
1256 | #define MIPS64_REFILL_INSNS 32 | |
1257 | ||
078a55fc | 1258 | static void build_r4000_tlb_refill_handler(void) |
1da177e4 LT |
1259 | { |
1260 | u32 *p = tlb_handler; | |
e30ec452 TS |
1261 | struct uasm_label *l = labels; |
1262 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1263 | u32 *f; |
1264 | unsigned int final_len; | |
4a9040f4 RB |
1265 | struct mips_huge_tlb_info htlb_info __maybe_unused; |
1266 | enum vmalloc64_mode vmalloc_mode __maybe_unused; | |
18280eda | 1267 | |
1da177e4 LT |
1268 | memset(tlb_handler, 0, sizeof(tlb_handler)); |
1269 | memset(labels, 0, sizeof(labels)); | |
1270 | memset(relocs, 0, sizeof(relocs)); | |
1271 | memset(final_handler, 0, sizeof(final_handler)); | |
1272 | ||
18280eda | 1273 | if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) { |
2c8c53e2 DD |
1274 | htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1, |
1275 | scratch_reg); | |
1276 | vmalloc_mode = refill_scratch; | |
1277 | } else { | |
1278 | htlb_info.huge_pte = K0; | |
1279 | htlb_info.restore_scratch = 0; | |
9e0f162a | 1280 | htlb_info.need_reload_pte = true; |
2c8c53e2 DD |
1281 | vmalloc_mode = refill_noscratch; |
1282 | /* | |
1283 | * create the plain linear handler | |
1284 | */ | |
1285 | if (bcm1250_m3_war()) { | |
1286 | unsigned int segbits = 44; | |
1287 | ||
1288 | uasm_i_dmfc0(&p, K0, C0_BADVADDR); | |
1289 | uasm_i_dmfc0(&p, K1, C0_ENTRYHI); | |
1290 | uasm_i_xor(&p, K0, K0, K1); | |
1291 | uasm_i_dsrl_safe(&p, K1, K0, 62); | |
1292 | uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); | |
1293 | uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); | |
1294 | uasm_i_or(&p, K0, K0, K1); | |
1295 | uasm_il_bnez(&p, &r, K0, label_leave); | |
1296 | /* No need for uasm_i_nop */ | |
1297 | } | |
1da177e4 | 1298 | |
875d43e7 | 1299 | #ifdef CONFIG_64BIT |
2c8c53e2 | 1300 | build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ |
1da177e4 | 1301 | #else |
2c8c53e2 | 1302 | build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ |
1da177e4 LT |
1303 | #endif |
1304 | ||
aa1762f4 | 1305 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
2c8c53e2 | 1306 | build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update); |
fd062c84 DD |
1307 | #endif |
1308 | ||
2c8c53e2 DD |
1309 | build_get_ptep(&p, K0, K1); |
1310 | build_update_entries(&p, K0, K1); | |
1311 | build_tlb_write_entry(&p, &l, &r, tlb_random); | |
1312 | uasm_l_leave(&l, p); | |
1313 | uasm_i_eret(&p); /* return from trap */ | |
1314 | } | |
aa1762f4 | 1315 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 | 1316 | uasm_l_tlb_huge_update(&l, p); |
9e0f162a DD |
1317 | if (htlb_info.need_reload_pte) |
1318 | UASM_i_LW(&p, htlb_info.huge_pte, 0, K1); | |
2c8c53e2 DD |
1319 | build_huge_update_entries(&p, htlb_info.huge_pte, K1); |
1320 | build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random, | |
1321 | htlb_info.restore_scratch); | |
fd062c84 DD |
1322 | #endif |
1323 | ||
875d43e7 | 1324 | #ifdef CONFIG_64BIT |
2c8c53e2 | 1325 | build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode); |
1da177e4 LT |
1326 | #endif |
1327 | ||
1328 | /* | |
1329 | * Overflow check: For the 64bit handler, we need at least one | |
1330 | * free instruction slot for the wrap-around branch. In worst | |
1331 | * case, if the intended insertion point is a delay slot, we | |
4b3f686d | 1332 | * need three, with the second nop'ed and the third being |
1da177e4 LT |
1333 | * unused. |
1334 | */ | |
14bd8c08 RB |
1335 | switch (boot_cpu_type()) { |
1336 | default: | |
1337 | if (sizeof(long) == 4) { | |
1338 | case CPU_LOONGSON2: | |
1339 | /* Loongson2 ebase is different than r4k, we have more space */ | |
1340 | if ((p - tlb_handler) > 64) | |
1341 | panic("TLB refill handler space exceeded"); | |
95affdda | 1342 | /* |
14bd8c08 | 1343 | * Now fold the handler in the TLB refill handler space. |
95affdda | 1344 | */ |
14bd8c08 RB |
1345 | f = final_handler; |
1346 | /* Simplest case, just copy the handler. */ | |
1347 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); | |
1348 | final_len = p - tlb_handler; | |
1349 | break; | |
1350 | } else { | |
1351 | if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1) | |
1352 | || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3) | |
1353 | && uasm_insn_has_bdelay(relocs, | |
1354 | tlb_handler + MIPS64_REFILL_INSNS - 3))) | |
1355 | panic("TLB refill handler space exceeded"); | |
95affdda | 1356 | /* |
14bd8c08 | 1357 | * Now fold the handler in the TLB refill handler space. |
95affdda | 1358 | */ |
14bd8c08 RB |
1359 | f = final_handler + MIPS64_REFILL_INSNS; |
1360 | if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) { | |
1361 | /* Just copy the handler. */ | |
1362 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); | |
1363 | final_len = p - tlb_handler; | |
1364 | } else { | |
1365 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT | |
1366 | const enum label_id ls = label_tlb_huge_update; | |
1367 | #else | |
1368 | const enum label_id ls = label_vmalloc; | |
1369 | #endif | |
1370 | u32 *split; | |
1371 | int ov = 0; | |
1372 | int i; | |
1373 | ||
1374 | for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++) | |
1375 | ; | |
1376 | BUG_ON(i == ARRAY_SIZE(labels)); | |
1377 | split = labels[i].addr; | |
1378 | ||
1379 | /* | |
1380 | * See if we have overflown one way or the other. | |
1381 | */ | |
1382 | if (split > tlb_handler + MIPS64_REFILL_INSNS || | |
1383 | split < p - MIPS64_REFILL_INSNS) | |
1384 | ov = 1; | |
1385 | ||
1386 | if (ov) { | |
1387 | /* | |
1388 | * Split two instructions before the end. One | |
1389 | * for the branch and one for the instruction | |
1390 | * in the delay slot. | |
1391 | */ | |
1392 | split = tlb_handler + MIPS64_REFILL_INSNS - 2; | |
1393 | ||
1394 | /* | |
1395 | * If the branch would fall in a delay slot, | |
1396 | * we must back up an additional instruction | |
1397 | * so that it is no longer in a delay slot. | |
1398 | */ | |
1399 | if (uasm_insn_has_bdelay(relocs, split - 1)) | |
1400 | split--; | |
1401 | } | |
1402 | /* Copy first part of the handler. */ | |
1403 | uasm_copy_handler(relocs, labels, tlb_handler, split, f); | |
1404 | f += split - tlb_handler; | |
1405 | ||
1406 | if (ov) { | |
1407 | /* Insert branch. */ | |
1408 | uasm_l_split(&l, final_handler); | |
1409 | uasm_il_b(&f, &r, label_split); | |
1410 | if (uasm_insn_has_bdelay(relocs, split)) | |
1411 | uasm_i_nop(&f); | |
1412 | else { | |
1413 | uasm_copy_handler(relocs, labels, | |
1414 | split, split + 1, f); | |
1415 | uasm_move_labels(labels, f, f + 1, -1); | |
1416 | f++; | |
1417 | split++; | |
1418 | } | |
1419 | } | |
1420 | ||
1421 | /* Copy the rest of the handler. */ | |
1422 | uasm_copy_handler(relocs, labels, split, p, final_handler); | |
1423 | final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) + | |
1424 | (p - split); | |
95affdda | 1425 | } |
1da177e4 | 1426 | } |
14bd8c08 | 1427 | break; |
1da177e4 | 1428 | } |
1da177e4 | 1429 | |
e30ec452 TS |
1430 | uasm_resolve_relocs(relocs, labels); |
1431 | pr_debug("Wrote TLB refill handler (%u instructions).\n", | |
1432 | final_len); | |
1da177e4 | 1433 | |
91b05e67 | 1434 | memcpy((void *)ebase, final_handler, 0x100); |
1062080a | 1435 | local_flush_icache_range(ebase, ebase + 0x100); |
92b1e6a6 | 1436 | |
a2c763e0 | 1437 | dump_handler("r4000_tlb_refill", (u32 *)ebase, 64); |
1da177e4 LT |
1438 | } |
1439 | ||
6ba045f9 J |
1440 | extern u32 handle_tlbl[], handle_tlbl_end[]; |
1441 | extern u32 handle_tlbs[], handle_tlbs_end[]; | |
1442 | extern u32 handle_tlbm[], handle_tlbm_end[]; | |
7bb39409 SH |
1443 | extern u32 tlbmiss_handler_setup_pgd_start[], tlbmiss_handler_setup_pgd[]; |
1444 | extern u32 tlbmiss_handler_setup_pgd_end[]; | |
3d8bfdd0 | 1445 | |
f4ae17aa | 1446 | static void build_setup_pgd(void) |
3d8bfdd0 DD |
1447 | { |
1448 | const int a0 = 4; | |
f4ae17aa J |
1449 | const int __maybe_unused a1 = 5; |
1450 | const int __maybe_unused a2 = 6; | |
7bb39409 | 1451 | u32 *p = tlbmiss_handler_setup_pgd_start; |
6ba045f9 | 1452 | const int tlbmiss_handler_setup_pgd_size = |
7bb39409 | 1453 | tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd_start; |
f4ae17aa J |
1454 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
1455 | long pgdc = (long)pgd_current; | |
1456 | #endif | |
3d8bfdd0 | 1457 | |
6ba045f9 J |
1458 | memset(tlbmiss_handler_setup_pgd, 0, tlbmiss_handler_setup_pgd_size * |
1459 | sizeof(tlbmiss_handler_setup_pgd[0])); | |
3d8bfdd0 DD |
1460 | memset(labels, 0, sizeof(labels)); |
1461 | memset(relocs, 0, sizeof(relocs)); | |
3d8bfdd0 | 1462 | pgd_reg = allocate_kscratch(); |
f4ae17aa | 1463 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
3d8bfdd0 | 1464 | if (pgd_reg == -1) { |
f4ae17aa J |
1465 | struct uasm_label *l = labels; |
1466 | struct uasm_reloc *r = relocs; | |
1467 | ||
3d8bfdd0 DD |
1468 | /* PGD << 11 in c0_Context */ |
1469 | /* | |
1470 | * If it is a ckseg0 address, convert to a physical | |
1471 | * address. Shifting right by 29 and adding 4 will | |
1472 | * result in zero for these addresses. | |
1473 | * | |
1474 | */ | |
1475 | UASM_i_SRA(&p, a1, a0, 29); | |
1476 | UASM_i_ADDIU(&p, a1, a1, 4); | |
1477 | uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1); | |
1478 | uasm_i_nop(&p); | |
1479 | uasm_i_dinsm(&p, a0, 0, 29, 64 - 29); | |
1480 | uasm_l_tlbl_goaround1(&l, p); | |
1481 | UASM_i_SLL(&p, a0, a0, 11); | |
1482 | uasm_i_jr(&p, 31); | |
1483 | UASM_i_MTC0(&p, a0, C0_CONTEXT); | |
1484 | } else { | |
1485 | /* PGD in c0_KScratch */ | |
1486 | uasm_i_jr(&p, 31); | |
7777b939 | 1487 | UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); |
3d8bfdd0 | 1488 | } |
f4ae17aa J |
1489 | #else |
1490 | #ifdef CONFIG_SMP | |
1491 | /* Save PGD to pgd_current[smp_processor_id()] */ | |
1492 | UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG); | |
1493 | UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT); | |
1494 | UASM_i_LA_mostly(&p, a2, pgdc); | |
1495 | UASM_i_ADDU(&p, a2, a2, a1); | |
1496 | UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); | |
1497 | #else | |
1498 | UASM_i_LA_mostly(&p, a2, pgdc); | |
1499 | UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); | |
1500 | #endif /* SMP */ | |
1501 | uasm_i_jr(&p, 31); | |
1502 | ||
1503 | /* if pgd_reg is allocated, save PGD also to scratch register */ | |
1504 | if (pgd_reg != -1) | |
1505 | UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); | |
1506 | else | |
1507 | uasm_i_nop(&p); | |
1508 | #endif | |
6ba045f9 J |
1509 | if (p >= tlbmiss_handler_setup_pgd_end) |
1510 | panic("tlbmiss_handler_setup_pgd space exceeded"); | |
1511 | ||
3d8bfdd0 | 1512 | uasm_resolve_relocs(relocs, labels); |
6ba045f9 J |
1513 | pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n", |
1514 | (unsigned int)(p - tlbmiss_handler_setup_pgd)); | |
3d8bfdd0 | 1515 | |
6ba045f9 J |
1516 | dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd, |
1517 | tlbmiss_handler_setup_pgd_size); | |
3d8bfdd0 | 1518 | } |
1da177e4 | 1519 | |
078a55fc | 1520 | static void |
bd1437e4 | 1521 | iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) |
1da177e4 LT |
1522 | { |
1523 | #ifdef CONFIG_SMP | |
34adb28d | 1524 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
1da177e4 | 1525 | if (cpu_has_64bits) |
e30ec452 | 1526 | uasm_i_lld(p, pte, 0, ptr); |
1da177e4 LT |
1527 | else |
1528 | # endif | |
e30ec452 | 1529 | UASM_i_LL(p, pte, 0, ptr); |
1da177e4 | 1530 | #else |
34adb28d | 1531 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
1da177e4 | 1532 | if (cpu_has_64bits) |
e30ec452 | 1533 | uasm_i_ld(p, pte, 0, ptr); |
1da177e4 LT |
1534 | else |
1535 | # endif | |
e30ec452 | 1536 | UASM_i_LW(p, pte, 0, ptr); |
1da177e4 LT |
1537 | #endif |
1538 | } | |
1539 | ||
078a55fc | 1540 | static void |
e30ec452 | 1541 | iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, |
63b2d2f4 | 1542 | unsigned int mode) |
1da177e4 | 1543 | { |
34adb28d | 1544 | #ifdef CONFIG_PHYS_ADDR_T_64BIT |
63b2d2f4 | 1545 | unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); |
63b2d2f4 | 1546 | |
c5b36783 SH |
1547 | if (!cpu_has_64bits) { |
1548 | const int scratch = 1; /* Our extra working register */ | |
1549 | ||
1550 | uasm_i_lui(p, scratch, (mode >> 16)); | |
1551 | uasm_i_or(p, pte, pte, scratch); | |
1552 | } else | |
1553 | #endif | |
e30ec452 | 1554 | uasm_i_ori(p, pte, pte, mode); |
1da177e4 | 1555 | #ifdef CONFIG_SMP |
34adb28d | 1556 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
1da177e4 | 1557 | if (cpu_has_64bits) |
e30ec452 | 1558 | uasm_i_scd(p, pte, 0, ptr); |
1da177e4 LT |
1559 | else |
1560 | # endif | |
e30ec452 | 1561 | UASM_i_SC(p, pte, 0, ptr); |
1da177e4 LT |
1562 | |
1563 | if (r10000_llsc_war()) | |
e30ec452 | 1564 | uasm_il_beqzl(p, r, pte, label_smp_pgtable_change); |
1da177e4 | 1565 | else |
e30ec452 | 1566 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); |
1da177e4 | 1567 | |
34adb28d | 1568 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
1da177e4 | 1569 | if (!cpu_has_64bits) { |
e30ec452 TS |
1570 | /* no uasm_i_nop needed */ |
1571 | uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr); | |
1572 | uasm_i_ori(p, pte, pte, hwmode); | |
1573 | uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr); | |
1574 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); | |
1575 | /* no uasm_i_nop needed */ | |
1576 | uasm_i_lw(p, pte, 0, ptr); | |
1da177e4 | 1577 | } else |
e30ec452 | 1578 | uasm_i_nop(p); |
1da177e4 | 1579 | # else |
e30ec452 | 1580 | uasm_i_nop(p); |
1da177e4 LT |
1581 | # endif |
1582 | #else | |
34adb28d | 1583 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
1da177e4 | 1584 | if (cpu_has_64bits) |
e30ec452 | 1585 | uasm_i_sd(p, pte, 0, ptr); |
1da177e4 LT |
1586 | else |
1587 | # endif | |
e30ec452 | 1588 | UASM_i_SW(p, pte, 0, ptr); |
1da177e4 | 1589 | |
34adb28d | 1590 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
1da177e4 | 1591 | if (!cpu_has_64bits) { |
e30ec452 TS |
1592 | uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr); |
1593 | uasm_i_ori(p, pte, pte, hwmode); | |
1594 | uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr); | |
1595 | uasm_i_lw(p, pte, 0, ptr); | |
1da177e4 LT |
1596 | } |
1597 | # endif | |
1598 | #endif | |
1599 | } | |
1600 | ||
1601 | /* | |
1602 | * Check if PTE is present, if not then jump to LABEL. PTR points to | |
1603 | * the page table where this PTE is located, PTE will be re-loaded | |
1604 | * with it's original value. | |
1605 | */ | |
078a55fc | 1606 | static void |
bd1437e4 | 1607 | build_pte_present(u32 **p, struct uasm_reloc **r, |
bf28607f | 1608 | int pte, int ptr, int scratch, enum label_id lid) |
1da177e4 | 1609 | { |
bf28607f DD |
1610 | int t = scratch >= 0 ? scratch : pte; |
1611 | ||
05857c64 | 1612 | if (cpu_has_rixi) { |
cc33ae43 DD |
1613 | if (use_bbit_insns()) { |
1614 | uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); | |
1615 | uasm_i_nop(p); | |
1616 | } else { | |
c5b36783 SH |
1617 | uasm_i_srl(p, t, pte, _PAGE_PRESENT_SHIFT); |
1618 | uasm_i_andi(p, t, t, 1); | |
bf28607f DD |
1619 | uasm_il_beqz(p, r, t, lid); |
1620 | if (pte == t) | |
1621 | /* You lose the SMP race :-(*/ | |
1622 | iPTE_LW(p, pte, ptr); | |
cc33ae43 | 1623 | } |
6dd9344c | 1624 | } else { |
c5b36783 | 1625 | uasm_i_srl(p, t, pte, _PAGE_PRESENT_SHIFT); |
a3ae565a JH |
1626 | uasm_i_andi(p, t, t, |
1627 | (_PAGE_PRESENT | _PAGE_READ) >> _PAGE_PRESENT_SHIFT); | |
1628 | uasm_i_xori(p, t, t, | |
1629 | (_PAGE_PRESENT | _PAGE_READ) >> _PAGE_PRESENT_SHIFT); | |
bf28607f DD |
1630 | uasm_il_bnez(p, r, t, lid); |
1631 | if (pte == t) | |
1632 | /* You lose the SMP race :-(*/ | |
1633 | iPTE_LW(p, pte, ptr); | |
6dd9344c | 1634 | } |
1da177e4 LT |
1635 | } |
1636 | ||
1637 | /* Make PTE valid, store result in PTR. */ | |
078a55fc | 1638 | static void |
e30ec452 | 1639 | build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte, |
1da177e4 LT |
1640 | unsigned int ptr) |
1641 | { | |
63b2d2f4 TS |
1642 | unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; |
1643 | ||
1644 | iPTE_SW(p, r, pte, ptr, mode); | |
1da177e4 LT |
1645 | } |
1646 | ||
1647 | /* | |
1648 | * Check if PTE can be written to, if not branch to LABEL. Regardless | |
1649 | * restore PTE with value from PTR when done. | |
1650 | */ | |
078a55fc | 1651 | static void |
bd1437e4 | 1652 | build_pte_writable(u32 **p, struct uasm_reloc **r, |
bf28607f DD |
1653 | unsigned int pte, unsigned int ptr, int scratch, |
1654 | enum label_id lid) | |
1da177e4 | 1655 | { |
bf28607f DD |
1656 | int t = scratch >= 0 ? scratch : pte; |
1657 | ||
c5b36783 | 1658 | uasm_i_srl(p, t, pte, _PAGE_PRESENT_SHIFT); |
a3ae565a JH |
1659 | uasm_i_andi(p, t, t, |
1660 | (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT); | |
1661 | uasm_i_xori(p, t, t, | |
1662 | (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT); | |
bf28607f DD |
1663 | uasm_il_bnez(p, r, t, lid); |
1664 | if (pte == t) | |
1665 | /* You lose the SMP race :-(*/ | |
cc33ae43 | 1666 | iPTE_LW(p, pte, ptr); |
bf28607f DD |
1667 | else |
1668 | uasm_i_nop(p); | |
1da177e4 LT |
1669 | } |
1670 | ||
1671 | /* Make PTE writable, update software status bits as well, then store | |
1672 | * at PTR. | |
1673 | */ | |
078a55fc | 1674 | static void |
e30ec452 | 1675 | build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte, |
1da177e4 LT |
1676 | unsigned int ptr) |
1677 | { | |
63b2d2f4 TS |
1678 | unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID |
1679 | | _PAGE_DIRTY); | |
1680 | ||
1681 | iPTE_SW(p, r, pte, ptr, mode); | |
1da177e4 LT |
1682 | } |
1683 | ||
1684 | /* | |
1685 | * Check if PTE can be modified, if not branch to LABEL. Regardless | |
1686 | * restore PTE with value from PTR when done. | |
1687 | */ | |
078a55fc | 1688 | static void |
bd1437e4 | 1689 | build_pte_modifiable(u32 **p, struct uasm_reloc **r, |
bf28607f DD |
1690 | unsigned int pte, unsigned int ptr, int scratch, |
1691 | enum label_id lid) | |
1da177e4 | 1692 | { |
cc33ae43 DD |
1693 | if (use_bbit_insns()) { |
1694 | uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid); | |
1695 | uasm_i_nop(p); | |
1696 | } else { | |
bf28607f | 1697 | int t = scratch >= 0 ? scratch : pte; |
c5b36783 SH |
1698 | uasm_i_srl(p, t, pte, _PAGE_WRITE_SHIFT); |
1699 | uasm_i_andi(p, t, t, 1); | |
bf28607f DD |
1700 | uasm_il_beqz(p, r, t, lid); |
1701 | if (pte == t) | |
1702 | /* You lose the SMP race :-(*/ | |
1703 | iPTE_LW(p, pte, ptr); | |
cc33ae43 | 1704 | } |
1da177e4 LT |
1705 | } |
1706 | ||
82622284 | 1707 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
3d8bfdd0 DD |
1708 | |
1709 | ||
1da177e4 LT |
1710 | /* |
1711 | * R3000 style TLB load/store/modify handlers. | |
1712 | */ | |
1713 | ||
fded2e50 MR |
1714 | /* |
1715 | * This places the pte into ENTRYLO0 and writes it with tlbwi. | |
1716 | * Then it returns. | |
1717 | */ | |
078a55fc | 1718 | static void |
fded2e50 | 1719 | build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) |
1da177e4 | 1720 | { |
e30ec452 TS |
1721 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ |
1722 | uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ | |
1723 | uasm_i_tlbwi(p); | |
1724 | uasm_i_jr(p, tmp); | |
1725 | uasm_i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1726 | } |
1727 | ||
1728 | /* | |
fded2e50 MR |
1729 | * This places the pte into ENTRYLO0 and writes it with tlbwi |
1730 | * or tlbwr as appropriate. This is because the index register | |
1731 | * may have the probe fail bit set as a result of a trap on a | |
1732 | * kseg2 access, i.e. without refill. Then it returns. | |
1da177e4 | 1733 | */ |
078a55fc | 1734 | static void |
e30ec452 TS |
1735 | build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l, |
1736 | struct uasm_reloc **r, unsigned int pte, | |
1737 | unsigned int tmp) | |
1738 | { | |
1739 | uasm_i_mfc0(p, tmp, C0_INDEX); | |
1740 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ | |
1741 | uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ | |
1742 | uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */ | |
1743 | uasm_i_tlbwi(p); /* cp0 delay */ | |
1744 | uasm_i_jr(p, tmp); | |
1745 | uasm_i_rfe(p); /* branch delay */ | |
1746 | uasm_l_r3000_write_probe_fail(l, *p); | |
1747 | uasm_i_tlbwr(p); /* cp0 delay */ | |
1748 | uasm_i_jr(p, tmp); | |
1749 | uasm_i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1750 | } |
1751 | ||
078a55fc | 1752 | static void |
1da177e4 LT |
1753 | build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, |
1754 | unsigned int ptr) | |
1755 | { | |
1756 | long pgdc = (long)pgd_current; | |
1757 | ||
e30ec452 TS |
1758 | uasm_i_mfc0(p, pte, C0_BADVADDR); |
1759 | uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */ | |
1760 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1761 | uasm_i_srl(p, pte, pte, 22); /* load delay */ | |
1762 | uasm_i_sll(p, pte, pte, 2); | |
1763 | uasm_i_addu(p, ptr, ptr, pte); | |
1764 | uasm_i_mfc0(p, pte, C0_CONTEXT); | |
1765 | uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */ | |
1766 | uasm_i_andi(p, pte, pte, 0xffc); /* load delay */ | |
1767 | uasm_i_addu(p, ptr, ptr, pte); | |
1768 | uasm_i_lw(p, pte, 0, ptr); | |
1769 | uasm_i_tlbp(p); /* load delay */ | |
1da177e4 LT |
1770 | } |
1771 | ||
078a55fc | 1772 | static void build_r3000_tlb_load_handler(void) |
1da177e4 LT |
1773 | { |
1774 | u32 *p = handle_tlbl; | |
6ba045f9 | 1775 | const int handle_tlbl_size = handle_tlbl_end - handle_tlbl; |
e30ec452 TS |
1776 | struct uasm_label *l = labels; |
1777 | struct uasm_reloc *r = relocs; | |
1da177e4 | 1778 | |
6ba045f9 | 1779 | memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0])); |
1da177e4 LT |
1780 | memset(labels, 0, sizeof(labels)); |
1781 | memset(relocs, 0, sizeof(relocs)); | |
1782 | ||
1783 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
bf28607f | 1784 | build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl); |
e30ec452 | 1785 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1786 | build_make_valid(&p, &r, K0, K1); |
fded2e50 | 1787 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 | 1788 | |
e30ec452 TS |
1789 | uasm_l_nopage_tlbl(&l, p); |
1790 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); | |
1791 | uasm_i_nop(&p); | |
1da177e4 | 1792 | |
6ba045f9 | 1793 | if (p >= handle_tlbl_end) |
1da177e4 LT |
1794 | panic("TLB load handler fastpath space exceeded"); |
1795 | ||
e30ec452 TS |
1796 | uasm_resolve_relocs(relocs, labels); |
1797 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", | |
1798 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 1799 | |
6ba045f9 | 1800 | dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_size); |
1da177e4 LT |
1801 | } |
1802 | ||
078a55fc | 1803 | static void build_r3000_tlb_store_handler(void) |
1da177e4 LT |
1804 | { |
1805 | u32 *p = handle_tlbs; | |
6ba045f9 | 1806 | const int handle_tlbs_size = handle_tlbs_end - handle_tlbs; |
e30ec452 TS |
1807 | struct uasm_label *l = labels; |
1808 | struct uasm_reloc *r = relocs; | |
1da177e4 | 1809 | |
6ba045f9 | 1810 | memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0])); |
1da177e4 LT |
1811 | memset(labels, 0, sizeof(labels)); |
1812 | memset(relocs, 0, sizeof(relocs)); | |
1813 | ||
1814 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
bf28607f | 1815 | build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs); |
e30ec452 | 1816 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1817 | build_make_write(&p, &r, K0, K1); |
fded2e50 | 1818 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 | 1819 | |
e30ec452 TS |
1820 | uasm_l_nopage_tlbs(&l, p); |
1821 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1822 | uasm_i_nop(&p); | |
1da177e4 | 1823 | |
afc813ae | 1824 | if (p >= handle_tlbs_end) |
1da177e4 LT |
1825 | panic("TLB store handler fastpath space exceeded"); |
1826 | ||
e30ec452 TS |
1827 | uasm_resolve_relocs(relocs, labels); |
1828 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", | |
1829 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 1830 | |
6ba045f9 | 1831 | dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_size); |
1da177e4 LT |
1832 | } |
1833 | ||
078a55fc | 1834 | static void build_r3000_tlb_modify_handler(void) |
1da177e4 LT |
1835 | { |
1836 | u32 *p = handle_tlbm; | |
6ba045f9 | 1837 | const int handle_tlbm_size = handle_tlbm_end - handle_tlbm; |
e30ec452 TS |
1838 | struct uasm_label *l = labels; |
1839 | struct uasm_reloc *r = relocs; | |
1da177e4 | 1840 | |
6ba045f9 | 1841 | memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0])); |
1da177e4 LT |
1842 | memset(labels, 0, sizeof(labels)); |
1843 | memset(relocs, 0, sizeof(relocs)); | |
1844 | ||
1845 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
d954ffe3 | 1846 | build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm); |
e30ec452 | 1847 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1848 | build_make_write(&p, &r, K0, K1); |
fded2e50 | 1849 | build_r3000_pte_reload_tlbwi(&p, K0, K1); |
1da177e4 | 1850 | |
e30ec452 TS |
1851 | uasm_l_nopage_tlbm(&l, p); |
1852 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1853 | uasm_i_nop(&p); | |
1da177e4 | 1854 | |
6ba045f9 | 1855 | if (p >= handle_tlbm_end) |
1da177e4 LT |
1856 | panic("TLB modify handler fastpath space exceeded"); |
1857 | ||
e30ec452 TS |
1858 | uasm_resolve_relocs(relocs, labels); |
1859 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", | |
1860 | (unsigned int)(p - handle_tlbm)); | |
1da177e4 | 1861 | |
6ba045f9 | 1862 | dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_size); |
1da177e4 | 1863 | } |
82622284 | 1864 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ |
1da177e4 LT |
1865 | |
1866 | /* | |
1867 | * R4000 style TLB load/store/modify handlers. | |
1868 | */ | |
078a55fc | 1869 | static struct work_registers |
e30ec452 | 1870 | build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l, |
bf28607f | 1871 | struct uasm_reloc **r) |
1da177e4 | 1872 | { |
bf28607f DD |
1873 | struct work_registers wr = build_get_work_registers(p); |
1874 | ||
875d43e7 | 1875 | #ifdef CONFIG_64BIT |
bf28607f | 1876 | build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */ |
1da177e4 | 1877 | #else |
bf28607f | 1878 | build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */ |
1da177e4 LT |
1879 | #endif |
1880 | ||
aa1762f4 | 1881 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
1882 | /* |
1883 | * For huge tlb entries, pmd doesn't contain an address but | |
1884 | * instead contains the tlb pte. Check the PAGE_HUGE bit and | |
1885 | * see if we need to jump to huge tlb processing. | |
1886 | */ | |
bf28607f | 1887 | build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update); |
fd062c84 DD |
1888 | #endif |
1889 | ||
bf28607f DD |
1890 | UASM_i_MFC0(p, wr.r1, C0_BADVADDR); |
1891 | UASM_i_LW(p, wr.r2, 0, wr.r2); | |
1892 | UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); | |
1893 | uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2); | |
1894 | UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1); | |
1da177e4 LT |
1895 | |
1896 | #ifdef CONFIG_SMP | |
e30ec452 TS |
1897 | uasm_l_smp_pgtable_change(l, *p); |
1898 | #endif | |
bf28607f | 1899 | iPTE_LW(p, wr.r1, wr.r2); /* get even pte */ |
070e76cb | 1900 | if (!m4kc_tlbp_war()) { |
8df5beac | 1901 | build_tlb_probe_entry(p); |
070e76cb LY |
1902 | if (cpu_has_htw) { |
1903 | /* race condition happens, leaving */ | |
1904 | uasm_i_ehb(p); | |
1905 | uasm_i_mfc0(p, wr.r3, C0_INDEX); | |
1906 | uasm_il_bltz(p, r, wr.r3, label_leave); | |
1907 | uasm_i_nop(p); | |
1908 | } | |
1909 | } | |
bf28607f | 1910 | return wr; |
1da177e4 LT |
1911 | } |
1912 | ||
078a55fc | 1913 | static void |
e30ec452 TS |
1914 | build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, |
1915 | struct uasm_reloc **r, unsigned int tmp, | |
1da177e4 LT |
1916 | unsigned int ptr) |
1917 | { | |
e30ec452 TS |
1918 | uasm_i_ori(p, ptr, ptr, sizeof(pte_t)); |
1919 | uasm_i_xori(p, ptr, ptr, sizeof(pte_t)); | |
1da177e4 LT |
1920 | build_update_entries(p, tmp, ptr); |
1921 | build_tlb_write_entry(p, l, r, tlb_indexed); | |
e30ec452 | 1922 | uasm_l_leave(l, *p); |
bf28607f | 1923 | build_restore_work_registers(p); |
e30ec452 | 1924 | uasm_i_eret(p); /* return from trap */ |
1da177e4 | 1925 | |
875d43e7 | 1926 | #ifdef CONFIG_64BIT |
1ec56329 | 1927 | build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill); |
1da177e4 LT |
1928 | #endif |
1929 | } | |
1930 | ||
078a55fc | 1931 | static void build_r4000_tlb_load_handler(void) |
1da177e4 LT |
1932 | { |
1933 | u32 *p = handle_tlbl; | |
6ba045f9 | 1934 | const int handle_tlbl_size = handle_tlbl_end - handle_tlbl; |
e30ec452 TS |
1935 | struct uasm_label *l = labels; |
1936 | struct uasm_reloc *r = relocs; | |
bf28607f | 1937 | struct work_registers wr; |
1da177e4 | 1938 | |
6ba045f9 | 1939 | memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0])); |
1da177e4 LT |
1940 | memset(labels, 0, sizeof(labels)); |
1941 | memset(relocs, 0, sizeof(relocs)); | |
1942 | ||
1943 | if (bcm1250_m3_war()) { | |
3d45285d RB |
1944 | unsigned int segbits = 44; |
1945 | ||
1946 | uasm_i_dmfc0(&p, K0, C0_BADVADDR); | |
1947 | uasm_i_dmfc0(&p, K1, C0_ENTRYHI); | |
e30ec452 | 1948 | uasm_i_xor(&p, K0, K0, K1); |
3be6022c DD |
1949 | uasm_i_dsrl_safe(&p, K1, K0, 62); |
1950 | uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); | |
1951 | uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); | |
3d45285d | 1952 | uasm_i_or(&p, K0, K0, K1); |
e30ec452 TS |
1953 | uasm_il_bnez(&p, &r, K0, label_leave); |
1954 | /* No need for uasm_i_nop */ | |
1da177e4 LT |
1955 | } |
1956 | ||
bf28607f DD |
1957 | wr = build_r4000_tlbchange_handler_head(&p, &l, &r); |
1958 | build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); | |
8df5beac MR |
1959 | if (m4kc_tlbp_war()) |
1960 | build_tlb_probe_entry(&p); | |
6dd9344c | 1961 | |
5890f70f | 1962 | if (cpu_has_rixi && !cpu_has_rixiex) { |
6dd9344c DD |
1963 | /* |
1964 | * If the page is not _PAGE_VALID, RI or XI could not | |
1965 | * have triggered it. Skip the expensive test.. | |
1966 | */ | |
cc33ae43 | 1967 | if (use_bbit_insns()) { |
bf28607f | 1968 | uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), |
cc33ae43 DD |
1969 | label_tlbl_goaround1); |
1970 | } else { | |
bf28607f DD |
1971 | uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); |
1972 | uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1); | |
cc33ae43 | 1973 | } |
6dd9344c DD |
1974 | uasm_i_nop(&p); |
1975 | ||
1976 | uasm_i_tlbr(&p); | |
73acc7df RB |
1977 | |
1978 | switch (current_cpu_type()) { | |
1979 | default: | |
77f3ee59 | 1980 | if (cpu_has_mips_r2_exec_hazard) { |
73acc7df RB |
1981 | uasm_i_ehb(&p); |
1982 | ||
1983 | case CPU_CAVIUM_OCTEON: | |
1984 | case CPU_CAVIUM_OCTEON_PLUS: | |
1985 | case CPU_CAVIUM_OCTEON2: | |
1986 | break; | |
1987 | } | |
1988 | } | |
1989 | ||
6dd9344c | 1990 | /* Examine entrylo 0 or 1 based on ptr. */ |
cc33ae43 | 1991 | if (use_bbit_insns()) { |
bf28607f | 1992 | uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); |
cc33ae43 | 1993 | } else { |
bf28607f DD |
1994 | uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); |
1995 | uasm_i_beqz(&p, wr.r3, 8); | |
cc33ae43 | 1996 | } |
bf28607f DD |
1997 | /* load it in the delay slot*/ |
1998 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); | |
1999 | /* load it if ptr is odd */ | |
2000 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); | |
6dd9344c | 2001 | /* |
bf28607f | 2002 | * If the entryLo (now in wr.r3) is valid (bit 1), RI or |
6dd9344c DD |
2003 | * XI must have triggered it. |
2004 | */ | |
cc33ae43 | 2005 | if (use_bbit_insns()) { |
bf28607f DD |
2006 | uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl); |
2007 | uasm_i_nop(&p); | |
cc33ae43 DD |
2008 | uasm_l_tlbl_goaround1(&l, p); |
2009 | } else { | |
bf28607f DD |
2010 | uasm_i_andi(&p, wr.r3, wr.r3, 2); |
2011 | uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl); | |
2012 | uasm_i_nop(&p); | |
cc33ae43 | 2013 | } |
bf28607f | 2014 | uasm_l_tlbl_goaround1(&l, p); |
6dd9344c | 2015 | } |
bf28607f DD |
2016 | build_make_valid(&p, &r, wr.r1, wr.r2); |
2017 | build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); | |
1da177e4 | 2018 | |
aa1762f4 | 2019 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
2020 | /* |
2021 | * This is the entry point when build_r4000_tlbchange_handler_head | |
2022 | * spots a huge page. | |
2023 | */ | |
2024 | uasm_l_tlb_huge_update(&l, p); | |
bf28607f DD |
2025 | iPTE_LW(&p, wr.r1, wr.r2); |
2026 | build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); | |
fd062c84 | 2027 | build_tlb_probe_entry(&p); |
6dd9344c | 2028 | |
5890f70f | 2029 | if (cpu_has_rixi && !cpu_has_rixiex) { |
6dd9344c DD |
2030 | /* |
2031 | * If the page is not _PAGE_VALID, RI or XI could not | |
2032 | * have triggered it. Skip the expensive test.. | |
2033 | */ | |
cc33ae43 | 2034 | if (use_bbit_insns()) { |
bf28607f | 2035 | uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), |
cc33ae43 DD |
2036 | label_tlbl_goaround2); |
2037 | } else { | |
bf28607f DD |
2038 | uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); |
2039 | uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); | |
cc33ae43 | 2040 | } |
6dd9344c DD |
2041 | uasm_i_nop(&p); |
2042 | ||
2043 | uasm_i_tlbr(&p); | |
73acc7df RB |
2044 | |
2045 | switch (current_cpu_type()) { | |
2046 | default: | |
77f3ee59 | 2047 | if (cpu_has_mips_r2_exec_hazard) { |
73acc7df RB |
2048 | uasm_i_ehb(&p); |
2049 | ||
2050 | case CPU_CAVIUM_OCTEON: | |
2051 | case CPU_CAVIUM_OCTEON_PLUS: | |
2052 | case CPU_CAVIUM_OCTEON2: | |
2053 | break; | |
2054 | } | |
2055 | } | |
2056 | ||
6dd9344c | 2057 | /* Examine entrylo 0 or 1 based on ptr. */ |
cc33ae43 | 2058 | if (use_bbit_insns()) { |
bf28607f | 2059 | uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); |
cc33ae43 | 2060 | } else { |
bf28607f DD |
2061 | uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); |
2062 | uasm_i_beqz(&p, wr.r3, 8); | |
cc33ae43 | 2063 | } |
bf28607f DD |
2064 | /* load it in the delay slot*/ |
2065 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); | |
2066 | /* load it if ptr is odd */ | |
2067 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); | |
6dd9344c | 2068 | /* |
bf28607f | 2069 | * If the entryLo (now in wr.r3) is valid (bit 1), RI or |
6dd9344c DD |
2070 | * XI must have triggered it. |
2071 | */ | |
cc33ae43 | 2072 | if (use_bbit_insns()) { |
bf28607f | 2073 | uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2); |
cc33ae43 | 2074 | } else { |
bf28607f DD |
2075 | uasm_i_andi(&p, wr.r3, wr.r3, 2); |
2076 | uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); | |
cc33ae43 | 2077 | } |
0f4ccbc8 DD |
2078 | if (PM_DEFAULT_MASK == 0) |
2079 | uasm_i_nop(&p); | |
6dd9344c DD |
2080 | /* |
2081 | * We clobbered C0_PAGEMASK, restore it. On the other branch | |
2082 | * it is restored in build_huge_tlb_write_entry. | |
2083 | */ | |
bf28607f | 2084 | build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0); |
6dd9344c DD |
2085 | |
2086 | uasm_l_tlbl_goaround2(&l, p); | |
2087 | } | |
bf28607f DD |
2088 | uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID)); |
2089 | build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2); | |
fd062c84 DD |
2090 | #endif |
2091 | ||
e30ec452 | 2092 | uasm_l_nopage_tlbl(&l, p); |
bf28607f | 2093 | build_restore_work_registers(&p); |
2a0b24f5 SH |
2094 | #ifdef CONFIG_CPU_MICROMIPS |
2095 | if ((unsigned long)tlb_do_page_fault_0 & 1) { | |
2096 | uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0)); | |
2097 | uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0)); | |
2098 | uasm_i_jr(&p, K0); | |
2099 | } else | |
2100 | #endif | |
e30ec452 TS |
2101 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); |
2102 | uasm_i_nop(&p); | |
1da177e4 | 2103 | |
6ba045f9 | 2104 | if (p >= handle_tlbl_end) |
1da177e4 LT |
2105 | panic("TLB load handler fastpath space exceeded"); |
2106 | ||
e30ec452 TS |
2107 | uasm_resolve_relocs(relocs, labels); |
2108 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", | |
2109 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 2110 | |
6ba045f9 | 2111 | dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_size); |
1da177e4 LT |
2112 | } |
2113 | ||
078a55fc | 2114 | static void build_r4000_tlb_store_handler(void) |
1da177e4 LT |
2115 | { |
2116 | u32 *p = handle_tlbs; | |
6ba045f9 | 2117 | const int handle_tlbs_size = handle_tlbs_end - handle_tlbs; |
e30ec452 TS |
2118 | struct uasm_label *l = labels; |
2119 | struct uasm_reloc *r = relocs; | |
bf28607f | 2120 | struct work_registers wr; |
1da177e4 | 2121 | |
6ba045f9 | 2122 | memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0])); |
1da177e4 LT |
2123 | memset(labels, 0, sizeof(labels)); |
2124 | memset(relocs, 0, sizeof(relocs)); | |
2125 | ||
bf28607f DD |
2126 | wr = build_r4000_tlbchange_handler_head(&p, &l, &r); |
2127 | build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); | |
8df5beac MR |
2128 | if (m4kc_tlbp_war()) |
2129 | build_tlb_probe_entry(&p); | |
bf28607f DD |
2130 | build_make_write(&p, &r, wr.r1, wr.r2); |
2131 | build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); | |
1da177e4 | 2132 | |
aa1762f4 | 2133 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
2134 | /* |
2135 | * This is the entry point when | |
2136 | * build_r4000_tlbchange_handler_head spots a huge page. | |
2137 | */ | |
2138 | uasm_l_tlb_huge_update(&l, p); | |
bf28607f DD |
2139 | iPTE_LW(&p, wr.r1, wr.r2); |
2140 | build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); | |
fd062c84 | 2141 | build_tlb_probe_entry(&p); |
bf28607f | 2142 | uasm_i_ori(&p, wr.r1, wr.r1, |
fd062c84 | 2143 | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); |
bf28607f | 2144 | build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2); |
fd062c84 DD |
2145 | #endif |
2146 | ||
e30ec452 | 2147 | uasm_l_nopage_tlbs(&l, p); |
bf28607f | 2148 | build_restore_work_registers(&p); |
2a0b24f5 SH |
2149 | #ifdef CONFIG_CPU_MICROMIPS |
2150 | if ((unsigned long)tlb_do_page_fault_1 & 1) { | |
2151 | uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); | |
2152 | uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); | |
2153 | uasm_i_jr(&p, K0); | |
2154 | } else | |
2155 | #endif | |
e30ec452 TS |
2156 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); |
2157 | uasm_i_nop(&p); | |
1da177e4 | 2158 | |
6ba045f9 | 2159 | if (p >= handle_tlbs_end) |
1da177e4 LT |
2160 | panic("TLB store handler fastpath space exceeded"); |
2161 | ||
e30ec452 TS |
2162 | uasm_resolve_relocs(relocs, labels); |
2163 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", | |
2164 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 2165 | |
6ba045f9 | 2166 | dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_size); |
1da177e4 LT |
2167 | } |
2168 | ||
078a55fc | 2169 | static void build_r4000_tlb_modify_handler(void) |
1da177e4 LT |
2170 | { |
2171 | u32 *p = handle_tlbm; | |
6ba045f9 | 2172 | const int handle_tlbm_size = handle_tlbm_end - handle_tlbm; |
e30ec452 TS |
2173 | struct uasm_label *l = labels; |
2174 | struct uasm_reloc *r = relocs; | |
bf28607f | 2175 | struct work_registers wr; |
1da177e4 | 2176 | |
6ba045f9 | 2177 | memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0])); |
1da177e4 LT |
2178 | memset(labels, 0, sizeof(labels)); |
2179 | memset(relocs, 0, sizeof(relocs)); | |
2180 | ||
bf28607f DD |
2181 | wr = build_r4000_tlbchange_handler_head(&p, &l, &r); |
2182 | build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); | |
8df5beac MR |
2183 | if (m4kc_tlbp_war()) |
2184 | build_tlb_probe_entry(&p); | |
1da177e4 | 2185 | /* Present and writable bits set, set accessed and dirty bits. */ |
bf28607f DD |
2186 | build_make_write(&p, &r, wr.r1, wr.r2); |
2187 | build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); | |
1da177e4 | 2188 | |
aa1762f4 | 2189 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
2190 | /* |
2191 | * This is the entry point when | |
2192 | * build_r4000_tlbchange_handler_head spots a huge page. | |
2193 | */ | |
2194 | uasm_l_tlb_huge_update(&l, p); | |
bf28607f DD |
2195 | iPTE_LW(&p, wr.r1, wr.r2); |
2196 | build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); | |
fd062c84 | 2197 | build_tlb_probe_entry(&p); |
bf28607f | 2198 | uasm_i_ori(&p, wr.r1, wr.r1, |
fd062c84 | 2199 | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); |
bf28607f | 2200 | build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2); |
fd062c84 DD |
2201 | #endif |
2202 | ||
e30ec452 | 2203 | uasm_l_nopage_tlbm(&l, p); |
bf28607f | 2204 | build_restore_work_registers(&p); |
2a0b24f5 SH |
2205 | #ifdef CONFIG_CPU_MICROMIPS |
2206 | if ((unsigned long)tlb_do_page_fault_1 & 1) { | |
2207 | uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); | |
2208 | uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); | |
2209 | uasm_i_jr(&p, K0); | |
2210 | } else | |
2211 | #endif | |
e30ec452 TS |
2212 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); |
2213 | uasm_i_nop(&p); | |
1da177e4 | 2214 | |
6ba045f9 | 2215 | if (p >= handle_tlbm_end) |
1da177e4 LT |
2216 | panic("TLB modify handler fastpath space exceeded"); |
2217 | ||
e30ec452 TS |
2218 | uasm_resolve_relocs(relocs, labels); |
2219 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", | |
2220 | (unsigned int)(p - handle_tlbm)); | |
115f2a44 | 2221 | |
6ba045f9 | 2222 | dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_size); |
1da177e4 LT |
2223 | } |
2224 | ||
078a55fc | 2225 | static void flush_tlb_handlers(void) |
a3d9086b JG |
2226 | { |
2227 | local_flush_icache_range((unsigned long)handle_tlbl, | |
6ac5310e | 2228 | (unsigned long)handle_tlbl_end); |
a3d9086b | 2229 | local_flush_icache_range((unsigned long)handle_tlbs, |
6ac5310e | 2230 | (unsigned long)handle_tlbs_end); |
a3d9086b | 2231 | local_flush_icache_range((unsigned long)handle_tlbm, |
6ac5310e | 2232 | (unsigned long)handle_tlbm_end); |
6ac5310e RB |
2233 | local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, |
2234 | (unsigned long)tlbmiss_handler_setup_pgd_end); | |
a3d9086b JG |
2235 | } |
2236 | ||
f1014d1b MC |
2237 | static void print_htw_config(void) |
2238 | { | |
2239 | unsigned long config; | |
2240 | unsigned int pwctl; | |
2241 | const int field = 2 * sizeof(unsigned long); | |
2242 | ||
2243 | config = read_c0_pwfield(); | |
2244 | pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n", | |
2245 | field, config, | |
2246 | (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT, | |
2247 | (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT, | |
2248 | (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT, | |
2249 | (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT, | |
2250 | (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT); | |
2251 | ||
2252 | config = read_c0_pwsize(); | |
2253 | pr_debug("PWSize (0x%0*lx): GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n", | |
2254 | field, config, | |
2255 | (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT, | |
2256 | (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT, | |
2257 | (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT, | |
2258 | (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT, | |
2259 | (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT); | |
2260 | ||
2261 | pwctl = read_c0_pwctl(); | |
2262 | pr_debug("PWCtl (0x%x): PWEn: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n", | |
2263 | pwctl, | |
2264 | (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT, | |
2265 | (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT, | |
2266 | (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT, | |
2267 | (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT); | |
2268 | } | |
2269 | ||
2270 | static void config_htw_params(void) | |
2271 | { | |
2272 | unsigned long pwfield, pwsize, ptei; | |
2273 | unsigned int config; | |
2274 | ||
2275 | /* | |
2276 | * We are using 2-level page tables, so we only need to | |
2277 | * setup GDW and PTW appropriately. UDW and MDW will remain 0. | |
2278 | * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to | |
2279 | * write values less than 0xc in these fields because the entire | |
2280 | * write will be dropped. As a result of which, we must preserve | |
2281 | * the original reset values and overwrite only what we really want. | |
2282 | */ | |
2283 | ||
2284 | pwfield = read_c0_pwfield(); | |
2285 | /* re-initialize the GDI field */ | |
2286 | pwfield &= ~MIPS_PWFIELD_GDI_MASK; | |
2287 | pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT; | |
2288 | /* re-initialize the PTI field including the even/odd bit */ | |
2289 | pwfield &= ~MIPS_PWFIELD_PTI_MASK; | |
2290 | pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT; | |
2291 | /* Set the PTEI right shift */ | |
2292 | ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT; | |
2293 | pwfield |= ptei; | |
2294 | write_c0_pwfield(pwfield); | |
2295 | /* Check whether the PTEI value is supported */ | |
2296 | back_to_back_c0_hazard(); | |
2297 | pwfield = read_c0_pwfield(); | |
2298 | if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT) | |
2299 | != ptei) { | |
2300 | pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled", | |
2301 | ptei); | |
2302 | /* | |
2303 | * Drop option to avoid HTW being enabled via another path | |
2304 | * (eg htw_reset()) | |
2305 | */ | |
2306 | current_cpu_data.options &= ~MIPS_CPU_HTW; | |
2307 | return; | |
2308 | } | |
2309 | ||
2310 | pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT; | |
2311 | pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT; | |
c5b36783 SH |
2312 | |
2313 | /* If XPA has been enabled, PTEs are 64-bit in size. */ | |
2314 | if (read_c0_pagegrain() & PG_ELPA) | |
2315 | pwsize |= 1; | |
2316 | ||
f1014d1b MC |
2317 | write_c0_pwsize(pwsize); |
2318 | ||
2319 | /* Make sure everything is set before we enable the HTW */ | |
2320 | back_to_back_c0_hazard(); | |
2321 | ||
2322 | /* Enable HTW and disable the rest of the pwctl fields */ | |
2323 | config = 1 << MIPS_PWCTL_PWEN_SHIFT; | |
2324 | write_c0_pwctl(config); | |
2325 | pr_info("Hardware Page Table Walker enabled\n"); | |
2326 | ||
2327 | print_htw_config(); | |
2328 | } | |
2329 | ||
c5b36783 SH |
2330 | static void config_xpa_params(void) |
2331 | { | |
2332 | #ifdef CONFIG_XPA | |
2333 | unsigned int pagegrain; | |
2334 | ||
2335 | if (mips_xpa_disabled) { | |
2336 | pr_info("Extended Physical Addressing (XPA) disabled\n"); | |
2337 | return; | |
2338 | } | |
2339 | ||
2340 | pagegrain = read_c0_pagegrain(); | |
2341 | write_c0_pagegrain(pagegrain | PG_ELPA); | |
2342 | back_to_back_c0_hazard(); | |
2343 | pagegrain = read_c0_pagegrain(); | |
2344 | ||
2345 | if (pagegrain & PG_ELPA) | |
2346 | pr_info("Extended Physical Addressing (XPA) enabled\n"); | |
2347 | else | |
2348 | panic("Extended Physical Addressing (XPA) disabled"); | |
2349 | #endif | |
2350 | } | |
2351 | ||
078a55fc | 2352 | void build_tlb_refill_handler(void) |
1da177e4 LT |
2353 | { |
2354 | /* | |
2355 | * The refill handler is generated per-CPU, multi-node systems | |
2356 | * may have local storage for it. The other handlers are only | |
2357 | * needed once. | |
2358 | */ | |
2359 | static int run_once = 0; | |
2360 | ||
a2c763e0 RB |
2361 | output_pgtable_bits_defines(); |
2362 | ||
1ec56329 DD |
2363 | #ifdef CONFIG_64BIT |
2364 | check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); | |
2365 | #endif | |
2366 | ||
10cc3529 | 2367 | switch (current_cpu_type()) { |
1da177e4 LT |
2368 | case CPU_R2000: |
2369 | case CPU_R3000: | |
2370 | case CPU_R3000A: | |
2371 | case CPU_R3081E: | |
2372 | case CPU_TX3912: | |
2373 | case CPU_TX3922: | |
2374 | case CPU_TX3927: | |
82622284 | 2375 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
8759934e HC |
2376 | if (cpu_has_local_ebase) |
2377 | build_r3000_tlb_refill_handler(); | |
1da177e4 | 2378 | if (!run_once) { |
8759934e HC |
2379 | if (!cpu_has_local_ebase) |
2380 | build_r3000_tlb_refill_handler(); | |
f4ae17aa | 2381 | build_setup_pgd(); |
1da177e4 LT |
2382 | build_r3000_tlb_load_handler(); |
2383 | build_r3000_tlb_store_handler(); | |
2384 | build_r3000_tlb_modify_handler(); | |
a3d9086b | 2385 | flush_tlb_handlers(); |
1da177e4 LT |
2386 | run_once++; |
2387 | } | |
82622284 DD |
2388 | #else |
2389 | panic("No R3000 TLB refill handler"); | |
2390 | #endif | |
1da177e4 LT |
2391 | break; |
2392 | ||
2393 | case CPU_R6000: | |
2394 | case CPU_R6000A: | |
2395 | panic("No R6000 TLB refill handler yet"); | |
2396 | break; | |
2397 | ||
2398 | case CPU_R8000: | |
2399 | panic("No R8000 TLB refill handler yet"); | |
2400 | break; | |
2401 | ||
2402 | default: | |
1da177e4 | 2403 | if (!run_once) { |
bf28607f | 2404 | scratch_reg = allocate_kscratch(); |
f4ae17aa | 2405 | build_setup_pgd(); |
1da177e4 LT |
2406 | build_r4000_tlb_load_handler(); |
2407 | build_r4000_tlb_store_handler(); | |
2408 | build_r4000_tlb_modify_handler(); | |
8759934e HC |
2409 | if (!cpu_has_local_ebase) |
2410 | build_r4000_tlb_refill_handler(); | |
a3d9086b | 2411 | flush_tlb_handlers(); |
1da177e4 LT |
2412 | run_once++; |
2413 | } | |
8759934e HC |
2414 | if (cpu_has_local_ebase) |
2415 | build_r4000_tlb_refill_handler(); | |
c5b36783 SH |
2416 | if (cpu_has_xpa) |
2417 | config_xpa_params(); | |
f1014d1b MC |
2418 | if (cpu_has_htw) |
2419 | config_htw_params(); | |
1da177e4 LT |
2420 | } |
2421 | } |