Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Synthesize TLB refill handlers at runtime. | |
7 | * | |
e30ec452 | 8 | * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer |
95affdda | 9 | * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki |
41c594ab | 10 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) |
fd062c84 | 11 | * Copyright (C) 2008, 2009 Cavium Networks, Inc. |
41c594ab RB |
12 | * |
13 | * ... and the days got worse and worse and now you see | |
14 | * I've gone completly out of my mind. | |
15 | * | |
16 | * They're coming to take me a away haha | |
17 | * they're coming to take me a away hoho hihi haha | |
18 | * to the funny farm where code is beautiful all the time ... | |
19 | * | |
20 | * (Condolences to Napoleon XIV) | |
1da177e4 LT |
21 | */ |
22 | ||
95affdda | 23 | #include <linux/bug.h> |
1da177e4 LT |
24 | #include <linux/kernel.h> |
25 | #include <linux/types.h> | |
631330f5 | 26 | #include <linux/smp.h> |
1da177e4 LT |
27 | #include <linux/string.h> |
28 | #include <linux/init.h> | |
3d8bfdd0 | 29 | #include <linux/cache.h> |
1da177e4 | 30 | |
3d8bfdd0 DD |
31 | #include <asm/cacheflush.h> |
32 | #include <asm/pgtable.h> | |
1da177e4 | 33 | #include <asm/war.h> |
3482d713 | 34 | #include <asm/uasm.h> |
e30ec452 | 35 | |
1ec56329 DD |
36 | /* |
37 | * TLB load/store/modify handlers. | |
38 | * | |
39 | * Only the fastpath gets synthesized at runtime, the slowpath for | |
40 | * do_page_fault remains normal asm. | |
41 | */ | |
42 | extern void tlb_do_page_fault_0(void); | |
43 | extern void tlb_do_page_fault_1(void); | |
44 | ||
45 | ||
aeffdbba | 46 | static inline int r45k_bvahwbug(void) |
1da177e4 LT |
47 | { |
48 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
49 | return 0; | |
50 | } | |
51 | ||
aeffdbba | 52 | static inline int r4k_250MHZhwbug(void) |
1da177e4 LT |
53 | { |
54 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
55 | return 0; | |
56 | } | |
57 | ||
aeffdbba | 58 | static inline int __maybe_unused bcm1250_m3_war(void) |
1da177e4 LT |
59 | { |
60 | return BCM1250_M3_WAR; | |
61 | } | |
62 | ||
aeffdbba | 63 | static inline int __maybe_unused r10000_llsc_war(void) |
1da177e4 LT |
64 | { |
65 | return R10000_LLSC_WAR; | |
66 | } | |
67 | ||
8df5beac MR |
68 | /* |
69 | * Found by experiment: At least some revisions of the 4kc throw under | |
70 | * some circumstances a machine check exception, triggered by invalid | |
71 | * values in the index register. Delaying the tlbp instruction until | |
72 | * after the next branch, plus adding an additional nop in front of | |
73 | * tlbwi/tlbwr avoids the invalid index register values. Nobody knows | |
74 | * why; it's not an issue caused by the core RTL. | |
75 | * | |
76 | */ | |
234fcd14 | 77 | static int __cpuinit m4kc_tlbp_war(void) |
8df5beac MR |
78 | { |
79 | return (current_cpu_data.processor_id & 0xffff00) == | |
80 | (PRID_COMP_MIPS | PRID_IMP_4KC); | |
81 | } | |
82 | ||
e30ec452 | 83 | /* Handle labels (which must be positive integers). */ |
1da177e4 | 84 | enum label_id { |
e30ec452 | 85 | label_second_part = 1, |
1da177e4 LT |
86 | label_leave, |
87 | label_vmalloc, | |
88 | label_vmalloc_done, | |
89 | label_tlbw_hazard, | |
90 | label_split, | |
6dd9344c DD |
91 | label_tlbl_goaround1, |
92 | label_tlbl_goaround2, | |
1da177e4 LT |
93 | label_nopage_tlbl, |
94 | label_nopage_tlbs, | |
95 | label_nopage_tlbm, | |
96 | label_smp_pgtable_change, | |
97 | label_r3000_write_probe_fail, | |
1ec56329 | 98 | label_large_segbits_fault, |
fd062c84 DD |
99 | #ifdef CONFIG_HUGETLB_PAGE |
100 | label_tlb_huge_update, | |
101 | #endif | |
1da177e4 LT |
102 | }; |
103 | ||
e30ec452 TS |
104 | UASM_L_LA(_second_part) |
105 | UASM_L_LA(_leave) | |
e30ec452 TS |
106 | UASM_L_LA(_vmalloc) |
107 | UASM_L_LA(_vmalloc_done) | |
108 | UASM_L_LA(_tlbw_hazard) | |
109 | UASM_L_LA(_split) | |
6dd9344c DD |
110 | UASM_L_LA(_tlbl_goaround1) |
111 | UASM_L_LA(_tlbl_goaround2) | |
e30ec452 TS |
112 | UASM_L_LA(_nopage_tlbl) |
113 | UASM_L_LA(_nopage_tlbs) | |
114 | UASM_L_LA(_nopage_tlbm) | |
115 | UASM_L_LA(_smp_pgtable_change) | |
116 | UASM_L_LA(_r3000_write_probe_fail) | |
1ec56329 | 117 | UASM_L_LA(_large_segbits_fault) |
fd062c84 DD |
118 | #ifdef CONFIG_HUGETLB_PAGE |
119 | UASM_L_LA(_tlb_huge_update) | |
120 | #endif | |
656be92f | 121 | |
92b1e6a6 FBH |
122 | /* |
123 | * For debug purposes. | |
124 | */ | |
125 | static inline void dump_handler(const u32 *handler, int count) | |
126 | { | |
127 | int i; | |
128 | ||
129 | pr_debug("\t.set push\n"); | |
130 | pr_debug("\t.set noreorder\n"); | |
131 | ||
132 | for (i = 0; i < count; i++) | |
133 | pr_debug("\t%p\t.word 0x%08x\n", &handler[i], handler[i]); | |
134 | ||
135 | pr_debug("\t.set pop\n"); | |
136 | } | |
137 | ||
1da177e4 LT |
138 | /* The only general purpose registers allowed in TLB handlers. */ |
139 | #define K0 26 | |
140 | #define K1 27 | |
141 | ||
142 | /* Some CP0 registers */ | |
41c594ab RB |
143 | #define C0_INDEX 0, 0 |
144 | #define C0_ENTRYLO0 2, 0 | |
145 | #define C0_TCBIND 2, 2 | |
146 | #define C0_ENTRYLO1 3, 0 | |
147 | #define C0_CONTEXT 4, 0 | |
fd062c84 | 148 | #define C0_PAGEMASK 5, 0 |
41c594ab RB |
149 | #define C0_BADVADDR 8, 0 |
150 | #define C0_ENTRYHI 10, 0 | |
151 | #define C0_EPC 14, 0 | |
152 | #define C0_XCONTEXT 20, 0 | |
1da177e4 | 153 | |
875d43e7 | 154 | #ifdef CONFIG_64BIT |
e30ec452 | 155 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT) |
1da177e4 | 156 | #else |
e30ec452 | 157 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT) |
1da177e4 LT |
158 | #endif |
159 | ||
160 | /* The worst case length of the handler is around 18 instructions for | |
161 | * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. | |
162 | * Maximum space available is 32 instructions for R3000 and 64 | |
163 | * instructions for R4000. | |
164 | * | |
165 | * We deliberately chose a buffer size of 128, so we won't scribble | |
166 | * over anything important on overflow before we panic. | |
167 | */ | |
234fcd14 | 168 | static u32 tlb_handler[128] __cpuinitdata; |
1da177e4 LT |
169 | |
170 | /* simply assume worst case size for labels and relocs */ | |
234fcd14 RB |
171 | static struct uasm_label labels[128] __cpuinitdata; |
172 | static struct uasm_reloc relocs[128] __cpuinitdata; | |
1da177e4 | 173 | |
1ec56329 DD |
174 | #ifdef CONFIG_64BIT |
175 | static int check_for_high_segbits __cpuinitdata; | |
176 | #endif | |
177 | ||
3d8bfdd0 DD |
178 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
179 | ||
180 | static unsigned int kscratch_used_mask __cpuinitdata; | |
181 | ||
182 | static int __cpuinit allocate_kscratch(void) | |
183 | { | |
184 | int r; | |
185 | unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask; | |
186 | ||
187 | r = ffs(a); | |
188 | ||
189 | if (r == 0) | |
190 | return -1; | |
191 | ||
192 | r--; /* make it zero based */ | |
193 | ||
194 | kscratch_used_mask |= (1 << r); | |
195 | ||
196 | return r; | |
197 | } | |
198 | ||
199 | static int pgd_reg __cpuinitdata; | |
200 | ||
201 | #else /* !CONFIG_MIPS_PGD_C0_CONTEXT*/ | |
82622284 DD |
202 | /* |
203 | * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current, | |
204 | * we cannot do r3000 under these circumstances. | |
3d8bfdd0 DD |
205 | * |
206 | * Declare pgd_current here instead of including mmu_context.h to avoid type | |
207 | * conflicts for tlbmiss_handler_setup_pgd | |
82622284 | 208 | */ |
3d8bfdd0 | 209 | extern unsigned long pgd_current[]; |
82622284 | 210 | |
1da177e4 LT |
211 | /* |
212 | * The R3000 TLB handler is simple. | |
213 | */ | |
234fcd14 | 214 | static void __cpuinit build_r3000_tlb_refill_handler(void) |
1da177e4 LT |
215 | { |
216 | long pgdc = (long)pgd_current; | |
217 | u32 *p; | |
218 | ||
219 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
220 | p = tlb_handler; | |
221 | ||
e30ec452 TS |
222 | uasm_i_mfc0(&p, K0, C0_BADVADDR); |
223 | uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */ | |
224 | uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1); | |
225 | uasm_i_srl(&p, K0, K0, 22); /* load delay */ | |
226 | uasm_i_sll(&p, K0, K0, 2); | |
227 | uasm_i_addu(&p, K1, K1, K0); | |
228 | uasm_i_mfc0(&p, K0, C0_CONTEXT); | |
229 | uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */ | |
230 | uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */ | |
231 | uasm_i_addu(&p, K1, K1, K0); | |
232 | uasm_i_lw(&p, K0, 0, K1); | |
233 | uasm_i_nop(&p); /* load delay */ | |
234 | uasm_i_mtc0(&p, K0, C0_ENTRYLO0); | |
235 | uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ | |
236 | uasm_i_tlbwr(&p); /* cp0 delay */ | |
237 | uasm_i_jr(&p, K1); | |
238 | uasm_i_rfe(&p); /* branch delay */ | |
1da177e4 LT |
239 | |
240 | if (p > tlb_handler + 32) | |
241 | panic("TLB refill handler space exceeded"); | |
242 | ||
e30ec452 TS |
243 | pr_debug("Wrote TLB refill handler (%u instructions).\n", |
244 | (unsigned int)(p - tlb_handler)); | |
1da177e4 | 245 | |
91b05e67 | 246 | memcpy((void *)ebase, tlb_handler, 0x80); |
92b1e6a6 FBH |
247 | |
248 | dump_handler((u32 *)ebase, 32); | |
1da177e4 | 249 | } |
82622284 | 250 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ |
1da177e4 LT |
251 | |
252 | /* | |
253 | * The R4000 TLB handler is much more complicated. We have two | |
254 | * consecutive handler areas with 32 instructions space each. | |
255 | * Since they aren't used at the same time, we can overflow in the | |
256 | * other one.To keep things simple, we first assume linear space, | |
257 | * then we relocate it to the final handler layout as needed. | |
258 | */ | |
234fcd14 | 259 | static u32 final_handler[64] __cpuinitdata; |
1da177e4 LT |
260 | |
261 | /* | |
262 | * Hazards | |
263 | * | |
264 | * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: | |
265 | * 2. A timing hazard exists for the TLBP instruction. | |
266 | * | |
267 | * stalling_instruction | |
268 | * TLBP | |
269 | * | |
270 | * The JTLB is being read for the TLBP throughout the stall generated by the | |
271 | * previous instruction. This is not really correct as the stalling instruction | |
272 | * can modify the address used to access the JTLB. The failure symptom is that | |
273 | * the TLBP instruction will use an address created for the stalling instruction | |
274 | * and not the address held in C0_ENHI and thus report the wrong results. | |
275 | * | |
276 | * The software work-around is to not allow the instruction preceding the TLBP | |
277 | * to stall - make it an NOP or some other instruction guaranteed not to stall. | |
278 | * | |
279 | * Errata 2 will not be fixed. This errata is also on the R5000. | |
280 | * | |
281 | * As if we MIPS hackers wouldn't know how to nop pipelines happy ... | |
282 | */ | |
234fcd14 | 283 | static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p) |
1da177e4 | 284 | { |
10cc3529 | 285 | switch (current_cpu_type()) { |
326e2e1a | 286 | /* Found by experiment: R4600 v2.0/R4700 needs this, too. */ |
f5b4d956 | 287 | case CPU_R4600: |
326e2e1a | 288 | case CPU_R4700: |
1da177e4 LT |
289 | case CPU_R5000: |
290 | case CPU_R5000A: | |
291 | case CPU_NEVADA: | |
e30ec452 TS |
292 | uasm_i_nop(p); |
293 | uasm_i_tlbp(p); | |
1da177e4 LT |
294 | break; |
295 | ||
296 | default: | |
e30ec452 | 297 | uasm_i_tlbp(p); |
1da177e4 LT |
298 | break; |
299 | } | |
300 | } | |
301 | ||
302 | /* | |
303 | * Write random or indexed TLB entry, and care about the hazards from | |
304 | * the preceeding mtc0 and for the following eret. | |
305 | */ | |
306 | enum tlb_write_entry { tlb_random, tlb_indexed }; | |
307 | ||
234fcd14 | 308 | static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, |
e30ec452 | 309 | struct uasm_reloc **r, |
1da177e4 LT |
310 | enum tlb_write_entry wmode) |
311 | { | |
312 | void(*tlbw)(u32 **) = NULL; | |
313 | ||
314 | switch (wmode) { | |
e30ec452 TS |
315 | case tlb_random: tlbw = uasm_i_tlbwr; break; |
316 | case tlb_indexed: tlbw = uasm_i_tlbwi; break; | |
1da177e4 LT |
317 | } |
318 | ||
161548bf | 319 | if (cpu_has_mips_r2) { |
41f0e4d0 DD |
320 | if (cpu_has_mips_r2_exec_hazard) |
321 | uasm_i_ehb(p); | |
161548bf RB |
322 | tlbw(p); |
323 | return; | |
324 | } | |
325 | ||
10cc3529 | 326 | switch (current_cpu_type()) { |
1da177e4 LT |
327 | case CPU_R4000PC: |
328 | case CPU_R4000SC: | |
329 | case CPU_R4000MC: | |
330 | case CPU_R4400PC: | |
331 | case CPU_R4400SC: | |
332 | case CPU_R4400MC: | |
333 | /* | |
334 | * This branch uses up a mtc0 hazard nop slot and saves | |
335 | * two nops after the tlbw instruction. | |
336 | */ | |
e30ec452 | 337 | uasm_il_bgezl(p, r, 0, label_tlbw_hazard); |
1da177e4 | 338 | tlbw(p); |
e30ec452 TS |
339 | uasm_l_tlbw_hazard(l, *p); |
340 | uasm_i_nop(p); | |
1da177e4 LT |
341 | break; |
342 | ||
343 | case CPU_R4600: | |
344 | case CPU_R4700: | |
345 | case CPU_R5000: | |
346 | case CPU_R5000A: | |
e30ec452 | 347 | uasm_i_nop(p); |
2c93e12c | 348 | tlbw(p); |
e30ec452 | 349 | uasm_i_nop(p); |
2c93e12c MR |
350 | break; |
351 | ||
352 | case CPU_R4300: | |
1da177e4 LT |
353 | case CPU_5KC: |
354 | case CPU_TX49XX: | |
bdf21b18 | 355 | case CPU_PR4450: |
e30ec452 | 356 | uasm_i_nop(p); |
1da177e4 LT |
357 | tlbw(p); |
358 | break; | |
359 | ||
360 | case CPU_R10000: | |
361 | case CPU_R12000: | |
44d921b2 | 362 | case CPU_R14000: |
1da177e4 | 363 | case CPU_4KC: |
b1ec4c8e | 364 | case CPU_4KEC: |
1da177e4 | 365 | case CPU_SB1: |
93ce2f52 | 366 | case CPU_SB1A: |
1da177e4 LT |
367 | case CPU_4KSC: |
368 | case CPU_20KC: | |
369 | case CPU_25KF: | |
602977b0 KC |
370 | case CPU_BMIPS32: |
371 | case CPU_BMIPS3300: | |
372 | case CPU_BMIPS4350: | |
373 | case CPU_BMIPS4380: | |
374 | case CPU_BMIPS5000: | |
2a21c730 | 375 | case CPU_LOONGSON2: |
a644b277 | 376 | case CPU_R5500: |
8df5beac | 377 | if (m4kc_tlbp_war()) |
e30ec452 | 378 | uasm_i_nop(p); |
2f794d09 | 379 | case CPU_ALCHEMY: |
1da177e4 LT |
380 | tlbw(p); |
381 | break; | |
382 | ||
383 | case CPU_NEVADA: | |
e30ec452 | 384 | uasm_i_nop(p); /* QED specifies 2 nops hazard */ |
1da177e4 LT |
385 | /* |
386 | * This branch uses up a mtc0 hazard nop slot and saves | |
387 | * a nop after the tlbw instruction. | |
388 | */ | |
e30ec452 | 389 | uasm_il_bgezl(p, r, 0, label_tlbw_hazard); |
1da177e4 | 390 | tlbw(p); |
e30ec452 | 391 | uasm_l_tlbw_hazard(l, *p); |
1da177e4 LT |
392 | break; |
393 | ||
394 | case CPU_RM7000: | |
e30ec452 TS |
395 | uasm_i_nop(p); |
396 | uasm_i_nop(p); | |
397 | uasm_i_nop(p); | |
398 | uasm_i_nop(p); | |
1da177e4 LT |
399 | tlbw(p); |
400 | break; | |
401 | ||
1da177e4 LT |
402 | case CPU_RM9000: |
403 | /* | |
404 | * When the JTLB is updated by tlbwi or tlbwr, a subsequent | |
405 | * use of the JTLB for instructions should not occur for 4 | |
406 | * cpu cycles and use for data translations should not occur | |
407 | * for 3 cpu cycles. | |
408 | */ | |
e30ec452 TS |
409 | uasm_i_ssnop(p); |
410 | uasm_i_ssnop(p); | |
411 | uasm_i_ssnop(p); | |
412 | uasm_i_ssnop(p); | |
1da177e4 | 413 | tlbw(p); |
e30ec452 TS |
414 | uasm_i_ssnop(p); |
415 | uasm_i_ssnop(p); | |
416 | uasm_i_ssnop(p); | |
417 | uasm_i_ssnop(p); | |
1da177e4 LT |
418 | break; |
419 | ||
420 | case CPU_VR4111: | |
421 | case CPU_VR4121: | |
422 | case CPU_VR4122: | |
423 | case CPU_VR4181: | |
424 | case CPU_VR4181A: | |
e30ec452 TS |
425 | uasm_i_nop(p); |
426 | uasm_i_nop(p); | |
1da177e4 | 427 | tlbw(p); |
e30ec452 TS |
428 | uasm_i_nop(p); |
429 | uasm_i_nop(p); | |
1da177e4 LT |
430 | break; |
431 | ||
432 | case CPU_VR4131: | |
433 | case CPU_VR4133: | |
7623debf | 434 | case CPU_R5432: |
e30ec452 TS |
435 | uasm_i_nop(p); |
436 | uasm_i_nop(p); | |
1da177e4 LT |
437 | tlbw(p); |
438 | break; | |
439 | ||
83ccf69d LPC |
440 | case CPU_JZRISC: |
441 | tlbw(p); | |
442 | uasm_i_nop(p); | |
443 | break; | |
444 | ||
1da177e4 LT |
445 | default: |
446 | panic("No TLB refill handler yet (CPU type: %d)", | |
447 | current_cpu_data.cputype); | |
448 | break; | |
449 | } | |
450 | } | |
451 | ||
6dd9344c DD |
452 | static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p, |
453 | unsigned int reg) | |
fd062c84 | 454 | { |
6dd9344c DD |
455 | if (kernel_uses_smartmips_rixi) { |
456 | UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC)); | |
457 | UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); | |
458 | } else { | |
459 | #ifdef CONFIG_64BIT_PHYS_ADDR | |
3be6022c | 460 | uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL)); |
6dd9344c DD |
461 | #else |
462 | UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL)); | |
463 | #endif | |
464 | } | |
465 | } | |
fd062c84 | 466 | |
6dd9344c | 467 | #ifdef CONFIG_HUGETLB_PAGE |
fd062c84 | 468 | |
6dd9344c DD |
469 | static __cpuinit void build_restore_pagemask(u32 **p, |
470 | struct uasm_reloc **r, | |
471 | unsigned int tmp, | |
472 | enum label_id lid) | |
473 | { | |
fd062c84 DD |
474 | /* Reset default page size */ |
475 | if (PM_DEFAULT_MASK >> 16) { | |
476 | uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); | |
477 | uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); | |
6dd9344c | 478 | uasm_il_b(p, r, lid); |
fd062c84 DD |
479 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); |
480 | } else if (PM_DEFAULT_MASK) { | |
481 | uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); | |
6dd9344c | 482 | uasm_il_b(p, r, lid); |
fd062c84 DD |
483 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); |
484 | } else { | |
6dd9344c | 485 | uasm_il_b(p, r, lid); |
fd062c84 DD |
486 | uasm_i_mtc0(p, 0, C0_PAGEMASK); |
487 | } | |
488 | } | |
489 | ||
6dd9344c DD |
490 | static __cpuinit void build_huge_tlb_write_entry(u32 **p, |
491 | struct uasm_label **l, | |
492 | struct uasm_reloc **r, | |
493 | unsigned int tmp, | |
494 | enum tlb_write_entry wmode) | |
495 | { | |
496 | /* Set huge page tlb entry size */ | |
497 | uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16); | |
498 | uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff); | |
499 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
500 | ||
501 | build_tlb_write_entry(p, l, r, wmode); | |
502 | ||
503 | build_restore_pagemask(p, r, tmp, label_leave); | |
504 | } | |
505 | ||
fd062c84 DD |
506 | /* |
507 | * Check if Huge PTE is present, if so then jump to LABEL. | |
508 | */ | |
509 | static void __cpuinit | |
510 | build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp, | |
511 | unsigned int pmd, int lid) | |
512 | { | |
513 | UASM_i_LW(p, tmp, 0, pmd); | |
514 | uasm_i_andi(p, tmp, tmp, _PAGE_HUGE); | |
515 | uasm_il_bnez(p, r, tmp, lid); | |
516 | } | |
517 | ||
518 | static __cpuinit void build_huge_update_entries(u32 **p, | |
519 | unsigned int pte, | |
520 | unsigned int tmp) | |
521 | { | |
522 | int small_sequence; | |
523 | ||
524 | /* | |
525 | * A huge PTE describes an area the size of the | |
526 | * configured huge page size. This is twice the | |
527 | * of the large TLB entry size we intend to use. | |
528 | * A TLB entry half the size of the configured | |
529 | * huge page size is configured into entrylo0 | |
530 | * and entrylo1 to cover the contiguous huge PTE | |
531 | * address space. | |
532 | */ | |
533 | small_sequence = (HPAGE_SIZE >> 7) < 0x10000; | |
534 | ||
535 | /* We can clobber tmp. It isn't used after this.*/ | |
536 | if (!small_sequence) | |
537 | uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16)); | |
538 | ||
6dd9344c | 539 | build_convert_pte_to_entrylo(p, pte); |
9b8c3891 | 540 | UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */ |
fd062c84 DD |
541 | /* convert to entrylo1 */ |
542 | if (small_sequence) | |
543 | UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7); | |
544 | else | |
545 | UASM_i_ADDU(p, pte, pte, tmp); | |
546 | ||
9b8c3891 | 547 | UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */ |
fd062c84 DD |
548 | } |
549 | ||
550 | static __cpuinit void build_huge_handler_tail(u32 **p, | |
551 | struct uasm_reloc **r, | |
552 | struct uasm_label **l, | |
553 | unsigned int pte, | |
554 | unsigned int ptr) | |
555 | { | |
556 | #ifdef CONFIG_SMP | |
557 | UASM_i_SC(p, pte, 0, ptr); | |
558 | uasm_il_beqz(p, r, pte, label_tlb_huge_update); | |
559 | UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */ | |
560 | #else | |
561 | UASM_i_SW(p, pte, 0, ptr); | |
562 | #endif | |
563 | build_huge_update_entries(p, pte, ptr); | |
564 | build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed); | |
565 | } | |
566 | #endif /* CONFIG_HUGETLB_PAGE */ | |
567 | ||
875d43e7 | 568 | #ifdef CONFIG_64BIT |
1da177e4 LT |
569 | /* |
570 | * TMP and PTR are scratch. | |
571 | * TMP will be clobbered, PTR will hold the pmd entry. | |
572 | */ | |
234fcd14 | 573 | static void __cpuinit |
e30ec452 | 574 | build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
1da177e4 LT |
575 | unsigned int tmp, unsigned int ptr) |
576 | { | |
82622284 | 577 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
1da177e4 | 578 | long pgdc = (long)pgd_current; |
82622284 | 579 | #endif |
1da177e4 LT |
580 | /* |
581 | * The vmalloc handling is not in the hotpath. | |
582 | */ | |
e30ec452 | 583 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); |
1ec56329 DD |
584 | |
585 | if (check_for_high_segbits) { | |
586 | /* | |
587 | * The kernel currently implicitely assumes that the | |
588 | * MIPS SEGBITS parameter for the processor is | |
589 | * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never | |
590 | * allocate virtual addresses outside the maximum | |
591 | * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But | |
592 | * that doesn't prevent user code from accessing the | |
593 | * higher xuseg addresses. Here, we make sure that | |
594 | * everything but the lower xuseg addresses goes down | |
595 | * the module_alloc/vmalloc path. | |
596 | */ | |
597 | uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); | |
598 | uasm_il_bnez(p, r, ptr, label_vmalloc); | |
599 | } else { | |
600 | uasm_il_bltz(p, r, tmp, label_vmalloc); | |
601 | } | |
e30ec452 | 602 | /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ |
1da177e4 | 603 | |
82622284 | 604 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
3d8bfdd0 DD |
605 | if (pgd_reg != -1) { |
606 | /* pgd is in pgd_reg */ | |
607 | UASM_i_MFC0(p, ptr, 31, pgd_reg); | |
608 | } else { | |
609 | /* | |
610 | * &pgd << 11 stored in CONTEXT [23..63]. | |
611 | */ | |
612 | UASM_i_MFC0(p, ptr, C0_CONTEXT); | |
613 | ||
614 | /* Clear lower 23 bits of context. */ | |
615 | uasm_i_dins(p, ptr, 0, 0, 23); | |
616 | ||
617 | /* 1 0 1 0 1 << 6 xkphys cached */ | |
618 | uasm_i_ori(p, ptr, ptr, 0x540); | |
619 | uasm_i_drotr(p, ptr, ptr, 11); | |
620 | } | |
82622284 | 621 | #elif defined(CONFIG_SMP) |
41c594ab RB |
622 | # ifdef CONFIG_MIPS_MT_SMTC |
623 | /* | |
624 | * SMTC uses TCBind value as "CPU" index | |
625 | */ | |
e30ec452 | 626 | uasm_i_mfc0(p, ptr, C0_TCBIND); |
3be6022c | 627 | uasm_i_dsrl_safe(p, ptr, ptr, 19); |
41c594ab | 628 | # else |
1da177e4 | 629 | /* |
1b3a6e97 | 630 | * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 |
1da177e4 LT |
631 | * stored in CONTEXT. |
632 | */ | |
e30ec452 | 633 | uasm_i_dmfc0(p, ptr, C0_CONTEXT); |
3be6022c | 634 | uasm_i_dsrl_safe(p, ptr, ptr, 23); |
82622284 | 635 | # endif |
e30ec452 TS |
636 | UASM_i_LA_mostly(p, tmp, pgdc); |
637 | uasm_i_daddu(p, ptr, ptr, tmp); | |
638 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); | |
639 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1da177e4 | 640 | #else |
e30ec452 TS |
641 | UASM_i_LA_mostly(p, ptr, pgdc); |
642 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1da177e4 LT |
643 | #endif |
644 | ||
e30ec452 | 645 | uasm_l_vmalloc_done(l, *p); |
242954b5 | 646 | |
3be6022c DD |
647 | /* get pgd offset in bytes */ |
648 | uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3); | |
e30ec452 TS |
649 | |
650 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); | |
651 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
325f8a0a | 652 | #ifndef __PAGETABLE_PMD_FOLDED |
e30ec452 TS |
653 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ |
654 | uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ | |
3be6022c | 655 | uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ |
e30ec452 TS |
656 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); |
657 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ | |
325f8a0a | 658 | #endif |
1da177e4 LT |
659 | } |
660 | ||
1ec56329 | 661 | enum vmalloc64_mode {not_refill, refill}; |
1da177e4 LT |
662 | /* |
663 | * BVADDR is the faulting address, PTR is scratch. | |
664 | * PTR will hold the pgd for vmalloc. | |
665 | */ | |
234fcd14 | 666 | static void __cpuinit |
e30ec452 | 667 | build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
1ec56329 DD |
668 | unsigned int bvaddr, unsigned int ptr, |
669 | enum vmalloc64_mode mode) | |
1da177e4 LT |
670 | { |
671 | long swpd = (long)swapper_pg_dir; | |
1ec56329 DD |
672 | int single_insn_swpd; |
673 | int did_vmalloc_branch = 0; | |
674 | ||
675 | single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd); | |
1da177e4 | 676 | |
e30ec452 | 677 | uasm_l_vmalloc(l, *p); |
1da177e4 | 678 | |
1ec56329 DD |
679 | if (mode == refill && check_for_high_segbits) { |
680 | if (single_insn_swpd) { | |
681 | uasm_il_bltz(p, r, bvaddr, label_vmalloc_done); | |
682 | uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); | |
683 | did_vmalloc_branch = 1; | |
684 | /* fall through */ | |
685 | } else { | |
686 | uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault); | |
687 | } | |
688 | } | |
689 | if (!did_vmalloc_branch) { | |
690 | if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) { | |
691 | uasm_il_b(p, r, label_vmalloc_done); | |
692 | uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); | |
693 | } else { | |
694 | UASM_i_LA_mostly(p, ptr, swpd); | |
695 | uasm_il_b(p, r, label_vmalloc_done); | |
696 | if (uasm_in_compat_space_p(swpd)) | |
697 | uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd)); | |
698 | else | |
699 | uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); | |
700 | } | |
701 | } | |
702 | if (mode == refill && check_for_high_segbits) { | |
703 | uasm_l_large_segbits_fault(l, *p); | |
704 | /* | |
705 | * We get here if we are an xsseg address, or if we are | |
706 | * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary. | |
707 | * | |
708 | * Ignoring xsseg (assume disabled so would generate | |
709 | * (address errors?), the only remaining possibility | |
710 | * is the upper xuseg addresses. On processors with | |
711 | * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these | |
712 | * addresses would have taken an address error. We try | |
713 | * to mimic that here by taking a load/istream page | |
714 | * fault. | |
715 | */ | |
716 | UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0); | |
717 | uasm_i_jr(p, ptr); | |
718 | uasm_i_nop(p); | |
1da177e4 LT |
719 | } |
720 | } | |
721 | ||
875d43e7 | 722 | #else /* !CONFIG_64BIT */ |
1da177e4 LT |
723 | |
724 | /* | |
725 | * TMP and PTR are scratch. | |
726 | * TMP will be clobbered, PTR will hold the pgd entry. | |
727 | */ | |
234fcd14 | 728 | static void __cpuinit __maybe_unused |
1da177e4 LT |
729 | build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) |
730 | { | |
731 | long pgdc = (long)pgd_current; | |
732 | ||
733 | /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ | |
734 | #ifdef CONFIG_SMP | |
41c594ab RB |
735 | #ifdef CONFIG_MIPS_MT_SMTC |
736 | /* | |
737 | * SMTC uses TCBind value as "CPU" index | |
738 | */ | |
e30ec452 TS |
739 | uasm_i_mfc0(p, ptr, C0_TCBIND); |
740 | UASM_i_LA_mostly(p, tmp, pgdc); | |
741 | uasm_i_srl(p, ptr, ptr, 19); | |
41c594ab RB |
742 | #else |
743 | /* | |
744 | * smp_processor_id() << 3 is stored in CONTEXT. | |
745 | */ | |
e30ec452 TS |
746 | uasm_i_mfc0(p, ptr, C0_CONTEXT); |
747 | UASM_i_LA_mostly(p, tmp, pgdc); | |
748 | uasm_i_srl(p, ptr, ptr, 23); | |
41c594ab | 749 | #endif |
e30ec452 | 750 | uasm_i_addu(p, ptr, tmp, ptr); |
1da177e4 | 751 | #else |
e30ec452 | 752 | UASM_i_LA_mostly(p, ptr, pgdc); |
1da177e4 | 753 | #endif |
e30ec452 TS |
754 | uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ |
755 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); | |
756 | uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ | |
757 | uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); | |
758 | uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
1da177e4 LT |
759 | } |
760 | ||
875d43e7 | 761 | #endif /* !CONFIG_64BIT */ |
1da177e4 | 762 | |
234fcd14 | 763 | static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx) |
1da177e4 | 764 | { |
242954b5 | 765 | unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; |
1da177e4 LT |
766 | unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); |
767 | ||
10cc3529 | 768 | switch (current_cpu_type()) { |
1da177e4 LT |
769 | case CPU_VR41XX: |
770 | case CPU_VR4111: | |
771 | case CPU_VR4121: | |
772 | case CPU_VR4122: | |
773 | case CPU_VR4131: | |
774 | case CPU_VR4181: | |
775 | case CPU_VR4181A: | |
776 | case CPU_VR4133: | |
777 | shift += 2; | |
778 | break; | |
779 | ||
780 | default: | |
781 | break; | |
782 | } | |
783 | ||
784 | if (shift) | |
e30ec452 TS |
785 | UASM_i_SRL(p, ctx, ctx, shift); |
786 | uasm_i_andi(p, ctx, ctx, mask); | |
1da177e4 LT |
787 | } |
788 | ||
234fcd14 | 789 | static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) |
1da177e4 LT |
790 | { |
791 | /* | |
792 | * Bug workaround for the Nevada. It seems as if under certain | |
793 | * circumstances the move from cp0_context might produce a | |
794 | * bogus result when the mfc0 instruction and its consumer are | |
795 | * in a different cacheline or a load instruction, probably any | |
796 | * memory reference, is between them. | |
797 | */ | |
10cc3529 | 798 | switch (current_cpu_type()) { |
1da177e4 | 799 | case CPU_NEVADA: |
e30ec452 | 800 | UASM_i_LW(p, ptr, 0, ptr); |
1da177e4 LT |
801 | GET_CONTEXT(p, tmp); /* get context reg */ |
802 | break; | |
803 | ||
804 | default: | |
805 | GET_CONTEXT(p, tmp); /* get context reg */ | |
e30ec452 | 806 | UASM_i_LW(p, ptr, 0, ptr); |
1da177e4 LT |
807 | break; |
808 | } | |
809 | ||
810 | build_adjust_context(p, tmp); | |
e30ec452 | 811 | UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ |
1da177e4 LT |
812 | } |
813 | ||
234fcd14 | 814 | static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, |
1da177e4 LT |
815 | unsigned int ptep) |
816 | { | |
817 | /* | |
818 | * 64bit address support (36bit on a 32bit CPU) in a 32bit | |
819 | * Kernel is a special case. Only a few CPUs use it. | |
820 | */ | |
821 | #ifdef CONFIG_64BIT_PHYS_ADDR | |
822 | if (cpu_has_64bits) { | |
e30ec452 TS |
823 | uasm_i_ld(p, tmp, 0, ptep); /* get even pte */ |
824 | uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ | |
6dd9344c DD |
825 | if (kernel_uses_smartmips_rixi) { |
826 | UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC)); | |
827 | UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC)); | |
828 | UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); | |
829 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ | |
830 | UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); | |
831 | } else { | |
3be6022c | 832 | uasm_i_dsrl_safe(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */ |
6dd9344c | 833 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ |
3be6022c | 834 | uasm_i_dsrl_safe(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */ |
6dd9344c | 835 | } |
9b8c3891 | 836 | UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ |
1da177e4 LT |
837 | } else { |
838 | int pte_off_even = sizeof(pte_t) / 2; | |
839 | int pte_off_odd = pte_off_even + sizeof(pte_t); | |
840 | ||
841 | /* The pte entries are pre-shifted */ | |
e30ec452 | 842 | uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */ |
9b8c3891 | 843 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ |
e30ec452 | 844 | uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */ |
9b8c3891 | 845 | UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ |
1da177e4 LT |
846 | } |
847 | #else | |
e30ec452 TS |
848 | UASM_i_LW(p, tmp, 0, ptep); /* get even pte */ |
849 | UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ | |
1da177e4 LT |
850 | if (r45k_bvahwbug()) |
851 | build_tlb_probe_entry(p); | |
6dd9344c DD |
852 | if (kernel_uses_smartmips_rixi) { |
853 | UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC)); | |
854 | UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC)); | |
855 | UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); | |
856 | if (r4k_250MHZhwbug()) | |
857 | UASM_i_MTC0(p, 0, C0_ENTRYLO0); | |
858 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ | |
859 | UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); | |
860 | } else { | |
861 | UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */ | |
862 | if (r4k_250MHZhwbug()) | |
863 | UASM_i_MTC0(p, 0, C0_ENTRYLO0); | |
864 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ | |
865 | UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */ | |
866 | if (r45k_bvahwbug()) | |
867 | uasm_i_mfc0(p, tmp, C0_INDEX); | |
868 | } | |
1da177e4 | 869 | if (r4k_250MHZhwbug()) |
9b8c3891 DD |
870 | UASM_i_MTC0(p, 0, C0_ENTRYLO1); |
871 | UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ | |
1da177e4 LT |
872 | #endif |
873 | } | |
874 | ||
e6f72d3a DD |
875 | /* |
876 | * For a 64-bit kernel, we are using the 64-bit XTLB refill exception | |
877 | * because EXL == 0. If we wrap, we can also use the 32 instruction | |
878 | * slots before the XTLB refill exception handler which belong to the | |
879 | * unused TLB refill exception. | |
880 | */ | |
881 | #define MIPS64_REFILL_INSNS 32 | |
882 | ||
234fcd14 | 883 | static void __cpuinit build_r4000_tlb_refill_handler(void) |
1da177e4 LT |
884 | { |
885 | u32 *p = tlb_handler; | |
e30ec452 TS |
886 | struct uasm_label *l = labels; |
887 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
888 | u32 *f; |
889 | unsigned int final_len; | |
890 | ||
891 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
892 | memset(labels, 0, sizeof(labels)); | |
893 | memset(relocs, 0, sizeof(relocs)); | |
894 | memset(final_handler, 0, sizeof(final_handler)); | |
895 | ||
896 | /* | |
897 | * create the plain linear handler | |
898 | */ | |
899 | if (bcm1250_m3_war()) { | |
3d45285d RB |
900 | unsigned int segbits = 44; |
901 | ||
902 | uasm_i_dmfc0(&p, K0, C0_BADVADDR); | |
903 | uasm_i_dmfc0(&p, K1, C0_ENTRYHI); | |
e30ec452 | 904 | uasm_i_xor(&p, K0, K0, K1); |
3be6022c DD |
905 | uasm_i_dsrl_safe(&p, K1, K0, 62); |
906 | uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); | |
907 | uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); | |
3d45285d | 908 | uasm_i_or(&p, K0, K0, K1); |
e30ec452 TS |
909 | uasm_il_bnez(&p, &r, K0, label_leave); |
910 | /* No need for uasm_i_nop */ | |
1da177e4 LT |
911 | } |
912 | ||
875d43e7 | 913 | #ifdef CONFIG_64BIT |
1da177e4 LT |
914 | build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ |
915 | #else | |
916 | build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ | |
917 | #endif | |
918 | ||
fd062c84 DD |
919 | #ifdef CONFIG_HUGETLB_PAGE |
920 | build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update); | |
921 | #endif | |
922 | ||
1da177e4 LT |
923 | build_get_ptep(&p, K0, K1); |
924 | build_update_entries(&p, K0, K1); | |
925 | build_tlb_write_entry(&p, &l, &r, tlb_random); | |
e30ec452 TS |
926 | uasm_l_leave(&l, p); |
927 | uasm_i_eret(&p); /* return from trap */ | |
1da177e4 | 928 | |
fd062c84 DD |
929 | #ifdef CONFIG_HUGETLB_PAGE |
930 | uasm_l_tlb_huge_update(&l, p); | |
931 | UASM_i_LW(&p, K0, 0, K1); | |
932 | build_huge_update_entries(&p, K0, K1); | |
933 | build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random); | |
934 | #endif | |
935 | ||
875d43e7 | 936 | #ifdef CONFIG_64BIT |
1ec56329 | 937 | build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, refill); |
1da177e4 LT |
938 | #endif |
939 | ||
940 | /* | |
941 | * Overflow check: For the 64bit handler, we need at least one | |
942 | * free instruction slot for the wrap-around branch. In worst | |
943 | * case, if the intended insertion point is a delay slot, we | |
4b3f686d | 944 | * need three, with the second nop'ed and the third being |
1da177e4 LT |
945 | * unused. |
946 | */ | |
2a21c730 FZ |
947 | /* Loongson2 ebase is different than r4k, we have more space */ |
948 | #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) | |
1da177e4 LT |
949 | if ((p - tlb_handler) > 64) |
950 | panic("TLB refill handler space exceeded"); | |
951 | #else | |
e6f72d3a DD |
952 | if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1) |
953 | || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3) | |
954 | && uasm_insn_has_bdelay(relocs, | |
955 | tlb_handler + MIPS64_REFILL_INSNS - 3))) | |
1da177e4 LT |
956 | panic("TLB refill handler space exceeded"); |
957 | #endif | |
958 | ||
959 | /* | |
960 | * Now fold the handler in the TLB refill handler space. | |
961 | */ | |
2a21c730 | 962 | #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) |
1da177e4 LT |
963 | f = final_handler; |
964 | /* Simplest case, just copy the handler. */ | |
e30ec452 | 965 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); |
1da177e4 | 966 | final_len = p - tlb_handler; |
875d43e7 | 967 | #else /* CONFIG_64BIT */ |
e6f72d3a DD |
968 | f = final_handler + MIPS64_REFILL_INSNS; |
969 | if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) { | |
1da177e4 | 970 | /* Just copy the handler. */ |
e30ec452 | 971 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); |
1da177e4 LT |
972 | final_len = p - tlb_handler; |
973 | } else { | |
fd062c84 DD |
974 | #if defined(CONFIG_HUGETLB_PAGE) |
975 | const enum label_id ls = label_tlb_huge_update; | |
95affdda DD |
976 | #else |
977 | const enum label_id ls = label_vmalloc; | |
978 | #endif | |
979 | u32 *split; | |
980 | int ov = 0; | |
981 | int i; | |
982 | ||
983 | for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++) | |
984 | ; | |
985 | BUG_ON(i == ARRAY_SIZE(labels)); | |
986 | split = labels[i].addr; | |
1da177e4 LT |
987 | |
988 | /* | |
95affdda | 989 | * See if we have overflown one way or the other. |
1da177e4 | 990 | */ |
95affdda DD |
991 | if (split > tlb_handler + MIPS64_REFILL_INSNS || |
992 | split < p - MIPS64_REFILL_INSNS) | |
993 | ov = 1; | |
994 | ||
995 | if (ov) { | |
996 | /* | |
997 | * Split two instructions before the end. One | |
998 | * for the branch and one for the instruction | |
999 | * in the delay slot. | |
1000 | */ | |
1001 | split = tlb_handler + MIPS64_REFILL_INSNS - 2; | |
1002 | ||
1003 | /* | |
1004 | * If the branch would fall in a delay slot, | |
1005 | * we must back up an additional instruction | |
1006 | * so that it is no longer in a delay slot. | |
1007 | */ | |
1008 | if (uasm_insn_has_bdelay(relocs, split - 1)) | |
1009 | split--; | |
1010 | } | |
1da177e4 | 1011 | /* Copy first part of the handler. */ |
e30ec452 | 1012 | uasm_copy_handler(relocs, labels, tlb_handler, split, f); |
1da177e4 LT |
1013 | f += split - tlb_handler; |
1014 | ||
95affdda DD |
1015 | if (ov) { |
1016 | /* Insert branch. */ | |
1017 | uasm_l_split(&l, final_handler); | |
1018 | uasm_il_b(&f, &r, label_split); | |
1019 | if (uasm_insn_has_bdelay(relocs, split)) | |
1020 | uasm_i_nop(&f); | |
1021 | else { | |
1022 | uasm_copy_handler(relocs, labels, | |
1023 | split, split + 1, f); | |
1024 | uasm_move_labels(labels, f, f + 1, -1); | |
1025 | f++; | |
1026 | split++; | |
1027 | } | |
1da177e4 LT |
1028 | } |
1029 | ||
1030 | /* Copy the rest of the handler. */ | |
e30ec452 | 1031 | uasm_copy_handler(relocs, labels, split, p, final_handler); |
e6f72d3a DD |
1032 | final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) + |
1033 | (p - split); | |
1da177e4 | 1034 | } |
875d43e7 | 1035 | #endif /* CONFIG_64BIT */ |
1da177e4 | 1036 | |
e30ec452 TS |
1037 | uasm_resolve_relocs(relocs, labels); |
1038 | pr_debug("Wrote TLB refill handler (%u instructions).\n", | |
1039 | final_len); | |
1da177e4 | 1040 | |
91b05e67 | 1041 | memcpy((void *)ebase, final_handler, 0x100); |
92b1e6a6 FBH |
1042 | |
1043 | dump_handler((u32 *)ebase, 64); | |
1da177e4 LT |
1044 | } |
1045 | ||
1da177e4 LT |
1046 | /* |
1047 | * 128 instructions for the fastpath handler is generous and should | |
1048 | * never be exceeded. | |
1049 | */ | |
1050 | #define FASTPATH_SIZE 128 | |
1051 | ||
cbdbe07f FBH |
1052 | u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned; |
1053 | u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned; | |
1054 | u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned; | |
3d8bfdd0 DD |
1055 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
1056 | u32 tlbmiss_handler_setup_pgd[16] __cacheline_aligned; | |
1057 | ||
1058 | static void __cpuinit build_r4000_setup_pgd(void) | |
1059 | { | |
1060 | const int a0 = 4; | |
1061 | const int a1 = 5; | |
1062 | u32 *p = tlbmiss_handler_setup_pgd; | |
1063 | struct uasm_label *l = labels; | |
1064 | struct uasm_reloc *r = relocs; | |
1065 | ||
1066 | memset(tlbmiss_handler_setup_pgd, 0, sizeof(tlbmiss_handler_setup_pgd)); | |
1067 | memset(labels, 0, sizeof(labels)); | |
1068 | memset(relocs, 0, sizeof(relocs)); | |
1069 | ||
1070 | pgd_reg = allocate_kscratch(); | |
1071 | ||
1072 | if (pgd_reg == -1) { | |
1073 | /* PGD << 11 in c0_Context */ | |
1074 | /* | |
1075 | * If it is a ckseg0 address, convert to a physical | |
1076 | * address. Shifting right by 29 and adding 4 will | |
1077 | * result in zero for these addresses. | |
1078 | * | |
1079 | */ | |
1080 | UASM_i_SRA(&p, a1, a0, 29); | |
1081 | UASM_i_ADDIU(&p, a1, a1, 4); | |
1082 | uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1); | |
1083 | uasm_i_nop(&p); | |
1084 | uasm_i_dinsm(&p, a0, 0, 29, 64 - 29); | |
1085 | uasm_l_tlbl_goaround1(&l, p); | |
1086 | UASM_i_SLL(&p, a0, a0, 11); | |
1087 | uasm_i_jr(&p, 31); | |
1088 | UASM_i_MTC0(&p, a0, C0_CONTEXT); | |
1089 | } else { | |
1090 | /* PGD in c0_KScratch */ | |
1091 | uasm_i_jr(&p, 31); | |
1092 | UASM_i_MTC0(&p, a0, 31, pgd_reg); | |
1093 | } | |
1094 | if (p - tlbmiss_handler_setup_pgd > ARRAY_SIZE(tlbmiss_handler_setup_pgd)) | |
1095 | panic("tlbmiss_handler_setup_pgd space exceeded"); | |
1096 | uasm_resolve_relocs(relocs, labels); | |
1097 | pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n", | |
1098 | (unsigned int)(p - tlbmiss_handler_setup_pgd)); | |
1099 | ||
1100 | dump_handler(tlbmiss_handler_setup_pgd, | |
1101 | ARRAY_SIZE(tlbmiss_handler_setup_pgd)); | |
1102 | } | |
1103 | #endif | |
1da177e4 | 1104 | |
234fcd14 | 1105 | static void __cpuinit |
bd1437e4 | 1106 | iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) |
1da177e4 LT |
1107 | { |
1108 | #ifdef CONFIG_SMP | |
1109 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1110 | if (cpu_has_64bits) | |
e30ec452 | 1111 | uasm_i_lld(p, pte, 0, ptr); |
1da177e4 LT |
1112 | else |
1113 | # endif | |
e30ec452 | 1114 | UASM_i_LL(p, pte, 0, ptr); |
1da177e4 LT |
1115 | #else |
1116 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1117 | if (cpu_has_64bits) | |
e30ec452 | 1118 | uasm_i_ld(p, pte, 0, ptr); |
1da177e4 LT |
1119 | else |
1120 | # endif | |
e30ec452 | 1121 | UASM_i_LW(p, pte, 0, ptr); |
1da177e4 LT |
1122 | #endif |
1123 | } | |
1124 | ||
234fcd14 | 1125 | static void __cpuinit |
e30ec452 | 1126 | iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, |
63b2d2f4 | 1127 | unsigned int mode) |
1da177e4 | 1128 | { |
63b2d2f4 TS |
1129 | #ifdef CONFIG_64BIT_PHYS_ADDR |
1130 | unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); | |
1131 | #endif | |
1132 | ||
e30ec452 | 1133 | uasm_i_ori(p, pte, pte, mode); |
1da177e4 LT |
1134 | #ifdef CONFIG_SMP |
1135 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1136 | if (cpu_has_64bits) | |
e30ec452 | 1137 | uasm_i_scd(p, pte, 0, ptr); |
1da177e4 LT |
1138 | else |
1139 | # endif | |
e30ec452 | 1140 | UASM_i_SC(p, pte, 0, ptr); |
1da177e4 LT |
1141 | |
1142 | if (r10000_llsc_war()) | |
e30ec452 | 1143 | uasm_il_beqzl(p, r, pte, label_smp_pgtable_change); |
1da177e4 | 1144 | else |
e30ec452 | 1145 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); |
1da177e4 LT |
1146 | |
1147 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1148 | if (!cpu_has_64bits) { | |
e30ec452 TS |
1149 | /* no uasm_i_nop needed */ |
1150 | uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr); | |
1151 | uasm_i_ori(p, pte, pte, hwmode); | |
1152 | uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr); | |
1153 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); | |
1154 | /* no uasm_i_nop needed */ | |
1155 | uasm_i_lw(p, pte, 0, ptr); | |
1da177e4 | 1156 | } else |
e30ec452 | 1157 | uasm_i_nop(p); |
1da177e4 | 1158 | # else |
e30ec452 | 1159 | uasm_i_nop(p); |
1da177e4 LT |
1160 | # endif |
1161 | #else | |
1162 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1163 | if (cpu_has_64bits) | |
e30ec452 | 1164 | uasm_i_sd(p, pte, 0, ptr); |
1da177e4 LT |
1165 | else |
1166 | # endif | |
e30ec452 | 1167 | UASM_i_SW(p, pte, 0, ptr); |
1da177e4 LT |
1168 | |
1169 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1170 | if (!cpu_has_64bits) { | |
e30ec452 TS |
1171 | uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr); |
1172 | uasm_i_ori(p, pte, pte, hwmode); | |
1173 | uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr); | |
1174 | uasm_i_lw(p, pte, 0, ptr); | |
1da177e4 LT |
1175 | } |
1176 | # endif | |
1177 | #endif | |
1178 | } | |
1179 | ||
1180 | /* | |
1181 | * Check if PTE is present, if not then jump to LABEL. PTR points to | |
1182 | * the page table where this PTE is located, PTE will be re-loaded | |
1183 | * with it's original value. | |
1184 | */ | |
234fcd14 | 1185 | static void __cpuinit |
bd1437e4 | 1186 | build_pte_present(u32 **p, struct uasm_reloc **r, |
1da177e4 LT |
1187 | unsigned int pte, unsigned int ptr, enum label_id lid) |
1188 | { | |
6dd9344c DD |
1189 | if (kernel_uses_smartmips_rixi) { |
1190 | uasm_i_andi(p, pte, pte, _PAGE_PRESENT); | |
1191 | uasm_il_beqz(p, r, pte, lid); | |
1192 | } else { | |
1193 | uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); | |
1194 | uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); | |
1195 | uasm_il_bnez(p, r, pte, lid); | |
1196 | } | |
bd1437e4 | 1197 | iPTE_LW(p, pte, ptr); |
1da177e4 LT |
1198 | } |
1199 | ||
1200 | /* Make PTE valid, store result in PTR. */ | |
234fcd14 | 1201 | static void __cpuinit |
e30ec452 | 1202 | build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte, |
1da177e4 LT |
1203 | unsigned int ptr) |
1204 | { | |
63b2d2f4 TS |
1205 | unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; |
1206 | ||
1207 | iPTE_SW(p, r, pte, ptr, mode); | |
1da177e4 LT |
1208 | } |
1209 | ||
1210 | /* | |
1211 | * Check if PTE can be written to, if not branch to LABEL. Regardless | |
1212 | * restore PTE with value from PTR when done. | |
1213 | */ | |
234fcd14 | 1214 | static void __cpuinit |
bd1437e4 | 1215 | build_pte_writable(u32 **p, struct uasm_reloc **r, |
1da177e4 LT |
1216 | unsigned int pte, unsigned int ptr, enum label_id lid) |
1217 | { | |
e30ec452 TS |
1218 | uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); |
1219 | uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); | |
1220 | uasm_il_bnez(p, r, pte, lid); | |
bd1437e4 | 1221 | iPTE_LW(p, pte, ptr); |
1da177e4 LT |
1222 | } |
1223 | ||
1224 | /* Make PTE writable, update software status bits as well, then store | |
1225 | * at PTR. | |
1226 | */ | |
234fcd14 | 1227 | static void __cpuinit |
e30ec452 | 1228 | build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte, |
1da177e4 LT |
1229 | unsigned int ptr) |
1230 | { | |
63b2d2f4 TS |
1231 | unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID |
1232 | | _PAGE_DIRTY); | |
1233 | ||
1234 | iPTE_SW(p, r, pte, ptr, mode); | |
1da177e4 LT |
1235 | } |
1236 | ||
1237 | /* | |
1238 | * Check if PTE can be modified, if not branch to LABEL. Regardless | |
1239 | * restore PTE with value from PTR when done. | |
1240 | */ | |
234fcd14 | 1241 | static void __cpuinit |
bd1437e4 | 1242 | build_pte_modifiable(u32 **p, struct uasm_reloc **r, |
1da177e4 LT |
1243 | unsigned int pte, unsigned int ptr, enum label_id lid) |
1244 | { | |
e30ec452 TS |
1245 | uasm_i_andi(p, pte, pte, _PAGE_WRITE); |
1246 | uasm_il_beqz(p, r, pte, lid); | |
bd1437e4 | 1247 | iPTE_LW(p, pte, ptr); |
1da177e4 LT |
1248 | } |
1249 | ||
82622284 | 1250 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
3d8bfdd0 DD |
1251 | |
1252 | ||
1da177e4 LT |
1253 | /* |
1254 | * R3000 style TLB load/store/modify handlers. | |
1255 | */ | |
1256 | ||
fded2e50 MR |
1257 | /* |
1258 | * This places the pte into ENTRYLO0 and writes it with tlbwi. | |
1259 | * Then it returns. | |
1260 | */ | |
234fcd14 | 1261 | static void __cpuinit |
fded2e50 | 1262 | build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) |
1da177e4 | 1263 | { |
e30ec452 TS |
1264 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ |
1265 | uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ | |
1266 | uasm_i_tlbwi(p); | |
1267 | uasm_i_jr(p, tmp); | |
1268 | uasm_i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1269 | } |
1270 | ||
1271 | /* | |
fded2e50 MR |
1272 | * This places the pte into ENTRYLO0 and writes it with tlbwi |
1273 | * or tlbwr as appropriate. This is because the index register | |
1274 | * may have the probe fail bit set as a result of a trap on a | |
1275 | * kseg2 access, i.e. without refill. Then it returns. | |
1da177e4 | 1276 | */ |
234fcd14 | 1277 | static void __cpuinit |
e30ec452 TS |
1278 | build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l, |
1279 | struct uasm_reloc **r, unsigned int pte, | |
1280 | unsigned int tmp) | |
1281 | { | |
1282 | uasm_i_mfc0(p, tmp, C0_INDEX); | |
1283 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ | |
1284 | uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ | |
1285 | uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */ | |
1286 | uasm_i_tlbwi(p); /* cp0 delay */ | |
1287 | uasm_i_jr(p, tmp); | |
1288 | uasm_i_rfe(p); /* branch delay */ | |
1289 | uasm_l_r3000_write_probe_fail(l, *p); | |
1290 | uasm_i_tlbwr(p); /* cp0 delay */ | |
1291 | uasm_i_jr(p, tmp); | |
1292 | uasm_i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1293 | } |
1294 | ||
234fcd14 | 1295 | static void __cpuinit |
1da177e4 LT |
1296 | build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, |
1297 | unsigned int ptr) | |
1298 | { | |
1299 | long pgdc = (long)pgd_current; | |
1300 | ||
e30ec452 TS |
1301 | uasm_i_mfc0(p, pte, C0_BADVADDR); |
1302 | uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */ | |
1303 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1304 | uasm_i_srl(p, pte, pte, 22); /* load delay */ | |
1305 | uasm_i_sll(p, pte, pte, 2); | |
1306 | uasm_i_addu(p, ptr, ptr, pte); | |
1307 | uasm_i_mfc0(p, pte, C0_CONTEXT); | |
1308 | uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */ | |
1309 | uasm_i_andi(p, pte, pte, 0xffc); /* load delay */ | |
1310 | uasm_i_addu(p, ptr, ptr, pte); | |
1311 | uasm_i_lw(p, pte, 0, ptr); | |
1312 | uasm_i_tlbp(p); /* load delay */ | |
1da177e4 LT |
1313 | } |
1314 | ||
234fcd14 | 1315 | static void __cpuinit build_r3000_tlb_load_handler(void) |
1da177e4 LT |
1316 | { |
1317 | u32 *p = handle_tlbl; | |
e30ec452 TS |
1318 | struct uasm_label *l = labels; |
1319 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1320 | |
1321 | memset(handle_tlbl, 0, sizeof(handle_tlbl)); | |
1322 | memset(labels, 0, sizeof(labels)); | |
1323 | memset(relocs, 0, sizeof(relocs)); | |
1324 | ||
1325 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
bd1437e4 | 1326 | build_pte_present(&p, &r, K0, K1, label_nopage_tlbl); |
e30ec452 | 1327 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1328 | build_make_valid(&p, &r, K0, K1); |
fded2e50 | 1329 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 | 1330 | |
e30ec452 TS |
1331 | uasm_l_nopage_tlbl(&l, p); |
1332 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); | |
1333 | uasm_i_nop(&p); | |
1da177e4 LT |
1334 | |
1335 | if ((p - handle_tlbl) > FASTPATH_SIZE) | |
1336 | panic("TLB load handler fastpath space exceeded"); | |
1337 | ||
e30ec452 TS |
1338 | uasm_resolve_relocs(relocs, labels); |
1339 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", | |
1340 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 1341 | |
92b1e6a6 | 1342 | dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl)); |
1da177e4 LT |
1343 | } |
1344 | ||
234fcd14 | 1345 | static void __cpuinit build_r3000_tlb_store_handler(void) |
1da177e4 LT |
1346 | { |
1347 | u32 *p = handle_tlbs; | |
e30ec452 TS |
1348 | struct uasm_label *l = labels; |
1349 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1350 | |
1351 | memset(handle_tlbs, 0, sizeof(handle_tlbs)); | |
1352 | memset(labels, 0, sizeof(labels)); | |
1353 | memset(relocs, 0, sizeof(relocs)); | |
1354 | ||
1355 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
bd1437e4 | 1356 | build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs); |
e30ec452 | 1357 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1358 | build_make_write(&p, &r, K0, K1); |
fded2e50 | 1359 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 | 1360 | |
e30ec452 TS |
1361 | uasm_l_nopage_tlbs(&l, p); |
1362 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1363 | uasm_i_nop(&p); | |
1da177e4 LT |
1364 | |
1365 | if ((p - handle_tlbs) > FASTPATH_SIZE) | |
1366 | panic("TLB store handler fastpath space exceeded"); | |
1367 | ||
e30ec452 TS |
1368 | uasm_resolve_relocs(relocs, labels); |
1369 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", | |
1370 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 1371 | |
92b1e6a6 | 1372 | dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs)); |
1da177e4 LT |
1373 | } |
1374 | ||
234fcd14 | 1375 | static void __cpuinit build_r3000_tlb_modify_handler(void) |
1da177e4 LT |
1376 | { |
1377 | u32 *p = handle_tlbm; | |
e30ec452 TS |
1378 | struct uasm_label *l = labels; |
1379 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1380 | |
1381 | memset(handle_tlbm, 0, sizeof(handle_tlbm)); | |
1382 | memset(labels, 0, sizeof(labels)); | |
1383 | memset(relocs, 0, sizeof(relocs)); | |
1384 | ||
1385 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
bd1437e4 | 1386 | build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm); |
e30ec452 | 1387 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1388 | build_make_write(&p, &r, K0, K1); |
fded2e50 | 1389 | build_r3000_pte_reload_tlbwi(&p, K0, K1); |
1da177e4 | 1390 | |
e30ec452 TS |
1391 | uasm_l_nopage_tlbm(&l, p); |
1392 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1393 | uasm_i_nop(&p); | |
1da177e4 LT |
1394 | |
1395 | if ((p - handle_tlbm) > FASTPATH_SIZE) | |
1396 | panic("TLB modify handler fastpath space exceeded"); | |
1397 | ||
e30ec452 TS |
1398 | uasm_resolve_relocs(relocs, labels); |
1399 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", | |
1400 | (unsigned int)(p - handle_tlbm)); | |
1da177e4 | 1401 | |
92b1e6a6 | 1402 | dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm)); |
1da177e4 | 1403 | } |
82622284 | 1404 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ |
1da177e4 LT |
1405 | |
1406 | /* | |
1407 | * R4000 style TLB load/store/modify handlers. | |
1408 | */ | |
234fcd14 | 1409 | static void __cpuinit |
e30ec452 TS |
1410 | build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l, |
1411 | struct uasm_reloc **r, unsigned int pte, | |
1da177e4 LT |
1412 | unsigned int ptr) |
1413 | { | |
875d43e7 | 1414 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1415 | build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */ |
1416 | #else | |
1417 | build_get_pgde32(p, pte, ptr); /* get pgd in ptr */ | |
1418 | #endif | |
1419 | ||
fd062c84 DD |
1420 | #ifdef CONFIG_HUGETLB_PAGE |
1421 | /* | |
1422 | * For huge tlb entries, pmd doesn't contain an address but | |
1423 | * instead contains the tlb pte. Check the PAGE_HUGE bit and | |
1424 | * see if we need to jump to huge tlb processing. | |
1425 | */ | |
1426 | build_is_huge_pte(p, r, pte, ptr, label_tlb_huge_update); | |
1427 | #endif | |
1428 | ||
e30ec452 TS |
1429 | UASM_i_MFC0(p, pte, C0_BADVADDR); |
1430 | UASM_i_LW(p, ptr, 0, ptr); | |
1431 | UASM_i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); | |
1432 | uasm_i_andi(p, pte, pte, (PTRS_PER_PTE - 1) << PTE_T_LOG2); | |
1433 | UASM_i_ADDU(p, ptr, ptr, pte); | |
1da177e4 LT |
1434 | |
1435 | #ifdef CONFIG_SMP | |
e30ec452 TS |
1436 | uasm_l_smp_pgtable_change(l, *p); |
1437 | #endif | |
bd1437e4 | 1438 | iPTE_LW(p, pte, ptr); /* get even pte */ |
8df5beac MR |
1439 | if (!m4kc_tlbp_war()) |
1440 | build_tlb_probe_entry(p); | |
1da177e4 LT |
1441 | } |
1442 | ||
234fcd14 | 1443 | static void __cpuinit |
e30ec452 TS |
1444 | build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, |
1445 | struct uasm_reloc **r, unsigned int tmp, | |
1da177e4 LT |
1446 | unsigned int ptr) |
1447 | { | |
e30ec452 TS |
1448 | uasm_i_ori(p, ptr, ptr, sizeof(pte_t)); |
1449 | uasm_i_xori(p, ptr, ptr, sizeof(pte_t)); | |
1da177e4 LT |
1450 | build_update_entries(p, tmp, ptr); |
1451 | build_tlb_write_entry(p, l, r, tlb_indexed); | |
e30ec452 TS |
1452 | uasm_l_leave(l, *p); |
1453 | uasm_i_eret(p); /* return from trap */ | |
1da177e4 | 1454 | |
875d43e7 | 1455 | #ifdef CONFIG_64BIT |
1ec56329 | 1456 | build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill); |
1da177e4 LT |
1457 | #endif |
1458 | } | |
1459 | ||
234fcd14 | 1460 | static void __cpuinit build_r4000_tlb_load_handler(void) |
1da177e4 LT |
1461 | { |
1462 | u32 *p = handle_tlbl; | |
e30ec452 TS |
1463 | struct uasm_label *l = labels; |
1464 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1465 | |
1466 | memset(handle_tlbl, 0, sizeof(handle_tlbl)); | |
1467 | memset(labels, 0, sizeof(labels)); | |
1468 | memset(relocs, 0, sizeof(relocs)); | |
1469 | ||
1470 | if (bcm1250_m3_war()) { | |
3d45285d RB |
1471 | unsigned int segbits = 44; |
1472 | ||
1473 | uasm_i_dmfc0(&p, K0, C0_BADVADDR); | |
1474 | uasm_i_dmfc0(&p, K1, C0_ENTRYHI); | |
e30ec452 | 1475 | uasm_i_xor(&p, K0, K0, K1); |
3be6022c DD |
1476 | uasm_i_dsrl_safe(&p, K1, K0, 62); |
1477 | uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); | |
1478 | uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); | |
3d45285d | 1479 | uasm_i_or(&p, K0, K0, K1); |
e30ec452 TS |
1480 | uasm_il_bnez(&p, &r, K0, label_leave); |
1481 | /* No need for uasm_i_nop */ | |
1da177e4 LT |
1482 | } |
1483 | ||
1484 | build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); | |
bd1437e4 | 1485 | build_pte_present(&p, &r, K0, K1, label_nopage_tlbl); |
8df5beac MR |
1486 | if (m4kc_tlbp_war()) |
1487 | build_tlb_probe_entry(&p); | |
6dd9344c DD |
1488 | |
1489 | if (kernel_uses_smartmips_rixi) { | |
1490 | /* | |
1491 | * If the page is not _PAGE_VALID, RI or XI could not | |
1492 | * have triggered it. Skip the expensive test.. | |
1493 | */ | |
1494 | uasm_i_andi(&p, K0, K0, _PAGE_VALID); | |
1495 | uasm_il_beqz(&p, &r, K0, label_tlbl_goaround1); | |
1496 | uasm_i_nop(&p); | |
1497 | ||
1498 | uasm_i_tlbr(&p); | |
1499 | /* Examine entrylo 0 or 1 based on ptr. */ | |
1500 | uasm_i_andi(&p, K0, K1, sizeof(pte_t)); | |
1501 | uasm_i_beqz(&p, K0, 8); | |
1502 | ||
1503 | UASM_i_MFC0(&p, K0, C0_ENTRYLO0); /* load it in the delay slot*/ | |
1504 | UASM_i_MFC0(&p, K0, C0_ENTRYLO1); /* load it if ptr is odd */ | |
1505 | /* | |
1506 | * If the entryLo (now in K0) is valid (bit 1), RI or | |
1507 | * XI must have triggered it. | |
1508 | */ | |
1509 | uasm_i_andi(&p, K0, K0, 2); | |
1510 | uasm_il_bnez(&p, &r, K0, label_nopage_tlbl); | |
1511 | ||
1512 | uasm_l_tlbl_goaround1(&l, p); | |
1513 | /* Reload the PTE value */ | |
1514 | iPTE_LW(&p, K0, K1); | |
1515 | } | |
1da177e4 LT |
1516 | build_make_valid(&p, &r, K0, K1); |
1517 | build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); | |
1518 | ||
fd062c84 DD |
1519 | #ifdef CONFIG_HUGETLB_PAGE |
1520 | /* | |
1521 | * This is the entry point when build_r4000_tlbchange_handler_head | |
1522 | * spots a huge page. | |
1523 | */ | |
1524 | uasm_l_tlb_huge_update(&l, p); | |
1525 | iPTE_LW(&p, K0, K1); | |
1526 | build_pte_present(&p, &r, K0, K1, label_nopage_tlbl); | |
1527 | build_tlb_probe_entry(&p); | |
6dd9344c DD |
1528 | |
1529 | if (kernel_uses_smartmips_rixi) { | |
1530 | /* | |
1531 | * If the page is not _PAGE_VALID, RI or XI could not | |
1532 | * have triggered it. Skip the expensive test.. | |
1533 | */ | |
1534 | uasm_i_andi(&p, K0, K0, _PAGE_VALID); | |
1535 | uasm_il_beqz(&p, &r, K0, label_tlbl_goaround2); | |
1536 | uasm_i_nop(&p); | |
1537 | ||
1538 | uasm_i_tlbr(&p); | |
1539 | /* Examine entrylo 0 or 1 based on ptr. */ | |
1540 | uasm_i_andi(&p, K0, K1, sizeof(pte_t)); | |
1541 | uasm_i_beqz(&p, K0, 8); | |
1542 | ||
1543 | UASM_i_MFC0(&p, K0, C0_ENTRYLO0); /* load it in the delay slot*/ | |
1544 | UASM_i_MFC0(&p, K0, C0_ENTRYLO1); /* load it if ptr is odd */ | |
1545 | /* | |
1546 | * If the entryLo (now in K0) is valid (bit 1), RI or | |
1547 | * XI must have triggered it. | |
1548 | */ | |
1549 | uasm_i_andi(&p, K0, K0, 2); | |
1550 | uasm_il_beqz(&p, &r, K0, label_tlbl_goaround2); | |
1551 | /* Reload the PTE value */ | |
1552 | iPTE_LW(&p, K0, K1); | |
1553 | ||
1554 | /* | |
1555 | * We clobbered C0_PAGEMASK, restore it. On the other branch | |
1556 | * it is restored in build_huge_tlb_write_entry. | |
1557 | */ | |
1558 | build_restore_pagemask(&p, &r, K0, label_nopage_tlbl); | |
1559 | ||
1560 | uasm_l_tlbl_goaround2(&l, p); | |
1561 | } | |
fd062c84 DD |
1562 | uasm_i_ori(&p, K0, K0, (_PAGE_ACCESSED | _PAGE_VALID)); |
1563 | build_huge_handler_tail(&p, &r, &l, K0, K1); | |
1564 | #endif | |
1565 | ||
e30ec452 TS |
1566 | uasm_l_nopage_tlbl(&l, p); |
1567 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); | |
1568 | uasm_i_nop(&p); | |
1da177e4 LT |
1569 | |
1570 | if ((p - handle_tlbl) > FASTPATH_SIZE) | |
1571 | panic("TLB load handler fastpath space exceeded"); | |
1572 | ||
e30ec452 TS |
1573 | uasm_resolve_relocs(relocs, labels); |
1574 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", | |
1575 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 1576 | |
92b1e6a6 | 1577 | dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl)); |
1da177e4 LT |
1578 | } |
1579 | ||
234fcd14 | 1580 | static void __cpuinit build_r4000_tlb_store_handler(void) |
1da177e4 LT |
1581 | { |
1582 | u32 *p = handle_tlbs; | |
e30ec452 TS |
1583 | struct uasm_label *l = labels; |
1584 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1585 | |
1586 | memset(handle_tlbs, 0, sizeof(handle_tlbs)); | |
1587 | memset(labels, 0, sizeof(labels)); | |
1588 | memset(relocs, 0, sizeof(relocs)); | |
1589 | ||
1590 | build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); | |
bd1437e4 | 1591 | build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs); |
8df5beac MR |
1592 | if (m4kc_tlbp_war()) |
1593 | build_tlb_probe_entry(&p); | |
1da177e4 LT |
1594 | build_make_write(&p, &r, K0, K1); |
1595 | build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); | |
1596 | ||
fd062c84 DD |
1597 | #ifdef CONFIG_HUGETLB_PAGE |
1598 | /* | |
1599 | * This is the entry point when | |
1600 | * build_r4000_tlbchange_handler_head spots a huge page. | |
1601 | */ | |
1602 | uasm_l_tlb_huge_update(&l, p); | |
1603 | iPTE_LW(&p, K0, K1); | |
1604 | build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs); | |
1605 | build_tlb_probe_entry(&p); | |
1606 | uasm_i_ori(&p, K0, K0, | |
1607 | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); | |
1608 | build_huge_handler_tail(&p, &r, &l, K0, K1); | |
1609 | #endif | |
1610 | ||
e30ec452 TS |
1611 | uasm_l_nopage_tlbs(&l, p); |
1612 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1613 | uasm_i_nop(&p); | |
1da177e4 LT |
1614 | |
1615 | if ((p - handle_tlbs) > FASTPATH_SIZE) | |
1616 | panic("TLB store handler fastpath space exceeded"); | |
1617 | ||
e30ec452 TS |
1618 | uasm_resolve_relocs(relocs, labels); |
1619 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", | |
1620 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 1621 | |
92b1e6a6 | 1622 | dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs)); |
1da177e4 LT |
1623 | } |
1624 | ||
234fcd14 | 1625 | static void __cpuinit build_r4000_tlb_modify_handler(void) |
1da177e4 LT |
1626 | { |
1627 | u32 *p = handle_tlbm; | |
e30ec452 TS |
1628 | struct uasm_label *l = labels; |
1629 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1630 | |
1631 | memset(handle_tlbm, 0, sizeof(handle_tlbm)); | |
1632 | memset(labels, 0, sizeof(labels)); | |
1633 | memset(relocs, 0, sizeof(relocs)); | |
1634 | ||
1635 | build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); | |
bd1437e4 | 1636 | build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm); |
8df5beac MR |
1637 | if (m4kc_tlbp_war()) |
1638 | build_tlb_probe_entry(&p); | |
1da177e4 LT |
1639 | /* Present and writable bits set, set accessed and dirty bits. */ |
1640 | build_make_write(&p, &r, K0, K1); | |
1641 | build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); | |
1642 | ||
fd062c84 DD |
1643 | #ifdef CONFIG_HUGETLB_PAGE |
1644 | /* | |
1645 | * This is the entry point when | |
1646 | * build_r4000_tlbchange_handler_head spots a huge page. | |
1647 | */ | |
1648 | uasm_l_tlb_huge_update(&l, p); | |
1649 | iPTE_LW(&p, K0, K1); | |
1650 | build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm); | |
1651 | build_tlb_probe_entry(&p); | |
1652 | uasm_i_ori(&p, K0, K0, | |
1653 | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); | |
1654 | build_huge_handler_tail(&p, &r, &l, K0, K1); | |
1655 | #endif | |
1656 | ||
e30ec452 TS |
1657 | uasm_l_nopage_tlbm(&l, p); |
1658 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1659 | uasm_i_nop(&p); | |
1da177e4 LT |
1660 | |
1661 | if ((p - handle_tlbm) > FASTPATH_SIZE) | |
1662 | panic("TLB modify handler fastpath space exceeded"); | |
1663 | ||
e30ec452 TS |
1664 | uasm_resolve_relocs(relocs, labels); |
1665 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", | |
1666 | (unsigned int)(p - handle_tlbm)); | |
115f2a44 | 1667 | |
92b1e6a6 | 1668 | dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm)); |
1da177e4 LT |
1669 | } |
1670 | ||
234fcd14 | 1671 | void __cpuinit build_tlb_refill_handler(void) |
1da177e4 LT |
1672 | { |
1673 | /* | |
1674 | * The refill handler is generated per-CPU, multi-node systems | |
1675 | * may have local storage for it. The other handlers are only | |
1676 | * needed once. | |
1677 | */ | |
1678 | static int run_once = 0; | |
1679 | ||
1ec56329 DD |
1680 | #ifdef CONFIG_64BIT |
1681 | check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); | |
1682 | #endif | |
1683 | ||
10cc3529 | 1684 | switch (current_cpu_type()) { |
1da177e4 LT |
1685 | case CPU_R2000: |
1686 | case CPU_R3000: | |
1687 | case CPU_R3000A: | |
1688 | case CPU_R3081E: | |
1689 | case CPU_TX3912: | |
1690 | case CPU_TX3922: | |
1691 | case CPU_TX3927: | |
82622284 | 1692 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
1da177e4 LT |
1693 | build_r3000_tlb_refill_handler(); |
1694 | if (!run_once) { | |
1695 | build_r3000_tlb_load_handler(); | |
1696 | build_r3000_tlb_store_handler(); | |
1697 | build_r3000_tlb_modify_handler(); | |
1698 | run_once++; | |
1699 | } | |
82622284 DD |
1700 | #else |
1701 | panic("No R3000 TLB refill handler"); | |
1702 | #endif | |
1da177e4 LT |
1703 | break; |
1704 | ||
1705 | case CPU_R6000: | |
1706 | case CPU_R6000A: | |
1707 | panic("No R6000 TLB refill handler yet"); | |
1708 | break; | |
1709 | ||
1710 | case CPU_R8000: | |
1711 | panic("No R8000 TLB refill handler yet"); | |
1712 | break; | |
1713 | ||
1714 | default: | |
1da177e4 | 1715 | if (!run_once) { |
3d8bfdd0 DD |
1716 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
1717 | build_r4000_setup_pgd(); | |
1718 | #endif | |
1da177e4 LT |
1719 | build_r4000_tlb_load_handler(); |
1720 | build_r4000_tlb_store_handler(); | |
1721 | build_r4000_tlb_modify_handler(); | |
1722 | run_once++; | |
1723 | } | |
3d8bfdd0 | 1724 | build_r4000_tlb_refill_handler(); |
1da177e4 LT |
1725 | } |
1726 | } | |
1d40cfcd | 1727 | |
234fcd14 | 1728 | void __cpuinit flush_tlb_handlers(void) |
1d40cfcd | 1729 | { |
e0cee3ee | 1730 | local_flush_icache_range((unsigned long)handle_tlbl, |
1d40cfcd | 1731 | (unsigned long)handle_tlbl + sizeof(handle_tlbl)); |
e0cee3ee | 1732 | local_flush_icache_range((unsigned long)handle_tlbs, |
1d40cfcd | 1733 | (unsigned long)handle_tlbs + sizeof(handle_tlbs)); |
e0cee3ee | 1734 | local_flush_icache_range((unsigned long)handle_tlbm, |
1d40cfcd | 1735 | (unsigned long)handle_tlbm + sizeof(handle_tlbm)); |
3d8bfdd0 DD |
1736 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
1737 | local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, | |
1738 | (unsigned long)tlbmiss_handler_setup_pgd + sizeof(handle_tlbm)); | |
1739 | #endif | |
1d40cfcd | 1740 | } |