Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Synthesize TLB refill handlers at runtime. | |
7 | * | |
e30ec452 | 8 | * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer |
95affdda | 9 | * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki |
41c594ab | 10 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) |
fd062c84 | 11 | * Copyright (C) 2008, 2009 Cavium Networks, Inc. |
41c594ab RB |
12 | * |
13 | * ... and the days got worse and worse and now you see | |
14 | * I've gone completly out of my mind. | |
15 | * | |
16 | * They're coming to take me a away haha | |
17 | * they're coming to take me a away hoho hihi haha | |
18 | * to the funny farm where code is beautiful all the time ... | |
19 | * | |
20 | * (Condolences to Napoleon XIV) | |
1da177e4 LT |
21 | */ |
22 | ||
95affdda | 23 | #include <linux/bug.h> |
1da177e4 LT |
24 | #include <linux/kernel.h> |
25 | #include <linux/types.h> | |
631330f5 | 26 | #include <linux/smp.h> |
1da177e4 LT |
27 | #include <linux/string.h> |
28 | #include <linux/init.h> | |
3d8bfdd0 | 29 | #include <linux/cache.h> |
1da177e4 | 30 | |
3d8bfdd0 DD |
31 | #include <asm/cacheflush.h> |
32 | #include <asm/pgtable.h> | |
1da177e4 | 33 | #include <asm/war.h> |
3482d713 | 34 | #include <asm/uasm.h> |
e30ec452 | 35 | |
1ec56329 DD |
36 | /* |
37 | * TLB load/store/modify handlers. | |
38 | * | |
39 | * Only the fastpath gets synthesized at runtime, the slowpath for | |
40 | * do_page_fault remains normal asm. | |
41 | */ | |
42 | extern void tlb_do_page_fault_0(void); | |
43 | extern void tlb_do_page_fault_1(void); | |
44 | ||
45 | ||
aeffdbba | 46 | static inline int r45k_bvahwbug(void) |
1da177e4 LT |
47 | { |
48 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
49 | return 0; | |
50 | } | |
51 | ||
aeffdbba | 52 | static inline int r4k_250MHZhwbug(void) |
1da177e4 LT |
53 | { |
54 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
55 | return 0; | |
56 | } | |
57 | ||
aeffdbba | 58 | static inline int __maybe_unused bcm1250_m3_war(void) |
1da177e4 LT |
59 | { |
60 | return BCM1250_M3_WAR; | |
61 | } | |
62 | ||
aeffdbba | 63 | static inline int __maybe_unused r10000_llsc_war(void) |
1da177e4 LT |
64 | { |
65 | return R10000_LLSC_WAR; | |
66 | } | |
67 | ||
cc33ae43 DD |
68 | static int use_bbit_insns(void) |
69 | { | |
70 | switch (current_cpu_type()) { | |
71 | case CPU_CAVIUM_OCTEON: | |
72 | case CPU_CAVIUM_OCTEON_PLUS: | |
73 | case CPU_CAVIUM_OCTEON2: | |
74 | return 1; | |
75 | default: | |
76 | return 0; | |
77 | } | |
78 | } | |
79 | ||
8df5beac MR |
80 | /* |
81 | * Found by experiment: At least some revisions of the 4kc throw under | |
82 | * some circumstances a machine check exception, triggered by invalid | |
83 | * values in the index register. Delaying the tlbp instruction until | |
84 | * after the next branch, plus adding an additional nop in front of | |
85 | * tlbwi/tlbwr avoids the invalid index register values. Nobody knows | |
86 | * why; it's not an issue caused by the core RTL. | |
87 | * | |
88 | */ | |
234fcd14 | 89 | static int __cpuinit m4kc_tlbp_war(void) |
8df5beac MR |
90 | { |
91 | return (current_cpu_data.processor_id & 0xffff00) == | |
92 | (PRID_COMP_MIPS | PRID_IMP_4KC); | |
93 | } | |
94 | ||
e30ec452 | 95 | /* Handle labels (which must be positive integers). */ |
1da177e4 | 96 | enum label_id { |
e30ec452 | 97 | label_second_part = 1, |
1da177e4 LT |
98 | label_leave, |
99 | label_vmalloc, | |
100 | label_vmalloc_done, | |
101 | label_tlbw_hazard, | |
102 | label_split, | |
6dd9344c DD |
103 | label_tlbl_goaround1, |
104 | label_tlbl_goaround2, | |
1da177e4 LT |
105 | label_nopage_tlbl, |
106 | label_nopage_tlbs, | |
107 | label_nopage_tlbm, | |
108 | label_smp_pgtable_change, | |
109 | label_r3000_write_probe_fail, | |
1ec56329 | 110 | label_large_segbits_fault, |
fd062c84 DD |
111 | #ifdef CONFIG_HUGETLB_PAGE |
112 | label_tlb_huge_update, | |
113 | #endif | |
1da177e4 LT |
114 | }; |
115 | ||
e30ec452 TS |
116 | UASM_L_LA(_second_part) |
117 | UASM_L_LA(_leave) | |
e30ec452 TS |
118 | UASM_L_LA(_vmalloc) |
119 | UASM_L_LA(_vmalloc_done) | |
120 | UASM_L_LA(_tlbw_hazard) | |
121 | UASM_L_LA(_split) | |
6dd9344c DD |
122 | UASM_L_LA(_tlbl_goaround1) |
123 | UASM_L_LA(_tlbl_goaround2) | |
e30ec452 TS |
124 | UASM_L_LA(_nopage_tlbl) |
125 | UASM_L_LA(_nopage_tlbs) | |
126 | UASM_L_LA(_nopage_tlbm) | |
127 | UASM_L_LA(_smp_pgtable_change) | |
128 | UASM_L_LA(_r3000_write_probe_fail) | |
1ec56329 | 129 | UASM_L_LA(_large_segbits_fault) |
fd062c84 DD |
130 | #ifdef CONFIG_HUGETLB_PAGE |
131 | UASM_L_LA(_tlb_huge_update) | |
132 | #endif | |
656be92f | 133 | |
92b1e6a6 FBH |
134 | /* |
135 | * For debug purposes. | |
136 | */ | |
137 | static inline void dump_handler(const u32 *handler, int count) | |
138 | { | |
139 | int i; | |
140 | ||
141 | pr_debug("\t.set push\n"); | |
142 | pr_debug("\t.set noreorder\n"); | |
143 | ||
144 | for (i = 0; i < count; i++) | |
145 | pr_debug("\t%p\t.word 0x%08x\n", &handler[i], handler[i]); | |
146 | ||
147 | pr_debug("\t.set pop\n"); | |
148 | } | |
149 | ||
1da177e4 LT |
150 | /* The only general purpose registers allowed in TLB handlers. */ |
151 | #define K0 26 | |
152 | #define K1 27 | |
153 | ||
154 | /* Some CP0 registers */ | |
41c594ab RB |
155 | #define C0_INDEX 0, 0 |
156 | #define C0_ENTRYLO0 2, 0 | |
157 | #define C0_TCBIND 2, 2 | |
158 | #define C0_ENTRYLO1 3, 0 | |
159 | #define C0_CONTEXT 4, 0 | |
fd062c84 | 160 | #define C0_PAGEMASK 5, 0 |
41c594ab RB |
161 | #define C0_BADVADDR 8, 0 |
162 | #define C0_ENTRYHI 10, 0 | |
163 | #define C0_EPC 14, 0 | |
164 | #define C0_XCONTEXT 20, 0 | |
1da177e4 | 165 | |
875d43e7 | 166 | #ifdef CONFIG_64BIT |
e30ec452 | 167 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT) |
1da177e4 | 168 | #else |
e30ec452 | 169 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT) |
1da177e4 LT |
170 | #endif |
171 | ||
172 | /* The worst case length of the handler is around 18 instructions for | |
173 | * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. | |
174 | * Maximum space available is 32 instructions for R3000 and 64 | |
175 | * instructions for R4000. | |
176 | * | |
177 | * We deliberately chose a buffer size of 128, so we won't scribble | |
178 | * over anything important on overflow before we panic. | |
179 | */ | |
234fcd14 | 180 | static u32 tlb_handler[128] __cpuinitdata; |
1da177e4 LT |
181 | |
182 | /* simply assume worst case size for labels and relocs */ | |
234fcd14 RB |
183 | static struct uasm_label labels[128] __cpuinitdata; |
184 | static struct uasm_reloc relocs[128] __cpuinitdata; | |
1da177e4 | 185 | |
1ec56329 DD |
186 | #ifdef CONFIG_64BIT |
187 | static int check_for_high_segbits __cpuinitdata; | |
188 | #endif | |
189 | ||
3d8bfdd0 DD |
190 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
191 | ||
192 | static unsigned int kscratch_used_mask __cpuinitdata; | |
193 | ||
194 | static int __cpuinit allocate_kscratch(void) | |
195 | { | |
196 | int r; | |
197 | unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask; | |
198 | ||
199 | r = ffs(a); | |
200 | ||
201 | if (r == 0) | |
202 | return -1; | |
203 | ||
204 | r--; /* make it zero based */ | |
205 | ||
206 | kscratch_used_mask |= (1 << r); | |
207 | ||
208 | return r; | |
209 | } | |
210 | ||
211 | static int pgd_reg __cpuinitdata; | |
212 | ||
213 | #else /* !CONFIG_MIPS_PGD_C0_CONTEXT*/ | |
82622284 DD |
214 | /* |
215 | * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current, | |
216 | * we cannot do r3000 under these circumstances. | |
3d8bfdd0 DD |
217 | * |
218 | * Declare pgd_current here instead of including mmu_context.h to avoid type | |
219 | * conflicts for tlbmiss_handler_setup_pgd | |
82622284 | 220 | */ |
3d8bfdd0 | 221 | extern unsigned long pgd_current[]; |
82622284 | 222 | |
1da177e4 LT |
223 | /* |
224 | * The R3000 TLB handler is simple. | |
225 | */ | |
234fcd14 | 226 | static void __cpuinit build_r3000_tlb_refill_handler(void) |
1da177e4 LT |
227 | { |
228 | long pgdc = (long)pgd_current; | |
229 | u32 *p; | |
230 | ||
231 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
232 | p = tlb_handler; | |
233 | ||
e30ec452 TS |
234 | uasm_i_mfc0(&p, K0, C0_BADVADDR); |
235 | uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */ | |
236 | uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1); | |
237 | uasm_i_srl(&p, K0, K0, 22); /* load delay */ | |
238 | uasm_i_sll(&p, K0, K0, 2); | |
239 | uasm_i_addu(&p, K1, K1, K0); | |
240 | uasm_i_mfc0(&p, K0, C0_CONTEXT); | |
241 | uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */ | |
242 | uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */ | |
243 | uasm_i_addu(&p, K1, K1, K0); | |
244 | uasm_i_lw(&p, K0, 0, K1); | |
245 | uasm_i_nop(&p); /* load delay */ | |
246 | uasm_i_mtc0(&p, K0, C0_ENTRYLO0); | |
247 | uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ | |
248 | uasm_i_tlbwr(&p); /* cp0 delay */ | |
249 | uasm_i_jr(&p, K1); | |
250 | uasm_i_rfe(&p); /* branch delay */ | |
1da177e4 LT |
251 | |
252 | if (p > tlb_handler + 32) | |
253 | panic("TLB refill handler space exceeded"); | |
254 | ||
e30ec452 TS |
255 | pr_debug("Wrote TLB refill handler (%u instructions).\n", |
256 | (unsigned int)(p - tlb_handler)); | |
1da177e4 | 257 | |
91b05e67 | 258 | memcpy((void *)ebase, tlb_handler, 0x80); |
92b1e6a6 FBH |
259 | |
260 | dump_handler((u32 *)ebase, 32); | |
1da177e4 | 261 | } |
82622284 | 262 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ |
1da177e4 LT |
263 | |
264 | /* | |
265 | * The R4000 TLB handler is much more complicated. We have two | |
266 | * consecutive handler areas with 32 instructions space each. | |
267 | * Since they aren't used at the same time, we can overflow in the | |
268 | * other one.To keep things simple, we first assume linear space, | |
269 | * then we relocate it to the final handler layout as needed. | |
270 | */ | |
234fcd14 | 271 | static u32 final_handler[64] __cpuinitdata; |
1da177e4 LT |
272 | |
273 | /* | |
274 | * Hazards | |
275 | * | |
276 | * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: | |
277 | * 2. A timing hazard exists for the TLBP instruction. | |
278 | * | |
279 | * stalling_instruction | |
280 | * TLBP | |
281 | * | |
282 | * The JTLB is being read for the TLBP throughout the stall generated by the | |
283 | * previous instruction. This is not really correct as the stalling instruction | |
284 | * can modify the address used to access the JTLB. The failure symptom is that | |
285 | * the TLBP instruction will use an address created for the stalling instruction | |
286 | * and not the address held in C0_ENHI and thus report the wrong results. | |
287 | * | |
288 | * The software work-around is to not allow the instruction preceding the TLBP | |
289 | * to stall - make it an NOP or some other instruction guaranteed not to stall. | |
290 | * | |
291 | * Errata 2 will not be fixed. This errata is also on the R5000. | |
292 | * | |
293 | * As if we MIPS hackers wouldn't know how to nop pipelines happy ... | |
294 | */ | |
234fcd14 | 295 | static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p) |
1da177e4 | 296 | { |
10cc3529 | 297 | switch (current_cpu_type()) { |
326e2e1a | 298 | /* Found by experiment: R4600 v2.0/R4700 needs this, too. */ |
f5b4d956 | 299 | case CPU_R4600: |
326e2e1a | 300 | case CPU_R4700: |
1da177e4 LT |
301 | case CPU_R5000: |
302 | case CPU_R5000A: | |
303 | case CPU_NEVADA: | |
e30ec452 TS |
304 | uasm_i_nop(p); |
305 | uasm_i_tlbp(p); | |
1da177e4 LT |
306 | break; |
307 | ||
308 | default: | |
e30ec452 | 309 | uasm_i_tlbp(p); |
1da177e4 LT |
310 | break; |
311 | } | |
312 | } | |
313 | ||
314 | /* | |
315 | * Write random or indexed TLB entry, and care about the hazards from | |
316 | * the preceeding mtc0 and for the following eret. | |
317 | */ | |
318 | enum tlb_write_entry { tlb_random, tlb_indexed }; | |
319 | ||
234fcd14 | 320 | static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, |
e30ec452 | 321 | struct uasm_reloc **r, |
1da177e4 LT |
322 | enum tlb_write_entry wmode) |
323 | { | |
324 | void(*tlbw)(u32 **) = NULL; | |
325 | ||
326 | switch (wmode) { | |
e30ec452 TS |
327 | case tlb_random: tlbw = uasm_i_tlbwr; break; |
328 | case tlb_indexed: tlbw = uasm_i_tlbwi; break; | |
1da177e4 LT |
329 | } |
330 | ||
161548bf | 331 | if (cpu_has_mips_r2) { |
41f0e4d0 DD |
332 | if (cpu_has_mips_r2_exec_hazard) |
333 | uasm_i_ehb(p); | |
161548bf RB |
334 | tlbw(p); |
335 | return; | |
336 | } | |
337 | ||
10cc3529 | 338 | switch (current_cpu_type()) { |
1da177e4 LT |
339 | case CPU_R4000PC: |
340 | case CPU_R4000SC: | |
341 | case CPU_R4000MC: | |
342 | case CPU_R4400PC: | |
343 | case CPU_R4400SC: | |
344 | case CPU_R4400MC: | |
345 | /* | |
346 | * This branch uses up a mtc0 hazard nop slot and saves | |
347 | * two nops after the tlbw instruction. | |
348 | */ | |
e30ec452 | 349 | uasm_il_bgezl(p, r, 0, label_tlbw_hazard); |
1da177e4 | 350 | tlbw(p); |
e30ec452 TS |
351 | uasm_l_tlbw_hazard(l, *p); |
352 | uasm_i_nop(p); | |
1da177e4 LT |
353 | break; |
354 | ||
355 | case CPU_R4600: | |
356 | case CPU_R4700: | |
357 | case CPU_R5000: | |
358 | case CPU_R5000A: | |
e30ec452 | 359 | uasm_i_nop(p); |
2c93e12c | 360 | tlbw(p); |
e30ec452 | 361 | uasm_i_nop(p); |
2c93e12c MR |
362 | break; |
363 | ||
364 | case CPU_R4300: | |
1da177e4 LT |
365 | case CPU_5KC: |
366 | case CPU_TX49XX: | |
bdf21b18 | 367 | case CPU_PR4450: |
e30ec452 | 368 | uasm_i_nop(p); |
1da177e4 LT |
369 | tlbw(p); |
370 | break; | |
371 | ||
372 | case CPU_R10000: | |
373 | case CPU_R12000: | |
44d921b2 | 374 | case CPU_R14000: |
1da177e4 | 375 | case CPU_4KC: |
b1ec4c8e | 376 | case CPU_4KEC: |
1da177e4 | 377 | case CPU_SB1: |
93ce2f52 | 378 | case CPU_SB1A: |
1da177e4 LT |
379 | case CPU_4KSC: |
380 | case CPU_20KC: | |
381 | case CPU_25KF: | |
602977b0 KC |
382 | case CPU_BMIPS32: |
383 | case CPU_BMIPS3300: | |
384 | case CPU_BMIPS4350: | |
385 | case CPU_BMIPS4380: | |
386 | case CPU_BMIPS5000: | |
2a21c730 | 387 | case CPU_LOONGSON2: |
a644b277 | 388 | case CPU_R5500: |
8df5beac | 389 | if (m4kc_tlbp_war()) |
e30ec452 | 390 | uasm_i_nop(p); |
2f794d09 | 391 | case CPU_ALCHEMY: |
1da177e4 LT |
392 | tlbw(p); |
393 | break; | |
394 | ||
395 | case CPU_NEVADA: | |
e30ec452 | 396 | uasm_i_nop(p); /* QED specifies 2 nops hazard */ |
1da177e4 LT |
397 | /* |
398 | * This branch uses up a mtc0 hazard nop slot and saves | |
399 | * a nop after the tlbw instruction. | |
400 | */ | |
e30ec452 | 401 | uasm_il_bgezl(p, r, 0, label_tlbw_hazard); |
1da177e4 | 402 | tlbw(p); |
e30ec452 | 403 | uasm_l_tlbw_hazard(l, *p); |
1da177e4 LT |
404 | break; |
405 | ||
406 | case CPU_RM7000: | |
e30ec452 TS |
407 | uasm_i_nop(p); |
408 | uasm_i_nop(p); | |
409 | uasm_i_nop(p); | |
410 | uasm_i_nop(p); | |
1da177e4 LT |
411 | tlbw(p); |
412 | break; | |
413 | ||
1da177e4 LT |
414 | case CPU_RM9000: |
415 | /* | |
416 | * When the JTLB is updated by tlbwi or tlbwr, a subsequent | |
417 | * use of the JTLB for instructions should not occur for 4 | |
418 | * cpu cycles and use for data translations should not occur | |
419 | * for 3 cpu cycles. | |
420 | */ | |
e30ec452 TS |
421 | uasm_i_ssnop(p); |
422 | uasm_i_ssnop(p); | |
423 | uasm_i_ssnop(p); | |
424 | uasm_i_ssnop(p); | |
1da177e4 | 425 | tlbw(p); |
e30ec452 TS |
426 | uasm_i_ssnop(p); |
427 | uasm_i_ssnop(p); | |
428 | uasm_i_ssnop(p); | |
429 | uasm_i_ssnop(p); | |
1da177e4 LT |
430 | break; |
431 | ||
432 | case CPU_VR4111: | |
433 | case CPU_VR4121: | |
434 | case CPU_VR4122: | |
435 | case CPU_VR4181: | |
436 | case CPU_VR4181A: | |
e30ec452 TS |
437 | uasm_i_nop(p); |
438 | uasm_i_nop(p); | |
1da177e4 | 439 | tlbw(p); |
e30ec452 TS |
440 | uasm_i_nop(p); |
441 | uasm_i_nop(p); | |
1da177e4 LT |
442 | break; |
443 | ||
444 | case CPU_VR4131: | |
445 | case CPU_VR4133: | |
7623debf | 446 | case CPU_R5432: |
e30ec452 TS |
447 | uasm_i_nop(p); |
448 | uasm_i_nop(p); | |
1da177e4 LT |
449 | tlbw(p); |
450 | break; | |
451 | ||
83ccf69d LPC |
452 | case CPU_JZRISC: |
453 | tlbw(p); | |
454 | uasm_i_nop(p); | |
455 | break; | |
456 | ||
1da177e4 LT |
457 | default: |
458 | panic("No TLB refill handler yet (CPU type: %d)", | |
459 | current_cpu_data.cputype); | |
460 | break; | |
461 | } | |
462 | } | |
463 | ||
6dd9344c DD |
464 | static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p, |
465 | unsigned int reg) | |
fd062c84 | 466 | { |
6dd9344c DD |
467 | if (kernel_uses_smartmips_rixi) { |
468 | UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC)); | |
469 | UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); | |
470 | } else { | |
471 | #ifdef CONFIG_64BIT_PHYS_ADDR | |
3be6022c | 472 | uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL)); |
6dd9344c DD |
473 | #else |
474 | UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL)); | |
475 | #endif | |
476 | } | |
477 | } | |
fd062c84 | 478 | |
6dd9344c | 479 | #ifdef CONFIG_HUGETLB_PAGE |
fd062c84 | 480 | |
6dd9344c DD |
481 | static __cpuinit void build_restore_pagemask(u32 **p, |
482 | struct uasm_reloc **r, | |
483 | unsigned int tmp, | |
484 | enum label_id lid) | |
485 | { | |
fd062c84 DD |
486 | /* Reset default page size */ |
487 | if (PM_DEFAULT_MASK >> 16) { | |
488 | uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); | |
489 | uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); | |
6dd9344c | 490 | uasm_il_b(p, r, lid); |
fd062c84 DD |
491 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); |
492 | } else if (PM_DEFAULT_MASK) { | |
493 | uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); | |
6dd9344c | 494 | uasm_il_b(p, r, lid); |
fd062c84 DD |
495 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); |
496 | } else { | |
6dd9344c | 497 | uasm_il_b(p, r, lid); |
fd062c84 DD |
498 | uasm_i_mtc0(p, 0, C0_PAGEMASK); |
499 | } | |
500 | } | |
501 | ||
6dd9344c DD |
502 | static __cpuinit void build_huge_tlb_write_entry(u32 **p, |
503 | struct uasm_label **l, | |
504 | struct uasm_reloc **r, | |
505 | unsigned int tmp, | |
506 | enum tlb_write_entry wmode) | |
507 | { | |
508 | /* Set huge page tlb entry size */ | |
509 | uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16); | |
510 | uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff); | |
511 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
512 | ||
513 | build_tlb_write_entry(p, l, r, wmode); | |
514 | ||
515 | build_restore_pagemask(p, r, tmp, label_leave); | |
516 | } | |
517 | ||
fd062c84 DD |
518 | /* |
519 | * Check if Huge PTE is present, if so then jump to LABEL. | |
520 | */ | |
521 | static void __cpuinit | |
522 | build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp, | |
523 | unsigned int pmd, int lid) | |
524 | { | |
525 | UASM_i_LW(p, tmp, 0, pmd); | |
cc33ae43 DD |
526 | if (use_bbit_insns()) { |
527 | uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid); | |
528 | } else { | |
529 | uasm_i_andi(p, tmp, tmp, _PAGE_HUGE); | |
530 | uasm_il_bnez(p, r, tmp, lid); | |
531 | } | |
fd062c84 DD |
532 | } |
533 | ||
534 | static __cpuinit void build_huge_update_entries(u32 **p, | |
535 | unsigned int pte, | |
536 | unsigned int tmp) | |
537 | { | |
538 | int small_sequence; | |
539 | ||
540 | /* | |
541 | * A huge PTE describes an area the size of the | |
542 | * configured huge page size. This is twice the | |
543 | * of the large TLB entry size we intend to use. | |
544 | * A TLB entry half the size of the configured | |
545 | * huge page size is configured into entrylo0 | |
546 | * and entrylo1 to cover the contiguous huge PTE | |
547 | * address space. | |
548 | */ | |
549 | small_sequence = (HPAGE_SIZE >> 7) < 0x10000; | |
550 | ||
551 | /* We can clobber tmp. It isn't used after this.*/ | |
552 | if (!small_sequence) | |
553 | uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16)); | |
554 | ||
6dd9344c | 555 | build_convert_pte_to_entrylo(p, pte); |
9b8c3891 | 556 | UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */ |
fd062c84 DD |
557 | /* convert to entrylo1 */ |
558 | if (small_sequence) | |
559 | UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7); | |
560 | else | |
561 | UASM_i_ADDU(p, pte, pte, tmp); | |
562 | ||
9b8c3891 | 563 | UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */ |
fd062c84 DD |
564 | } |
565 | ||
566 | static __cpuinit void build_huge_handler_tail(u32 **p, | |
567 | struct uasm_reloc **r, | |
568 | struct uasm_label **l, | |
569 | unsigned int pte, | |
570 | unsigned int ptr) | |
571 | { | |
572 | #ifdef CONFIG_SMP | |
573 | UASM_i_SC(p, pte, 0, ptr); | |
574 | uasm_il_beqz(p, r, pte, label_tlb_huge_update); | |
575 | UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */ | |
576 | #else | |
577 | UASM_i_SW(p, pte, 0, ptr); | |
578 | #endif | |
579 | build_huge_update_entries(p, pte, ptr); | |
580 | build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed); | |
581 | } | |
582 | #endif /* CONFIG_HUGETLB_PAGE */ | |
583 | ||
875d43e7 | 584 | #ifdef CONFIG_64BIT |
1da177e4 LT |
585 | /* |
586 | * TMP and PTR are scratch. | |
587 | * TMP will be clobbered, PTR will hold the pmd entry. | |
588 | */ | |
234fcd14 | 589 | static void __cpuinit |
e30ec452 | 590 | build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
1da177e4 LT |
591 | unsigned int tmp, unsigned int ptr) |
592 | { | |
82622284 | 593 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
1da177e4 | 594 | long pgdc = (long)pgd_current; |
82622284 | 595 | #endif |
1da177e4 LT |
596 | /* |
597 | * The vmalloc handling is not in the hotpath. | |
598 | */ | |
e30ec452 | 599 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); |
1ec56329 DD |
600 | |
601 | if (check_for_high_segbits) { | |
602 | /* | |
603 | * The kernel currently implicitely assumes that the | |
604 | * MIPS SEGBITS parameter for the processor is | |
605 | * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never | |
606 | * allocate virtual addresses outside the maximum | |
607 | * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But | |
608 | * that doesn't prevent user code from accessing the | |
609 | * higher xuseg addresses. Here, we make sure that | |
610 | * everything but the lower xuseg addresses goes down | |
611 | * the module_alloc/vmalloc path. | |
612 | */ | |
613 | uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); | |
614 | uasm_il_bnez(p, r, ptr, label_vmalloc); | |
615 | } else { | |
616 | uasm_il_bltz(p, r, tmp, label_vmalloc); | |
617 | } | |
e30ec452 | 618 | /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ |
1da177e4 | 619 | |
82622284 | 620 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
3d8bfdd0 DD |
621 | if (pgd_reg != -1) { |
622 | /* pgd is in pgd_reg */ | |
623 | UASM_i_MFC0(p, ptr, 31, pgd_reg); | |
624 | } else { | |
625 | /* | |
626 | * &pgd << 11 stored in CONTEXT [23..63]. | |
627 | */ | |
628 | UASM_i_MFC0(p, ptr, C0_CONTEXT); | |
629 | ||
630 | /* Clear lower 23 bits of context. */ | |
631 | uasm_i_dins(p, ptr, 0, 0, 23); | |
632 | ||
633 | /* 1 0 1 0 1 << 6 xkphys cached */ | |
634 | uasm_i_ori(p, ptr, ptr, 0x540); | |
635 | uasm_i_drotr(p, ptr, ptr, 11); | |
636 | } | |
82622284 | 637 | #elif defined(CONFIG_SMP) |
41c594ab RB |
638 | # ifdef CONFIG_MIPS_MT_SMTC |
639 | /* | |
640 | * SMTC uses TCBind value as "CPU" index | |
641 | */ | |
e30ec452 | 642 | uasm_i_mfc0(p, ptr, C0_TCBIND); |
3be6022c | 643 | uasm_i_dsrl_safe(p, ptr, ptr, 19); |
41c594ab | 644 | # else |
1da177e4 | 645 | /* |
1b3a6e97 | 646 | * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 |
1da177e4 LT |
647 | * stored in CONTEXT. |
648 | */ | |
e30ec452 | 649 | uasm_i_dmfc0(p, ptr, C0_CONTEXT); |
3be6022c | 650 | uasm_i_dsrl_safe(p, ptr, ptr, 23); |
82622284 | 651 | # endif |
e30ec452 TS |
652 | UASM_i_LA_mostly(p, tmp, pgdc); |
653 | uasm_i_daddu(p, ptr, ptr, tmp); | |
654 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); | |
655 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1da177e4 | 656 | #else |
e30ec452 TS |
657 | UASM_i_LA_mostly(p, ptr, pgdc); |
658 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1da177e4 LT |
659 | #endif |
660 | ||
e30ec452 | 661 | uasm_l_vmalloc_done(l, *p); |
242954b5 | 662 | |
3be6022c DD |
663 | /* get pgd offset in bytes */ |
664 | uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3); | |
e30ec452 TS |
665 | |
666 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); | |
667 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
325f8a0a | 668 | #ifndef __PAGETABLE_PMD_FOLDED |
e30ec452 TS |
669 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ |
670 | uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ | |
3be6022c | 671 | uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ |
e30ec452 TS |
672 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); |
673 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ | |
325f8a0a | 674 | #endif |
1da177e4 LT |
675 | } |
676 | ||
1ec56329 | 677 | enum vmalloc64_mode {not_refill, refill}; |
1da177e4 LT |
678 | /* |
679 | * BVADDR is the faulting address, PTR is scratch. | |
680 | * PTR will hold the pgd for vmalloc. | |
681 | */ | |
234fcd14 | 682 | static void __cpuinit |
e30ec452 | 683 | build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
1ec56329 DD |
684 | unsigned int bvaddr, unsigned int ptr, |
685 | enum vmalloc64_mode mode) | |
1da177e4 LT |
686 | { |
687 | long swpd = (long)swapper_pg_dir; | |
1ec56329 DD |
688 | int single_insn_swpd; |
689 | int did_vmalloc_branch = 0; | |
690 | ||
691 | single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd); | |
1da177e4 | 692 | |
e30ec452 | 693 | uasm_l_vmalloc(l, *p); |
1da177e4 | 694 | |
1ec56329 DD |
695 | if (mode == refill && check_for_high_segbits) { |
696 | if (single_insn_swpd) { | |
697 | uasm_il_bltz(p, r, bvaddr, label_vmalloc_done); | |
698 | uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); | |
699 | did_vmalloc_branch = 1; | |
700 | /* fall through */ | |
701 | } else { | |
702 | uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault); | |
703 | } | |
704 | } | |
705 | if (!did_vmalloc_branch) { | |
706 | if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) { | |
707 | uasm_il_b(p, r, label_vmalloc_done); | |
708 | uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); | |
709 | } else { | |
710 | UASM_i_LA_mostly(p, ptr, swpd); | |
711 | uasm_il_b(p, r, label_vmalloc_done); | |
712 | if (uasm_in_compat_space_p(swpd)) | |
713 | uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd)); | |
714 | else | |
715 | uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); | |
716 | } | |
717 | } | |
718 | if (mode == refill && check_for_high_segbits) { | |
719 | uasm_l_large_segbits_fault(l, *p); | |
720 | /* | |
721 | * We get here if we are an xsseg address, or if we are | |
722 | * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary. | |
723 | * | |
724 | * Ignoring xsseg (assume disabled so would generate | |
725 | * (address errors?), the only remaining possibility | |
726 | * is the upper xuseg addresses. On processors with | |
727 | * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these | |
728 | * addresses would have taken an address error. We try | |
729 | * to mimic that here by taking a load/istream page | |
730 | * fault. | |
731 | */ | |
732 | UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0); | |
733 | uasm_i_jr(p, ptr); | |
734 | uasm_i_nop(p); | |
1da177e4 LT |
735 | } |
736 | } | |
737 | ||
875d43e7 | 738 | #else /* !CONFIG_64BIT */ |
1da177e4 LT |
739 | |
740 | /* | |
741 | * TMP and PTR are scratch. | |
742 | * TMP will be clobbered, PTR will hold the pgd entry. | |
743 | */ | |
234fcd14 | 744 | static void __cpuinit __maybe_unused |
1da177e4 LT |
745 | build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) |
746 | { | |
747 | long pgdc = (long)pgd_current; | |
748 | ||
749 | /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ | |
750 | #ifdef CONFIG_SMP | |
41c594ab RB |
751 | #ifdef CONFIG_MIPS_MT_SMTC |
752 | /* | |
753 | * SMTC uses TCBind value as "CPU" index | |
754 | */ | |
e30ec452 TS |
755 | uasm_i_mfc0(p, ptr, C0_TCBIND); |
756 | UASM_i_LA_mostly(p, tmp, pgdc); | |
757 | uasm_i_srl(p, ptr, ptr, 19); | |
41c594ab RB |
758 | #else |
759 | /* | |
760 | * smp_processor_id() << 3 is stored in CONTEXT. | |
761 | */ | |
e30ec452 TS |
762 | uasm_i_mfc0(p, ptr, C0_CONTEXT); |
763 | UASM_i_LA_mostly(p, tmp, pgdc); | |
764 | uasm_i_srl(p, ptr, ptr, 23); | |
41c594ab | 765 | #endif |
e30ec452 | 766 | uasm_i_addu(p, ptr, tmp, ptr); |
1da177e4 | 767 | #else |
e30ec452 | 768 | UASM_i_LA_mostly(p, ptr, pgdc); |
1da177e4 | 769 | #endif |
e30ec452 TS |
770 | uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ |
771 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); | |
772 | uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ | |
773 | uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); | |
774 | uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
1da177e4 LT |
775 | } |
776 | ||
875d43e7 | 777 | #endif /* !CONFIG_64BIT */ |
1da177e4 | 778 | |
234fcd14 | 779 | static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx) |
1da177e4 | 780 | { |
242954b5 | 781 | unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; |
1da177e4 LT |
782 | unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); |
783 | ||
10cc3529 | 784 | switch (current_cpu_type()) { |
1da177e4 LT |
785 | case CPU_VR41XX: |
786 | case CPU_VR4111: | |
787 | case CPU_VR4121: | |
788 | case CPU_VR4122: | |
789 | case CPU_VR4131: | |
790 | case CPU_VR4181: | |
791 | case CPU_VR4181A: | |
792 | case CPU_VR4133: | |
793 | shift += 2; | |
794 | break; | |
795 | ||
796 | default: | |
797 | break; | |
798 | } | |
799 | ||
800 | if (shift) | |
e30ec452 TS |
801 | UASM_i_SRL(p, ctx, ctx, shift); |
802 | uasm_i_andi(p, ctx, ctx, mask); | |
1da177e4 LT |
803 | } |
804 | ||
234fcd14 | 805 | static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) |
1da177e4 LT |
806 | { |
807 | /* | |
808 | * Bug workaround for the Nevada. It seems as if under certain | |
809 | * circumstances the move from cp0_context might produce a | |
810 | * bogus result when the mfc0 instruction and its consumer are | |
811 | * in a different cacheline or a load instruction, probably any | |
812 | * memory reference, is between them. | |
813 | */ | |
10cc3529 | 814 | switch (current_cpu_type()) { |
1da177e4 | 815 | case CPU_NEVADA: |
e30ec452 | 816 | UASM_i_LW(p, ptr, 0, ptr); |
1da177e4 LT |
817 | GET_CONTEXT(p, tmp); /* get context reg */ |
818 | break; | |
819 | ||
820 | default: | |
821 | GET_CONTEXT(p, tmp); /* get context reg */ | |
e30ec452 | 822 | UASM_i_LW(p, ptr, 0, ptr); |
1da177e4 LT |
823 | break; |
824 | } | |
825 | ||
826 | build_adjust_context(p, tmp); | |
e30ec452 | 827 | UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ |
1da177e4 LT |
828 | } |
829 | ||
234fcd14 | 830 | static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, |
1da177e4 LT |
831 | unsigned int ptep) |
832 | { | |
833 | /* | |
834 | * 64bit address support (36bit on a 32bit CPU) in a 32bit | |
835 | * Kernel is a special case. Only a few CPUs use it. | |
836 | */ | |
837 | #ifdef CONFIG_64BIT_PHYS_ADDR | |
838 | if (cpu_has_64bits) { | |
e30ec452 TS |
839 | uasm_i_ld(p, tmp, 0, ptep); /* get even pte */ |
840 | uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ | |
6dd9344c DD |
841 | if (kernel_uses_smartmips_rixi) { |
842 | UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC)); | |
843 | UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC)); | |
844 | UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); | |
845 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ | |
846 | UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); | |
847 | } else { | |
3be6022c | 848 | uasm_i_dsrl_safe(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */ |
6dd9344c | 849 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ |
3be6022c | 850 | uasm_i_dsrl_safe(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */ |
6dd9344c | 851 | } |
9b8c3891 | 852 | UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ |
1da177e4 LT |
853 | } else { |
854 | int pte_off_even = sizeof(pte_t) / 2; | |
855 | int pte_off_odd = pte_off_even + sizeof(pte_t); | |
856 | ||
857 | /* The pte entries are pre-shifted */ | |
e30ec452 | 858 | uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */ |
9b8c3891 | 859 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ |
e30ec452 | 860 | uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */ |
9b8c3891 | 861 | UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ |
1da177e4 LT |
862 | } |
863 | #else | |
e30ec452 TS |
864 | UASM_i_LW(p, tmp, 0, ptep); /* get even pte */ |
865 | UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ | |
1da177e4 LT |
866 | if (r45k_bvahwbug()) |
867 | build_tlb_probe_entry(p); | |
6dd9344c DD |
868 | if (kernel_uses_smartmips_rixi) { |
869 | UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC)); | |
870 | UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC)); | |
871 | UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); | |
872 | if (r4k_250MHZhwbug()) | |
873 | UASM_i_MTC0(p, 0, C0_ENTRYLO0); | |
874 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ | |
875 | UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); | |
876 | } else { | |
877 | UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */ | |
878 | if (r4k_250MHZhwbug()) | |
879 | UASM_i_MTC0(p, 0, C0_ENTRYLO0); | |
880 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ | |
881 | UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */ | |
882 | if (r45k_bvahwbug()) | |
883 | uasm_i_mfc0(p, tmp, C0_INDEX); | |
884 | } | |
1da177e4 | 885 | if (r4k_250MHZhwbug()) |
9b8c3891 DD |
886 | UASM_i_MTC0(p, 0, C0_ENTRYLO1); |
887 | UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ | |
1da177e4 LT |
888 | #endif |
889 | } | |
890 | ||
e6f72d3a DD |
891 | /* |
892 | * For a 64-bit kernel, we are using the 64-bit XTLB refill exception | |
893 | * because EXL == 0. If we wrap, we can also use the 32 instruction | |
894 | * slots before the XTLB refill exception handler which belong to the | |
895 | * unused TLB refill exception. | |
896 | */ | |
897 | #define MIPS64_REFILL_INSNS 32 | |
898 | ||
234fcd14 | 899 | static void __cpuinit build_r4000_tlb_refill_handler(void) |
1da177e4 LT |
900 | { |
901 | u32 *p = tlb_handler; | |
e30ec452 TS |
902 | struct uasm_label *l = labels; |
903 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
904 | u32 *f; |
905 | unsigned int final_len; | |
906 | ||
907 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
908 | memset(labels, 0, sizeof(labels)); | |
909 | memset(relocs, 0, sizeof(relocs)); | |
910 | memset(final_handler, 0, sizeof(final_handler)); | |
911 | ||
912 | /* | |
913 | * create the plain linear handler | |
914 | */ | |
915 | if (bcm1250_m3_war()) { | |
3d45285d RB |
916 | unsigned int segbits = 44; |
917 | ||
918 | uasm_i_dmfc0(&p, K0, C0_BADVADDR); | |
919 | uasm_i_dmfc0(&p, K1, C0_ENTRYHI); | |
e30ec452 | 920 | uasm_i_xor(&p, K0, K0, K1); |
3be6022c DD |
921 | uasm_i_dsrl_safe(&p, K1, K0, 62); |
922 | uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); | |
923 | uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); | |
3d45285d | 924 | uasm_i_or(&p, K0, K0, K1); |
e30ec452 TS |
925 | uasm_il_bnez(&p, &r, K0, label_leave); |
926 | /* No need for uasm_i_nop */ | |
1da177e4 LT |
927 | } |
928 | ||
875d43e7 | 929 | #ifdef CONFIG_64BIT |
1da177e4 LT |
930 | build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ |
931 | #else | |
932 | build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ | |
933 | #endif | |
934 | ||
fd062c84 DD |
935 | #ifdef CONFIG_HUGETLB_PAGE |
936 | build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update); | |
937 | #endif | |
938 | ||
1da177e4 LT |
939 | build_get_ptep(&p, K0, K1); |
940 | build_update_entries(&p, K0, K1); | |
941 | build_tlb_write_entry(&p, &l, &r, tlb_random); | |
e30ec452 TS |
942 | uasm_l_leave(&l, p); |
943 | uasm_i_eret(&p); /* return from trap */ | |
1da177e4 | 944 | |
fd062c84 DD |
945 | #ifdef CONFIG_HUGETLB_PAGE |
946 | uasm_l_tlb_huge_update(&l, p); | |
947 | UASM_i_LW(&p, K0, 0, K1); | |
948 | build_huge_update_entries(&p, K0, K1); | |
949 | build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random); | |
950 | #endif | |
951 | ||
875d43e7 | 952 | #ifdef CONFIG_64BIT |
1ec56329 | 953 | build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, refill); |
1da177e4 LT |
954 | #endif |
955 | ||
956 | /* | |
957 | * Overflow check: For the 64bit handler, we need at least one | |
958 | * free instruction slot for the wrap-around branch. In worst | |
959 | * case, if the intended insertion point is a delay slot, we | |
4b3f686d | 960 | * need three, with the second nop'ed and the third being |
1da177e4 LT |
961 | * unused. |
962 | */ | |
2a21c730 FZ |
963 | /* Loongson2 ebase is different than r4k, we have more space */ |
964 | #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) | |
1da177e4 LT |
965 | if ((p - tlb_handler) > 64) |
966 | panic("TLB refill handler space exceeded"); | |
967 | #else | |
e6f72d3a DD |
968 | if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1) |
969 | || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3) | |
970 | && uasm_insn_has_bdelay(relocs, | |
971 | tlb_handler + MIPS64_REFILL_INSNS - 3))) | |
1da177e4 LT |
972 | panic("TLB refill handler space exceeded"); |
973 | #endif | |
974 | ||
975 | /* | |
976 | * Now fold the handler in the TLB refill handler space. | |
977 | */ | |
2a21c730 | 978 | #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) |
1da177e4 LT |
979 | f = final_handler; |
980 | /* Simplest case, just copy the handler. */ | |
e30ec452 | 981 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); |
1da177e4 | 982 | final_len = p - tlb_handler; |
875d43e7 | 983 | #else /* CONFIG_64BIT */ |
e6f72d3a DD |
984 | f = final_handler + MIPS64_REFILL_INSNS; |
985 | if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) { | |
1da177e4 | 986 | /* Just copy the handler. */ |
e30ec452 | 987 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); |
1da177e4 LT |
988 | final_len = p - tlb_handler; |
989 | } else { | |
fd062c84 DD |
990 | #if defined(CONFIG_HUGETLB_PAGE) |
991 | const enum label_id ls = label_tlb_huge_update; | |
95affdda DD |
992 | #else |
993 | const enum label_id ls = label_vmalloc; | |
994 | #endif | |
995 | u32 *split; | |
996 | int ov = 0; | |
997 | int i; | |
998 | ||
999 | for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++) | |
1000 | ; | |
1001 | BUG_ON(i == ARRAY_SIZE(labels)); | |
1002 | split = labels[i].addr; | |
1da177e4 LT |
1003 | |
1004 | /* | |
95affdda | 1005 | * See if we have overflown one way or the other. |
1da177e4 | 1006 | */ |
95affdda DD |
1007 | if (split > tlb_handler + MIPS64_REFILL_INSNS || |
1008 | split < p - MIPS64_REFILL_INSNS) | |
1009 | ov = 1; | |
1010 | ||
1011 | if (ov) { | |
1012 | /* | |
1013 | * Split two instructions before the end. One | |
1014 | * for the branch and one for the instruction | |
1015 | * in the delay slot. | |
1016 | */ | |
1017 | split = tlb_handler + MIPS64_REFILL_INSNS - 2; | |
1018 | ||
1019 | /* | |
1020 | * If the branch would fall in a delay slot, | |
1021 | * we must back up an additional instruction | |
1022 | * so that it is no longer in a delay slot. | |
1023 | */ | |
1024 | if (uasm_insn_has_bdelay(relocs, split - 1)) | |
1025 | split--; | |
1026 | } | |
1da177e4 | 1027 | /* Copy first part of the handler. */ |
e30ec452 | 1028 | uasm_copy_handler(relocs, labels, tlb_handler, split, f); |
1da177e4 LT |
1029 | f += split - tlb_handler; |
1030 | ||
95affdda DD |
1031 | if (ov) { |
1032 | /* Insert branch. */ | |
1033 | uasm_l_split(&l, final_handler); | |
1034 | uasm_il_b(&f, &r, label_split); | |
1035 | if (uasm_insn_has_bdelay(relocs, split)) | |
1036 | uasm_i_nop(&f); | |
1037 | else { | |
1038 | uasm_copy_handler(relocs, labels, | |
1039 | split, split + 1, f); | |
1040 | uasm_move_labels(labels, f, f + 1, -1); | |
1041 | f++; | |
1042 | split++; | |
1043 | } | |
1da177e4 LT |
1044 | } |
1045 | ||
1046 | /* Copy the rest of the handler. */ | |
e30ec452 | 1047 | uasm_copy_handler(relocs, labels, split, p, final_handler); |
e6f72d3a DD |
1048 | final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) + |
1049 | (p - split); | |
1da177e4 | 1050 | } |
875d43e7 | 1051 | #endif /* CONFIG_64BIT */ |
1da177e4 | 1052 | |
e30ec452 TS |
1053 | uasm_resolve_relocs(relocs, labels); |
1054 | pr_debug("Wrote TLB refill handler (%u instructions).\n", | |
1055 | final_len); | |
1da177e4 | 1056 | |
91b05e67 | 1057 | memcpy((void *)ebase, final_handler, 0x100); |
92b1e6a6 FBH |
1058 | |
1059 | dump_handler((u32 *)ebase, 64); | |
1da177e4 LT |
1060 | } |
1061 | ||
1da177e4 LT |
1062 | /* |
1063 | * 128 instructions for the fastpath handler is generous and should | |
1064 | * never be exceeded. | |
1065 | */ | |
1066 | #define FASTPATH_SIZE 128 | |
1067 | ||
cbdbe07f FBH |
1068 | u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned; |
1069 | u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned; | |
1070 | u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned; | |
3d8bfdd0 DD |
1071 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
1072 | u32 tlbmiss_handler_setup_pgd[16] __cacheline_aligned; | |
1073 | ||
1074 | static void __cpuinit build_r4000_setup_pgd(void) | |
1075 | { | |
1076 | const int a0 = 4; | |
1077 | const int a1 = 5; | |
1078 | u32 *p = tlbmiss_handler_setup_pgd; | |
1079 | struct uasm_label *l = labels; | |
1080 | struct uasm_reloc *r = relocs; | |
1081 | ||
1082 | memset(tlbmiss_handler_setup_pgd, 0, sizeof(tlbmiss_handler_setup_pgd)); | |
1083 | memset(labels, 0, sizeof(labels)); | |
1084 | memset(relocs, 0, sizeof(relocs)); | |
1085 | ||
1086 | pgd_reg = allocate_kscratch(); | |
1087 | ||
1088 | if (pgd_reg == -1) { | |
1089 | /* PGD << 11 in c0_Context */ | |
1090 | /* | |
1091 | * If it is a ckseg0 address, convert to a physical | |
1092 | * address. Shifting right by 29 and adding 4 will | |
1093 | * result in zero for these addresses. | |
1094 | * | |
1095 | */ | |
1096 | UASM_i_SRA(&p, a1, a0, 29); | |
1097 | UASM_i_ADDIU(&p, a1, a1, 4); | |
1098 | uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1); | |
1099 | uasm_i_nop(&p); | |
1100 | uasm_i_dinsm(&p, a0, 0, 29, 64 - 29); | |
1101 | uasm_l_tlbl_goaround1(&l, p); | |
1102 | UASM_i_SLL(&p, a0, a0, 11); | |
1103 | uasm_i_jr(&p, 31); | |
1104 | UASM_i_MTC0(&p, a0, C0_CONTEXT); | |
1105 | } else { | |
1106 | /* PGD in c0_KScratch */ | |
1107 | uasm_i_jr(&p, 31); | |
1108 | UASM_i_MTC0(&p, a0, 31, pgd_reg); | |
1109 | } | |
1110 | if (p - tlbmiss_handler_setup_pgd > ARRAY_SIZE(tlbmiss_handler_setup_pgd)) | |
1111 | panic("tlbmiss_handler_setup_pgd space exceeded"); | |
1112 | uasm_resolve_relocs(relocs, labels); | |
1113 | pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n", | |
1114 | (unsigned int)(p - tlbmiss_handler_setup_pgd)); | |
1115 | ||
1116 | dump_handler(tlbmiss_handler_setup_pgd, | |
1117 | ARRAY_SIZE(tlbmiss_handler_setup_pgd)); | |
1118 | } | |
1119 | #endif | |
1da177e4 | 1120 | |
234fcd14 | 1121 | static void __cpuinit |
bd1437e4 | 1122 | iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) |
1da177e4 LT |
1123 | { |
1124 | #ifdef CONFIG_SMP | |
1125 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1126 | if (cpu_has_64bits) | |
e30ec452 | 1127 | uasm_i_lld(p, pte, 0, ptr); |
1da177e4 LT |
1128 | else |
1129 | # endif | |
e30ec452 | 1130 | UASM_i_LL(p, pte, 0, ptr); |
1da177e4 LT |
1131 | #else |
1132 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1133 | if (cpu_has_64bits) | |
e30ec452 | 1134 | uasm_i_ld(p, pte, 0, ptr); |
1da177e4 LT |
1135 | else |
1136 | # endif | |
e30ec452 | 1137 | UASM_i_LW(p, pte, 0, ptr); |
1da177e4 LT |
1138 | #endif |
1139 | } | |
1140 | ||
234fcd14 | 1141 | static void __cpuinit |
e30ec452 | 1142 | iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, |
63b2d2f4 | 1143 | unsigned int mode) |
1da177e4 | 1144 | { |
63b2d2f4 TS |
1145 | #ifdef CONFIG_64BIT_PHYS_ADDR |
1146 | unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); | |
1147 | #endif | |
1148 | ||
e30ec452 | 1149 | uasm_i_ori(p, pte, pte, mode); |
1da177e4 LT |
1150 | #ifdef CONFIG_SMP |
1151 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1152 | if (cpu_has_64bits) | |
e30ec452 | 1153 | uasm_i_scd(p, pte, 0, ptr); |
1da177e4 LT |
1154 | else |
1155 | # endif | |
e30ec452 | 1156 | UASM_i_SC(p, pte, 0, ptr); |
1da177e4 LT |
1157 | |
1158 | if (r10000_llsc_war()) | |
e30ec452 | 1159 | uasm_il_beqzl(p, r, pte, label_smp_pgtable_change); |
1da177e4 | 1160 | else |
e30ec452 | 1161 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); |
1da177e4 LT |
1162 | |
1163 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1164 | if (!cpu_has_64bits) { | |
e30ec452 TS |
1165 | /* no uasm_i_nop needed */ |
1166 | uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr); | |
1167 | uasm_i_ori(p, pte, pte, hwmode); | |
1168 | uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr); | |
1169 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); | |
1170 | /* no uasm_i_nop needed */ | |
1171 | uasm_i_lw(p, pte, 0, ptr); | |
1da177e4 | 1172 | } else |
e30ec452 | 1173 | uasm_i_nop(p); |
1da177e4 | 1174 | # else |
e30ec452 | 1175 | uasm_i_nop(p); |
1da177e4 LT |
1176 | # endif |
1177 | #else | |
1178 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1179 | if (cpu_has_64bits) | |
e30ec452 | 1180 | uasm_i_sd(p, pte, 0, ptr); |
1da177e4 LT |
1181 | else |
1182 | # endif | |
e30ec452 | 1183 | UASM_i_SW(p, pte, 0, ptr); |
1da177e4 LT |
1184 | |
1185 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1186 | if (!cpu_has_64bits) { | |
e30ec452 TS |
1187 | uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr); |
1188 | uasm_i_ori(p, pte, pte, hwmode); | |
1189 | uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr); | |
1190 | uasm_i_lw(p, pte, 0, ptr); | |
1da177e4 LT |
1191 | } |
1192 | # endif | |
1193 | #endif | |
1194 | } | |
1195 | ||
1196 | /* | |
1197 | * Check if PTE is present, if not then jump to LABEL. PTR points to | |
1198 | * the page table where this PTE is located, PTE will be re-loaded | |
1199 | * with it's original value. | |
1200 | */ | |
234fcd14 | 1201 | static void __cpuinit |
bd1437e4 | 1202 | build_pte_present(u32 **p, struct uasm_reloc **r, |
1da177e4 LT |
1203 | unsigned int pte, unsigned int ptr, enum label_id lid) |
1204 | { | |
6dd9344c | 1205 | if (kernel_uses_smartmips_rixi) { |
cc33ae43 DD |
1206 | if (use_bbit_insns()) { |
1207 | uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); | |
1208 | uasm_i_nop(p); | |
1209 | } else { | |
1210 | uasm_i_andi(p, pte, pte, _PAGE_PRESENT); | |
1211 | uasm_il_beqz(p, r, pte, lid); | |
1212 | iPTE_LW(p, pte, ptr); | |
1213 | } | |
6dd9344c DD |
1214 | } else { |
1215 | uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); | |
1216 | uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); | |
1217 | uasm_il_bnez(p, r, pte, lid); | |
cc33ae43 | 1218 | iPTE_LW(p, pte, ptr); |
6dd9344c | 1219 | } |
1da177e4 LT |
1220 | } |
1221 | ||
1222 | /* Make PTE valid, store result in PTR. */ | |
234fcd14 | 1223 | static void __cpuinit |
e30ec452 | 1224 | build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte, |
1da177e4 LT |
1225 | unsigned int ptr) |
1226 | { | |
63b2d2f4 TS |
1227 | unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; |
1228 | ||
1229 | iPTE_SW(p, r, pte, ptr, mode); | |
1da177e4 LT |
1230 | } |
1231 | ||
1232 | /* | |
1233 | * Check if PTE can be written to, if not branch to LABEL. Regardless | |
1234 | * restore PTE with value from PTR when done. | |
1235 | */ | |
234fcd14 | 1236 | static void __cpuinit |
bd1437e4 | 1237 | build_pte_writable(u32 **p, struct uasm_reloc **r, |
1da177e4 LT |
1238 | unsigned int pte, unsigned int ptr, enum label_id lid) |
1239 | { | |
cc33ae43 DD |
1240 | if (use_bbit_insns()) { |
1241 | uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); | |
1242 | uasm_i_nop(p); | |
1243 | uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid); | |
1244 | uasm_i_nop(p); | |
1245 | } else { | |
1246 | uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); | |
1247 | uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); | |
1248 | uasm_il_bnez(p, r, pte, lid); | |
1249 | iPTE_LW(p, pte, ptr); | |
1250 | } | |
1da177e4 LT |
1251 | } |
1252 | ||
1253 | /* Make PTE writable, update software status bits as well, then store | |
1254 | * at PTR. | |
1255 | */ | |
234fcd14 | 1256 | static void __cpuinit |
e30ec452 | 1257 | build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte, |
1da177e4 LT |
1258 | unsigned int ptr) |
1259 | { | |
63b2d2f4 TS |
1260 | unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID |
1261 | | _PAGE_DIRTY); | |
1262 | ||
1263 | iPTE_SW(p, r, pte, ptr, mode); | |
1da177e4 LT |
1264 | } |
1265 | ||
1266 | /* | |
1267 | * Check if PTE can be modified, if not branch to LABEL. Regardless | |
1268 | * restore PTE with value from PTR when done. | |
1269 | */ | |
234fcd14 | 1270 | static void __cpuinit |
bd1437e4 | 1271 | build_pte_modifiable(u32 **p, struct uasm_reloc **r, |
1da177e4 LT |
1272 | unsigned int pte, unsigned int ptr, enum label_id lid) |
1273 | { | |
cc33ae43 DD |
1274 | if (use_bbit_insns()) { |
1275 | uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid); | |
1276 | uasm_i_nop(p); | |
1277 | } else { | |
1278 | uasm_i_andi(p, pte, pte, _PAGE_WRITE); | |
1279 | uasm_il_beqz(p, r, pte, lid); | |
1280 | iPTE_LW(p, pte, ptr); | |
1281 | } | |
1da177e4 LT |
1282 | } |
1283 | ||
82622284 | 1284 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
3d8bfdd0 DD |
1285 | |
1286 | ||
1da177e4 LT |
1287 | /* |
1288 | * R3000 style TLB load/store/modify handlers. | |
1289 | */ | |
1290 | ||
fded2e50 MR |
1291 | /* |
1292 | * This places the pte into ENTRYLO0 and writes it with tlbwi. | |
1293 | * Then it returns. | |
1294 | */ | |
234fcd14 | 1295 | static void __cpuinit |
fded2e50 | 1296 | build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) |
1da177e4 | 1297 | { |
e30ec452 TS |
1298 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ |
1299 | uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ | |
1300 | uasm_i_tlbwi(p); | |
1301 | uasm_i_jr(p, tmp); | |
1302 | uasm_i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1303 | } |
1304 | ||
1305 | /* | |
fded2e50 MR |
1306 | * This places the pte into ENTRYLO0 and writes it with tlbwi |
1307 | * or tlbwr as appropriate. This is because the index register | |
1308 | * may have the probe fail bit set as a result of a trap on a | |
1309 | * kseg2 access, i.e. without refill. Then it returns. | |
1da177e4 | 1310 | */ |
234fcd14 | 1311 | static void __cpuinit |
e30ec452 TS |
1312 | build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l, |
1313 | struct uasm_reloc **r, unsigned int pte, | |
1314 | unsigned int tmp) | |
1315 | { | |
1316 | uasm_i_mfc0(p, tmp, C0_INDEX); | |
1317 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ | |
1318 | uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ | |
1319 | uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */ | |
1320 | uasm_i_tlbwi(p); /* cp0 delay */ | |
1321 | uasm_i_jr(p, tmp); | |
1322 | uasm_i_rfe(p); /* branch delay */ | |
1323 | uasm_l_r3000_write_probe_fail(l, *p); | |
1324 | uasm_i_tlbwr(p); /* cp0 delay */ | |
1325 | uasm_i_jr(p, tmp); | |
1326 | uasm_i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1327 | } |
1328 | ||
234fcd14 | 1329 | static void __cpuinit |
1da177e4 LT |
1330 | build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, |
1331 | unsigned int ptr) | |
1332 | { | |
1333 | long pgdc = (long)pgd_current; | |
1334 | ||
e30ec452 TS |
1335 | uasm_i_mfc0(p, pte, C0_BADVADDR); |
1336 | uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */ | |
1337 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1338 | uasm_i_srl(p, pte, pte, 22); /* load delay */ | |
1339 | uasm_i_sll(p, pte, pte, 2); | |
1340 | uasm_i_addu(p, ptr, ptr, pte); | |
1341 | uasm_i_mfc0(p, pte, C0_CONTEXT); | |
1342 | uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */ | |
1343 | uasm_i_andi(p, pte, pte, 0xffc); /* load delay */ | |
1344 | uasm_i_addu(p, ptr, ptr, pte); | |
1345 | uasm_i_lw(p, pte, 0, ptr); | |
1346 | uasm_i_tlbp(p); /* load delay */ | |
1da177e4 LT |
1347 | } |
1348 | ||
234fcd14 | 1349 | static void __cpuinit build_r3000_tlb_load_handler(void) |
1da177e4 LT |
1350 | { |
1351 | u32 *p = handle_tlbl; | |
e30ec452 TS |
1352 | struct uasm_label *l = labels; |
1353 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1354 | |
1355 | memset(handle_tlbl, 0, sizeof(handle_tlbl)); | |
1356 | memset(labels, 0, sizeof(labels)); | |
1357 | memset(relocs, 0, sizeof(relocs)); | |
1358 | ||
1359 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
bd1437e4 | 1360 | build_pte_present(&p, &r, K0, K1, label_nopage_tlbl); |
e30ec452 | 1361 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1362 | build_make_valid(&p, &r, K0, K1); |
fded2e50 | 1363 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 | 1364 | |
e30ec452 TS |
1365 | uasm_l_nopage_tlbl(&l, p); |
1366 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); | |
1367 | uasm_i_nop(&p); | |
1da177e4 LT |
1368 | |
1369 | if ((p - handle_tlbl) > FASTPATH_SIZE) | |
1370 | panic("TLB load handler fastpath space exceeded"); | |
1371 | ||
e30ec452 TS |
1372 | uasm_resolve_relocs(relocs, labels); |
1373 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", | |
1374 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 1375 | |
92b1e6a6 | 1376 | dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl)); |
1da177e4 LT |
1377 | } |
1378 | ||
234fcd14 | 1379 | static void __cpuinit build_r3000_tlb_store_handler(void) |
1da177e4 LT |
1380 | { |
1381 | u32 *p = handle_tlbs; | |
e30ec452 TS |
1382 | struct uasm_label *l = labels; |
1383 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1384 | |
1385 | memset(handle_tlbs, 0, sizeof(handle_tlbs)); | |
1386 | memset(labels, 0, sizeof(labels)); | |
1387 | memset(relocs, 0, sizeof(relocs)); | |
1388 | ||
1389 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
bd1437e4 | 1390 | build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs); |
e30ec452 | 1391 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1392 | build_make_write(&p, &r, K0, K1); |
fded2e50 | 1393 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 | 1394 | |
e30ec452 TS |
1395 | uasm_l_nopage_tlbs(&l, p); |
1396 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1397 | uasm_i_nop(&p); | |
1da177e4 LT |
1398 | |
1399 | if ((p - handle_tlbs) > FASTPATH_SIZE) | |
1400 | panic("TLB store handler fastpath space exceeded"); | |
1401 | ||
e30ec452 TS |
1402 | uasm_resolve_relocs(relocs, labels); |
1403 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", | |
1404 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 1405 | |
92b1e6a6 | 1406 | dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs)); |
1da177e4 LT |
1407 | } |
1408 | ||
234fcd14 | 1409 | static void __cpuinit build_r3000_tlb_modify_handler(void) |
1da177e4 LT |
1410 | { |
1411 | u32 *p = handle_tlbm; | |
e30ec452 TS |
1412 | struct uasm_label *l = labels; |
1413 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1414 | |
1415 | memset(handle_tlbm, 0, sizeof(handle_tlbm)); | |
1416 | memset(labels, 0, sizeof(labels)); | |
1417 | memset(relocs, 0, sizeof(relocs)); | |
1418 | ||
1419 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
bd1437e4 | 1420 | build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm); |
e30ec452 | 1421 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1422 | build_make_write(&p, &r, K0, K1); |
fded2e50 | 1423 | build_r3000_pte_reload_tlbwi(&p, K0, K1); |
1da177e4 | 1424 | |
e30ec452 TS |
1425 | uasm_l_nopage_tlbm(&l, p); |
1426 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1427 | uasm_i_nop(&p); | |
1da177e4 LT |
1428 | |
1429 | if ((p - handle_tlbm) > FASTPATH_SIZE) | |
1430 | panic("TLB modify handler fastpath space exceeded"); | |
1431 | ||
e30ec452 TS |
1432 | uasm_resolve_relocs(relocs, labels); |
1433 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", | |
1434 | (unsigned int)(p - handle_tlbm)); | |
1da177e4 | 1435 | |
92b1e6a6 | 1436 | dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm)); |
1da177e4 | 1437 | } |
82622284 | 1438 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ |
1da177e4 LT |
1439 | |
1440 | /* | |
1441 | * R4000 style TLB load/store/modify handlers. | |
1442 | */ | |
234fcd14 | 1443 | static void __cpuinit |
e30ec452 TS |
1444 | build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l, |
1445 | struct uasm_reloc **r, unsigned int pte, | |
1da177e4 LT |
1446 | unsigned int ptr) |
1447 | { | |
875d43e7 | 1448 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1449 | build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */ |
1450 | #else | |
1451 | build_get_pgde32(p, pte, ptr); /* get pgd in ptr */ | |
1452 | #endif | |
1453 | ||
fd062c84 DD |
1454 | #ifdef CONFIG_HUGETLB_PAGE |
1455 | /* | |
1456 | * For huge tlb entries, pmd doesn't contain an address but | |
1457 | * instead contains the tlb pte. Check the PAGE_HUGE bit and | |
1458 | * see if we need to jump to huge tlb processing. | |
1459 | */ | |
1460 | build_is_huge_pte(p, r, pte, ptr, label_tlb_huge_update); | |
1461 | #endif | |
1462 | ||
e30ec452 TS |
1463 | UASM_i_MFC0(p, pte, C0_BADVADDR); |
1464 | UASM_i_LW(p, ptr, 0, ptr); | |
1465 | UASM_i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); | |
1466 | uasm_i_andi(p, pte, pte, (PTRS_PER_PTE - 1) << PTE_T_LOG2); | |
1467 | UASM_i_ADDU(p, ptr, ptr, pte); | |
1da177e4 LT |
1468 | |
1469 | #ifdef CONFIG_SMP | |
e30ec452 TS |
1470 | uasm_l_smp_pgtable_change(l, *p); |
1471 | #endif | |
bd1437e4 | 1472 | iPTE_LW(p, pte, ptr); /* get even pte */ |
8df5beac MR |
1473 | if (!m4kc_tlbp_war()) |
1474 | build_tlb_probe_entry(p); | |
1da177e4 LT |
1475 | } |
1476 | ||
234fcd14 | 1477 | static void __cpuinit |
e30ec452 TS |
1478 | build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, |
1479 | struct uasm_reloc **r, unsigned int tmp, | |
1da177e4 LT |
1480 | unsigned int ptr) |
1481 | { | |
e30ec452 TS |
1482 | uasm_i_ori(p, ptr, ptr, sizeof(pte_t)); |
1483 | uasm_i_xori(p, ptr, ptr, sizeof(pte_t)); | |
1da177e4 LT |
1484 | build_update_entries(p, tmp, ptr); |
1485 | build_tlb_write_entry(p, l, r, tlb_indexed); | |
e30ec452 TS |
1486 | uasm_l_leave(l, *p); |
1487 | uasm_i_eret(p); /* return from trap */ | |
1da177e4 | 1488 | |
875d43e7 | 1489 | #ifdef CONFIG_64BIT |
1ec56329 | 1490 | build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill); |
1da177e4 LT |
1491 | #endif |
1492 | } | |
1493 | ||
234fcd14 | 1494 | static void __cpuinit build_r4000_tlb_load_handler(void) |
1da177e4 LT |
1495 | { |
1496 | u32 *p = handle_tlbl; | |
e30ec452 TS |
1497 | struct uasm_label *l = labels; |
1498 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1499 | |
1500 | memset(handle_tlbl, 0, sizeof(handle_tlbl)); | |
1501 | memset(labels, 0, sizeof(labels)); | |
1502 | memset(relocs, 0, sizeof(relocs)); | |
1503 | ||
1504 | if (bcm1250_m3_war()) { | |
3d45285d RB |
1505 | unsigned int segbits = 44; |
1506 | ||
1507 | uasm_i_dmfc0(&p, K0, C0_BADVADDR); | |
1508 | uasm_i_dmfc0(&p, K1, C0_ENTRYHI); | |
e30ec452 | 1509 | uasm_i_xor(&p, K0, K0, K1); |
3be6022c DD |
1510 | uasm_i_dsrl_safe(&p, K1, K0, 62); |
1511 | uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); | |
1512 | uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); | |
3d45285d | 1513 | uasm_i_or(&p, K0, K0, K1); |
e30ec452 TS |
1514 | uasm_il_bnez(&p, &r, K0, label_leave); |
1515 | /* No need for uasm_i_nop */ | |
1da177e4 LT |
1516 | } |
1517 | ||
1518 | build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); | |
bd1437e4 | 1519 | build_pte_present(&p, &r, K0, K1, label_nopage_tlbl); |
8df5beac MR |
1520 | if (m4kc_tlbp_war()) |
1521 | build_tlb_probe_entry(&p); | |
6dd9344c DD |
1522 | |
1523 | if (kernel_uses_smartmips_rixi) { | |
1524 | /* | |
1525 | * If the page is not _PAGE_VALID, RI or XI could not | |
1526 | * have triggered it. Skip the expensive test.. | |
1527 | */ | |
cc33ae43 DD |
1528 | if (use_bbit_insns()) { |
1529 | uasm_il_bbit0(&p, &r, K0, ilog2(_PAGE_VALID), | |
1530 | label_tlbl_goaround1); | |
1531 | } else { | |
1532 | uasm_i_andi(&p, K0, K0, _PAGE_VALID); | |
1533 | uasm_il_beqz(&p, &r, K0, label_tlbl_goaround1); | |
1534 | } | |
6dd9344c DD |
1535 | uasm_i_nop(&p); |
1536 | ||
1537 | uasm_i_tlbr(&p); | |
1538 | /* Examine entrylo 0 or 1 based on ptr. */ | |
cc33ae43 DD |
1539 | if (use_bbit_insns()) { |
1540 | uasm_i_bbit0(&p, K1, ilog2(sizeof(pte_t)), 8); | |
1541 | } else { | |
1542 | uasm_i_andi(&p, K0, K1, sizeof(pte_t)); | |
1543 | uasm_i_beqz(&p, K0, 8); | |
1544 | } | |
6dd9344c DD |
1545 | |
1546 | UASM_i_MFC0(&p, K0, C0_ENTRYLO0); /* load it in the delay slot*/ | |
1547 | UASM_i_MFC0(&p, K0, C0_ENTRYLO1); /* load it if ptr is odd */ | |
1548 | /* | |
1549 | * If the entryLo (now in K0) is valid (bit 1), RI or | |
1550 | * XI must have triggered it. | |
1551 | */ | |
cc33ae43 DD |
1552 | if (use_bbit_insns()) { |
1553 | uasm_il_bbit1(&p, &r, K0, 1, label_nopage_tlbl); | |
1554 | /* Reload the PTE value */ | |
1555 | iPTE_LW(&p, K0, K1); | |
1556 | uasm_l_tlbl_goaround1(&l, p); | |
1557 | } else { | |
1558 | uasm_i_andi(&p, K0, K0, 2); | |
1559 | uasm_il_bnez(&p, &r, K0, label_nopage_tlbl); | |
1560 | uasm_l_tlbl_goaround1(&l, p); | |
1561 | /* Reload the PTE value */ | |
1562 | iPTE_LW(&p, K0, K1); | |
1563 | } | |
6dd9344c | 1564 | } |
1da177e4 LT |
1565 | build_make_valid(&p, &r, K0, K1); |
1566 | build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); | |
1567 | ||
fd062c84 DD |
1568 | #ifdef CONFIG_HUGETLB_PAGE |
1569 | /* | |
1570 | * This is the entry point when build_r4000_tlbchange_handler_head | |
1571 | * spots a huge page. | |
1572 | */ | |
1573 | uasm_l_tlb_huge_update(&l, p); | |
1574 | iPTE_LW(&p, K0, K1); | |
1575 | build_pte_present(&p, &r, K0, K1, label_nopage_tlbl); | |
1576 | build_tlb_probe_entry(&p); | |
6dd9344c DD |
1577 | |
1578 | if (kernel_uses_smartmips_rixi) { | |
1579 | /* | |
1580 | * If the page is not _PAGE_VALID, RI or XI could not | |
1581 | * have triggered it. Skip the expensive test.. | |
1582 | */ | |
cc33ae43 DD |
1583 | if (use_bbit_insns()) { |
1584 | uasm_il_bbit0(&p, &r, K0, ilog2(_PAGE_VALID), | |
1585 | label_tlbl_goaround2); | |
1586 | } else { | |
1587 | uasm_i_andi(&p, K0, K0, _PAGE_VALID); | |
1588 | uasm_il_beqz(&p, &r, K0, label_tlbl_goaround2); | |
1589 | } | |
6dd9344c DD |
1590 | uasm_i_nop(&p); |
1591 | ||
1592 | uasm_i_tlbr(&p); | |
1593 | /* Examine entrylo 0 or 1 based on ptr. */ | |
cc33ae43 DD |
1594 | if (use_bbit_insns()) { |
1595 | uasm_i_bbit0(&p, K1, ilog2(sizeof(pte_t)), 8); | |
1596 | } else { | |
1597 | uasm_i_andi(&p, K0, K1, sizeof(pte_t)); | |
1598 | uasm_i_beqz(&p, K0, 8); | |
1599 | } | |
6dd9344c DD |
1600 | UASM_i_MFC0(&p, K0, C0_ENTRYLO0); /* load it in the delay slot*/ |
1601 | UASM_i_MFC0(&p, K0, C0_ENTRYLO1); /* load it if ptr is odd */ | |
1602 | /* | |
1603 | * If the entryLo (now in K0) is valid (bit 1), RI or | |
1604 | * XI must have triggered it. | |
1605 | */ | |
cc33ae43 DD |
1606 | if (use_bbit_insns()) { |
1607 | uasm_il_bbit0(&p, &r, K0, 1, label_tlbl_goaround2); | |
1608 | } else { | |
1609 | uasm_i_andi(&p, K0, K0, 2); | |
1610 | uasm_il_beqz(&p, &r, K0, label_tlbl_goaround2); | |
1611 | } | |
6dd9344c DD |
1612 | /* Reload the PTE value */ |
1613 | iPTE_LW(&p, K0, K1); | |
1614 | ||
1615 | /* | |
1616 | * We clobbered C0_PAGEMASK, restore it. On the other branch | |
1617 | * it is restored in build_huge_tlb_write_entry. | |
1618 | */ | |
1619 | build_restore_pagemask(&p, &r, K0, label_nopage_tlbl); | |
1620 | ||
1621 | uasm_l_tlbl_goaround2(&l, p); | |
1622 | } | |
fd062c84 DD |
1623 | uasm_i_ori(&p, K0, K0, (_PAGE_ACCESSED | _PAGE_VALID)); |
1624 | build_huge_handler_tail(&p, &r, &l, K0, K1); | |
1625 | #endif | |
1626 | ||
e30ec452 TS |
1627 | uasm_l_nopage_tlbl(&l, p); |
1628 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); | |
1629 | uasm_i_nop(&p); | |
1da177e4 LT |
1630 | |
1631 | if ((p - handle_tlbl) > FASTPATH_SIZE) | |
1632 | panic("TLB load handler fastpath space exceeded"); | |
1633 | ||
e30ec452 TS |
1634 | uasm_resolve_relocs(relocs, labels); |
1635 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", | |
1636 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 1637 | |
92b1e6a6 | 1638 | dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl)); |
1da177e4 LT |
1639 | } |
1640 | ||
234fcd14 | 1641 | static void __cpuinit build_r4000_tlb_store_handler(void) |
1da177e4 LT |
1642 | { |
1643 | u32 *p = handle_tlbs; | |
e30ec452 TS |
1644 | struct uasm_label *l = labels; |
1645 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1646 | |
1647 | memset(handle_tlbs, 0, sizeof(handle_tlbs)); | |
1648 | memset(labels, 0, sizeof(labels)); | |
1649 | memset(relocs, 0, sizeof(relocs)); | |
1650 | ||
1651 | build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); | |
bd1437e4 | 1652 | build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs); |
8df5beac MR |
1653 | if (m4kc_tlbp_war()) |
1654 | build_tlb_probe_entry(&p); | |
1da177e4 LT |
1655 | build_make_write(&p, &r, K0, K1); |
1656 | build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); | |
1657 | ||
fd062c84 DD |
1658 | #ifdef CONFIG_HUGETLB_PAGE |
1659 | /* | |
1660 | * This is the entry point when | |
1661 | * build_r4000_tlbchange_handler_head spots a huge page. | |
1662 | */ | |
1663 | uasm_l_tlb_huge_update(&l, p); | |
1664 | iPTE_LW(&p, K0, K1); | |
1665 | build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs); | |
1666 | build_tlb_probe_entry(&p); | |
1667 | uasm_i_ori(&p, K0, K0, | |
1668 | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); | |
1669 | build_huge_handler_tail(&p, &r, &l, K0, K1); | |
1670 | #endif | |
1671 | ||
e30ec452 TS |
1672 | uasm_l_nopage_tlbs(&l, p); |
1673 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1674 | uasm_i_nop(&p); | |
1da177e4 LT |
1675 | |
1676 | if ((p - handle_tlbs) > FASTPATH_SIZE) | |
1677 | panic("TLB store handler fastpath space exceeded"); | |
1678 | ||
e30ec452 TS |
1679 | uasm_resolve_relocs(relocs, labels); |
1680 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", | |
1681 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 1682 | |
92b1e6a6 | 1683 | dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs)); |
1da177e4 LT |
1684 | } |
1685 | ||
234fcd14 | 1686 | static void __cpuinit build_r4000_tlb_modify_handler(void) |
1da177e4 LT |
1687 | { |
1688 | u32 *p = handle_tlbm; | |
e30ec452 TS |
1689 | struct uasm_label *l = labels; |
1690 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1691 | |
1692 | memset(handle_tlbm, 0, sizeof(handle_tlbm)); | |
1693 | memset(labels, 0, sizeof(labels)); | |
1694 | memset(relocs, 0, sizeof(relocs)); | |
1695 | ||
1696 | build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); | |
bd1437e4 | 1697 | build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm); |
8df5beac MR |
1698 | if (m4kc_tlbp_war()) |
1699 | build_tlb_probe_entry(&p); | |
1da177e4 LT |
1700 | /* Present and writable bits set, set accessed and dirty bits. */ |
1701 | build_make_write(&p, &r, K0, K1); | |
1702 | build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); | |
1703 | ||
fd062c84 DD |
1704 | #ifdef CONFIG_HUGETLB_PAGE |
1705 | /* | |
1706 | * This is the entry point when | |
1707 | * build_r4000_tlbchange_handler_head spots a huge page. | |
1708 | */ | |
1709 | uasm_l_tlb_huge_update(&l, p); | |
1710 | iPTE_LW(&p, K0, K1); | |
1711 | build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm); | |
1712 | build_tlb_probe_entry(&p); | |
1713 | uasm_i_ori(&p, K0, K0, | |
1714 | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); | |
1715 | build_huge_handler_tail(&p, &r, &l, K0, K1); | |
1716 | #endif | |
1717 | ||
e30ec452 TS |
1718 | uasm_l_nopage_tlbm(&l, p); |
1719 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1720 | uasm_i_nop(&p); | |
1da177e4 LT |
1721 | |
1722 | if ((p - handle_tlbm) > FASTPATH_SIZE) | |
1723 | panic("TLB modify handler fastpath space exceeded"); | |
1724 | ||
e30ec452 TS |
1725 | uasm_resolve_relocs(relocs, labels); |
1726 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", | |
1727 | (unsigned int)(p - handle_tlbm)); | |
115f2a44 | 1728 | |
92b1e6a6 | 1729 | dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm)); |
1da177e4 LT |
1730 | } |
1731 | ||
234fcd14 | 1732 | void __cpuinit build_tlb_refill_handler(void) |
1da177e4 LT |
1733 | { |
1734 | /* | |
1735 | * The refill handler is generated per-CPU, multi-node systems | |
1736 | * may have local storage for it. The other handlers are only | |
1737 | * needed once. | |
1738 | */ | |
1739 | static int run_once = 0; | |
1740 | ||
1ec56329 DD |
1741 | #ifdef CONFIG_64BIT |
1742 | check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); | |
1743 | #endif | |
1744 | ||
10cc3529 | 1745 | switch (current_cpu_type()) { |
1da177e4 LT |
1746 | case CPU_R2000: |
1747 | case CPU_R3000: | |
1748 | case CPU_R3000A: | |
1749 | case CPU_R3081E: | |
1750 | case CPU_TX3912: | |
1751 | case CPU_TX3922: | |
1752 | case CPU_TX3927: | |
82622284 | 1753 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
1da177e4 LT |
1754 | build_r3000_tlb_refill_handler(); |
1755 | if (!run_once) { | |
1756 | build_r3000_tlb_load_handler(); | |
1757 | build_r3000_tlb_store_handler(); | |
1758 | build_r3000_tlb_modify_handler(); | |
1759 | run_once++; | |
1760 | } | |
82622284 DD |
1761 | #else |
1762 | panic("No R3000 TLB refill handler"); | |
1763 | #endif | |
1da177e4 LT |
1764 | break; |
1765 | ||
1766 | case CPU_R6000: | |
1767 | case CPU_R6000A: | |
1768 | panic("No R6000 TLB refill handler yet"); | |
1769 | break; | |
1770 | ||
1771 | case CPU_R8000: | |
1772 | panic("No R8000 TLB refill handler yet"); | |
1773 | break; | |
1774 | ||
1775 | default: | |
1da177e4 | 1776 | if (!run_once) { |
3d8bfdd0 DD |
1777 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
1778 | build_r4000_setup_pgd(); | |
1779 | #endif | |
1da177e4 LT |
1780 | build_r4000_tlb_load_handler(); |
1781 | build_r4000_tlb_store_handler(); | |
1782 | build_r4000_tlb_modify_handler(); | |
1783 | run_once++; | |
1784 | } | |
3d8bfdd0 | 1785 | build_r4000_tlb_refill_handler(); |
1da177e4 LT |
1786 | } |
1787 | } | |
1d40cfcd | 1788 | |
234fcd14 | 1789 | void __cpuinit flush_tlb_handlers(void) |
1d40cfcd | 1790 | { |
e0cee3ee | 1791 | local_flush_icache_range((unsigned long)handle_tlbl, |
1d40cfcd | 1792 | (unsigned long)handle_tlbl + sizeof(handle_tlbl)); |
e0cee3ee | 1793 | local_flush_icache_range((unsigned long)handle_tlbs, |
1d40cfcd | 1794 | (unsigned long)handle_tlbs + sizeof(handle_tlbs)); |
e0cee3ee | 1795 | local_flush_icache_range((unsigned long)handle_tlbm, |
1d40cfcd | 1796 | (unsigned long)handle_tlbm + sizeof(handle_tlbm)); |
3d8bfdd0 DD |
1797 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
1798 | local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, | |
1799 | (unsigned long)tlbmiss_handler_setup_pgd + sizeof(handle_tlbm)); | |
1800 | #endif | |
1d40cfcd | 1801 | } |