Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Synthesize TLB refill handlers at runtime. | |
7 | * | |
70342287 RB |
8 | * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer |
9 | * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki | |
41c594ab | 10 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) |
fd062c84 | 11 | * Copyright (C) 2008, 2009 Cavium Networks, Inc. |
113c62d9 | 12 | * Copyright (C) 2011 MIPS Technologies, Inc. |
41c594ab RB |
13 | * |
14 | * ... and the days got worse and worse and now you see | |
15 | * I've gone completly out of my mind. | |
16 | * | |
17 | * They're coming to take me a away haha | |
18 | * they're coming to take me a away hoho hihi haha | |
19 | * to the funny farm where code is beautiful all the time ... | |
20 | * | |
21 | * (Condolences to Napoleon XIV) | |
1da177e4 LT |
22 | */ |
23 | ||
95affdda | 24 | #include <linux/bug.h> |
1da177e4 LT |
25 | #include <linux/kernel.h> |
26 | #include <linux/types.h> | |
631330f5 | 27 | #include <linux/smp.h> |
1da177e4 | 28 | #include <linux/string.h> |
3d8bfdd0 | 29 | #include <linux/cache.h> |
1da177e4 | 30 | |
3d8bfdd0 | 31 | #include <asm/cacheflush.h> |
69f24d17 | 32 | #include <asm/cpu-type.h> |
3d8bfdd0 | 33 | #include <asm/pgtable.h> |
1da177e4 | 34 | #include <asm/war.h> |
3482d713 | 35 | #include <asm/uasm.h> |
b81947c6 | 36 | #include <asm/setup.h> |
e30ec452 | 37 | |
1ec56329 DD |
38 | /* |
39 | * TLB load/store/modify handlers. | |
40 | * | |
41 | * Only the fastpath gets synthesized at runtime, the slowpath for | |
42 | * do_page_fault remains normal asm. | |
43 | */ | |
44 | extern void tlb_do_page_fault_0(void); | |
45 | extern void tlb_do_page_fault_1(void); | |
46 | ||
bf28607f DD |
47 | struct work_registers { |
48 | int r1; | |
49 | int r2; | |
50 | int r3; | |
51 | }; | |
52 | ||
53 | struct tlb_reg_save { | |
54 | unsigned long a; | |
55 | unsigned long b; | |
56 | } ____cacheline_aligned_in_smp; | |
57 | ||
58 | static struct tlb_reg_save handler_reg_save[NR_CPUS]; | |
1ec56329 | 59 | |
aeffdbba | 60 | static inline int r45k_bvahwbug(void) |
1da177e4 LT |
61 | { |
62 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
63 | return 0; | |
64 | } | |
65 | ||
aeffdbba | 66 | static inline int r4k_250MHZhwbug(void) |
1da177e4 LT |
67 | { |
68 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
69 | return 0; | |
70 | } | |
71 | ||
aeffdbba | 72 | static inline int __maybe_unused bcm1250_m3_war(void) |
1da177e4 LT |
73 | { |
74 | return BCM1250_M3_WAR; | |
75 | } | |
76 | ||
aeffdbba | 77 | static inline int __maybe_unused r10000_llsc_war(void) |
1da177e4 LT |
78 | { |
79 | return R10000_LLSC_WAR; | |
80 | } | |
81 | ||
cc33ae43 DD |
82 | static int use_bbit_insns(void) |
83 | { | |
84 | switch (current_cpu_type()) { | |
85 | case CPU_CAVIUM_OCTEON: | |
86 | case CPU_CAVIUM_OCTEON_PLUS: | |
87 | case CPU_CAVIUM_OCTEON2: | |
4723b20a | 88 | case CPU_CAVIUM_OCTEON3: |
cc33ae43 DD |
89 | return 1; |
90 | default: | |
91 | return 0; | |
92 | } | |
93 | } | |
94 | ||
2c8c53e2 DD |
95 | static int use_lwx_insns(void) |
96 | { | |
97 | switch (current_cpu_type()) { | |
98 | case CPU_CAVIUM_OCTEON2: | |
4723b20a | 99 | case CPU_CAVIUM_OCTEON3: |
2c8c53e2 DD |
100 | return 1; |
101 | default: | |
102 | return 0; | |
103 | } | |
104 | } | |
105 | #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \ | |
106 | CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 | |
107 | static bool scratchpad_available(void) | |
108 | { | |
109 | return true; | |
110 | } | |
111 | static int scratchpad_offset(int i) | |
112 | { | |
113 | /* | |
114 | * CVMSEG starts at address -32768 and extends for | |
115 | * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines. | |
116 | */ | |
117 | i += 1; /* Kernel use starts at the top and works down. */ | |
118 | return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768; | |
119 | } | |
120 | #else | |
121 | static bool scratchpad_available(void) | |
122 | { | |
123 | return false; | |
124 | } | |
125 | static int scratchpad_offset(int i) | |
126 | { | |
127 | BUG(); | |
e1c87d2a DD |
128 | /* Really unreachable, but evidently some GCC want this. */ |
129 | return 0; | |
2c8c53e2 DD |
130 | } |
131 | #endif | |
8df5beac MR |
132 | /* |
133 | * Found by experiment: At least some revisions of the 4kc throw under | |
134 | * some circumstances a machine check exception, triggered by invalid | |
135 | * values in the index register. Delaying the tlbp instruction until | |
136 | * after the next branch, plus adding an additional nop in front of | |
137 | * tlbwi/tlbwr avoids the invalid index register values. Nobody knows | |
138 | * why; it's not an issue caused by the core RTL. | |
139 | * | |
140 | */ | |
078a55fc | 141 | static int m4kc_tlbp_war(void) |
8df5beac MR |
142 | { |
143 | return (current_cpu_data.processor_id & 0xffff00) == | |
144 | (PRID_COMP_MIPS | PRID_IMP_4KC); | |
145 | } | |
146 | ||
e30ec452 | 147 | /* Handle labels (which must be positive integers). */ |
1da177e4 | 148 | enum label_id { |
e30ec452 | 149 | label_second_part = 1, |
1da177e4 LT |
150 | label_leave, |
151 | label_vmalloc, | |
152 | label_vmalloc_done, | |
02a54177 RB |
153 | label_tlbw_hazard_0, |
154 | label_split = label_tlbw_hazard_0 + 8, | |
6dd9344c DD |
155 | label_tlbl_goaround1, |
156 | label_tlbl_goaround2, | |
1da177e4 LT |
157 | label_nopage_tlbl, |
158 | label_nopage_tlbs, | |
159 | label_nopage_tlbm, | |
160 | label_smp_pgtable_change, | |
161 | label_r3000_write_probe_fail, | |
1ec56329 | 162 | label_large_segbits_fault, |
aa1762f4 | 163 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
164 | label_tlb_huge_update, |
165 | #endif | |
1da177e4 LT |
166 | }; |
167 | ||
e30ec452 TS |
168 | UASM_L_LA(_second_part) |
169 | UASM_L_LA(_leave) | |
e30ec452 TS |
170 | UASM_L_LA(_vmalloc) |
171 | UASM_L_LA(_vmalloc_done) | |
02a54177 | 172 | /* _tlbw_hazard_x is handled differently. */ |
e30ec452 | 173 | UASM_L_LA(_split) |
6dd9344c DD |
174 | UASM_L_LA(_tlbl_goaround1) |
175 | UASM_L_LA(_tlbl_goaround2) | |
e30ec452 TS |
176 | UASM_L_LA(_nopage_tlbl) |
177 | UASM_L_LA(_nopage_tlbs) | |
178 | UASM_L_LA(_nopage_tlbm) | |
179 | UASM_L_LA(_smp_pgtable_change) | |
180 | UASM_L_LA(_r3000_write_probe_fail) | |
1ec56329 | 181 | UASM_L_LA(_large_segbits_fault) |
aa1762f4 | 182 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
183 | UASM_L_LA(_tlb_huge_update) |
184 | #endif | |
656be92f | 185 | |
078a55fc | 186 | static int hazard_instance; |
02a54177 | 187 | |
078a55fc | 188 | static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance) |
02a54177 RB |
189 | { |
190 | switch (instance) { | |
191 | case 0 ... 7: | |
192 | uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance); | |
193 | return; | |
194 | default: | |
195 | BUG(); | |
196 | } | |
197 | } | |
198 | ||
078a55fc | 199 | static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance) |
02a54177 RB |
200 | { |
201 | switch (instance) { | |
202 | case 0 ... 7: | |
203 | uasm_build_label(l, *p, label_tlbw_hazard_0 + instance); | |
204 | break; | |
205 | default: | |
206 | BUG(); | |
207 | } | |
208 | } | |
209 | ||
92b1e6a6 | 210 | /* |
a2c763e0 RB |
211 | * pgtable bits are assigned dynamically depending on processor feature |
212 | * and statically based on kernel configuration. This spits out the actual | |
70342287 | 213 | * values the kernel is using. Required to make sense from disassembled |
a2c763e0 | 214 | * TLB exception handlers. |
92b1e6a6 | 215 | */ |
a2c763e0 RB |
216 | static void output_pgtable_bits_defines(void) |
217 | { | |
218 | #define pr_define(fmt, ...) \ | |
219 | pr_debug("#define " fmt, ##__VA_ARGS__) | |
220 | ||
221 | pr_debug("#include <asm/asm.h>\n"); | |
222 | pr_debug("#include <asm/regdef.h>\n"); | |
223 | pr_debug("\n"); | |
224 | ||
225 | pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT); | |
226 | pr_define("_PAGE_READ_SHIFT %d\n", _PAGE_READ_SHIFT); | |
227 | pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT); | |
228 | pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT); | |
229 | pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT); | |
970d032f | 230 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
a2c763e0 | 231 | pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT); |
970d032f | 232 | pr_define("_PAGE_SPLITTING_SHIFT %d\n", _PAGE_SPLITTING_SHIFT); |
a2c763e0 RB |
233 | #endif |
234 | if (cpu_has_rixi) { | |
235 | #ifdef _PAGE_NO_EXEC_SHIFT | |
236 | pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT); | |
237 | #endif | |
238 | #ifdef _PAGE_NO_READ_SHIFT | |
239 | pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT); | |
240 | #endif | |
241 | } | |
242 | pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT); | |
243 | pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT); | |
244 | pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT); | |
245 | pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT); | |
246 | pr_debug("\n"); | |
247 | } | |
248 | ||
249 | static inline void dump_handler(const char *symbol, const u32 *handler, int count) | |
92b1e6a6 FBH |
250 | { |
251 | int i; | |
252 | ||
a2c763e0 RB |
253 | pr_debug("LEAF(%s)\n", symbol); |
254 | ||
92b1e6a6 FBH |
255 | pr_debug("\t.set push\n"); |
256 | pr_debug("\t.set noreorder\n"); | |
257 | ||
258 | for (i = 0; i < count; i++) | |
a2c763e0 | 259 | pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]); |
92b1e6a6 | 260 | |
a2c763e0 RB |
261 | pr_debug("\t.set\tpop\n"); |
262 | ||
263 | pr_debug("\tEND(%s)\n", symbol); | |
92b1e6a6 FBH |
264 | } |
265 | ||
1da177e4 LT |
266 | /* The only general purpose registers allowed in TLB handlers. */ |
267 | #define K0 26 | |
268 | #define K1 27 | |
269 | ||
270 | /* Some CP0 registers */ | |
41c594ab RB |
271 | #define C0_INDEX 0, 0 |
272 | #define C0_ENTRYLO0 2, 0 | |
273 | #define C0_TCBIND 2, 2 | |
274 | #define C0_ENTRYLO1 3, 0 | |
275 | #define C0_CONTEXT 4, 0 | |
fd062c84 | 276 | #define C0_PAGEMASK 5, 0 |
41c594ab RB |
277 | #define C0_BADVADDR 8, 0 |
278 | #define C0_ENTRYHI 10, 0 | |
279 | #define C0_EPC 14, 0 | |
280 | #define C0_XCONTEXT 20, 0 | |
1da177e4 | 281 | |
875d43e7 | 282 | #ifdef CONFIG_64BIT |
e30ec452 | 283 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT) |
1da177e4 | 284 | #else |
e30ec452 | 285 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT) |
1da177e4 LT |
286 | #endif |
287 | ||
288 | /* The worst case length of the handler is around 18 instructions for | |
289 | * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. | |
290 | * Maximum space available is 32 instructions for R3000 and 64 | |
291 | * instructions for R4000. | |
292 | * | |
293 | * We deliberately chose a buffer size of 128, so we won't scribble | |
294 | * over anything important on overflow before we panic. | |
295 | */ | |
078a55fc | 296 | static u32 tlb_handler[128]; |
1da177e4 LT |
297 | |
298 | /* simply assume worst case size for labels and relocs */ | |
078a55fc PG |
299 | static struct uasm_label labels[128]; |
300 | static struct uasm_reloc relocs[128]; | |
1da177e4 | 301 | |
078a55fc | 302 | static int check_for_high_segbits; |
3d8bfdd0 | 303 | |
078a55fc | 304 | static unsigned int kscratch_used_mask; |
3d8bfdd0 | 305 | |
7777b939 J |
306 | static inline int __maybe_unused c0_kscratch(void) |
307 | { | |
308 | switch (current_cpu_type()) { | |
309 | case CPU_XLP: | |
310 | case CPU_XLR: | |
311 | return 22; | |
312 | default: | |
313 | return 31; | |
314 | } | |
315 | } | |
316 | ||
078a55fc | 317 | static int allocate_kscratch(void) |
3d8bfdd0 DD |
318 | { |
319 | int r; | |
320 | unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask; | |
321 | ||
322 | r = ffs(a); | |
323 | ||
324 | if (r == 0) | |
325 | return -1; | |
326 | ||
327 | r--; /* make it zero based */ | |
328 | ||
329 | kscratch_used_mask |= (1 << r); | |
330 | ||
331 | return r; | |
332 | } | |
333 | ||
078a55fc PG |
334 | static int scratch_reg; |
335 | static int pgd_reg; | |
2c8c53e2 DD |
336 | enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch}; |
337 | ||
078a55fc | 338 | static struct work_registers build_get_work_registers(u32 **p) |
bf28607f DD |
339 | { |
340 | struct work_registers r; | |
341 | ||
0e6ecc1a | 342 | if (scratch_reg >= 0) { |
bf28607f | 343 | /* Save in CPU local C0_KScratch? */ |
7777b939 | 344 | UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg); |
bf28607f DD |
345 | r.r1 = K0; |
346 | r.r2 = K1; | |
347 | r.r3 = 1; | |
348 | return r; | |
349 | } | |
350 | ||
351 | if (num_possible_cpus() > 1) { | |
bf28607f | 352 | /* Get smp_processor_id */ |
c2377a42 J |
353 | UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG); |
354 | UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT); | |
bf28607f DD |
355 | |
356 | /* handler_reg_save index in K0 */ | |
357 | UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save))); | |
358 | ||
359 | UASM_i_LA(p, K1, (long)&handler_reg_save); | |
360 | UASM_i_ADDU(p, K0, K0, K1); | |
361 | } else { | |
362 | UASM_i_LA(p, K0, (long)&handler_reg_save); | |
363 | } | |
364 | /* K0 now points to save area, save $1 and $2 */ | |
365 | UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0); | |
366 | UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0); | |
367 | ||
368 | r.r1 = K1; | |
369 | r.r2 = 1; | |
370 | r.r3 = 2; | |
371 | return r; | |
372 | } | |
373 | ||
078a55fc | 374 | static void build_restore_work_registers(u32 **p) |
bf28607f | 375 | { |
0e6ecc1a | 376 | if (scratch_reg >= 0) { |
7777b939 | 377 | UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); |
bf28607f DD |
378 | return; |
379 | } | |
380 | /* K0 already points to save area, restore $1 and $2 */ | |
381 | UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0); | |
382 | UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0); | |
383 | } | |
384 | ||
2c8c53e2 | 385 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
3d8bfdd0 | 386 | |
82622284 DD |
387 | /* |
388 | * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current, | |
389 | * we cannot do r3000 under these circumstances. | |
3d8bfdd0 DD |
390 | * |
391 | * Declare pgd_current here instead of including mmu_context.h to avoid type | |
392 | * conflicts for tlbmiss_handler_setup_pgd | |
82622284 | 393 | */ |
3d8bfdd0 | 394 | extern unsigned long pgd_current[]; |
82622284 | 395 | |
1da177e4 LT |
396 | /* |
397 | * The R3000 TLB handler is simple. | |
398 | */ | |
078a55fc | 399 | static void build_r3000_tlb_refill_handler(void) |
1da177e4 LT |
400 | { |
401 | long pgdc = (long)pgd_current; | |
402 | u32 *p; | |
403 | ||
404 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
405 | p = tlb_handler; | |
406 | ||
e30ec452 TS |
407 | uasm_i_mfc0(&p, K0, C0_BADVADDR); |
408 | uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */ | |
409 | uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1); | |
410 | uasm_i_srl(&p, K0, K0, 22); /* load delay */ | |
411 | uasm_i_sll(&p, K0, K0, 2); | |
412 | uasm_i_addu(&p, K1, K1, K0); | |
413 | uasm_i_mfc0(&p, K0, C0_CONTEXT); | |
414 | uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */ | |
415 | uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */ | |
416 | uasm_i_addu(&p, K1, K1, K0); | |
417 | uasm_i_lw(&p, K0, 0, K1); | |
418 | uasm_i_nop(&p); /* load delay */ | |
419 | uasm_i_mtc0(&p, K0, C0_ENTRYLO0); | |
420 | uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ | |
421 | uasm_i_tlbwr(&p); /* cp0 delay */ | |
422 | uasm_i_jr(&p, K1); | |
423 | uasm_i_rfe(&p); /* branch delay */ | |
1da177e4 LT |
424 | |
425 | if (p > tlb_handler + 32) | |
426 | panic("TLB refill handler space exceeded"); | |
427 | ||
e30ec452 TS |
428 | pr_debug("Wrote TLB refill handler (%u instructions).\n", |
429 | (unsigned int)(p - tlb_handler)); | |
1da177e4 | 430 | |
91b05e67 | 431 | memcpy((void *)ebase, tlb_handler, 0x80); |
1062080a | 432 | local_flush_icache_range(ebase, ebase + 0x80); |
92b1e6a6 | 433 | |
a2c763e0 | 434 | dump_handler("r3000_tlb_refill", (u32 *)ebase, 32); |
1da177e4 | 435 | } |
82622284 | 436 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ |
1da177e4 LT |
437 | |
438 | /* | |
439 | * The R4000 TLB handler is much more complicated. We have two | |
440 | * consecutive handler areas with 32 instructions space each. | |
441 | * Since they aren't used at the same time, we can overflow in the | |
442 | * other one.To keep things simple, we first assume linear space, | |
443 | * then we relocate it to the final handler layout as needed. | |
444 | */ | |
078a55fc | 445 | static u32 final_handler[64]; |
1da177e4 LT |
446 | |
447 | /* | |
448 | * Hazards | |
449 | * | |
450 | * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: | |
451 | * 2. A timing hazard exists for the TLBP instruction. | |
452 | * | |
70342287 RB |
453 | * stalling_instruction |
454 | * TLBP | |
1da177e4 LT |
455 | * |
456 | * The JTLB is being read for the TLBP throughout the stall generated by the | |
457 | * previous instruction. This is not really correct as the stalling instruction | |
458 | * can modify the address used to access the JTLB. The failure symptom is that | |
459 | * the TLBP instruction will use an address created for the stalling instruction | |
460 | * and not the address held in C0_ENHI and thus report the wrong results. | |
461 | * | |
462 | * The software work-around is to not allow the instruction preceding the TLBP | |
463 | * to stall - make it an NOP or some other instruction guaranteed not to stall. | |
464 | * | |
70342287 | 465 | * Errata 2 will not be fixed. This errata is also on the R5000. |
1da177e4 LT |
466 | * |
467 | * As if we MIPS hackers wouldn't know how to nop pipelines happy ... | |
468 | */ | |
078a55fc | 469 | static void __maybe_unused build_tlb_probe_entry(u32 **p) |
1da177e4 | 470 | { |
10cc3529 | 471 | switch (current_cpu_type()) { |
326e2e1a | 472 | /* Found by experiment: R4600 v2.0/R4700 needs this, too. */ |
f5b4d956 | 473 | case CPU_R4600: |
326e2e1a | 474 | case CPU_R4700: |
1da177e4 | 475 | case CPU_R5000: |
1da177e4 | 476 | case CPU_NEVADA: |
e30ec452 TS |
477 | uasm_i_nop(p); |
478 | uasm_i_tlbp(p); | |
1da177e4 LT |
479 | break; |
480 | ||
481 | default: | |
e30ec452 | 482 | uasm_i_tlbp(p); |
1da177e4 LT |
483 | break; |
484 | } | |
485 | } | |
486 | ||
487 | /* | |
488 | * Write random or indexed TLB entry, and care about the hazards from | |
25985edc | 489 | * the preceding mtc0 and for the following eret. |
1da177e4 LT |
490 | */ |
491 | enum tlb_write_entry { tlb_random, tlb_indexed }; | |
492 | ||
078a55fc PG |
493 | static void build_tlb_write_entry(u32 **p, struct uasm_label **l, |
494 | struct uasm_reloc **r, | |
495 | enum tlb_write_entry wmode) | |
1da177e4 LT |
496 | { |
497 | void(*tlbw)(u32 **) = NULL; | |
498 | ||
499 | switch (wmode) { | |
e30ec452 TS |
500 | case tlb_random: tlbw = uasm_i_tlbwr; break; |
501 | case tlb_indexed: tlbw = uasm_i_tlbwi; break; | |
1da177e4 LT |
502 | } |
503 | ||
161548bf | 504 | if (cpu_has_mips_r2) { |
625c0a21 SH |
505 | /* |
506 | * The architecture spec says an ehb is required here, | |
507 | * but a number of cores do not have the hazard and | |
508 | * using an ehb causes an expensive pipeline stall. | |
509 | */ | |
510 | switch (current_cpu_type()) { | |
511 | case CPU_M14KC: | |
512 | case CPU_74K: | |
442e14a2 | 513 | case CPU_1074K: |
708ac4b8 | 514 | case CPU_PROAPTIV: |
aced4cbd | 515 | case CPU_P5600: |
f36c4720 | 516 | case CPU_M5150: |
4695089f | 517 | case CPU_QEMU_GENERIC: |
625c0a21 SH |
518 | break; |
519 | ||
520 | default: | |
41f0e4d0 | 521 | uasm_i_ehb(p); |
625c0a21 SH |
522 | break; |
523 | } | |
161548bf RB |
524 | tlbw(p); |
525 | return; | |
526 | } | |
527 | ||
10cc3529 | 528 | switch (current_cpu_type()) { |
1da177e4 LT |
529 | case CPU_R4000PC: |
530 | case CPU_R4000SC: | |
531 | case CPU_R4000MC: | |
532 | case CPU_R4400PC: | |
533 | case CPU_R4400SC: | |
534 | case CPU_R4400MC: | |
535 | /* | |
536 | * This branch uses up a mtc0 hazard nop slot and saves | |
537 | * two nops after the tlbw instruction. | |
538 | */ | |
02a54177 | 539 | uasm_bgezl_hazard(p, r, hazard_instance); |
1da177e4 | 540 | tlbw(p); |
02a54177 RB |
541 | uasm_bgezl_label(l, p, hazard_instance); |
542 | hazard_instance++; | |
e30ec452 | 543 | uasm_i_nop(p); |
1da177e4 LT |
544 | break; |
545 | ||
546 | case CPU_R4600: | |
547 | case CPU_R4700: | |
e30ec452 | 548 | uasm_i_nop(p); |
2c93e12c | 549 | tlbw(p); |
e30ec452 | 550 | uasm_i_nop(p); |
2c93e12c MR |
551 | break; |
552 | ||
359187d6 | 553 | case CPU_R5000: |
359187d6 RB |
554 | case CPU_NEVADA: |
555 | uasm_i_nop(p); /* QED specifies 2 nops hazard */ | |
556 | uasm_i_nop(p); /* QED specifies 2 nops hazard */ | |
557 | tlbw(p); | |
558 | break; | |
559 | ||
2c93e12c | 560 | case CPU_R4300: |
1da177e4 LT |
561 | case CPU_5KC: |
562 | case CPU_TX49XX: | |
bdf21b18 | 563 | case CPU_PR4450: |
efa0f81c | 564 | case CPU_XLR: |
e30ec452 | 565 | uasm_i_nop(p); |
1da177e4 LT |
566 | tlbw(p); |
567 | break; | |
568 | ||
569 | case CPU_R10000: | |
570 | case CPU_R12000: | |
44d921b2 | 571 | case CPU_R14000: |
1da177e4 | 572 | case CPU_4KC: |
b1ec4c8e | 573 | case CPU_4KEC: |
113c62d9 | 574 | case CPU_M14KC: |
f8fa4811 | 575 | case CPU_M14KEC: |
1da177e4 | 576 | case CPU_SB1: |
93ce2f52 | 577 | case CPU_SB1A: |
1da177e4 LT |
578 | case CPU_4KSC: |
579 | case CPU_20KC: | |
580 | case CPU_25KF: | |
602977b0 KC |
581 | case CPU_BMIPS32: |
582 | case CPU_BMIPS3300: | |
583 | case CPU_BMIPS4350: | |
584 | case CPU_BMIPS4380: | |
585 | case CPU_BMIPS5000: | |
2a21c730 | 586 | case CPU_LOONGSON2: |
c579d310 | 587 | case CPU_LOONGSON3: |
a644b277 | 588 | case CPU_R5500: |
8df5beac | 589 | if (m4kc_tlbp_war()) |
e30ec452 | 590 | uasm_i_nop(p); |
2f794d09 | 591 | case CPU_ALCHEMY: |
1da177e4 LT |
592 | tlbw(p); |
593 | break; | |
594 | ||
1da177e4 | 595 | case CPU_RM7000: |
e30ec452 TS |
596 | uasm_i_nop(p); |
597 | uasm_i_nop(p); | |
598 | uasm_i_nop(p); | |
599 | uasm_i_nop(p); | |
1da177e4 LT |
600 | tlbw(p); |
601 | break; | |
602 | ||
1da177e4 LT |
603 | case CPU_VR4111: |
604 | case CPU_VR4121: | |
605 | case CPU_VR4122: | |
606 | case CPU_VR4181: | |
607 | case CPU_VR4181A: | |
e30ec452 TS |
608 | uasm_i_nop(p); |
609 | uasm_i_nop(p); | |
1da177e4 | 610 | tlbw(p); |
e30ec452 TS |
611 | uasm_i_nop(p); |
612 | uasm_i_nop(p); | |
1da177e4 LT |
613 | break; |
614 | ||
615 | case CPU_VR4131: | |
616 | case CPU_VR4133: | |
7623debf | 617 | case CPU_R5432: |
e30ec452 TS |
618 | uasm_i_nop(p); |
619 | uasm_i_nop(p); | |
1da177e4 LT |
620 | tlbw(p); |
621 | break; | |
622 | ||
83ccf69d LPC |
623 | case CPU_JZRISC: |
624 | tlbw(p); | |
625 | uasm_i_nop(p); | |
626 | break; | |
627 | ||
1da177e4 LT |
628 | default: |
629 | panic("No TLB refill handler yet (CPU type: %d)", | |
d7b12056 | 630 | current_cpu_type()); |
1da177e4 LT |
631 | break; |
632 | } | |
633 | } | |
634 | ||
078a55fc PG |
635 | static __maybe_unused void build_convert_pte_to_entrylo(u32 **p, |
636 | unsigned int reg) | |
fd062c84 | 637 | { |
05857c64 | 638 | if (cpu_has_rixi) { |
748e787e | 639 | UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL)); |
6dd9344c | 640 | } else { |
34adb28d | 641 | #ifdef CONFIG_PHYS_ADDR_T_64BIT |
3be6022c | 642 | uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL)); |
6dd9344c DD |
643 | #else |
644 | UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL)); | |
645 | #endif | |
646 | } | |
647 | } | |
fd062c84 | 648 | |
aa1762f4 | 649 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 | 650 | |
078a55fc PG |
651 | static void build_restore_pagemask(u32 **p, struct uasm_reloc **r, |
652 | unsigned int tmp, enum label_id lid, | |
653 | int restore_scratch) | |
6dd9344c | 654 | { |
2c8c53e2 DD |
655 | if (restore_scratch) { |
656 | /* Reset default page size */ | |
657 | if (PM_DEFAULT_MASK >> 16) { | |
658 | uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); | |
659 | uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); | |
660 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
661 | uasm_il_b(p, r, lid); | |
662 | } else if (PM_DEFAULT_MASK) { | |
663 | uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); | |
664 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
665 | uasm_il_b(p, r, lid); | |
666 | } else { | |
667 | uasm_i_mtc0(p, 0, C0_PAGEMASK); | |
668 | uasm_il_b(p, r, lid); | |
669 | } | |
0e6ecc1a | 670 | if (scratch_reg >= 0) |
7777b939 | 671 | UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); |
2c8c53e2 DD |
672 | else |
673 | UASM_i_LW(p, 1, scratchpad_offset(0), 0); | |
fd062c84 | 674 | } else { |
2c8c53e2 DD |
675 | /* Reset default page size */ |
676 | if (PM_DEFAULT_MASK >> 16) { | |
677 | uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); | |
678 | uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); | |
679 | uasm_il_b(p, r, lid); | |
680 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
681 | } else if (PM_DEFAULT_MASK) { | |
682 | uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); | |
683 | uasm_il_b(p, r, lid); | |
684 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
685 | } else { | |
686 | uasm_il_b(p, r, lid); | |
687 | uasm_i_mtc0(p, 0, C0_PAGEMASK); | |
688 | } | |
fd062c84 DD |
689 | } |
690 | } | |
691 | ||
078a55fc PG |
692 | static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l, |
693 | struct uasm_reloc **r, | |
694 | unsigned int tmp, | |
695 | enum tlb_write_entry wmode, | |
696 | int restore_scratch) | |
6dd9344c DD |
697 | { |
698 | /* Set huge page tlb entry size */ | |
699 | uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16); | |
700 | uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff); | |
701 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
702 | ||
703 | build_tlb_write_entry(p, l, r, wmode); | |
704 | ||
2c8c53e2 | 705 | build_restore_pagemask(p, r, tmp, label_leave, restore_scratch); |
6dd9344c DD |
706 | } |
707 | ||
fd062c84 DD |
708 | /* |
709 | * Check if Huge PTE is present, if so then jump to LABEL. | |
710 | */ | |
078a55fc | 711 | static void |
fd062c84 | 712 | build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp, |
078a55fc | 713 | unsigned int pmd, int lid) |
fd062c84 DD |
714 | { |
715 | UASM_i_LW(p, tmp, 0, pmd); | |
cc33ae43 DD |
716 | if (use_bbit_insns()) { |
717 | uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid); | |
718 | } else { | |
719 | uasm_i_andi(p, tmp, tmp, _PAGE_HUGE); | |
720 | uasm_il_bnez(p, r, tmp, lid); | |
721 | } | |
fd062c84 DD |
722 | } |
723 | ||
078a55fc PG |
724 | static void build_huge_update_entries(u32 **p, unsigned int pte, |
725 | unsigned int tmp) | |
fd062c84 DD |
726 | { |
727 | int small_sequence; | |
728 | ||
729 | /* | |
730 | * A huge PTE describes an area the size of the | |
731 | * configured huge page size. This is twice the | |
732 | * of the large TLB entry size we intend to use. | |
733 | * A TLB entry half the size of the configured | |
734 | * huge page size is configured into entrylo0 | |
735 | * and entrylo1 to cover the contiguous huge PTE | |
736 | * address space. | |
737 | */ | |
738 | small_sequence = (HPAGE_SIZE >> 7) < 0x10000; | |
739 | ||
70342287 | 740 | /* We can clobber tmp. It isn't used after this.*/ |
fd062c84 DD |
741 | if (!small_sequence) |
742 | uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16)); | |
743 | ||
6dd9344c | 744 | build_convert_pte_to_entrylo(p, pte); |
9b8c3891 | 745 | UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */ |
fd062c84 DD |
746 | /* convert to entrylo1 */ |
747 | if (small_sequence) | |
748 | UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7); | |
749 | else | |
750 | UASM_i_ADDU(p, pte, pte, tmp); | |
751 | ||
9b8c3891 | 752 | UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */ |
fd062c84 DD |
753 | } |
754 | ||
078a55fc PG |
755 | static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r, |
756 | struct uasm_label **l, | |
757 | unsigned int pte, | |
758 | unsigned int ptr) | |
fd062c84 DD |
759 | { |
760 | #ifdef CONFIG_SMP | |
761 | UASM_i_SC(p, pte, 0, ptr); | |
762 | uasm_il_beqz(p, r, pte, label_tlb_huge_update); | |
763 | UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */ | |
764 | #else | |
765 | UASM_i_SW(p, pte, 0, ptr); | |
766 | #endif | |
767 | build_huge_update_entries(p, pte, ptr); | |
2c8c53e2 | 768 | build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0); |
fd062c84 | 769 | } |
aa1762f4 | 770 | #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ |
fd062c84 | 771 | |
875d43e7 | 772 | #ifdef CONFIG_64BIT |
1da177e4 LT |
773 | /* |
774 | * TMP and PTR are scratch. | |
775 | * TMP will be clobbered, PTR will hold the pmd entry. | |
776 | */ | |
078a55fc | 777 | static void |
e30ec452 | 778 | build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
1da177e4 LT |
779 | unsigned int tmp, unsigned int ptr) |
780 | { | |
82622284 | 781 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
1da177e4 | 782 | long pgdc = (long)pgd_current; |
82622284 | 783 | #endif |
1da177e4 LT |
784 | /* |
785 | * The vmalloc handling is not in the hotpath. | |
786 | */ | |
e30ec452 | 787 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); |
1ec56329 DD |
788 | |
789 | if (check_for_high_segbits) { | |
790 | /* | |
791 | * The kernel currently implicitely assumes that the | |
792 | * MIPS SEGBITS parameter for the processor is | |
793 | * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never | |
794 | * allocate virtual addresses outside the maximum | |
795 | * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But | |
796 | * that doesn't prevent user code from accessing the | |
797 | * higher xuseg addresses. Here, we make sure that | |
798 | * everything but the lower xuseg addresses goes down | |
799 | * the module_alloc/vmalloc path. | |
800 | */ | |
801 | uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); | |
802 | uasm_il_bnez(p, r, ptr, label_vmalloc); | |
803 | } else { | |
804 | uasm_il_bltz(p, r, tmp, label_vmalloc); | |
805 | } | |
e30ec452 | 806 | /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ |
1da177e4 | 807 | |
3d8bfdd0 DD |
808 | if (pgd_reg != -1) { |
809 | /* pgd is in pgd_reg */ | |
7777b939 | 810 | UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); |
3d8bfdd0 | 811 | } else { |
f4ae17aa | 812 | #if defined(CONFIG_MIPS_PGD_C0_CONTEXT) |
3d8bfdd0 DD |
813 | /* |
814 | * &pgd << 11 stored in CONTEXT [23..63]. | |
815 | */ | |
816 | UASM_i_MFC0(p, ptr, C0_CONTEXT); | |
817 | ||
818 | /* Clear lower 23 bits of context. */ | |
819 | uasm_i_dins(p, ptr, 0, 0, 23); | |
820 | ||
70342287 | 821 | /* 1 0 1 0 1 << 6 xkphys cached */ |
3d8bfdd0 DD |
822 | uasm_i_ori(p, ptr, ptr, 0x540); |
823 | uasm_i_drotr(p, ptr, ptr, 11); | |
82622284 | 824 | #elif defined(CONFIG_SMP) |
f4ae17aa J |
825 | UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG); |
826 | uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT); | |
827 | UASM_i_LA_mostly(p, tmp, pgdc); | |
828 | uasm_i_daddu(p, ptr, ptr, tmp); | |
829 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); | |
830 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1da177e4 | 831 | #else |
f4ae17aa J |
832 | UASM_i_LA_mostly(p, ptr, pgdc); |
833 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1da177e4 | 834 | #endif |
f4ae17aa | 835 | } |
1da177e4 | 836 | |
e30ec452 | 837 | uasm_l_vmalloc_done(l, *p); |
242954b5 | 838 | |
3be6022c DD |
839 | /* get pgd offset in bytes */ |
840 | uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3); | |
e30ec452 TS |
841 | |
842 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); | |
843 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
325f8a0a | 844 | #ifndef __PAGETABLE_PMD_FOLDED |
e30ec452 TS |
845 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ |
846 | uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ | |
3be6022c | 847 | uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ |
e30ec452 TS |
848 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); |
849 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ | |
325f8a0a | 850 | #endif |
1da177e4 LT |
851 | } |
852 | ||
853 | /* | |
854 | * BVADDR is the faulting address, PTR is scratch. | |
855 | * PTR will hold the pgd for vmalloc. | |
856 | */ | |
078a55fc | 857 | static void |
e30ec452 | 858 | build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
1ec56329 DD |
859 | unsigned int bvaddr, unsigned int ptr, |
860 | enum vmalloc64_mode mode) | |
1da177e4 LT |
861 | { |
862 | long swpd = (long)swapper_pg_dir; | |
1ec56329 DD |
863 | int single_insn_swpd; |
864 | int did_vmalloc_branch = 0; | |
865 | ||
866 | single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd); | |
1da177e4 | 867 | |
e30ec452 | 868 | uasm_l_vmalloc(l, *p); |
1da177e4 | 869 | |
2c8c53e2 | 870 | if (mode != not_refill && check_for_high_segbits) { |
1ec56329 DD |
871 | if (single_insn_swpd) { |
872 | uasm_il_bltz(p, r, bvaddr, label_vmalloc_done); | |
873 | uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); | |
874 | did_vmalloc_branch = 1; | |
875 | /* fall through */ | |
876 | } else { | |
877 | uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault); | |
878 | } | |
879 | } | |
880 | if (!did_vmalloc_branch) { | |
881 | if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) { | |
882 | uasm_il_b(p, r, label_vmalloc_done); | |
883 | uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); | |
884 | } else { | |
885 | UASM_i_LA_mostly(p, ptr, swpd); | |
886 | uasm_il_b(p, r, label_vmalloc_done); | |
887 | if (uasm_in_compat_space_p(swpd)) | |
888 | uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd)); | |
889 | else | |
890 | uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); | |
891 | } | |
892 | } | |
2c8c53e2 | 893 | if (mode != not_refill && check_for_high_segbits) { |
1ec56329 DD |
894 | uasm_l_large_segbits_fault(l, *p); |
895 | /* | |
896 | * We get here if we are an xsseg address, or if we are | |
897 | * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary. | |
898 | * | |
899 | * Ignoring xsseg (assume disabled so would generate | |
900 | * (address errors?), the only remaining possibility | |
901 | * is the upper xuseg addresses. On processors with | |
902 | * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these | |
903 | * addresses would have taken an address error. We try | |
904 | * to mimic that here by taking a load/istream page | |
905 | * fault. | |
906 | */ | |
907 | UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0); | |
908 | uasm_i_jr(p, ptr); | |
2c8c53e2 DD |
909 | |
910 | if (mode == refill_scratch) { | |
0e6ecc1a | 911 | if (scratch_reg >= 0) |
7777b939 | 912 | UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); |
2c8c53e2 DD |
913 | else |
914 | UASM_i_LW(p, 1, scratchpad_offset(0), 0); | |
915 | } else { | |
916 | uasm_i_nop(p); | |
917 | } | |
1da177e4 LT |
918 | } |
919 | } | |
920 | ||
875d43e7 | 921 | #else /* !CONFIG_64BIT */ |
1da177e4 LT |
922 | |
923 | /* | |
924 | * TMP and PTR are scratch. | |
925 | * TMP will be clobbered, PTR will hold the pgd entry. | |
926 | */ | |
078a55fc | 927 | static void __maybe_unused |
1da177e4 LT |
928 | build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) |
929 | { | |
f4ae17aa J |
930 | if (pgd_reg != -1) { |
931 | /* pgd is in pgd_reg */ | |
932 | uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg); | |
933 | uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ | |
934 | } else { | |
935 | long pgdc = (long)pgd_current; | |
1da177e4 | 936 | |
f4ae17aa | 937 | /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ |
1da177e4 | 938 | #ifdef CONFIG_SMP |
f4ae17aa J |
939 | uasm_i_mfc0(p, ptr, SMP_CPUID_REG); |
940 | UASM_i_LA_mostly(p, tmp, pgdc); | |
941 | uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT); | |
942 | uasm_i_addu(p, ptr, tmp, ptr); | |
1da177e4 | 943 | #else |
f4ae17aa | 944 | UASM_i_LA_mostly(p, ptr, pgdc); |
1da177e4 | 945 | #endif |
f4ae17aa J |
946 | uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ |
947 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); | |
948 | } | |
e30ec452 TS |
949 | uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ |
950 | uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); | |
951 | uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
1da177e4 LT |
952 | } |
953 | ||
875d43e7 | 954 | #endif /* !CONFIG_64BIT */ |
1da177e4 | 955 | |
078a55fc | 956 | static void build_adjust_context(u32 **p, unsigned int ctx) |
1da177e4 | 957 | { |
242954b5 | 958 | unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; |
1da177e4 LT |
959 | unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); |
960 | ||
10cc3529 | 961 | switch (current_cpu_type()) { |
1da177e4 LT |
962 | case CPU_VR41XX: |
963 | case CPU_VR4111: | |
964 | case CPU_VR4121: | |
965 | case CPU_VR4122: | |
966 | case CPU_VR4131: | |
967 | case CPU_VR4181: | |
968 | case CPU_VR4181A: | |
969 | case CPU_VR4133: | |
970 | shift += 2; | |
971 | break; | |
972 | ||
973 | default: | |
974 | break; | |
975 | } | |
976 | ||
977 | if (shift) | |
e30ec452 TS |
978 | UASM_i_SRL(p, ctx, ctx, shift); |
979 | uasm_i_andi(p, ctx, ctx, mask); | |
1da177e4 LT |
980 | } |
981 | ||
078a55fc | 982 | static void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) |
1da177e4 LT |
983 | { |
984 | /* | |
985 | * Bug workaround for the Nevada. It seems as if under certain | |
986 | * circumstances the move from cp0_context might produce a | |
987 | * bogus result when the mfc0 instruction and its consumer are | |
988 | * in a different cacheline or a load instruction, probably any | |
989 | * memory reference, is between them. | |
990 | */ | |
10cc3529 | 991 | switch (current_cpu_type()) { |
1da177e4 | 992 | case CPU_NEVADA: |
e30ec452 | 993 | UASM_i_LW(p, ptr, 0, ptr); |
1da177e4 LT |
994 | GET_CONTEXT(p, tmp); /* get context reg */ |
995 | break; | |
996 | ||
997 | default: | |
998 | GET_CONTEXT(p, tmp); /* get context reg */ | |
e30ec452 | 999 | UASM_i_LW(p, ptr, 0, ptr); |
1da177e4 LT |
1000 | break; |
1001 | } | |
1002 | ||
1003 | build_adjust_context(p, tmp); | |
e30ec452 | 1004 | UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ |
1da177e4 LT |
1005 | } |
1006 | ||
078a55fc | 1007 | static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep) |
1da177e4 LT |
1008 | { |
1009 | /* | |
1010 | * 64bit address support (36bit on a 32bit CPU) in a 32bit | |
1011 | * Kernel is a special case. Only a few CPUs use it. | |
1012 | */ | |
34adb28d | 1013 | #ifdef CONFIG_PHYS_ADDR_T_64BIT |
1da177e4 | 1014 | if (cpu_has_64bits) { |
e30ec452 TS |
1015 | uasm_i_ld(p, tmp, 0, ptep); /* get even pte */ |
1016 | uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ | |
05857c64 | 1017 | if (cpu_has_rixi) { |
748e787e | 1018 | UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); |
6dd9344c | 1019 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ |
748e787e | 1020 | UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); |
6dd9344c | 1021 | } else { |
3be6022c | 1022 | uasm_i_dsrl_safe(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */ |
6dd9344c | 1023 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ |
3be6022c | 1024 | uasm_i_dsrl_safe(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */ |
6dd9344c | 1025 | } |
9b8c3891 | 1026 | UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ |
1da177e4 LT |
1027 | } else { |
1028 | int pte_off_even = sizeof(pte_t) / 2; | |
1029 | int pte_off_odd = pte_off_even + sizeof(pte_t); | |
1030 | ||
1031 | /* The pte entries are pre-shifted */ | |
e30ec452 | 1032 | uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */ |
9b8c3891 | 1033 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ |
e30ec452 | 1034 | uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */ |
9b8c3891 | 1035 | UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ |
1da177e4 LT |
1036 | } |
1037 | #else | |
e30ec452 TS |
1038 | UASM_i_LW(p, tmp, 0, ptep); /* get even pte */ |
1039 | UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ | |
1da177e4 LT |
1040 | if (r45k_bvahwbug()) |
1041 | build_tlb_probe_entry(p); | |
05857c64 | 1042 | if (cpu_has_rixi) { |
748e787e | 1043 | UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); |
6dd9344c DD |
1044 | if (r4k_250MHZhwbug()) |
1045 | UASM_i_MTC0(p, 0, C0_ENTRYLO0); | |
1046 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ | |
748e787e | 1047 | UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); |
6dd9344c DD |
1048 | } else { |
1049 | UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */ | |
1050 | if (r4k_250MHZhwbug()) | |
1051 | UASM_i_MTC0(p, 0, C0_ENTRYLO0); | |
1052 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ | |
1053 | UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */ | |
1054 | if (r45k_bvahwbug()) | |
1055 | uasm_i_mfc0(p, tmp, C0_INDEX); | |
1056 | } | |
1da177e4 | 1057 | if (r4k_250MHZhwbug()) |
9b8c3891 DD |
1058 | UASM_i_MTC0(p, 0, C0_ENTRYLO1); |
1059 | UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ | |
1da177e4 LT |
1060 | #endif |
1061 | } | |
1062 | ||
2c8c53e2 DD |
1063 | struct mips_huge_tlb_info { |
1064 | int huge_pte; | |
1065 | int restore_scratch; | |
9e0f162a | 1066 | bool need_reload_pte; |
2c8c53e2 DD |
1067 | }; |
1068 | ||
078a55fc | 1069 | static struct mips_huge_tlb_info |
2c8c53e2 DD |
1070 | build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, |
1071 | struct uasm_reloc **r, unsigned int tmp, | |
7777b939 | 1072 | unsigned int ptr, int c0_scratch_reg) |
2c8c53e2 DD |
1073 | { |
1074 | struct mips_huge_tlb_info rv; | |
1075 | unsigned int even, odd; | |
1076 | int vmalloc_branch_delay_filled = 0; | |
1077 | const int scratch = 1; /* Our extra working register */ | |
1078 | ||
1079 | rv.huge_pte = scratch; | |
1080 | rv.restore_scratch = 0; | |
9e0f162a | 1081 | rv.need_reload_pte = false; |
2c8c53e2 DD |
1082 | |
1083 | if (check_for_high_segbits) { | |
1084 | UASM_i_MFC0(p, tmp, C0_BADVADDR); | |
1085 | ||
1086 | if (pgd_reg != -1) | |
7777b939 | 1087 | UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); |
2c8c53e2 DD |
1088 | else |
1089 | UASM_i_MFC0(p, ptr, C0_CONTEXT); | |
1090 | ||
7777b939 J |
1091 | if (c0_scratch_reg >= 0) |
1092 | UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); | |
2c8c53e2 DD |
1093 | else |
1094 | UASM_i_SW(p, scratch, scratchpad_offset(0), 0); | |
1095 | ||
1096 | uasm_i_dsrl_safe(p, scratch, tmp, | |
1097 | PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); | |
1098 | uasm_il_bnez(p, r, scratch, label_vmalloc); | |
1099 | ||
1100 | if (pgd_reg == -1) { | |
1101 | vmalloc_branch_delay_filled = 1; | |
1102 | /* Clear lower 23 bits of context. */ | |
1103 | uasm_i_dins(p, ptr, 0, 0, 23); | |
1104 | } | |
1105 | } else { | |
1106 | if (pgd_reg != -1) | |
7777b939 | 1107 | UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); |
2c8c53e2 DD |
1108 | else |
1109 | UASM_i_MFC0(p, ptr, C0_CONTEXT); | |
1110 | ||
1111 | UASM_i_MFC0(p, tmp, C0_BADVADDR); | |
1112 | ||
7777b939 J |
1113 | if (c0_scratch_reg >= 0) |
1114 | UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); | |
2c8c53e2 DD |
1115 | else |
1116 | UASM_i_SW(p, scratch, scratchpad_offset(0), 0); | |
1117 | ||
1118 | if (pgd_reg == -1) | |
1119 | /* Clear lower 23 bits of context. */ | |
1120 | uasm_i_dins(p, ptr, 0, 0, 23); | |
1121 | ||
1122 | uasm_il_bltz(p, r, tmp, label_vmalloc); | |
1123 | } | |
1124 | ||
1125 | if (pgd_reg == -1) { | |
1126 | vmalloc_branch_delay_filled = 1; | |
70342287 | 1127 | /* 1 0 1 0 1 << 6 xkphys cached */ |
2c8c53e2 DD |
1128 | uasm_i_ori(p, ptr, ptr, 0x540); |
1129 | uasm_i_drotr(p, ptr, ptr, 11); | |
1130 | } | |
1131 | ||
1132 | #ifdef __PAGETABLE_PMD_FOLDED | |
1133 | #define LOC_PTEP scratch | |
1134 | #else | |
1135 | #define LOC_PTEP ptr | |
1136 | #endif | |
1137 | ||
1138 | if (!vmalloc_branch_delay_filled) | |
1139 | /* get pgd offset in bytes */ | |
1140 | uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); | |
1141 | ||
1142 | uasm_l_vmalloc_done(l, *p); | |
1143 | ||
1144 | /* | |
70342287 RB |
1145 | * tmp ptr |
1146 | * fall-through case = badvaddr *pgd_current | |
1147 | * vmalloc case = badvaddr swapper_pg_dir | |
2c8c53e2 DD |
1148 | */ |
1149 | ||
1150 | if (vmalloc_branch_delay_filled) | |
1151 | /* get pgd offset in bytes */ | |
1152 | uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); | |
1153 | ||
1154 | #ifdef __PAGETABLE_PMD_FOLDED | |
1155 | GET_CONTEXT(p, tmp); /* get context reg */ | |
1156 | #endif | |
1157 | uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3); | |
1158 | ||
1159 | if (use_lwx_insns()) { | |
1160 | UASM_i_LWX(p, LOC_PTEP, scratch, ptr); | |
1161 | } else { | |
1162 | uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */ | |
1163 | uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */ | |
1164 | } | |
1165 | ||
1166 | #ifndef __PAGETABLE_PMD_FOLDED | |
1167 | /* get pmd offset in bytes */ | |
1168 | uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3); | |
1169 | uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3); | |
1170 | GET_CONTEXT(p, tmp); /* get context reg */ | |
1171 | ||
1172 | if (use_lwx_insns()) { | |
1173 | UASM_i_LWX(p, scratch, scratch, ptr); | |
1174 | } else { | |
1175 | uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */ | |
1176 | UASM_i_LW(p, scratch, 0, ptr); | |
1177 | } | |
1178 | #endif | |
1179 | /* Adjust the context during the load latency. */ | |
1180 | build_adjust_context(p, tmp); | |
1181 | ||
aa1762f4 | 1182 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
2c8c53e2 DD |
1183 | uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update); |
1184 | /* | |
1185 | * The in the LWX case we don't want to do the load in the | |
70342287 | 1186 | * delay slot. It cannot issue in the same cycle and may be |
2c8c53e2 DD |
1187 | * speculative and unneeded. |
1188 | */ | |
1189 | if (use_lwx_insns()) | |
1190 | uasm_i_nop(p); | |
aa1762f4 | 1191 | #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ |
2c8c53e2 DD |
1192 | |
1193 | ||
1194 | /* build_update_entries */ | |
1195 | if (use_lwx_insns()) { | |
1196 | even = ptr; | |
1197 | odd = tmp; | |
1198 | UASM_i_LWX(p, even, scratch, tmp); | |
1199 | UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t)); | |
1200 | UASM_i_LWX(p, odd, scratch, tmp); | |
1201 | } else { | |
1202 | UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */ | |
1203 | even = tmp; | |
1204 | odd = ptr; | |
1205 | UASM_i_LW(p, even, 0, ptr); /* get even pte */ | |
1206 | UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */ | |
1207 | } | |
05857c64 | 1208 | if (cpu_has_rixi) { |
748e787e | 1209 | uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL)); |
2c8c53e2 | 1210 | UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ |
748e787e | 1211 | uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL)); |
2c8c53e2 DD |
1212 | } else { |
1213 | uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL)); | |
1214 | UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ | |
1215 | uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL)); | |
1216 | } | |
1217 | UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */ | |
1218 | ||
7777b939 J |
1219 | if (c0_scratch_reg >= 0) { |
1220 | UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg); | |
2c8c53e2 DD |
1221 | build_tlb_write_entry(p, l, r, tlb_random); |
1222 | uasm_l_leave(l, *p); | |
1223 | rv.restore_scratch = 1; | |
1224 | } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) { | |
1225 | build_tlb_write_entry(p, l, r, tlb_random); | |
1226 | uasm_l_leave(l, *p); | |
1227 | UASM_i_LW(p, scratch, scratchpad_offset(0), 0); | |
1228 | } else { | |
1229 | UASM_i_LW(p, scratch, scratchpad_offset(0), 0); | |
1230 | build_tlb_write_entry(p, l, r, tlb_random); | |
1231 | uasm_l_leave(l, *p); | |
1232 | rv.restore_scratch = 1; | |
1233 | } | |
1234 | ||
1235 | uasm_i_eret(p); /* return from trap */ | |
1236 | ||
1237 | return rv; | |
1238 | } | |
1239 | ||
e6f72d3a DD |
1240 | /* |
1241 | * For a 64-bit kernel, we are using the 64-bit XTLB refill exception | |
1242 | * because EXL == 0. If we wrap, we can also use the 32 instruction | |
1243 | * slots before the XTLB refill exception handler which belong to the | |
1244 | * unused TLB refill exception. | |
1245 | */ | |
1246 | #define MIPS64_REFILL_INSNS 32 | |
1247 | ||
078a55fc | 1248 | static void build_r4000_tlb_refill_handler(void) |
1da177e4 LT |
1249 | { |
1250 | u32 *p = tlb_handler; | |
e30ec452 TS |
1251 | struct uasm_label *l = labels; |
1252 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1253 | u32 *f; |
1254 | unsigned int final_len; | |
4a9040f4 RB |
1255 | struct mips_huge_tlb_info htlb_info __maybe_unused; |
1256 | enum vmalloc64_mode vmalloc_mode __maybe_unused; | |
18280eda | 1257 | |
1da177e4 LT |
1258 | memset(tlb_handler, 0, sizeof(tlb_handler)); |
1259 | memset(labels, 0, sizeof(labels)); | |
1260 | memset(relocs, 0, sizeof(relocs)); | |
1261 | memset(final_handler, 0, sizeof(final_handler)); | |
1262 | ||
18280eda | 1263 | if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) { |
2c8c53e2 DD |
1264 | htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1, |
1265 | scratch_reg); | |
1266 | vmalloc_mode = refill_scratch; | |
1267 | } else { | |
1268 | htlb_info.huge_pte = K0; | |
1269 | htlb_info.restore_scratch = 0; | |
9e0f162a | 1270 | htlb_info.need_reload_pte = true; |
2c8c53e2 DD |
1271 | vmalloc_mode = refill_noscratch; |
1272 | /* | |
1273 | * create the plain linear handler | |
1274 | */ | |
1275 | if (bcm1250_m3_war()) { | |
1276 | unsigned int segbits = 44; | |
1277 | ||
1278 | uasm_i_dmfc0(&p, K0, C0_BADVADDR); | |
1279 | uasm_i_dmfc0(&p, K1, C0_ENTRYHI); | |
1280 | uasm_i_xor(&p, K0, K0, K1); | |
1281 | uasm_i_dsrl_safe(&p, K1, K0, 62); | |
1282 | uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); | |
1283 | uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); | |
1284 | uasm_i_or(&p, K0, K0, K1); | |
1285 | uasm_il_bnez(&p, &r, K0, label_leave); | |
1286 | /* No need for uasm_i_nop */ | |
1287 | } | |
1da177e4 | 1288 | |
875d43e7 | 1289 | #ifdef CONFIG_64BIT |
2c8c53e2 | 1290 | build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ |
1da177e4 | 1291 | #else |
2c8c53e2 | 1292 | build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ |
1da177e4 LT |
1293 | #endif |
1294 | ||
aa1762f4 | 1295 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
2c8c53e2 | 1296 | build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update); |
fd062c84 DD |
1297 | #endif |
1298 | ||
2c8c53e2 DD |
1299 | build_get_ptep(&p, K0, K1); |
1300 | build_update_entries(&p, K0, K1); | |
1301 | build_tlb_write_entry(&p, &l, &r, tlb_random); | |
1302 | uasm_l_leave(&l, p); | |
1303 | uasm_i_eret(&p); /* return from trap */ | |
1304 | } | |
aa1762f4 | 1305 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 | 1306 | uasm_l_tlb_huge_update(&l, p); |
9e0f162a DD |
1307 | if (htlb_info.need_reload_pte) |
1308 | UASM_i_LW(&p, htlb_info.huge_pte, 0, K1); | |
2c8c53e2 DD |
1309 | build_huge_update_entries(&p, htlb_info.huge_pte, K1); |
1310 | build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random, | |
1311 | htlb_info.restore_scratch); | |
fd062c84 DD |
1312 | #endif |
1313 | ||
875d43e7 | 1314 | #ifdef CONFIG_64BIT |
2c8c53e2 | 1315 | build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode); |
1da177e4 LT |
1316 | #endif |
1317 | ||
1318 | /* | |
1319 | * Overflow check: For the 64bit handler, we need at least one | |
1320 | * free instruction slot for the wrap-around branch. In worst | |
1321 | * case, if the intended insertion point is a delay slot, we | |
4b3f686d | 1322 | * need three, with the second nop'ed and the third being |
1da177e4 LT |
1323 | * unused. |
1324 | */ | |
14bd8c08 RB |
1325 | switch (boot_cpu_type()) { |
1326 | default: | |
1327 | if (sizeof(long) == 4) { | |
1328 | case CPU_LOONGSON2: | |
1329 | /* Loongson2 ebase is different than r4k, we have more space */ | |
1330 | if ((p - tlb_handler) > 64) | |
1331 | panic("TLB refill handler space exceeded"); | |
95affdda | 1332 | /* |
14bd8c08 | 1333 | * Now fold the handler in the TLB refill handler space. |
95affdda | 1334 | */ |
14bd8c08 RB |
1335 | f = final_handler; |
1336 | /* Simplest case, just copy the handler. */ | |
1337 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); | |
1338 | final_len = p - tlb_handler; | |
1339 | break; | |
1340 | } else { | |
1341 | if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1) | |
1342 | || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3) | |
1343 | && uasm_insn_has_bdelay(relocs, | |
1344 | tlb_handler + MIPS64_REFILL_INSNS - 3))) | |
1345 | panic("TLB refill handler space exceeded"); | |
95affdda | 1346 | /* |
14bd8c08 | 1347 | * Now fold the handler in the TLB refill handler space. |
95affdda | 1348 | */ |
14bd8c08 RB |
1349 | f = final_handler + MIPS64_REFILL_INSNS; |
1350 | if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) { | |
1351 | /* Just copy the handler. */ | |
1352 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); | |
1353 | final_len = p - tlb_handler; | |
1354 | } else { | |
1355 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT | |
1356 | const enum label_id ls = label_tlb_huge_update; | |
1357 | #else | |
1358 | const enum label_id ls = label_vmalloc; | |
1359 | #endif | |
1360 | u32 *split; | |
1361 | int ov = 0; | |
1362 | int i; | |
1363 | ||
1364 | for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++) | |
1365 | ; | |
1366 | BUG_ON(i == ARRAY_SIZE(labels)); | |
1367 | split = labels[i].addr; | |
1368 | ||
1369 | /* | |
1370 | * See if we have overflown one way or the other. | |
1371 | */ | |
1372 | if (split > tlb_handler + MIPS64_REFILL_INSNS || | |
1373 | split < p - MIPS64_REFILL_INSNS) | |
1374 | ov = 1; | |
1375 | ||
1376 | if (ov) { | |
1377 | /* | |
1378 | * Split two instructions before the end. One | |
1379 | * for the branch and one for the instruction | |
1380 | * in the delay slot. | |
1381 | */ | |
1382 | split = tlb_handler + MIPS64_REFILL_INSNS - 2; | |
1383 | ||
1384 | /* | |
1385 | * If the branch would fall in a delay slot, | |
1386 | * we must back up an additional instruction | |
1387 | * so that it is no longer in a delay slot. | |
1388 | */ | |
1389 | if (uasm_insn_has_bdelay(relocs, split - 1)) | |
1390 | split--; | |
1391 | } | |
1392 | /* Copy first part of the handler. */ | |
1393 | uasm_copy_handler(relocs, labels, tlb_handler, split, f); | |
1394 | f += split - tlb_handler; | |
1395 | ||
1396 | if (ov) { | |
1397 | /* Insert branch. */ | |
1398 | uasm_l_split(&l, final_handler); | |
1399 | uasm_il_b(&f, &r, label_split); | |
1400 | if (uasm_insn_has_bdelay(relocs, split)) | |
1401 | uasm_i_nop(&f); | |
1402 | else { | |
1403 | uasm_copy_handler(relocs, labels, | |
1404 | split, split + 1, f); | |
1405 | uasm_move_labels(labels, f, f + 1, -1); | |
1406 | f++; | |
1407 | split++; | |
1408 | } | |
1409 | } | |
1410 | ||
1411 | /* Copy the rest of the handler. */ | |
1412 | uasm_copy_handler(relocs, labels, split, p, final_handler); | |
1413 | final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) + | |
1414 | (p - split); | |
95affdda | 1415 | } |
1da177e4 | 1416 | } |
14bd8c08 | 1417 | break; |
1da177e4 | 1418 | } |
1da177e4 | 1419 | |
e30ec452 TS |
1420 | uasm_resolve_relocs(relocs, labels); |
1421 | pr_debug("Wrote TLB refill handler (%u instructions).\n", | |
1422 | final_len); | |
1da177e4 | 1423 | |
91b05e67 | 1424 | memcpy((void *)ebase, final_handler, 0x100); |
1062080a | 1425 | local_flush_icache_range(ebase, ebase + 0x100); |
92b1e6a6 | 1426 | |
a2c763e0 | 1427 | dump_handler("r4000_tlb_refill", (u32 *)ebase, 64); |
1da177e4 LT |
1428 | } |
1429 | ||
6ba045f9 J |
1430 | extern u32 handle_tlbl[], handle_tlbl_end[]; |
1431 | extern u32 handle_tlbs[], handle_tlbs_end[]; | |
1432 | extern u32 handle_tlbm[], handle_tlbm_end[]; | |
7bb39409 SH |
1433 | extern u32 tlbmiss_handler_setup_pgd_start[], tlbmiss_handler_setup_pgd[]; |
1434 | extern u32 tlbmiss_handler_setup_pgd_end[]; | |
3d8bfdd0 | 1435 | |
f4ae17aa | 1436 | static void build_setup_pgd(void) |
3d8bfdd0 DD |
1437 | { |
1438 | const int a0 = 4; | |
f4ae17aa J |
1439 | const int __maybe_unused a1 = 5; |
1440 | const int __maybe_unused a2 = 6; | |
7bb39409 | 1441 | u32 *p = tlbmiss_handler_setup_pgd_start; |
6ba045f9 | 1442 | const int tlbmiss_handler_setup_pgd_size = |
7bb39409 | 1443 | tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd_start; |
f4ae17aa J |
1444 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
1445 | long pgdc = (long)pgd_current; | |
1446 | #endif | |
3d8bfdd0 | 1447 | |
6ba045f9 J |
1448 | memset(tlbmiss_handler_setup_pgd, 0, tlbmiss_handler_setup_pgd_size * |
1449 | sizeof(tlbmiss_handler_setup_pgd[0])); | |
3d8bfdd0 DD |
1450 | memset(labels, 0, sizeof(labels)); |
1451 | memset(relocs, 0, sizeof(relocs)); | |
3d8bfdd0 | 1452 | pgd_reg = allocate_kscratch(); |
f4ae17aa | 1453 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
3d8bfdd0 | 1454 | if (pgd_reg == -1) { |
f4ae17aa J |
1455 | struct uasm_label *l = labels; |
1456 | struct uasm_reloc *r = relocs; | |
1457 | ||
3d8bfdd0 DD |
1458 | /* PGD << 11 in c0_Context */ |
1459 | /* | |
1460 | * If it is a ckseg0 address, convert to a physical | |
1461 | * address. Shifting right by 29 and adding 4 will | |
1462 | * result in zero for these addresses. | |
1463 | * | |
1464 | */ | |
1465 | UASM_i_SRA(&p, a1, a0, 29); | |
1466 | UASM_i_ADDIU(&p, a1, a1, 4); | |
1467 | uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1); | |
1468 | uasm_i_nop(&p); | |
1469 | uasm_i_dinsm(&p, a0, 0, 29, 64 - 29); | |
1470 | uasm_l_tlbl_goaround1(&l, p); | |
1471 | UASM_i_SLL(&p, a0, a0, 11); | |
1472 | uasm_i_jr(&p, 31); | |
1473 | UASM_i_MTC0(&p, a0, C0_CONTEXT); | |
1474 | } else { | |
1475 | /* PGD in c0_KScratch */ | |
1476 | uasm_i_jr(&p, 31); | |
7777b939 | 1477 | UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); |
3d8bfdd0 | 1478 | } |
f4ae17aa J |
1479 | #else |
1480 | #ifdef CONFIG_SMP | |
1481 | /* Save PGD to pgd_current[smp_processor_id()] */ | |
1482 | UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG); | |
1483 | UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT); | |
1484 | UASM_i_LA_mostly(&p, a2, pgdc); | |
1485 | UASM_i_ADDU(&p, a2, a2, a1); | |
1486 | UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); | |
1487 | #else | |
1488 | UASM_i_LA_mostly(&p, a2, pgdc); | |
1489 | UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); | |
1490 | #endif /* SMP */ | |
1491 | uasm_i_jr(&p, 31); | |
1492 | ||
1493 | /* if pgd_reg is allocated, save PGD also to scratch register */ | |
1494 | if (pgd_reg != -1) | |
1495 | UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); | |
1496 | else | |
1497 | uasm_i_nop(&p); | |
1498 | #endif | |
6ba045f9 J |
1499 | if (p >= tlbmiss_handler_setup_pgd_end) |
1500 | panic("tlbmiss_handler_setup_pgd space exceeded"); | |
1501 | ||
3d8bfdd0 | 1502 | uasm_resolve_relocs(relocs, labels); |
6ba045f9 J |
1503 | pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n", |
1504 | (unsigned int)(p - tlbmiss_handler_setup_pgd)); | |
3d8bfdd0 | 1505 | |
6ba045f9 J |
1506 | dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd, |
1507 | tlbmiss_handler_setup_pgd_size); | |
3d8bfdd0 | 1508 | } |
1da177e4 | 1509 | |
078a55fc | 1510 | static void |
bd1437e4 | 1511 | iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) |
1da177e4 LT |
1512 | { |
1513 | #ifdef CONFIG_SMP | |
34adb28d | 1514 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
1da177e4 | 1515 | if (cpu_has_64bits) |
e30ec452 | 1516 | uasm_i_lld(p, pte, 0, ptr); |
1da177e4 LT |
1517 | else |
1518 | # endif | |
e30ec452 | 1519 | UASM_i_LL(p, pte, 0, ptr); |
1da177e4 | 1520 | #else |
34adb28d | 1521 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
1da177e4 | 1522 | if (cpu_has_64bits) |
e30ec452 | 1523 | uasm_i_ld(p, pte, 0, ptr); |
1da177e4 LT |
1524 | else |
1525 | # endif | |
e30ec452 | 1526 | UASM_i_LW(p, pte, 0, ptr); |
1da177e4 LT |
1527 | #endif |
1528 | } | |
1529 | ||
078a55fc | 1530 | static void |
e30ec452 | 1531 | iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, |
63b2d2f4 | 1532 | unsigned int mode) |
1da177e4 | 1533 | { |
34adb28d | 1534 | #ifdef CONFIG_PHYS_ADDR_T_64BIT |
63b2d2f4 TS |
1535 | unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); |
1536 | #endif | |
1537 | ||
e30ec452 | 1538 | uasm_i_ori(p, pte, pte, mode); |
1da177e4 | 1539 | #ifdef CONFIG_SMP |
34adb28d | 1540 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
1da177e4 | 1541 | if (cpu_has_64bits) |
e30ec452 | 1542 | uasm_i_scd(p, pte, 0, ptr); |
1da177e4 LT |
1543 | else |
1544 | # endif | |
e30ec452 | 1545 | UASM_i_SC(p, pte, 0, ptr); |
1da177e4 LT |
1546 | |
1547 | if (r10000_llsc_war()) | |
e30ec452 | 1548 | uasm_il_beqzl(p, r, pte, label_smp_pgtable_change); |
1da177e4 | 1549 | else |
e30ec452 | 1550 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); |
1da177e4 | 1551 | |
34adb28d | 1552 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
1da177e4 | 1553 | if (!cpu_has_64bits) { |
e30ec452 TS |
1554 | /* no uasm_i_nop needed */ |
1555 | uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr); | |
1556 | uasm_i_ori(p, pte, pte, hwmode); | |
1557 | uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr); | |
1558 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); | |
1559 | /* no uasm_i_nop needed */ | |
1560 | uasm_i_lw(p, pte, 0, ptr); | |
1da177e4 | 1561 | } else |
e30ec452 | 1562 | uasm_i_nop(p); |
1da177e4 | 1563 | # else |
e30ec452 | 1564 | uasm_i_nop(p); |
1da177e4 LT |
1565 | # endif |
1566 | #else | |
34adb28d | 1567 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
1da177e4 | 1568 | if (cpu_has_64bits) |
e30ec452 | 1569 | uasm_i_sd(p, pte, 0, ptr); |
1da177e4 LT |
1570 | else |
1571 | # endif | |
e30ec452 | 1572 | UASM_i_SW(p, pte, 0, ptr); |
1da177e4 | 1573 | |
34adb28d | 1574 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
1da177e4 | 1575 | if (!cpu_has_64bits) { |
e30ec452 TS |
1576 | uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr); |
1577 | uasm_i_ori(p, pte, pte, hwmode); | |
1578 | uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr); | |
1579 | uasm_i_lw(p, pte, 0, ptr); | |
1da177e4 LT |
1580 | } |
1581 | # endif | |
1582 | #endif | |
1583 | } | |
1584 | ||
1585 | /* | |
1586 | * Check if PTE is present, if not then jump to LABEL. PTR points to | |
1587 | * the page table where this PTE is located, PTE will be re-loaded | |
1588 | * with it's original value. | |
1589 | */ | |
078a55fc | 1590 | static void |
bd1437e4 | 1591 | build_pte_present(u32 **p, struct uasm_reloc **r, |
bf28607f | 1592 | int pte, int ptr, int scratch, enum label_id lid) |
1da177e4 | 1593 | { |
bf28607f DD |
1594 | int t = scratch >= 0 ? scratch : pte; |
1595 | ||
05857c64 | 1596 | if (cpu_has_rixi) { |
cc33ae43 DD |
1597 | if (use_bbit_insns()) { |
1598 | uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); | |
1599 | uasm_i_nop(p); | |
1600 | } else { | |
bf28607f DD |
1601 | uasm_i_andi(p, t, pte, _PAGE_PRESENT); |
1602 | uasm_il_beqz(p, r, t, lid); | |
1603 | if (pte == t) | |
1604 | /* You lose the SMP race :-(*/ | |
1605 | iPTE_LW(p, pte, ptr); | |
cc33ae43 | 1606 | } |
6dd9344c | 1607 | } else { |
bf28607f DD |
1608 | uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_READ); |
1609 | uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_READ); | |
1610 | uasm_il_bnez(p, r, t, lid); | |
1611 | if (pte == t) | |
1612 | /* You lose the SMP race :-(*/ | |
1613 | iPTE_LW(p, pte, ptr); | |
6dd9344c | 1614 | } |
1da177e4 LT |
1615 | } |
1616 | ||
1617 | /* Make PTE valid, store result in PTR. */ | |
078a55fc | 1618 | static void |
e30ec452 | 1619 | build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte, |
1da177e4 LT |
1620 | unsigned int ptr) |
1621 | { | |
63b2d2f4 TS |
1622 | unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; |
1623 | ||
1624 | iPTE_SW(p, r, pte, ptr, mode); | |
1da177e4 LT |
1625 | } |
1626 | ||
1627 | /* | |
1628 | * Check if PTE can be written to, if not branch to LABEL. Regardless | |
1629 | * restore PTE with value from PTR when done. | |
1630 | */ | |
078a55fc | 1631 | static void |
bd1437e4 | 1632 | build_pte_writable(u32 **p, struct uasm_reloc **r, |
bf28607f DD |
1633 | unsigned int pte, unsigned int ptr, int scratch, |
1634 | enum label_id lid) | |
1da177e4 | 1635 | { |
bf28607f DD |
1636 | int t = scratch >= 0 ? scratch : pte; |
1637 | ||
1638 | uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_WRITE); | |
1639 | uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_WRITE); | |
1640 | uasm_il_bnez(p, r, t, lid); | |
1641 | if (pte == t) | |
1642 | /* You lose the SMP race :-(*/ | |
cc33ae43 | 1643 | iPTE_LW(p, pte, ptr); |
bf28607f DD |
1644 | else |
1645 | uasm_i_nop(p); | |
1da177e4 LT |
1646 | } |
1647 | ||
1648 | /* Make PTE writable, update software status bits as well, then store | |
1649 | * at PTR. | |
1650 | */ | |
078a55fc | 1651 | static void |
e30ec452 | 1652 | build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte, |
1da177e4 LT |
1653 | unsigned int ptr) |
1654 | { | |
63b2d2f4 TS |
1655 | unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID |
1656 | | _PAGE_DIRTY); | |
1657 | ||
1658 | iPTE_SW(p, r, pte, ptr, mode); | |
1da177e4 LT |
1659 | } |
1660 | ||
1661 | /* | |
1662 | * Check if PTE can be modified, if not branch to LABEL. Regardless | |
1663 | * restore PTE with value from PTR when done. | |
1664 | */ | |
078a55fc | 1665 | static void |
bd1437e4 | 1666 | build_pte_modifiable(u32 **p, struct uasm_reloc **r, |
bf28607f DD |
1667 | unsigned int pte, unsigned int ptr, int scratch, |
1668 | enum label_id lid) | |
1da177e4 | 1669 | { |
cc33ae43 DD |
1670 | if (use_bbit_insns()) { |
1671 | uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid); | |
1672 | uasm_i_nop(p); | |
1673 | } else { | |
bf28607f DD |
1674 | int t = scratch >= 0 ? scratch : pte; |
1675 | uasm_i_andi(p, t, pte, _PAGE_WRITE); | |
1676 | uasm_il_beqz(p, r, t, lid); | |
1677 | if (pte == t) | |
1678 | /* You lose the SMP race :-(*/ | |
1679 | iPTE_LW(p, pte, ptr); | |
cc33ae43 | 1680 | } |
1da177e4 LT |
1681 | } |
1682 | ||
82622284 | 1683 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
3d8bfdd0 DD |
1684 | |
1685 | ||
1da177e4 LT |
1686 | /* |
1687 | * R3000 style TLB load/store/modify handlers. | |
1688 | */ | |
1689 | ||
fded2e50 MR |
1690 | /* |
1691 | * This places the pte into ENTRYLO0 and writes it with tlbwi. | |
1692 | * Then it returns. | |
1693 | */ | |
078a55fc | 1694 | static void |
fded2e50 | 1695 | build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) |
1da177e4 | 1696 | { |
e30ec452 TS |
1697 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ |
1698 | uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ | |
1699 | uasm_i_tlbwi(p); | |
1700 | uasm_i_jr(p, tmp); | |
1701 | uasm_i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1702 | } |
1703 | ||
1704 | /* | |
fded2e50 MR |
1705 | * This places the pte into ENTRYLO0 and writes it with tlbwi |
1706 | * or tlbwr as appropriate. This is because the index register | |
1707 | * may have the probe fail bit set as a result of a trap on a | |
1708 | * kseg2 access, i.e. without refill. Then it returns. | |
1da177e4 | 1709 | */ |
078a55fc | 1710 | static void |
e30ec452 TS |
1711 | build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l, |
1712 | struct uasm_reloc **r, unsigned int pte, | |
1713 | unsigned int tmp) | |
1714 | { | |
1715 | uasm_i_mfc0(p, tmp, C0_INDEX); | |
1716 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ | |
1717 | uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ | |
1718 | uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */ | |
1719 | uasm_i_tlbwi(p); /* cp0 delay */ | |
1720 | uasm_i_jr(p, tmp); | |
1721 | uasm_i_rfe(p); /* branch delay */ | |
1722 | uasm_l_r3000_write_probe_fail(l, *p); | |
1723 | uasm_i_tlbwr(p); /* cp0 delay */ | |
1724 | uasm_i_jr(p, tmp); | |
1725 | uasm_i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1726 | } |
1727 | ||
078a55fc | 1728 | static void |
1da177e4 LT |
1729 | build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, |
1730 | unsigned int ptr) | |
1731 | { | |
1732 | long pgdc = (long)pgd_current; | |
1733 | ||
e30ec452 TS |
1734 | uasm_i_mfc0(p, pte, C0_BADVADDR); |
1735 | uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */ | |
1736 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1737 | uasm_i_srl(p, pte, pte, 22); /* load delay */ | |
1738 | uasm_i_sll(p, pte, pte, 2); | |
1739 | uasm_i_addu(p, ptr, ptr, pte); | |
1740 | uasm_i_mfc0(p, pte, C0_CONTEXT); | |
1741 | uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */ | |
1742 | uasm_i_andi(p, pte, pte, 0xffc); /* load delay */ | |
1743 | uasm_i_addu(p, ptr, ptr, pte); | |
1744 | uasm_i_lw(p, pte, 0, ptr); | |
1745 | uasm_i_tlbp(p); /* load delay */ | |
1da177e4 LT |
1746 | } |
1747 | ||
078a55fc | 1748 | static void build_r3000_tlb_load_handler(void) |
1da177e4 LT |
1749 | { |
1750 | u32 *p = handle_tlbl; | |
6ba045f9 | 1751 | const int handle_tlbl_size = handle_tlbl_end - handle_tlbl; |
e30ec452 TS |
1752 | struct uasm_label *l = labels; |
1753 | struct uasm_reloc *r = relocs; | |
1da177e4 | 1754 | |
6ba045f9 | 1755 | memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0])); |
1da177e4 LT |
1756 | memset(labels, 0, sizeof(labels)); |
1757 | memset(relocs, 0, sizeof(relocs)); | |
1758 | ||
1759 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
bf28607f | 1760 | build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl); |
e30ec452 | 1761 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1762 | build_make_valid(&p, &r, K0, K1); |
fded2e50 | 1763 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 | 1764 | |
e30ec452 TS |
1765 | uasm_l_nopage_tlbl(&l, p); |
1766 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); | |
1767 | uasm_i_nop(&p); | |
1da177e4 | 1768 | |
6ba045f9 | 1769 | if (p >= handle_tlbl_end) |
1da177e4 LT |
1770 | panic("TLB load handler fastpath space exceeded"); |
1771 | ||
e30ec452 TS |
1772 | uasm_resolve_relocs(relocs, labels); |
1773 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", | |
1774 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 1775 | |
6ba045f9 | 1776 | dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_size); |
1da177e4 LT |
1777 | } |
1778 | ||
078a55fc | 1779 | static void build_r3000_tlb_store_handler(void) |
1da177e4 LT |
1780 | { |
1781 | u32 *p = handle_tlbs; | |
6ba045f9 | 1782 | const int handle_tlbs_size = handle_tlbs_end - handle_tlbs; |
e30ec452 TS |
1783 | struct uasm_label *l = labels; |
1784 | struct uasm_reloc *r = relocs; | |
1da177e4 | 1785 | |
6ba045f9 | 1786 | memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0])); |
1da177e4 LT |
1787 | memset(labels, 0, sizeof(labels)); |
1788 | memset(relocs, 0, sizeof(relocs)); | |
1789 | ||
1790 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
bf28607f | 1791 | build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs); |
e30ec452 | 1792 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1793 | build_make_write(&p, &r, K0, K1); |
fded2e50 | 1794 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 | 1795 | |
e30ec452 TS |
1796 | uasm_l_nopage_tlbs(&l, p); |
1797 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1798 | uasm_i_nop(&p); | |
1da177e4 | 1799 | |
afc813ae | 1800 | if (p >= handle_tlbs_end) |
1da177e4 LT |
1801 | panic("TLB store handler fastpath space exceeded"); |
1802 | ||
e30ec452 TS |
1803 | uasm_resolve_relocs(relocs, labels); |
1804 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", | |
1805 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 1806 | |
6ba045f9 | 1807 | dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_size); |
1da177e4 LT |
1808 | } |
1809 | ||
078a55fc | 1810 | static void build_r3000_tlb_modify_handler(void) |
1da177e4 LT |
1811 | { |
1812 | u32 *p = handle_tlbm; | |
6ba045f9 | 1813 | const int handle_tlbm_size = handle_tlbm_end - handle_tlbm; |
e30ec452 TS |
1814 | struct uasm_label *l = labels; |
1815 | struct uasm_reloc *r = relocs; | |
1da177e4 | 1816 | |
6ba045f9 | 1817 | memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0])); |
1da177e4 LT |
1818 | memset(labels, 0, sizeof(labels)); |
1819 | memset(relocs, 0, sizeof(relocs)); | |
1820 | ||
1821 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
d954ffe3 | 1822 | build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm); |
e30ec452 | 1823 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1824 | build_make_write(&p, &r, K0, K1); |
fded2e50 | 1825 | build_r3000_pte_reload_tlbwi(&p, K0, K1); |
1da177e4 | 1826 | |
e30ec452 TS |
1827 | uasm_l_nopage_tlbm(&l, p); |
1828 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1829 | uasm_i_nop(&p); | |
1da177e4 | 1830 | |
6ba045f9 | 1831 | if (p >= handle_tlbm_end) |
1da177e4 LT |
1832 | panic("TLB modify handler fastpath space exceeded"); |
1833 | ||
e30ec452 TS |
1834 | uasm_resolve_relocs(relocs, labels); |
1835 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", | |
1836 | (unsigned int)(p - handle_tlbm)); | |
1da177e4 | 1837 | |
6ba045f9 | 1838 | dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_size); |
1da177e4 | 1839 | } |
82622284 | 1840 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ |
1da177e4 LT |
1841 | |
1842 | /* | |
1843 | * R4000 style TLB load/store/modify handlers. | |
1844 | */ | |
078a55fc | 1845 | static struct work_registers |
e30ec452 | 1846 | build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l, |
bf28607f | 1847 | struct uasm_reloc **r) |
1da177e4 | 1848 | { |
bf28607f DD |
1849 | struct work_registers wr = build_get_work_registers(p); |
1850 | ||
875d43e7 | 1851 | #ifdef CONFIG_64BIT |
bf28607f | 1852 | build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */ |
1da177e4 | 1853 | #else |
bf28607f | 1854 | build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */ |
1da177e4 LT |
1855 | #endif |
1856 | ||
aa1762f4 | 1857 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
1858 | /* |
1859 | * For huge tlb entries, pmd doesn't contain an address but | |
1860 | * instead contains the tlb pte. Check the PAGE_HUGE bit and | |
1861 | * see if we need to jump to huge tlb processing. | |
1862 | */ | |
bf28607f | 1863 | build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update); |
fd062c84 DD |
1864 | #endif |
1865 | ||
bf28607f DD |
1866 | UASM_i_MFC0(p, wr.r1, C0_BADVADDR); |
1867 | UASM_i_LW(p, wr.r2, 0, wr.r2); | |
1868 | UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); | |
1869 | uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2); | |
1870 | UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1); | |
1da177e4 LT |
1871 | |
1872 | #ifdef CONFIG_SMP | |
e30ec452 TS |
1873 | uasm_l_smp_pgtable_change(l, *p); |
1874 | #endif | |
bf28607f | 1875 | iPTE_LW(p, wr.r1, wr.r2); /* get even pte */ |
070e76cb | 1876 | if (!m4kc_tlbp_war()) { |
8df5beac | 1877 | build_tlb_probe_entry(p); |
070e76cb LY |
1878 | if (cpu_has_htw) { |
1879 | /* race condition happens, leaving */ | |
1880 | uasm_i_ehb(p); | |
1881 | uasm_i_mfc0(p, wr.r3, C0_INDEX); | |
1882 | uasm_il_bltz(p, r, wr.r3, label_leave); | |
1883 | uasm_i_nop(p); | |
1884 | } | |
1885 | } | |
bf28607f | 1886 | return wr; |
1da177e4 LT |
1887 | } |
1888 | ||
078a55fc | 1889 | static void |
e30ec452 TS |
1890 | build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, |
1891 | struct uasm_reloc **r, unsigned int tmp, | |
1da177e4 LT |
1892 | unsigned int ptr) |
1893 | { | |
e30ec452 TS |
1894 | uasm_i_ori(p, ptr, ptr, sizeof(pte_t)); |
1895 | uasm_i_xori(p, ptr, ptr, sizeof(pte_t)); | |
1da177e4 LT |
1896 | build_update_entries(p, tmp, ptr); |
1897 | build_tlb_write_entry(p, l, r, tlb_indexed); | |
e30ec452 | 1898 | uasm_l_leave(l, *p); |
bf28607f | 1899 | build_restore_work_registers(p); |
e30ec452 | 1900 | uasm_i_eret(p); /* return from trap */ |
1da177e4 | 1901 | |
875d43e7 | 1902 | #ifdef CONFIG_64BIT |
1ec56329 | 1903 | build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill); |
1da177e4 LT |
1904 | #endif |
1905 | } | |
1906 | ||
078a55fc | 1907 | static void build_r4000_tlb_load_handler(void) |
1da177e4 LT |
1908 | { |
1909 | u32 *p = handle_tlbl; | |
6ba045f9 | 1910 | const int handle_tlbl_size = handle_tlbl_end - handle_tlbl; |
e30ec452 TS |
1911 | struct uasm_label *l = labels; |
1912 | struct uasm_reloc *r = relocs; | |
bf28607f | 1913 | struct work_registers wr; |
1da177e4 | 1914 | |
6ba045f9 | 1915 | memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0])); |
1da177e4 LT |
1916 | memset(labels, 0, sizeof(labels)); |
1917 | memset(relocs, 0, sizeof(relocs)); | |
1918 | ||
1919 | if (bcm1250_m3_war()) { | |
3d45285d RB |
1920 | unsigned int segbits = 44; |
1921 | ||
1922 | uasm_i_dmfc0(&p, K0, C0_BADVADDR); | |
1923 | uasm_i_dmfc0(&p, K1, C0_ENTRYHI); | |
e30ec452 | 1924 | uasm_i_xor(&p, K0, K0, K1); |
3be6022c DD |
1925 | uasm_i_dsrl_safe(&p, K1, K0, 62); |
1926 | uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); | |
1927 | uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); | |
3d45285d | 1928 | uasm_i_or(&p, K0, K0, K1); |
e30ec452 TS |
1929 | uasm_il_bnez(&p, &r, K0, label_leave); |
1930 | /* No need for uasm_i_nop */ | |
1da177e4 LT |
1931 | } |
1932 | ||
bf28607f DD |
1933 | wr = build_r4000_tlbchange_handler_head(&p, &l, &r); |
1934 | build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); | |
8df5beac MR |
1935 | if (m4kc_tlbp_war()) |
1936 | build_tlb_probe_entry(&p); | |
6dd9344c | 1937 | |
5890f70f | 1938 | if (cpu_has_rixi && !cpu_has_rixiex) { |
6dd9344c DD |
1939 | /* |
1940 | * If the page is not _PAGE_VALID, RI or XI could not | |
1941 | * have triggered it. Skip the expensive test.. | |
1942 | */ | |
cc33ae43 | 1943 | if (use_bbit_insns()) { |
bf28607f | 1944 | uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), |
cc33ae43 DD |
1945 | label_tlbl_goaround1); |
1946 | } else { | |
bf28607f DD |
1947 | uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); |
1948 | uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1); | |
cc33ae43 | 1949 | } |
6dd9344c DD |
1950 | uasm_i_nop(&p); |
1951 | ||
1952 | uasm_i_tlbr(&p); | |
73acc7df RB |
1953 | |
1954 | switch (current_cpu_type()) { | |
1955 | default: | |
1956 | if (cpu_has_mips_r2) { | |
1957 | uasm_i_ehb(&p); | |
1958 | ||
1959 | case CPU_CAVIUM_OCTEON: | |
1960 | case CPU_CAVIUM_OCTEON_PLUS: | |
1961 | case CPU_CAVIUM_OCTEON2: | |
1962 | break; | |
1963 | } | |
1964 | } | |
1965 | ||
6dd9344c | 1966 | /* Examine entrylo 0 or 1 based on ptr. */ |
cc33ae43 | 1967 | if (use_bbit_insns()) { |
bf28607f | 1968 | uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); |
cc33ae43 | 1969 | } else { |
bf28607f DD |
1970 | uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); |
1971 | uasm_i_beqz(&p, wr.r3, 8); | |
cc33ae43 | 1972 | } |
bf28607f DD |
1973 | /* load it in the delay slot*/ |
1974 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); | |
1975 | /* load it if ptr is odd */ | |
1976 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); | |
6dd9344c | 1977 | /* |
bf28607f | 1978 | * If the entryLo (now in wr.r3) is valid (bit 1), RI or |
6dd9344c DD |
1979 | * XI must have triggered it. |
1980 | */ | |
cc33ae43 | 1981 | if (use_bbit_insns()) { |
bf28607f DD |
1982 | uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl); |
1983 | uasm_i_nop(&p); | |
cc33ae43 DD |
1984 | uasm_l_tlbl_goaround1(&l, p); |
1985 | } else { | |
bf28607f DD |
1986 | uasm_i_andi(&p, wr.r3, wr.r3, 2); |
1987 | uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl); | |
1988 | uasm_i_nop(&p); | |
cc33ae43 | 1989 | } |
bf28607f | 1990 | uasm_l_tlbl_goaround1(&l, p); |
6dd9344c | 1991 | } |
bf28607f DD |
1992 | build_make_valid(&p, &r, wr.r1, wr.r2); |
1993 | build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); | |
1da177e4 | 1994 | |
aa1762f4 | 1995 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
1996 | /* |
1997 | * This is the entry point when build_r4000_tlbchange_handler_head | |
1998 | * spots a huge page. | |
1999 | */ | |
2000 | uasm_l_tlb_huge_update(&l, p); | |
bf28607f DD |
2001 | iPTE_LW(&p, wr.r1, wr.r2); |
2002 | build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); | |
fd062c84 | 2003 | build_tlb_probe_entry(&p); |
6dd9344c | 2004 | |
5890f70f | 2005 | if (cpu_has_rixi && !cpu_has_rixiex) { |
6dd9344c DD |
2006 | /* |
2007 | * If the page is not _PAGE_VALID, RI or XI could not | |
2008 | * have triggered it. Skip the expensive test.. | |
2009 | */ | |
cc33ae43 | 2010 | if (use_bbit_insns()) { |
bf28607f | 2011 | uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), |
cc33ae43 DD |
2012 | label_tlbl_goaround2); |
2013 | } else { | |
bf28607f DD |
2014 | uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); |
2015 | uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); | |
cc33ae43 | 2016 | } |
6dd9344c DD |
2017 | uasm_i_nop(&p); |
2018 | ||
2019 | uasm_i_tlbr(&p); | |
73acc7df RB |
2020 | |
2021 | switch (current_cpu_type()) { | |
2022 | default: | |
2023 | if (cpu_has_mips_r2) { | |
2024 | uasm_i_ehb(&p); | |
2025 | ||
2026 | case CPU_CAVIUM_OCTEON: | |
2027 | case CPU_CAVIUM_OCTEON_PLUS: | |
2028 | case CPU_CAVIUM_OCTEON2: | |
2029 | break; | |
2030 | } | |
2031 | } | |
2032 | ||
6dd9344c | 2033 | /* Examine entrylo 0 or 1 based on ptr. */ |
cc33ae43 | 2034 | if (use_bbit_insns()) { |
bf28607f | 2035 | uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); |
cc33ae43 | 2036 | } else { |
bf28607f DD |
2037 | uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); |
2038 | uasm_i_beqz(&p, wr.r3, 8); | |
cc33ae43 | 2039 | } |
bf28607f DD |
2040 | /* load it in the delay slot*/ |
2041 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); | |
2042 | /* load it if ptr is odd */ | |
2043 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); | |
6dd9344c | 2044 | /* |
bf28607f | 2045 | * If the entryLo (now in wr.r3) is valid (bit 1), RI or |
6dd9344c DD |
2046 | * XI must have triggered it. |
2047 | */ | |
cc33ae43 | 2048 | if (use_bbit_insns()) { |
bf28607f | 2049 | uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2); |
cc33ae43 | 2050 | } else { |
bf28607f DD |
2051 | uasm_i_andi(&p, wr.r3, wr.r3, 2); |
2052 | uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); | |
cc33ae43 | 2053 | } |
0f4ccbc8 DD |
2054 | if (PM_DEFAULT_MASK == 0) |
2055 | uasm_i_nop(&p); | |
6dd9344c DD |
2056 | /* |
2057 | * We clobbered C0_PAGEMASK, restore it. On the other branch | |
2058 | * it is restored in build_huge_tlb_write_entry. | |
2059 | */ | |
bf28607f | 2060 | build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0); |
6dd9344c DD |
2061 | |
2062 | uasm_l_tlbl_goaround2(&l, p); | |
2063 | } | |
bf28607f DD |
2064 | uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID)); |
2065 | build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2); | |
fd062c84 DD |
2066 | #endif |
2067 | ||
e30ec452 | 2068 | uasm_l_nopage_tlbl(&l, p); |
bf28607f | 2069 | build_restore_work_registers(&p); |
2a0b24f5 SH |
2070 | #ifdef CONFIG_CPU_MICROMIPS |
2071 | if ((unsigned long)tlb_do_page_fault_0 & 1) { | |
2072 | uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0)); | |
2073 | uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0)); | |
2074 | uasm_i_jr(&p, K0); | |
2075 | } else | |
2076 | #endif | |
e30ec452 TS |
2077 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); |
2078 | uasm_i_nop(&p); | |
1da177e4 | 2079 | |
6ba045f9 | 2080 | if (p >= handle_tlbl_end) |
1da177e4 LT |
2081 | panic("TLB load handler fastpath space exceeded"); |
2082 | ||
e30ec452 TS |
2083 | uasm_resolve_relocs(relocs, labels); |
2084 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", | |
2085 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 2086 | |
6ba045f9 | 2087 | dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_size); |
1da177e4 LT |
2088 | } |
2089 | ||
078a55fc | 2090 | static void build_r4000_tlb_store_handler(void) |
1da177e4 LT |
2091 | { |
2092 | u32 *p = handle_tlbs; | |
6ba045f9 | 2093 | const int handle_tlbs_size = handle_tlbs_end - handle_tlbs; |
e30ec452 TS |
2094 | struct uasm_label *l = labels; |
2095 | struct uasm_reloc *r = relocs; | |
bf28607f | 2096 | struct work_registers wr; |
1da177e4 | 2097 | |
6ba045f9 | 2098 | memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0])); |
1da177e4 LT |
2099 | memset(labels, 0, sizeof(labels)); |
2100 | memset(relocs, 0, sizeof(relocs)); | |
2101 | ||
bf28607f DD |
2102 | wr = build_r4000_tlbchange_handler_head(&p, &l, &r); |
2103 | build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); | |
8df5beac MR |
2104 | if (m4kc_tlbp_war()) |
2105 | build_tlb_probe_entry(&p); | |
bf28607f DD |
2106 | build_make_write(&p, &r, wr.r1, wr.r2); |
2107 | build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); | |
1da177e4 | 2108 | |
aa1762f4 | 2109 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
2110 | /* |
2111 | * This is the entry point when | |
2112 | * build_r4000_tlbchange_handler_head spots a huge page. | |
2113 | */ | |
2114 | uasm_l_tlb_huge_update(&l, p); | |
bf28607f DD |
2115 | iPTE_LW(&p, wr.r1, wr.r2); |
2116 | build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); | |
fd062c84 | 2117 | build_tlb_probe_entry(&p); |
bf28607f | 2118 | uasm_i_ori(&p, wr.r1, wr.r1, |
fd062c84 | 2119 | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); |
bf28607f | 2120 | build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2); |
fd062c84 DD |
2121 | #endif |
2122 | ||
e30ec452 | 2123 | uasm_l_nopage_tlbs(&l, p); |
bf28607f | 2124 | build_restore_work_registers(&p); |
2a0b24f5 SH |
2125 | #ifdef CONFIG_CPU_MICROMIPS |
2126 | if ((unsigned long)tlb_do_page_fault_1 & 1) { | |
2127 | uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); | |
2128 | uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); | |
2129 | uasm_i_jr(&p, K0); | |
2130 | } else | |
2131 | #endif | |
e30ec452 TS |
2132 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); |
2133 | uasm_i_nop(&p); | |
1da177e4 | 2134 | |
6ba045f9 | 2135 | if (p >= handle_tlbs_end) |
1da177e4 LT |
2136 | panic("TLB store handler fastpath space exceeded"); |
2137 | ||
e30ec452 TS |
2138 | uasm_resolve_relocs(relocs, labels); |
2139 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", | |
2140 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 2141 | |
6ba045f9 | 2142 | dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_size); |
1da177e4 LT |
2143 | } |
2144 | ||
078a55fc | 2145 | static void build_r4000_tlb_modify_handler(void) |
1da177e4 LT |
2146 | { |
2147 | u32 *p = handle_tlbm; | |
6ba045f9 | 2148 | const int handle_tlbm_size = handle_tlbm_end - handle_tlbm; |
e30ec452 TS |
2149 | struct uasm_label *l = labels; |
2150 | struct uasm_reloc *r = relocs; | |
bf28607f | 2151 | struct work_registers wr; |
1da177e4 | 2152 | |
6ba045f9 | 2153 | memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0])); |
1da177e4 LT |
2154 | memset(labels, 0, sizeof(labels)); |
2155 | memset(relocs, 0, sizeof(relocs)); | |
2156 | ||
bf28607f DD |
2157 | wr = build_r4000_tlbchange_handler_head(&p, &l, &r); |
2158 | build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); | |
8df5beac MR |
2159 | if (m4kc_tlbp_war()) |
2160 | build_tlb_probe_entry(&p); | |
1da177e4 | 2161 | /* Present and writable bits set, set accessed and dirty bits. */ |
bf28607f DD |
2162 | build_make_write(&p, &r, wr.r1, wr.r2); |
2163 | build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); | |
1da177e4 | 2164 | |
aa1762f4 | 2165 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
2166 | /* |
2167 | * This is the entry point when | |
2168 | * build_r4000_tlbchange_handler_head spots a huge page. | |
2169 | */ | |
2170 | uasm_l_tlb_huge_update(&l, p); | |
bf28607f DD |
2171 | iPTE_LW(&p, wr.r1, wr.r2); |
2172 | build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); | |
fd062c84 | 2173 | build_tlb_probe_entry(&p); |
bf28607f | 2174 | uasm_i_ori(&p, wr.r1, wr.r1, |
fd062c84 | 2175 | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); |
bf28607f | 2176 | build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2); |
fd062c84 DD |
2177 | #endif |
2178 | ||
e30ec452 | 2179 | uasm_l_nopage_tlbm(&l, p); |
bf28607f | 2180 | build_restore_work_registers(&p); |
2a0b24f5 SH |
2181 | #ifdef CONFIG_CPU_MICROMIPS |
2182 | if ((unsigned long)tlb_do_page_fault_1 & 1) { | |
2183 | uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); | |
2184 | uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); | |
2185 | uasm_i_jr(&p, K0); | |
2186 | } else | |
2187 | #endif | |
e30ec452 TS |
2188 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); |
2189 | uasm_i_nop(&p); | |
1da177e4 | 2190 | |
6ba045f9 | 2191 | if (p >= handle_tlbm_end) |
1da177e4 LT |
2192 | panic("TLB modify handler fastpath space exceeded"); |
2193 | ||
e30ec452 TS |
2194 | uasm_resolve_relocs(relocs, labels); |
2195 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", | |
2196 | (unsigned int)(p - handle_tlbm)); | |
115f2a44 | 2197 | |
6ba045f9 | 2198 | dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_size); |
1da177e4 LT |
2199 | } |
2200 | ||
078a55fc | 2201 | static void flush_tlb_handlers(void) |
a3d9086b JG |
2202 | { |
2203 | local_flush_icache_range((unsigned long)handle_tlbl, | |
6ac5310e | 2204 | (unsigned long)handle_tlbl_end); |
a3d9086b | 2205 | local_flush_icache_range((unsigned long)handle_tlbs, |
6ac5310e | 2206 | (unsigned long)handle_tlbs_end); |
a3d9086b | 2207 | local_flush_icache_range((unsigned long)handle_tlbm, |
6ac5310e | 2208 | (unsigned long)handle_tlbm_end); |
6ac5310e RB |
2209 | local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, |
2210 | (unsigned long)tlbmiss_handler_setup_pgd_end); | |
a3d9086b JG |
2211 | } |
2212 | ||
f1014d1b MC |
2213 | static void print_htw_config(void) |
2214 | { | |
2215 | unsigned long config; | |
2216 | unsigned int pwctl; | |
2217 | const int field = 2 * sizeof(unsigned long); | |
2218 | ||
2219 | config = read_c0_pwfield(); | |
2220 | pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n", | |
2221 | field, config, | |
2222 | (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT, | |
2223 | (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT, | |
2224 | (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT, | |
2225 | (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT, | |
2226 | (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT); | |
2227 | ||
2228 | config = read_c0_pwsize(); | |
2229 | pr_debug("PWSize (0x%0*lx): GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n", | |
2230 | field, config, | |
2231 | (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT, | |
2232 | (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT, | |
2233 | (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT, | |
2234 | (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT, | |
2235 | (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT); | |
2236 | ||
2237 | pwctl = read_c0_pwctl(); | |
2238 | pr_debug("PWCtl (0x%x): PWEn: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n", | |
2239 | pwctl, | |
2240 | (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT, | |
2241 | (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT, | |
2242 | (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT, | |
2243 | (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT); | |
2244 | } | |
2245 | ||
2246 | static void config_htw_params(void) | |
2247 | { | |
2248 | unsigned long pwfield, pwsize, ptei; | |
2249 | unsigned int config; | |
2250 | ||
2251 | /* | |
2252 | * We are using 2-level page tables, so we only need to | |
2253 | * setup GDW and PTW appropriately. UDW and MDW will remain 0. | |
2254 | * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to | |
2255 | * write values less than 0xc in these fields because the entire | |
2256 | * write will be dropped. As a result of which, we must preserve | |
2257 | * the original reset values and overwrite only what we really want. | |
2258 | */ | |
2259 | ||
2260 | pwfield = read_c0_pwfield(); | |
2261 | /* re-initialize the GDI field */ | |
2262 | pwfield &= ~MIPS_PWFIELD_GDI_MASK; | |
2263 | pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT; | |
2264 | /* re-initialize the PTI field including the even/odd bit */ | |
2265 | pwfield &= ~MIPS_PWFIELD_PTI_MASK; | |
2266 | pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT; | |
2267 | /* Set the PTEI right shift */ | |
2268 | ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT; | |
2269 | pwfield |= ptei; | |
2270 | write_c0_pwfield(pwfield); | |
2271 | /* Check whether the PTEI value is supported */ | |
2272 | back_to_back_c0_hazard(); | |
2273 | pwfield = read_c0_pwfield(); | |
2274 | if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT) | |
2275 | != ptei) { | |
2276 | pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled", | |
2277 | ptei); | |
2278 | /* | |
2279 | * Drop option to avoid HTW being enabled via another path | |
2280 | * (eg htw_reset()) | |
2281 | */ | |
2282 | current_cpu_data.options &= ~MIPS_CPU_HTW; | |
2283 | return; | |
2284 | } | |
2285 | ||
2286 | pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT; | |
2287 | pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT; | |
2288 | write_c0_pwsize(pwsize); | |
2289 | ||
2290 | /* Make sure everything is set before we enable the HTW */ | |
2291 | back_to_back_c0_hazard(); | |
2292 | ||
2293 | /* Enable HTW and disable the rest of the pwctl fields */ | |
2294 | config = 1 << MIPS_PWCTL_PWEN_SHIFT; | |
2295 | write_c0_pwctl(config); | |
2296 | pr_info("Hardware Page Table Walker enabled\n"); | |
2297 | ||
2298 | print_htw_config(); | |
2299 | } | |
2300 | ||
078a55fc | 2301 | void build_tlb_refill_handler(void) |
1da177e4 LT |
2302 | { |
2303 | /* | |
2304 | * The refill handler is generated per-CPU, multi-node systems | |
2305 | * may have local storage for it. The other handlers are only | |
2306 | * needed once. | |
2307 | */ | |
2308 | static int run_once = 0; | |
2309 | ||
a2c763e0 RB |
2310 | output_pgtable_bits_defines(); |
2311 | ||
1ec56329 DD |
2312 | #ifdef CONFIG_64BIT |
2313 | check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); | |
2314 | #endif | |
2315 | ||
10cc3529 | 2316 | switch (current_cpu_type()) { |
1da177e4 LT |
2317 | case CPU_R2000: |
2318 | case CPU_R3000: | |
2319 | case CPU_R3000A: | |
2320 | case CPU_R3081E: | |
2321 | case CPU_TX3912: | |
2322 | case CPU_TX3922: | |
2323 | case CPU_TX3927: | |
82622284 | 2324 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
8759934e HC |
2325 | if (cpu_has_local_ebase) |
2326 | build_r3000_tlb_refill_handler(); | |
1da177e4 | 2327 | if (!run_once) { |
8759934e HC |
2328 | if (!cpu_has_local_ebase) |
2329 | build_r3000_tlb_refill_handler(); | |
f4ae17aa | 2330 | build_setup_pgd(); |
1da177e4 LT |
2331 | build_r3000_tlb_load_handler(); |
2332 | build_r3000_tlb_store_handler(); | |
2333 | build_r3000_tlb_modify_handler(); | |
a3d9086b | 2334 | flush_tlb_handlers(); |
1da177e4 LT |
2335 | run_once++; |
2336 | } | |
82622284 DD |
2337 | #else |
2338 | panic("No R3000 TLB refill handler"); | |
2339 | #endif | |
1da177e4 LT |
2340 | break; |
2341 | ||
2342 | case CPU_R6000: | |
2343 | case CPU_R6000A: | |
2344 | panic("No R6000 TLB refill handler yet"); | |
2345 | break; | |
2346 | ||
2347 | case CPU_R8000: | |
2348 | panic("No R8000 TLB refill handler yet"); | |
2349 | break; | |
2350 | ||
2351 | default: | |
1da177e4 | 2352 | if (!run_once) { |
bf28607f | 2353 | scratch_reg = allocate_kscratch(); |
f4ae17aa | 2354 | build_setup_pgd(); |
1da177e4 LT |
2355 | build_r4000_tlb_load_handler(); |
2356 | build_r4000_tlb_store_handler(); | |
2357 | build_r4000_tlb_modify_handler(); | |
8759934e HC |
2358 | if (!cpu_has_local_ebase) |
2359 | build_r4000_tlb_refill_handler(); | |
a3d9086b | 2360 | flush_tlb_handlers(); |
1da177e4 LT |
2361 | run_once++; |
2362 | } | |
8759934e HC |
2363 | if (cpu_has_local_ebase) |
2364 | build_r4000_tlb_refill_handler(); | |
f1014d1b MC |
2365 | if (cpu_has_htw) |
2366 | config_htw_params(); | |
2367 | ||
1da177e4 LT |
2368 | } |
2369 | } |