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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Synthesize TLB refill handlers at runtime. | |
7 | * | |
70342287 RB |
8 | * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer |
9 | * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki | |
41c594ab | 10 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) |
fd062c84 | 11 | * Copyright (C) 2008, 2009 Cavium Networks, Inc. |
113c62d9 | 12 | * Copyright (C) 2011 MIPS Technologies, Inc. |
41c594ab RB |
13 | * |
14 | * ... and the days got worse and worse and now you see | |
15 | * I've gone completly out of my mind. | |
16 | * | |
17 | * They're coming to take me a away haha | |
18 | * they're coming to take me a away hoho hihi haha | |
19 | * to the funny farm where code is beautiful all the time ... | |
20 | * | |
21 | * (Condolences to Napoleon XIV) | |
1da177e4 LT |
22 | */ |
23 | ||
95affdda | 24 | #include <linux/bug.h> |
1da177e4 LT |
25 | #include <linux/kernel.h> |
26 | #include <linux/types.h> | |
631330f5 | 27 | #include <linux/smp.h> |
1da177e4 LT |
28 | #include <linux/string.h> |
29 | #include <linux/init.h> | |
3d8bfdd0 | 30 | #include <linux/cache.h> |
1da177e4 | 31 | |
d532f3d2 | 32 | #include <asm/mmu_context.h> |
3d8bfdd0 DD |
33 | #include <asm/cacheflush.h> |
34 | #include <asm/pgtable.h> | |
1da177e4 | 35 | #include <asm/war.h> |
3482d713 | 36 | #include <asm/uasm.h> |
b81947c6 | 37 | #include <asm/setup.h> |
e30ec452 | 38 | |
1ec56329 DD |
39 | /* |
40 | * TLB load/store/modify handlers. | |
41 | * | |
42 | * Only the fastpath gets synthesized at runtime, the slowpath for | |
43 | * do_page_fault remains normal asm. | |
44 | */ | |
45 | extern void tlb_do_page_fault_0(void); | |
46 | extern void tlb_do_page_fault_1(void); | |
47 | ||
bf28607f DD |
48 | struct work_registers { |
49 | int r1; | |
50 | int r2; | |
51 | int r3; | |
52 | }; | |
53 | ||
54 | struct tlb_reg_save { | |
55 | unsigned long a; | |
56 | unsigned long b; | |
57 | } ____cacheline_aligned_in_smp; | |
58 | ||
59 | static struct tlb_reg_save handler_reg_save[NR_CPUS]; | |
1ec56329 | 60 | |
aeffdbba | 61 | static inline int r45k_bvahwbug(void) |
1da177e4 LT |
62 | { |
63 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
64 | return 0; | |
65 | } | |
66 | ||
aeffdbba | 67 | static inline int r4k_250MHZhwbug(void) |
1da177e4 LT |
68 | { |
69 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
70 | return 0; | |
71 | } | |
72 | ||
aeffdbba | 73 | static inline int __maybe_unused bcm1250_m3_war(void) |
1da177e4 LT |
74 | { |
75 | return BCM1250_M3_WAR; | |
76 | } | |
77 | ||
aeffdbba | 78 | static inline int __maybe_unused r10000_llsc_war(void) |
1da177e4 LT |
79 | { |
80 | return R10000_LLSC_WAR; | |
81 | } | |
82 | ||
cc33ae43 DD |
83 | static int use_bbit_insns(void) |
84 | { | |
85 | switch (current_cpu_type()) { | |
86 | case CPU_CAVIUM_OCTEON: | |
87 | case CPU_CAVIUM_OCTEON_PLUS: | |
88 | case CPU_CAVIUM_OCTEON2: | |
89 | return 1; | |
90 | default: | |
91 | return 0; | |
92 | } | |
93 | } | |
94 | ||
2c8c53e2 DD |
95 | static int use_lwx_insns(void) |
96 | { | |
97 | switch (current_cpu_type()) { | |
98 | case CPU_CAVIUM_OCTEON2: | |
99 | return 1; | |
100 | default: | |
101 | return 0; | |
102 | } | |
103 | } | |
104 | #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \ | |
105 | CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 | |
106 | static bool scratchpad_available(void) | |
107 | { | |
108 | return true; | |
109 | } | |
110 | static int scratchpad_offset(int i) | |
111 | { | |
112 | /* | |
113 | * CVMSEG starts at address -32768 and extends for | |
114 | * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines. | |
115 | */ | |
116 | i += 1; /* Kernel use starts at the top and works down. */ | |
117 | return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768; | |
118 | } | |
119 | #else | |
120 | static bool scratchpad_available(void) | |
121 | { | |
122 | return false; | |
123 | } | |
124 | static int scratchpad_offset(int i) | |
125 | { | |
126 | BUG(); | |
e1c87d2a DD |
127 | /* Really unreachable, but evidently some GCC want this. */ |
128 | return 0; | |
2c8c53e2 DD |
129 | } |
130 | #endif | |
8df5beac MR |
131 | /* |
132 | * Found by experiment: At least some revisions of the 4kc throw under | |
133 | * some circumstances a machine check exception, triggered by invalid | |
134 | * values in the index register. Delaying the tlbp instruction until | |
135 | * after the next branch, plus adding an additional nop in front of | |
136 | * tlbwi/tlbwr avoids the invalid index register values. Nobody knows | |
137 | * why; it's not an issue caused by the core RTL. | |
138 | * | |
139 | */ | |
234fcd14 | 140 | static int __cpuinit m4kc_tlbp_war(void) |
8df5beac MR |
141 | { |
142 | return (current_cpu_data.processor_id & 0xffff00) == | |
143 | (PRID_COMP_MIPS | PRID_IMP_4KC); | |
144 | } | |
145 | ||
e30ec452 | 146 | /* Handle labels (which must be positive integers). */ |
1da177e4 | 147 | enum label_id { |
e30ec452 | 148 | label_second_part = 1, |
1da177e4 LT |
149 | label_leave, |
150 | label_vmalloc, | |
151 | label_vmalloc_done, | |
02a54177 RB |
152 | label_tlbw_hazard_0, |
153 | label_split = label_tlbw_hazard_0 + 8, | |
6dd9344c DD |
154 | label_tlbl_goaround1, |
155 | label_tlbl_goaround2, | |
1da177e4 LT |
156 | label_nopage_tlbl, |
157 | label_nopage_tlbs, | |
158 | label_nopage_tlbm, | |
159 | label_smp_pgtable_change, | |
160 | label_r3000_write_probe_fail, | |
1ec56329 | 161 | label_large_segbits_fault, |
aa1762f4 | 162 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
163 | label_tlb_huge_update, |
164 | #endif | |
1da177e4 LT |
165 | }; |
166 | ||
e30ec452 TS |
167 | UASM_L_LA(_second_part) |
168 | UASM_L_LA(_leave) | |
e30ec452 TS |
169 | UASM_L_LA(_vmalloc) |
170 | UASM_L_LA(_vmalloc_done) | |
02a54177 | 171 | /* _tlbw_hazard_x is handled differently. */ |
e30ec452 | 172 | UASM_L_LA(_split) |
6dd9344c DD |
173 | UASM_L_LA(_tlbl_goaround1) |
174 | UASM_L_LA(_tlbl_goaround2) | |
e30ec452 TS |
175 | UASM_L_LA(_nopage_tlbl) |
176 | UASM_L_LA(_nopage_tlbs) | |
177 | UASM_L_LA(_nopage_tlbm) | |
178 | UASM_L_LA(_smp_pgtable_change) | |
179 | UASM_L_LA(_r3000_write_probe_fail) | |
1ec56329 | 180 | UASM_L_LA(_large_segbits_fault) |
aa1762f4 | 181 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
182 | UASM_L_LA(_tlb_huge_update) |
183 | #endif | |
656be92f | 184 | |
02a54177 RB |
185 | static int __cpuinitdata hazard_instance; |
186 | ||
f151f3b9 KC |
187 | static void __cpuinit uasm_bgezl_hazard(u32 **p, |
188 | struct uasm_reloc **r, | |
189 | int instance) | |
02a54177 RB |
190 | { |
191 | switch (instance) { | |
192 | case 0 ... 7: | |
193 | uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance); | |
194 | return; | |
195 | default: | |
196 | BUG(); | |
197 | } | |
198 | } | |
199 | ||
f151f3b9 KC |
200 | static void __cpuinit uasm_bgezl_label(struct uasm_label **l, |
201 | u32 **p, | |
202 | int instance) | |
02a54177 RB |
203 | { |
204 | switch (instance) { | |
205 | case 0 ... 7: | |
206 | uasm_build_label(l, *p, label_tlbw_hazard_0 + instance); | |
207 | break; | |
208 | default: | |
209 | BUG(); | |
210 | } | |
211 | } | |
212 | ||
92b1e6a6 | 213 | /* |
a2c763e0 RB |
214 | * pgtable bits are assigned dynamically depending on processor feature |
215 | * and statically based on kernel configuration. This spits out the actual | |
70342287 | 216 | * values the kernel is using. Required to make sense from disassembled |
a2c763e0 | 217 | * TLB exception handlers. |
92b1e6a6 | 218 | */ |
a2c763e0 RB |
219 | static void output_pgtable_bits_defines(void) |
220 | { | |
221 | #define pr_define(fmt, ...) \ | |
222 | pr_debug("#define " fmt, ##__VA_ARGS__) | |
223 | ||
224 | pr_debug("#include <asm/asm.h>\n"); | |
225 | pr_debug("#include <asm/regdef.h>\n"); | |
226 | pr_debug("\n"); | |
227 | ||
228 | pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT); | |
229 | pr_define("_PAGE_READ_SHIFT %d\n", _PAGE_READ_SHIFT); | |
230 | pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT); | |
231 | pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT); | |
232 | pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT); | |
970d032f | 233 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
a2c763e0 | 234 | pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT); |
970d032f | 235 | pr_define("_PAGE_SPLITTING_SHIFT %d\n", _PAGE_SPLITTING_SHIFT); |
a2c763e0 RB |
236 | #endif |
237 | if (cpu_has_rixi) { | |
238 | #ifdef _PAGE_NO_EXEC_SHIFT | |
239 | pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT); | |
240 | #endif | |
241 | #ifdef _PAGE_NO_READ_SHIFT | |
242 | pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT); | |
243 | #endif | |
244 | } | |
245 | pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT); | |
246 | pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT); | |
247 | pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT); | |
248 | pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT); | |
249 | pr_debug("\n"); | |
250 | } | |
251 | ||
252 | static inline void dump_handler(const char *symbol, const u32 *handler, int count) | |
92b1e6a6 FBH |
253 | { |
254 | int i; | |
255 | ||
a2c763e0 RB |
256 | pr_debug("LEAF(%s)\n", symbol); |
257 | ||
92b1e6a6 FBH |
258 | pr_debug("\t.set push\n"); |
259 | pr_debug("\t.set noreorder\n"); | |
260 | ||
261 | for (i = 0; i < count; i++) | |
a2c763e0 | 262 | pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]); |
92b1e6a6 | 263 | |
a2c763e0 RB |
264 | pr_debug("\t.set\tpop\n"); |
265 | ||
266 | pr_debug("\tEND(%s)\n", symbol); | |
92b1e6a6 FBH |
267 | } |
268 | ||
1da177e4 LT |
269 | /* The only general purpose registers allowed in TLB handlers. */ |
270 | #define K0 26 | |
271 | #define K1 27 | |
272 | ||
273 | /* Some CP0 registers */ | |
41c594ab RB |
274 | #define C0_INDEX 0, 0 |
275 | #define C0_ENTRYLO0 2, 0 | |
276 | #define C0_TCBIND 2, 2 | |
277 | #define C0_ENTRYLO1 3, 0 | |
278 | #define C0_CONTEXT 4, 0 | |
fd062c84 | 279 | #define C0_PAGEMASK 5, 0 |
41c594ab RB |
280 | #define C0_BADVADDR 8, 0 |
281 | #define C0_ENTRYHI 10, 0 | |
282 | #define C0_EPC 14, 0 | |
283 | #define C0_XCONTEXT 20, 0 | |
1da177e4 | 284 | |
875d43e7 | 285 | #ifdef CONFIG_64BIT |
e30ec452 | 286 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT) |
1da177e4 | 287 | #else |
e30ec452 | 288 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT) |
1da177e4 LT |
289 | #endif |
290 | ||
291 | /* The worst case length of the handler is around 18 instructions for | |
292 | * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. | |
293 | * Maximum space available is 32 instructions for R3000 and 64 | |
294 | * instructions for R4000. | |
295 | * | |
296 | * We deliberately chose a buffer size of 128, so we won't scribble | |
297 | * over anything important on overflow before we panic. | |
298 | */ | |
234fcd14 | 299 | static u32 tlb_handler[128] __cpuinitdata; |
1da177e4 LT |
300 | |
301 | /* simply assume worst case size for labels and relocs */ | |
234fcd14 RB |
302 | static struct uasm_label labels[128] __cpuinitdata; |
303 | static struct uasm_reloc relocs[128] __cpuinitdata; | |
1da177e4 | 304 | |
1ec56329 DD |
305 | #ifdef CONFIG_64BIT |
306 | static int check_for_high_segbits __cpuinitdata; | |
307 | #endif | |
308 | ||
d532f3d2 SH |
309 | static void __cpuinit insn_fixup(unsigned int **start, unsigned int **stop, |
310 | unsigned int i_const) | |
311 | { | |
f6b06d93 | 312 | unsigned int **p; |
d532f3d2 SH |
313 | |
314 | for (p = start; p < stop; p++) { | |
f6b06d93 SH |
315 | #ifndef CONFIG_CPU_MICROMIPS |
316 | unsigned int *ip; | |
317 | ||
d532f3d2 SH |
318 | ip = *p; |
319 | *ip = (*ip & 0xffff0000) | i_const; | |
f6b06d93 SH |
320 | #else |
321 | unsigned short *ip; | |
322 | ||
323 | ip = ((unsigned short *)((unsigned int)*p - 1)); | |
324 | if ((*ip & 0xf000) == 0x4000) { | |
325 | *ip &= 0xfff1; | |
326 | *ip |= (i_const << 1); | |
327 | } else if ((*ip & 0xf000) == 0x6000) { | |
328 | *ip &= 0xfff1; | |
329 | *ip |= ((i_const >> 2) << 1); | |
330 | } else { | |
331 | ip++; | |
332 | *ip = i_const; | |
333 | } | |
334 | #endif | |
335 | local_flush_icache_range((unsigned long)ip, | |
336 | (unsigned long)ip + sizeof(*ip)); | |
d532f3d2 | 337 | } |
d532f3d2 SH |
338 | } |
339 | ||
340 | #define asid_insn_fixup(section, const) \ | |
341 | do { \ | |
342 | extern unsigned int *__start_ ## section; \ | |
343 | extern unsigned int *__stop_ ## section; \ | |
344 | insn_fixup(&__start_ ## section, &__stop_ ## section, const); \ | |
345 | } while(0) | |
346 | ||
347 | /* | |
348 | * Caller is assumed to flush the caches before the first context switch. | |
349 | */ | |
350 | static void __cpuinit setup_asid(unsigned int inc, unsigned int mask, | |
351 | unsigned int version_mask, | |
352 | unsigned int first_version) | |
353 | { | |
354 | extern asmlinkage void handle_ri_rdhwr_vivt(void); | |
355 | unsigned long *vivt_exc; | |
356 | ||
f6b06d93 SH |
357 | #ifdef CONFIG_CPU_MICROMIPS |
358 | /* | |
359 | * Worst case optimised microMIPS addiu instructions support | |
360 | * only a 3-bit immediate value. | |
361 | */ | |
362 | if(inc > 7) | |
363 | panic("Invalid ASID increment value!"); | |
364 | #endif | |
d532f3d2 SH |
365 | asid_insn_fixup(__asid_inc, inc); |
366 | asid_insn_fixup(__asid_mask, mask); | |
367 | asid_insn_fixup(__asid_version_mask, version_mask); | |
368 | asid_insn_fixup(__asid_first_version, first_version); | |
369 | ||
370 | /* Patch up the 'handle_ri_rdhwr_vivt' handler. */ | |
371 | vivt_exc = (unsigned long *) &handle_ri_rdhwr_vivt; | |
f6b06d93 SH |
372 | #ifdef CONFIG_CPU_MICROMIPS |
373 | vivt_exc = (unsigned long *)((unsigned long) vivt_exc - 1); | |
374 | #endif | |
d532f3d2 SH |
375 | vivt_exc++; |
376 | *vivt_exc = (*vivt_exc & ~mask) | mask; | |
377 | ||
378 | current_cpu_data.asid_cache = first_version; | |
379 | } | |
380 | ||
2c8c53e2 | 381 | static int check_for_high_segbits __cpuinitdata; |
3d8bfdd0 DD |
382 | |
383 | static unsigned int kscratch_used_mask __cpuinitdata; | |
384 | ||
385 | static int __cpuinit allocate_kscratch(void) | |
386 | { | |
387 | int r; | |
388 | unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask; | |
389 | ||
390 | r = ffs(a); | |
391 | ||
392 | if (r == 0) | |
393 | return -1; | |
394 | ||
395 | r--; /* make it zero based */ | |
396 | ||
397 | kscratch_used_mask |= (1 << r); | |
398 | ||
399 | return r; | |
400 | } | |
401 | ||
2c8c53e2 | 402 | static int scratch_reg __cpuinitdata; |
3d8bfdd0 | 403 | static int pgd_reg __cpuinitdata; |
2c8c53e2 DD |
404 | enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch}; |
405 | ||
bf28607f DD |
406 | static struct work_registers __cpuinit build_get_work_registers(u32 **p) |
407 | { | |
408 | struct work_registers r; | |
409 | ||
410 | int smp_processor_id_reg; | |
411 | int smp_processor_id_sel; | |
412 | int smp_processor_id_shift; | |
413 | ||
414 | if (scratch_reg > 0) { | |
415 | /* Save in CPU local C0_KScratch? */ | |
416 | UASM_i_MTC0(p, 1, 31, scratch_reg); | |
417 | r.r1 = K0; | |
418 | r.r2 = K1; | |
419 | r.r3 = 1; | |
420 | return r; | |
421 | } | |
422 | ||
423 | if (num_possible_cpus() > 1) { | |
424 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT | |
425 | smp_processor_id_shift = 51; | |
426 | smp_processor_id_reg = 20; /* XContext */ | |
427 | smp_processor_id_sel = 0; | |
428 | #else | |
429 | # ifdef CONFIG_32BIT | |
430 | smp_processor_id_shift = 25; | |
431 | smp_processor_id_reg = 4; /* Context */ | |
432 | smp_processor_id_sel = 0; | |
433 | # endif | |
434 | # ifdef CONFIG_64BIT | |
435 | smp_processor_id_shift = 26; | |
436 | smp_processor_id_reg = 4; /* Context */ | |
437 | smp_processor_id_sel = 0; | |
438 | # endif | |
439 | #endif | |
440 | /* Get smp_processor_id */ | |
441 | UASM_i_MFC0(p, K0, smp_processor_id_reg, smp_processor_id_sel); | |
442 | UASM_i_SRL_SAFE(p, K0, K0, smp_processor_id_shift); | |
443 | ||
444 | /* handler_reg_save index in K0 */ | |
445 | UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save))); | |
446 | ||
447 | UASM_i_LA(p, K1, (long)&handler_reg_save); | |
448 | UASM_i_ADDU(p, K0, K0, K1); | |
449 | } else { | |
450 | UASM_i_LA(p, K0, (long)&handler_reg_save); | |
451 | } | |
452 | /* K0 now points to save area, save $1 and $2 */ | |
453 | UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0); | |
454 | UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0); | |
455 | ||
456 | r.r1 = K1; | |
457 | r.r2 = 1; | |
458 | r.r3 = 2; | |
459 | return r; | |
460 | } | |
461 | ||
462 | static void __cpuinit build_restore_work_registers(u32 **p) | |
463 | { | |
464 | if (scratch_reg > 0) { | |
465 | UASM_i_MFC0(p, 1, 31, scratch_reg); | |
466 | return; | |
467 | } | |
468 | /* K0 already points to save area, restore $1 and $2 */ | |
469 | UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0); | |
470 | UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0); | |
471 | } | |
472 | ||
2c8c53e2 | 473 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
3d8bfdd0 | 474 | |
82622284 DD |
475 | /* |
476 | * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current, | |
477 | * we cannot do r3000 under these circumstances. | |
3d8bfdd0 DD |
478 | * |
479 | * Declare pgd_current here instead of including mmu_context.h to avoid type | |
480 | * conflicts for tlbmiss_handler_setup_pgd | |
82622284 | 481 | */ |
3d8bfdd0 | 482 | extern unsigned long pgd_current[]; |
82622284 | 483 | |
1da177e4 LT |
484 | /* |
485 | * The R3000 TLB handler is simple. | |
486 | */ | |
234fcd14 | 487 | static void __cpuinit build_r3000_tlb_refill_handler(void) |
1da177e4 LT |
488 | { |
489 | long pgdc = (long)pgd_current; | |
490 | u32 *p; | |
491 | ||
492 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
493 | p = tlb_handler; | |
494 | ||
e30ec452 TS |
495 | uasm_i_mfc0(&p, K0, C0_BADVADDR); |
496 | uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */ | |
497 | uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1); | |
498 | uasm_i_srl(&p, K0, K0, 22); /* load delay */ | |
499 | uasm_i_sll(&p, K0, K0, 2); | |
500 | uasm_i_addu(&p, K1, K1, K0); | |
501 | uasm_i_mfc0(&p, K0, C0_CONTEXT); | |
502 | uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */ | |
503 | uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */ | |
504 | uasm_i_addu(&p, K1, K1, K0); | |
505 | uasm_i_lw(&p, K0, 0, K1); | |
506 | uasm_i_nop(&p); /* load delay */ | |
507 | uasm_i_mtc0(&p, K0, C0_ENTRYLO0); | |
508 | uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ | |
509 | uasm_i_tlbwr(&p); /* cp0 delay */ | |
510 | uasm_i_jr(&p, K1); | |
511 | uasm_i_rfe(&p); /* branch delay */ | |
1da177e4 LT |
512 | |
513 | if (p > tlb_handler + 32) | |
514 | panic("TLB refill handler space exceeded"); | |
515 | ||
e30ec452 TS |
516 | pr_debug("Wrote TLB refill handler (%u instructions).\n", |
517 | (unsigned int)(p - tlb_handler)); | |
1da177e4 | 518 | |
91b05e67 | 519 | memcpy((void *)ebase, tlb_handler, 0x80); |
92b1e6a6 | 520 | |
a2c763e0 | 521 | dump_handler("r3000_tlb_refill", (u32 *)ebase, 32); |
1da177e4 | 522 | } |
82622284 | 523 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ |
1da177e4 LT |
524 | |
525 | /* | |
526 | * The R4000 TLB handler is much more complicated. We have two | |
527 | * consecutive handler areas with 32 instructions space each. | |
528 | * Since they aren't used at the same time, we can overflow in the | |
529 | * other one.To keep things simple, we first assume linear space, | |
530 | * then we relocate it to the final handler layout as needed. | |
531 | */ | |
234fcd14 | 532 | static u32 final_handler[64] __cpuinitdata; |
1da177e4 LT |
533 | |
534 | /* | |
535 | * Hazards | |
536 | * | |
537 | * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: | |
538 | * 2. A timing hazard exists for the TLBP instruction. | |
539 | * | |
70342287 RB |
540 | * stalling_instruction |
541 | * TLBP | |
1da177e4 LT |
542 | * |
543 | * The JTLB is being read for the TLBP throughout the stall generated by the | |
544 | * previous instruction. This is not really correct as the stalling instruction | |
545 | * can modify the address used to access the JTLB. The failure symptom is that | |
546 | * the TLBP instruction will use an address created for the stalling instruction | |
547 | * and not the address held in C0_ENHI and thus report the wrong results. | |
548 | * | |
549 | * The software work-around is to not allow the instruction preceding the TLBP | |
550 | * to stall - make it an NOP or some other instruction guaranteed not to stall. | |
551 | * | |
70342287 | 552 | * Errata 2 will not be fixed. This errata is also on the R5000. |
1da177e4 LT |
553 | * |
554 | * As if we MIPS hackers wouldn't know how to nop pipelines happy ... | |
555 | */ | |
234fcd14 | 556 | static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p) |
1da177e4 | 557 | { |
10cc3529 | 558 | switch (current_cpu_type()) { |
326e2e1a | 559 | /* Found by experiment: R4600 v2.0/R4700 needs this, too. */ |
f5b4d956 | 560 | case CPU_R4600: |
326e2e1a | 561 | case CPU_R4700: |
1da177e4 | 562 | case CPU_R5000: |
1da177e4 | 563 | case CPU_NEVADA: |
e30ec452 TS |
564 | uasm_i_nop(p); |
565 | uasm_i_tlbp(p); | |
1da177e4 LT |
566 | break; |
567 | ||
568 | default: | |
e30ec452 | 569 | uasm_i_tlbp(p); |
1da177e4 LT |
570 | break; |
571 | } | |
572 | } | |
573 | ||
574 | /* | |
575 | * Write random or indexed TLB entry, and care about the hazards from | |
25985edc | 576 | * the preceding mtc0 and for the following eret. |
1da177e4 LT |
577 | */ |
578 | enum tlb_write_entry { tlb_random, tlb_indexed }; | |
579 | ||
234fcd14 | 580 | static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, |
e30ec452 | 581 | struct uasm_reloc **r, |
1da177e4 LT |
582 | enum tlb_write_entry wmode) |
583 | { | |
584 | void(*tlbw)(u32 **) = NULL; | |
585 | ||
586 | switch (wmode) { | |
e30ec452 TS |
587 | case tlb_random: tlbw = uasm_i_tlbwr; break; |
588 | case tlb_indexed: tlbw = uasm_i_tlbwi; break; | |
1da177e4 LT |
589 | } |
590 | ||
161548bf | 591 | if (cpu_has_mips_r2) { |
625c0a21 SH |
592 | /* |
593 | * The architecture spec says an ehb is required here, | |
594 | * but a number of cores do not have the hazard and | |
595 | * using an ehb causes an expensive pipeline stall. | |
596 | */ | |
597 | switch (current_cpu_type()) { | |
598 | case CPU_M14KC: | |
599 | case CPU_74K: | |
600 | break; | |
601 | ||
602 | default: | |
41f0e4d0 | 603 | uasm_i_ehb(p); |
625c0a21 SH |
604 | break; |
605 | } | |
161548bf RB |
606 | tlbw(p); |
607 | return; | |
608 | } | |
609 | ||
10cc3529 | 610 | switch (current_cpu_type()) { |
1da177e4 LT |
611 | case CPU_R4000PC: |
612 | case CPU_R4000SC: | |
613 | case CPU_R4000MC: | |
614 | case CPU_R4400PC: | |
615 | case CPU_R4400SC: | |
616 | case CPU_R4400MC: | |
617 | /* | |
618 | * This branch uses up a mtc0 hazard nop slot and saves | |
619 | * two nops after the tlbw instruction. | |
620 | */ | |
02a54177 | 621 | uasm_bgezl_hazard(p, r, hazard_instance); |
1da177e4 | 622 | tlbw(p); |
02a54177 RB |
623 | uasm_bgezl_label(l, p, hazard_instance); |
624 | hazard_instance++; | |
e30ec452 | 625 | uasm_i_nop(p); |
1da177e4 LT |
626 | break; |
627 | ||
628 | case CPU_R4600: | |
629 | case CPU_R4700: | |
e30ec452 | 630 | uasm_i_nop(p); |
2c93e12c | 631 | tlbw(p); |
e30ec452 | 632 | uasm_i_nop(p); |
2c93e12c MR |
633 | break; |
634 | ||
359187d6 | 635 | case CPU_R5000: |
359187d6 RB |
636 | case CPU_NEVADA: |
637 | uasm_i_nop(p); /* QED specifies 2 nops hazard */ | |
638 | uasm_i_nop(p); /* QED specifies 2 nops hazard */ | |
639 | tlbw(p); | |
640 | break; | |
641 | ||
2c93e12c | 642 | case CPU_R4300: |
1da177e4 LT |
643 | case CPU_5KC: |
644 | case CPU_TX49XX: | |
bdf21b18 | 645 | case CPU_PR4450: |
efa0f81c | 646 | case CPU_XLR: |
e30ec452 | 647 | uasm_i_nop(p); |
1da177e4 LT |
648 | tlbw(p); |
649 | break; | |
650 | ||
651 | case CPU_R10000: | |
652 | case CPU_R12000: | |
44d921b2 | 653 | case CPU_R14000: |
1da177e4 | 654 | case CPU_4KC: |
b1ec4c8e | 655 | case CPU_4KEC: |
113c62d9 | 656 | case CPU_M14KC: |
f8fa4811 | 657 | case CPU_M14KEC: |
1da177e4 | 658 | case CPU_SB1: |
93ce2f52 | 659 | case CPU_SB1A: |
1da177e4 LT |
660 | case CPU_4KSC: |
661 | case CPU_20KC: | |
662 | case CPU_25KF: | |
602977b0 KC |
663 | case CPU_BMIPS32: |
664 | case CPU_BMIPS3300: | |
665 | case CPU_BMIPS4350: | |
666 | case CPU_BMIPS4380: | |
667 | case CPU_BMIPS5000: | |
2a21c730 | 668 | case CPU_LOONGSON2: |
a644b277 | 669 | case CPU_R5500: |
8df5beac | 670 | if (m4kc_tlbp_war()) |
e30ec452 | 671 | uasm_i_nop(p); |
2f794d09 | 672 | case CPU_ALCHEMY: |
1da177e4 LT |
673 | tlbw(p); |
674 | break; | |
675 | ||
1da177e4 | 676 | case CPU_RM7000: |
e30ec452 TS |
677 | uasm_i_nop(p); |
678 | uasm_i_nop(p); | |
679 | uasm_i_nop(p); | |
680 | uasm_i_nop(p); | |
1da177e4 LT |
681 | tlbw(p); |
682 | break; | |
683 | ||
1da177e4 LT |
684 | case CPU_VR4111: |
685 | case CPU_VR4121: | |
686 | case CPU_VR4122: | |
687 | case CPU_VR4181: | |
688 | case CPU_VR4181A: | |
e30ec452 TS |
689 | uasm_i_nop(p); |
690 | uasm_i_nop(p); | |
1da177e4 | 691 | tlbw(p); |
e30ec452 TS |
692 | uasm_i_nop(p); |
693 | uasm_i_nop(p); | |
1da177e4 LT |
694 | break; |
695 | ||
696 | case CPU_VR4131: | |
697 | case CPU_VR4133: | |
7623debf | 698 | case CPU_R5432: |
e30ec452 TS |
699 | uasm_i_nop(p); |
700 | uasm_i_nop(p); | |
1da177e4 LT |
701 | tlbw(p); |
702 | break; | |
703 | ||
83ccf69d LPC |
704 | case CPU_JZRISC: |
705 | tlbw(p); | |
706 | uasm_i_nop(p); | |
707 | break; | |
708 | ||
1da177e4 LT |
709 | default: |
710 | panic("No TLB refill handler yet (CPU type: %d)", | |
711 | current_cpu_data.cputype); | |
712 | break; | |
713 | } | |
714 | } | |
715 | ||
6dd9344c DD |
716 | static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p, |
717 | unsigned int reg) | |
fd062c84 | 718 | { |
05857c64 | 719 | if (cpu_has_rixi) { |
748e787e | 720 | UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL)); |
6dd9344c DD |
721 | } else { |
722 | #ifdef CONFIG_64BIT_PHYS_ADDR | |
3be6022c | 723 | uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL)); |
6dd9344c DD |
724 | #else |
725 | UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL)); | |
726 | #endif | |
727 | } | |
728 | } | |
fd062c84 | 729 | |
aa1762f4 | 730 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 | 731 | |
6dd9344c DD |
732 | static __cpuinit void build_restore_pagemask(u32 **p, |
733 | struct uasm_reloc **r, | |
734 | unsigned int tmp, | |
2c8c53e2 DD |
735 | enum label_id lid, |
736 | int restore_scratch) | |
6dd9344c | 737 | { |
2c8c53e2 DD |
738 | if (restore_scratch) { |
739 | /* Reset default page size */ | |
740 | if (PM_DEFAULT_MASK >> 16) { | |
741 | uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); | |
742 | uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); | |
743 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
744 | uasm_il_b(p, r, lid); | |
745 | } else if (PM_DEFAULT_MASK) { | |
746 | uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); | |
747 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
748 | uasm_il_b(p, r, lid); | |
749 | } else { | |
750 | uasm_i_mtc0(p, 0, C0_PAGEMASK); | |
751 | uasm_il_b(p, r, lid); | |
752 | } | |
753 | if (scratch_reg > 0) | |
754 | UASM_i_MFC0(p, 1, 31, scratch_reg); | |
755 | else | |
756 | UASM_i_LW(p, 1, scratchpad_offset(0), 0); | |
fd062c84 | 757 | } else { |
2c8c53e2 DD |
758 | /* Reset default page size */ |
759 | if (PM_DEFAULT_MASK >> 16) { | |
760 | uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); | |
761 | uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); | |
762 | uasm_il_b(p, r, lid); | |
763 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
764 | } else if (PM_DEFAULT_MASK) { | |
765 | uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); | |
766 | uasm_il_b(p, r, lid); | |
767 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
768 | } else { | |
769 | uasm_il_b(p, r, lid); | |
770 | uasm_i_mtc0(p, 0, C0_PAGEMASK); | |
771 | } | |
fd062c84 DD |
772 | } |
773 | } | |
774 | ||
6dd9344c DD |
775 | static __cpuinit void build_huge_tlb_write_entry(u32 **p, |
776 | struct uasm_label **l, | |
777 | struct uasm_reloc **r, | |
778 | unsigned int tmp, | |
2c8c53e2 DD |
779 | enum tlb_write_entry wmode, |
780 | int restore_scratch) | |
6dd9344c DD |
781 | { |
782 | /* Set huge page tlb entry size */ | |
783 | uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16); | |
784 | uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff); | |
785 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
786 | ||
787 | build_tlb_write_entry(p, l, r, wmode); | |
788 | ||
2c8c53e2 | 789 | build_restore_pagemask(p, r, tmp, label_leave, restore_scratch); |
6dd9344c DD |
790 | } |
791 | ||
fd062c84 DD |
792 | /* |
793 | * Check if Huge PTE is present, if so then jump to LABEL. | |
794 | */ | |
795 | static void __cpuinit | |
796 | build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp, | |
797 | unsigned int pmd, int lid) | |
798 | { | |
799 | UASM_i_LW(p, tmp, 0, pmd); | |
cc33ae43 DD |
800 | if (use_bbit_insns()) { |
801 | uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid); | |
802 | } else { | |
803 | uasm_i_andi(p, tmp, tmp, _PAGE_HUGE); | |
804 | uasm_il_bnez(p, r, tmp, lid); | |
805 | } | |
fd062c84 DD |
806 | } |
807 | ||
808 | static __cpuinit void build_huge_update_entries(u32 **p, | |
809 | unsigned int pte, | |
810 | unsigned int tmp) | |
811 | { | |
812 | int small_sequence; | |
813 | ||
814 | /* | |
815 | * A huge PTE describes an area the size of the | |
816 | * configured huge page size. This is twice the | |
817 | * of the large TLB entry size we intend to use. | |
818 | * A TLB entry half the size of the configured | |
819 | * huge page size is configured into entrylo0 | |
820 | * and entrylo1 to cover the contiguous huge PTE | |
821 | * address space. | |
822 | */ | |
823 | small_sequence = (HPAGE_SIZE >> 7) < 0x10000; | |
824 | ||
70342287 | 825 | /* We can clobber tmp. It isn't used after this.*/ |
fd062c84 DD |
826 | if (!small_sequence) |
827 | uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16)); | |
828 | ||
6dd9344c | 829 | build_convert_pte_to_entrylo(p, pte); |
9b8c3891 | 830 | UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */ |
fd062c84 DD |
831 | /* convert to entrylo1 */ |
832 | if (small_sequence) | |
833 | UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7); | |
834 | else | |
835 | UASM_i_ADDU(p, pte, pte, tmp); | |
836 | ||
9b8c3891 | 837 | UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */ |
fd062c84 DD |
838 | } |
839 | ||
840 | static __cpuinit void build_huge_handler_tail(u32 **p, | |
841 | struct uasm_reloc **r, | |
842 | struct uasm_label **l, | |
843 | unsigned int pte, | |
844 | unsigned int ptr) | |
845 | { | |
846 | #ifdef CONFIG_SMP | |
847 | UASM_i_SC(p, pte, 0, ptr); | |
848 | uasm_il_beqz(p, r, pte, label_tlb_huge_update); | |
849 | UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */ | |
850 | #else | |
851 | UASM_i_SW(p, pte, 0, ptr); | |
852 | #endif | |
853 | build_huge_update_entries(p, pte, ptr); | |
2c8c53e2 | 854 | build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0); |
fd062c84 | 855 | } |
aa1762f4 | 856 | #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ |
fd062c84 | 857 | |
875d43e7 | 858 | #ifdef CONFIG_64BIT |
1da177e4 LT |
859 | /* |
860 | * TMP and PTR are scratch. | |
861 | * TMP will be clobbered, PTR will hold the pmd entry. | |
862 | */ | |
234fcd14 | 863 | static void __cpuinit |
e30ec452 | 864 | build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
1da177e4 LT |
865 | unsigned int tmp, unsigned int ptr) |
866 | { | |
82622284 | 867 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
1da177e4 | 868 | long pgdc = (long)pgd_current; |
82622284 | 869 | #endif |
1da177e4 LT |
870 | /* |
871 | * The vmalloc handling is not in the hotpath. | |
872 | */ | |
e30ec452 | 873 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); |
1ec56329 DD |
874 | |
875 | if (check_for_high_segbits) { | |
876 | /* | |
877 | * The kernel currently implicitely assumes that the | |
878 | * MIPS SEGBITS parameter for the processor is | |
879 | * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never | |
880 | * allocate virtual addresses outside the maximum | |
881 | * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But | |
882 | * that doesn't prevent user code from accessing the | |
883 | * higher xuseg addresses. Here, we make sure that | |
884 | * everything but the lower xuseg addresses goes down | |
885 | * the module_alloc/vmalloc path. | |
886 | */ | |
887 | uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); | |
888 | uasm_il_bnez(p, r, ptr, label_vmalloc); | |
889 | } else { | |
890 | uasm_il_bltz(p, r, tmp, label_vmalloc); | |
891 | } | |
e30ec452 | 892 | /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ |
1da177e4 | 893 | |
82622284 | 894 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
3d8bfdd0 DD |
895 | if (pgd_reg != -1) { |
896 | /* pgd is in pgd_reg */ | |
897 | UASM_i_MFC0(p, ptr, 31, pgd_reg); | |
898 | } else { | |
899 | /* | |
900 | * &pgd << 11 stored in CONTEXT [23..63]. | |
901 | */ | |
902 | UASM_i_MFC0(p, ptr, C0_CONTEXT); | |
903 | ||
904 | /* Clear lower 23 bits of context. */ | |
905 | uasm_i_dins(p, ptr, 0, 0, 23); | |
906 | ||
70342287 | 907 | /* 1 0 1 0 1 << 6 xkphys cached */ |
3d8bfdd0 DD |
908 | uasm_i_ori(p, ptr, ptr, 0x540); |
909 | uasm_i_drotr(p, ptr, ptr, 11); | |
910 | } | |
82622284 | 911 | #elif defined(CONFIG_SMP) |
70342287 | 912 | # ifdef CONFIG_MIPS_MT_SMTC |
41c594ab RB |
913 | /* |
914 | * SMTC uses TCBind value as "CPU" index | |
915 | */ | |
e30ec452 | 916 | uasm_i_mfc0(p, ptr, C0_TCBIND); |
3be6022c | 917 | uasm_i_dsrl_safe(p, ptr, ptr, 19); |
41c594ab | 918 | # else |
1da177e4 | 919 | /* |
1b3a6e97 | 920 | * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 |
1da177e4 LT |
921 | * stored in CONTEXT. |
922 | */ | |
e30ec452 | 923 | uasm_i_dmfc0(p, ptr, C0_CONTEXT); |
3be6022c | 924 | uasm_i_dsrl_safe(p, ptr, ptr, 23); |
82622284 | 925 | # endif |
e30ec452 TS |
926 | UASM_i_LA_mostly(p, tmp, pgdc); |
927 | uasm_i_daddu(p, ptr, ptr, tmp); | |
928 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); | |
929 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1da177e4 | 930 | #else |
e30ec452 TS |
931 | UASM_i_LA_mostly(p, ptr, pgdc); |
932 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1da177e4 LT |
933 | #endif |
934 | ||
e30ec452 | 935 | uasm_l_vmalloc_done(l, *p); |
242954b5 | 936 | |
3be6022c DD |
937 | /* get pgd offset in bytes */ |
938 | uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3); | |
e30ec452 TS |
939 | |
940 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); | |
941 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
325f8a0a | 942 | #ifndef __PAGETABLE_PMD_FOLDED |
e30ec452 TS |
943 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ |
944 | uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ | |
3be6022c | 945 | uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ |
e30ec452 TS |
946 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); |
947 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ | |
325f8a0a | 948 | #endif |
1da177e4 LT |
949 | } |
950 | ||
951 | /* | |
952 | * BVADDR is the faulting address, PTR is scratch. | |
953 | * PTR will hold the pgd for vmalloc. | |
954 | */ | |
234fcd14 | 955 | static void __cpuinit |
e30ec452 | 956 | build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
1ec56329 DD |
957 | unsigned int bvaddr, unsigned int ptr, |
958 | enum vmalloc64_mode mode) | |
1da177e4 LT |
959 | { |
960 | long swpd = (long)swapper_pg_dir; | |
1ec56329 DD |
961 | int single_insn_swpd; |
962 | int did_vmalloc_branch = 0; | |
963 | ||
964 | single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd); | |
1da177e4 | 965 | |
e30ec452 | 966 | uasm_l_vmalloc(l, *p); |
1da177e4 | 967 | |
2c8c53e2 | 968 | if (mode != not_refill && check_for_high_segbits) { |
1ec56329 DD |
969 | if (single_insn_swpd) { |
970 | uasm_il_bltz(p, r, bvaddr, label_vmalloc_done); | |
971 | uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); | |
972 | did_vmalloc_branch = 1; | |
973 | /* fall through */ | |
974 | } else { | |
975 | uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault); | |
976 | } | |
977 | } | |
978 | if (!did_vmalloc_branch) { | |
979 | if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) { | |
980 | uasm_il_b(p, r, label_vmalloc_done); | |
981 | uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); | |
982 | } else { | |
983 | UASM_i_LA_mostly(p, ptr, swpd); | |
984 | uasm_il_b(p, r, label_vmalloc_done); | |
985 | if (uasm_in_compat_space_p(swpd)) | |
986 | uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd)); | |
987 | else | |
988 | uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); | |
989 | } | |
990 | } | |
2c8c53e2 | 991 | if (mode != not_refill && check_for_high_segbits) { |
1ec56329 DD |
992 | uasm_l_large_segbits_fault(l, *p); |
993 | /* | |
994 | * We get here if we are an xsseg address, or if we are | |
995 | * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary. | |
996 | * | |
997 | * Ignoring xsseg (assume disabled so would generate | |
998 | * (address errors?), the only remaining possibility | |
999 | * is the upper xuseg addresses. On processors with | |
1000 | * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these | |
1001 | * addresses would have taken an address error. We try | |
1002 | * to mimic that here by taking a load/istream page | |
1003 | * fault. | |
1004 | */ | |
1005 | UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0); | |
1006 | uasm_i_jr(p, ptr); | |
2c8c53e2 DD |
1007 | |
1008 | if (mode == refill_scratch) { | |
1009 | if (scratch_reg > 0) | |
1010 | UASM_i_MFC0(p, 1, 31, scratch_reg); | |
1011 | else | |
1012 | UASM_i_LW(p, 1, scratchpad_offset(0), 0); | |
1013 | } else { | |
1014 | uasm_i_nop(p); | |
1015 | } | |
1da177e4 LT |
1016 | } |
1017 | } | |
1018 | ||
875d43e7 | 1019 | #else /* !CONFIG_64BIT */ |
1da177e4 LT |
1020 | |
1021 | /* | |
1022 | * TMP and PTR are scratch. | |
1023 | * TMP will be clobbered, PTR will hold the pgd entry. | |
1024 | */ | |
234fcd14 | 1025 | static void __cpuinit __maybe_unused |
1da177e4 LT |
1026 | build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) |
1027 | { | |
1028 | long pgdc = (long)pgd_current; | |
1029 | ||
1030 | /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ | |
1031 | #ifdef CONFIG_SMP | |
70342287 | 1032 | #ifdef CONFIG_MIPS_MT_SMTC |
41c594ab RB |
1033 | /* |
1034 | * SMTC uses TCBind value as "CPU" index | |
1035 | */ | |
e30ec452 TS |
1036 | uasm_i_mfc0(p, ptr, C0_TCBIND); |
1037 | UASM_i_LA_mostly(p, tmp, pgdc); | |
1038 | uasm_i_srl(p, ptr, ptr, 19); | |
41c594ab RB |
1039 | #else |
1040 | /* | |
1041 | * smp_processor_id() << 3 is stored in CONTEXT. | |
70342287 | 1042 | */ |
e30ec452 TS |
1043 | uasm_i_mfc0(p, ptr, C0_CONTEXT); |
1044 | UASM_i_LA_mostly(p, tmp, pgdc); | |
1045 | uasm_i_srl(p, ptr, ptr, 23); | |
41c594ab | 1046 | #endif |
e30ec452 | 1047 | uasm_i_addu(p, ptr, tmp, ptr); |
1da177e4 | 1048 | #else |
e30ec452 | 1049 | UASM_i_LA_mostly(p, ptr, pgdc); |
1da177e4 | 1050 | #endif |
e30ec452 TS |
1051 | uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ |
1052 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1053 | uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ | |
1054 | uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); | |
1055 | uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
1da177e4 LT |
1056 | } |
1057 | ||
875d43e7 | 1058 | #endif /* !CONFIG_64BIT */ |
1da177e4 | 1059 | |
234fcd14 | 1060 | static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx) |
1da177e4 | 1061 | { |
242954b5 | 1062 | unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; |
1da177e4 LT |
1063 | unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); |
1064 | ||
10cc3529 | 1065 | switch (current_cpu_type()) { |
1da177e4 LT |
1066 | case CPU_VR41XX: |
1067 | case CPU_VR4111: | |
1068 | case CPU_VR4121: | |
1069 | case CPU_VR4122: | |
1070 | case CPU_VR4131: | |
1071 | case CPU_VR4181: | |
1072 | case CPU_VR4181A: | |
1073 | case CPU_VR4133: | |
1074 | shift += 2; | |
1075 | break; | |
1076 | ||
1077 | default: | |
1078 | break; | |
1079 | } | |
1080 | ||
1081 | if (shift) | |
e30ec452 TS |
1082 | UASM_i_SRL(p, ctx, ctx, shift); |
1083 | uasm_i_andi(p, ctx, ctx, mask); | |
1da177e4 LT |
1084 | } |
1085 | ||
234fcd14 | 1086 | static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) |
1da177e4 LT |
1087 | { |
1088 | /* | |
1089 | * Bug workaround for the Nevada. It seems as if under certain | |
1090 | * circumstances the move from cp0_context might produce a | |
1091 | * bogus result when the mfc0 instruction and its consumer are | |
1092 | * in a different cacheline or a load instruction, probably any | |
1093 | * memory reference, is between them. | |
1094 | */ | |
10cc3529 | 1095 | switch (current_cpu_type()) { |
1da177e4 | 1096 | case CPU_NEVADA: |
e30ec452 | 1097 | UASM_i_LW(p, ptr, 0, ptr); |
1da177e4 LT |
1098 | GET_CONTEXT(p, tmp); /* get context reg */ |
1099 | break; | |
1100 | ||
1101 | default: | |
1102 | GET_CONTEXT(p, tmp); /* get context reg */ | |
e30ec452 | 1103 | UASM_i_LW(p, ptr, 0, ptr); |
1da177e4 LT |
1104 | break; |
1105 | } | |
1106 | ||
1107 | build_adjust_context(p, tmp); | |
e30ec452 | 1108 | UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ |
1da177e4 LT |
1109 | } |
1110 | ||
234fcd14 | 1111 | static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, |
1da177e4 LT |
1112 | unsigned int ptep) |
1113 | { | |
1114 | /* | |
1115 | * 64bit address support (36bit on a 32bit CPU) in a 32bit | |
1116 | * Kernel is a special case. Only a few CPUs use it. | |
1117 | */ | |
1118 | #ifdef CONFIG_64BIT_PHYS_ADDR | |
1119 | if (cpu_has_64bits) { | |
e30ec452 TS |
1120 | uasm_i_ld(p, tmp, 0, ptep); /* get even pte */ |
1121 | uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ | |
05857c64 | 1122 | if (cpu_has_rixi) { |
748e787e | 1123 | UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); |
6dd9344c | 1124 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ |
748e787e | 1125 | UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); |
6dd9344c | 1126 | } else { |
3be6022c | 1127 | uasm_i_dsrl_safe(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */ |
6dd9344c | 1128 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ |
3be6022c | 1129 | uasm_i_dsrl_safe(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */ |
6dd9344c | 1130 | } |
9b8c3891 | 1131 | UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ |
1da177e4 LT |
1132 | } else { |
1133 | int pte_off_even = sizeof(pte_t) / 2; | |
1134 | int pte_off_odd = pte_off_even + sizeof(pte_t); | |
1135 | ||
1136 | /* The pte entries are pre-shifted */ | |
e30ec452 | 1137 | uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */ |
9b8c3891 | 1138 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ |
e30ec452 | 1139 | uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */ |
9b8c3891 | 1140 | UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ |
1da177e4 LT |
1141 | } |
1142 | #else | |
e30ec452 TS |
1143 | UASM_i_LW(p, tmp, 0, ptep); /* get even pte */ |
1144 | UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ | |
1da177e4 LT |
1145 | if (r45k_bvahwbug()) |
1146 | build_tlb_probe_entry(p); | |
05857c64 | 1147 | if (cpu_has_rixi) { |
748e787e | 1148 | UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); |
6dd9344c DD |
1149 | if (r4k_250MHZhwbug()) |
1150 | UASM_i_MTC0(p, 0, C0_ENTRYLO0); | |
1151 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ | |
748e787e | 1152 | UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); |
6dd9344c DD |
1153 | } else { |
1154 | UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */ | |
1155 | if (r4k_250MHZhwbug()) | |
1156 | UASM_i_MTC0(p, 0, C0_ENTRYLO0); | |
1157 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ | |
1158 | UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */ | |
1159 | if (r45k_bvahwbug()) | |
1160 | uasm_i_mfc0(p, tmp, C0_INDEX); | |
1161 | } | |
1da177e4 | 1162 | if (r4k_250MHZhwbug()) |
9b8c3891 DD |
1163 | UASM_i_MTC0(p, 0, C0_ENTRYLO1); |
1164 | UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ | |
1da177e4 LT |
1165 | #endif |
1166 | } | |
1167 | ||
2c8c53e2 DD |
1168 | struct mips_huge_tlb_info { |
1169 | int huge_pte; | |
1170 | int restore_scratch; | |
1171 | }; | |
1172 | ||
1173 | static struct mips_huge_tlb_info __cpuinit | |
1174 | build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, | |
1175 | struct uasm_reloc **r, unsigned int tmp, | |
1176 | unsigned int ptr, int c0_scratch) | |
1177 | { | |
1178 | struct mips_huge_tlb_info rv; | |
1179 | unsigned int even, odd; | |
1180 | int vmalloc_branch_delay_filled = 0; | |
1181 | const int scratch = 1; /* Our extra working register */ | |
1182 | ||
1183 | rv.huge_pte = scratch; | |
1184 | rv.restore_scratch = 0; | |
1185 | ||
1186 | if (check_for_high_segbits) { | |
1187 | UASM_i_MFC0(p, tmp, C0_BADVADDR); | |
1188 | ||
1189 | if (pgd_reg != -1) | |
1190 | UASM_i_MFC0(p, ptr, 31, pgd_reg); | |
1191 | else | |
1192 | UASM_i_MFC0(p, ptr, C0_CONTEXT); | |
1193 | ||
1194 | if (c0_scratch >= 0) | |
1195 | UASM_i_MTC0(p, scratch, 31, c0_scratch); | |
1196 | else | |
1197 | UASM_i_SW(p, scratch, scratchpad_offset(0), 0); | |
1198 | ||
1199 | uasm_i_dsrl_safe(p, scratch, tmp, | |
1200 | PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); | |
1201 | uasm_il_bnez(p, r, scratch, label_vmalloc); | |
1202 | ||
1203 | if (pgd_reg == -1) { | |
1204 | vmalloc_branch_delay_filled = 1; | |
1205 | /* Clear lower 23 bits of context. */ | |
1206 | uasm_i_dins(p, ptr, 0, 0, 23); | |
1207 | } | |
1208 | } else { | |
1209 | if (pgd_reg != -1) | |
1210 | UASM_i_MFC0(p, ptr, 31, pgd_reg); | |
1211 | else | |
1212 | UASM_i_MFC0(p, ptr, C0_CONTEXT); | |
1213 | ||
1214 | UASM_i_MFC0(p, tmp, C0_BADVADDR); | |
1215 | ||
1216 | if (c0_scratch >= 0) | |
1217 | UASM_i_MTC0(p, scratch, 31, c0_scratch); | |
1218 | else | |
1219 | UASM_i_SW(p, scratch, scratchpad_offset(0), 0); | |
1220 | ||
1221 | if (pgd_reg == -1) | |
1222 | /* Clear lower 23 bits of context. */ | |
1223 | uasm_i_dins(p, ptr, 0, 0, 23); | |
1224 | ||
1225 | uasm_il_bltz(p, r, tmp, label_vmalloc); | |
1226 | } | |
1227 | ||
1228 | if (pgd_reg == -1) { | |
1229 | vmalloc_branch_delay_filled = 1; | |
70342287 | 1230 | /* 1 0 1 0 1 << 6 xkphys cached */ |
2c8c53e2 DD |
1231 | uasm_i_ori(p, ptr, ptr, 0x540); |
1232 | uasm_i_drotr(p, ptr, ptr, 11); | |
1233 | } | |
1234 | ||
1235 | #ifdef __PAGETABLE_PMD_FOLDED | |
1236 | #define LOC_PTEP scratch | |
1237 | #else | |
1238 | #define LOC_PTEP ptr | |
1239 | #endif | |
1240 | ||
1241 | if (!vmalloc_branch_delay_filled) | |
1242 | /* get pgd offset in bytes */ | |
1243 | uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); | |
1244 | ||
1245 | uasm_l_vmalloc_done(l, *p); | |
1246 | ||
1247 | /* | |
70342287 RB |
1248 | * tmp ptr |
1249 | * fall-through case = badvaddr *pgd_current | |
1250 | * vmalloc case = badvaddr swapper_pg_dir | |
2c8c53e2 DD |
1251 | */ |
1252 | ||
1253 | if (vmalloc_branch_delay_filled) | |
1254 | /* get pgd offset in bytes */ | |
1255 | uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); | |
1256 | ||
1257 | #ifdef __PAGETABLE_PMD_FOLDED | |
1258 | GET_CONTEXT(p, tmp); /* get context reg */ | |
1259 | #endif | |
1260 | uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3); | |
1261 | ||
1262 | if (use_lwx_insns()) { | |
1263 | UASM_i_LWX(p, LOC_PTEP, scratch, ptr); | |
1264 | } else { | |
1265 | uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */ | |
1266 | uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */ | |
1267 | } | |
1268 | ||
1269 | #ifndef __PAGETABLE_PMD_FOLDED | |
1270 | /* get pmd offset in bytes */ | |
1271 | uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3); | |
1272 | uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3); | |
1273 | GET_CONTEXT(p, tmp); /* get context reg */ | |
1274 | ||
1275 | if (use_lwx_insns()) { | |
1276 | UASM_i_LWX(p, scratch, scratch, ptr); | |
1277 | } else { | |
1278 | uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */ | |
1279 | UASM_i_LW(p, scratch, 0, ptr); | |
1280 | } | |
1281 | #endif | |
1282 | /* Adjust the context during the load latency. */ | |
1283 | build_adjust_context(p, tmp); | |
1284 | ||
aa1762f4 | 1285 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
2c8c53e2 DD |
1286 | uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update); |
1287 | /* | |
1288 | * The in the LWX case we don't want to do the load in the | |
70342287 | 1289 | * delay slot. It cannot issue in the same cycle and may be |
2c8c53e2 DD |
1290 | * speculative and unneeded. |
1291 | */ | |
1292 | if (use_lwx_insns()) | |
1293 | uasm_i_nop(p); | |
aa1762f4 | 1294 | #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ |
2c8c53e2 DD |
1295 | |
1296 | ||
1297 | /* build_update_entries */ | |
1298 | if (use_lwx_insns()) { | |
1299 | even = ptr; | |
1300 | odd = tmp; | |
1301 | UASM_i_LWX(p, even, scratch, tmp); | |
1302 | UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t)); | |
1303 | UASM_i_LWX(p, odd, scratch, tmp); | |
1304 | } else { | |
1305 | UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */ | |
1306 | even = tmp; | |
1307 | odd = ptr; | |
1308 | UASM_i_LW(p, even, 0, ptr); /* get even pte */ | |
1309 | UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */ | |
1310 | } | |
05857c64 | 1311 | if (cpu_has_rixi) { |
748e787e | 1312 | uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL)); |
2c8c53e2 | 1313 | UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ |
748e787e | 1314 | uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL)); |
2c8c53e2 DD |
1315 | } else { |
1316 | uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL)); | |
1317 | UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ | |
1318 | uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL)); | |
1319 | } | |
1320 | UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */ | |
1321 | ||
1322 | if (c0_scratch >= 0) { | |
1323 | UASM_i_MFC0(p, scratch, 31, c0_scratch); | |
1324 | build_tlb_write_entry(p, l, r, tlb_random); | |
1325 | uasm_l_leave(l, *p); | |
1326 | rv.restore_scratch = 1; | |
1327 | } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) { | |
1328 | build_tlb_write_entry(p, l, r, tlb_random); | |
1329 | uasm_l_leave(l, *p); | |
1330 | UASM_i_LW(p, scratch, scratchpad_offset(0), 0); | |
1331 | } else { | |
1332 | UASM_i_LW(p, scratch, scratchpad_offset(0), 0); | |
1333 | build_tlb_write_entry(p, l, r, tlb_random); | |
1334 | uasm_l_leave(l, *p); | |
1335 | rv.restore_scratch = 1; | |
1336 | } | |
1337 | ||
1338 | uasm_i_eret(p); /* return from trap */ | |
1339 | ||
1340 | return rv; | |
1341 | } | |
1342 | ||
e6f72d3a DD |
1343 | /* |
1344 | * For a 64-bit kernel, we are using the 64-bit XTLB refill exception | |
1345 | * because EXL == 0. If we wrap, we can also use the 32 instruction | |
1346 | * slots before the XTLB refill exception handler which belong to the | |
1347 | * unused TLB refill exception. | |
1348 | */ | |
1349 | #define MIPS64_REFILL_INSNS 32 | |
1350 | ||
234fcd14 | 1351 | static void __cpuinit build_r4000_tlb_refill_handler(void) |
1da177e4 LT |
1352 | { |
1353 | u32 *p = tlb_handler; | |
e30ec452 TS |
1354 | struct uasm_label *l = labels; |
1355 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1356 | u32 *f; |
1357 | unsigned int final_len; | |
4a9040f4 RB |
1358 | struct mips_huge_tlb_info htlb_info __maybe_unused; |
1359 | enum vmalloc64_mode vmalloc_mode __maybe_unused; | |
1da177e4 LT |
1360 | |
1361 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
1362 | memset(labels, 0, sizeof(labels)); | |
1363 | memset(relocs, 0, sizeof(relocs)); | |
1364 | memset(final_handler, 0, sizeof(final_handler)); | |
1365 | ||
2c8c53e2 DD |
1366 | if ((scratch_reg > 0 || scratchpad_available()) && use_bbit_insns()) { |
1367 | htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1, | |
1368 | scratch_reg); | |
1369 | vmalloc_mode = refill_scratch; | |
1370 | } else { | |
1371 | htlb_info.huge_pte = K0; | |
1372 | htlb_info.restore_scratch = 0; | |
1373 | vmalloc_mode = refill_noscratch; | |
1374 | /* | |
1375 | * create the plain linear handler | |
1376 | */ | |
1377 | if (bcm1250_m3_war()) { | |
1378 | unsigned int segbits = 44; | |
1379 | ||
1380 | uasm_i_dmfc0(&p, K0, C0_BADVADDR); | |
1381 | uasm_i_dmfc0(&p, K1, C0_ENTRYHI); | |
1382 | uasm_i_xor(&p, K0, K0, K1); | |
1383 | uasm_i_dsrl_safe(&p, K1, K0, 62); | |
1384 | uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); | |
1385 | uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); | |
1386 | uasm_i_or(&p, K0, K0, K1); | |
1387 | uasm_il_bnez(&p, &r, K0, label_leave); | |
1388 | /* No need for uasm_i_nop */ | |
1389 | } | |
1da177e4 | 1390 | |
875d43e7 | 1391 | #ifdef CONFIG_64BIT |
2c8c53e2 | 1392 | build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ |
1da177e4 | 1393 | #else |
2c8c53e2 | 1394 | build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ |
1da177e4 LT |
1395 | #endif |
1396 | ||
aa1762f4 | 1397 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
2c8c53e2 | 1398 | build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update); |
fd062c84 DD |
1399 | #endif |
1400 | ||
2c8c53e2 DD |
1401 | build_get_ptep(&p, K0, K1); |
1402 | build_update_entries(&p, K0, K1); | |
1403 | build_tlb_write_entry(&p, &l, &r, tlb_random); | |
1404 | uasm_l_leave(&l, p); | |
1405 | uasm_i_eret(&p); /* return from trap */ | |
1406 | } | |
aa1762f4 | 1407 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 | 1408 | uasm_l_tlb_huge_update(&l, p); |
2c8c53e2 DD |
1409 | build_huge_update_entries(&p, htlb_info.huge_pte, K1); |
1410 | build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random, | |
1411 | htlb_info.restore_scratch); | |
fd062c84 DD |
1412 | #endif |
1413 | ||
875d43e7 | 1414 | #ifdef CONFIG_64BIT |
2c8c53e2 | 1415 | build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode); |
1da177e4 LT |
1416 | #endif |
1417 | ||
1418 | /* | |
1419 | * Overflow check: For the 64bit handler, we need at least one | |
1420 | * free instruction slot for the wrap-around branch. In worst | |
1421 | * case, if the intended insertion point is a delay slot, we | |
4b3f686d | 1422 | * need three, with the second nop'ed and the third being |
1da177e4 LT |
1423 | * unused. |
1424 | */ | |
2a21c730 FZ |
1425 | /* Loongson2 ebase is different than r4k, we have more space */ |
1426 | #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) | |
1da177e4 LT |
1427 | if ((p - tlb_handler) > 64) |
1428 | panic("TLB refill handler space exceeded"); | |
1429 | #else | |
e6f72d3a DD |
1430 | if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1) |
1431 | || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3) | |
1432 | && uasm_insn_has_bdelay(relocs, | |
1433 | tlb_handler + MIPS64_REFILL_INSNS - 3))) | |
1da177e4 LT |
1434 | panic("TLB refill handler space exceeded"); |
1435 | #endif | |
1436 | ||
1437 | /* | |
1438 | * Now fold the handler in the TLB refill handler space. | |
1439 | */ | |
2a21c730 | 1440 | #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) |
1da177e4 LT |
1441 | f = final_handler; |
1442 | /* Simplest case, just copy the handler. */ | |
e30ec452 | 1443 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); |
1da177e4 | 1444 | final_len = p - tlb_handler; |
875d43e7 | 1445 | #else /* CONFIG_64BIT */ |
e6f72d3a DD |
1446 | f = final_handler + MIPS64_REFILL_INSNS; |
1447 | if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) { | |
1da177e4 | 1448 | /* Just copy the handler. */ |
e30ec452 | 1449 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); |
1da177e4 LT |
1450 | final_len = p - tlb_handler; |
1451 | } else { | |
aa1762f4 | 1452 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 | 1453 | const enum label_id ls = label_tlb_huge_update; |
95affdda DD |
1454 | #else |
1455 | const enum label_id ls = label_vmalloc; | |
1456 | #endif | |
1457 | u32 *split; | |
1458 | int ov = 0; | |
1459 | int i; | |
1460 | ||
1461 | for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++) | |
1462 | ; | |
1463 | BUG_ON(i == ARRAY_SIZE(labels)); | |
1464 | split = labels[i].addr; | |
1da177e4 LT |
1465 | |
1466 | /* | |
95affdda | 1467 | * See if we have overflown one way or the other. |
1da177e4 | 1468 | */ |
95affdda DD |
1469 | if (split > tlb_handler + MIPS64_REFILL_INSNS || |
1470 | split < p - MIPS64_REFILL_INSNS) | |
1471 | ov = 1; | |
1472 | ||
1473 | if (ov) { | |
1474 | /* | |
1475 | * Split two instructions before the end. One | |
1476 | * for the branch and one for the instruction | |
1477 | * in the delay slot. | |
1478 | */ | |
1479 | split = tlb_handler + MIPS64_REFILL_INSNS - 2; | |
1480 | ||
1481 | /* | |
1482 | * If the branch would fall in a delay slot, | |
1483 | * we must back up an additional instruction | |
1484 | * so that it is no longer in a delay slot. | |
1485 | */ | |
1486 | if (uasm_insn_has_bdelay(relocs, split - 1)) | |
1487 | split--; | |
1488 | } | |
1da177e4 | 1489 | /* Copy first part of the handler. */ |
e30ec452 | 1490 | uasm_copy_handler(relocs, labels, tlb_handler, split, f); |
1da177e4 LT |
1491 | f += split - tlb_handler; |
1492 | ||
95affdda DD |
1493 | if (ov) { |
1494 | /* Insert branch. */ | |
1495 | uasm_l_split(&l, final_handler); | |
1496 | uasm_il_b(&f, &r, label_split); | |
1497 | if (uasm_insn_has_bdelay(relocs, split)) | |
1498 | uasm_i_nop(&f); | |
1499 | else { | |
1500 | uasm_copy_handler(relocs, labels, | |
1501 | split, split + 1, f); | |
1502 | uasm_move_labels(labels, f, f + 1, -1); | |
1503 | f++; | |
1504 | split++; | |
1505 | } | |
1da177e4 LT |
1506 | } |
1507 | ||
1508 | /* Copy the rest of the handler. */ | |
e30ec452 | 1509 | uasm_copy_handler(relocs, labels, split, p, final_handler); |
e6f72d3a DD |
1510 | final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) + |
1511 | (p - split); | |
1da177e4 | 1512 | } |
875d43e7 | 1513 | #endif /* CONFIG_64BIT */ |
1da177e4 | 1514 | |
e30ec452 TS |
1515 | uasm_resolve_relocs(relocs, labels); |
1516 | pr_debug("Wrote TLB refill handler (%u instructions).\n", | |
1517 | final_len); | |
1da177e4 | 1518 | |
91b05e67 | 1519 | memcpy((void *)ebase, final_handler, 0x100); |
92b1e6a6 | 1520 | |
a2c763e0 | 1521 | dump_handler("r4000_tlb_refill", (u32 *)ebase, 64); |
1da177e4 LT |
1522 | } |
1523 | ||
1da177e4 LT |
1524 | /* |
1525 | * 128 instructions for the fastpath handler is generous and should | |
1526 | * never be exceeded. | |
1527 | */ | |
1528 | #define FASTPATH_SIZE 128 | |
1529 | ||
cbdbe07f FBH |
1530 | u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned; |
1531 | u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned; | |
1532 | u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned; | |
3d8bfdd0 DD |
1533 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
1534 | u32 tlbmiss_handler_setup_pgd[16] __cacheline_aligned; | |
1535 | ||
1536 | static void __cpuinit build_r4000_setup_pgd(void) | |
1537 | { | |
1538 | const int a0 = 4; | |
1539 | const int a1 = 5; | |
1540 | u32 *p = tlbmiss_handler_setup_pgd; | |
1541 | struct uasm_label *l = labels; | |
1542 | struct uasm_reloc *r = relocs; | |
1543 | ||
1544 | memset(tlbmiss_handler_setup_pgd, 0, sizeof(tlbmiss_handler_setup_pgd)); | |
1545 | memset(labels, 0, sizeof(labels)); | |
1546 | memset(relocs, 0, sizeof(relocs)); | |
1547 | ||
1548 | pgd_reg = allocate_kscratch(); | |
1549 | ||
1550 | if (pgd_reg == -1) { | |
1551 | /* PGD << 11 in c0_Context */ | |
1552 | /* | |
1553 | * If it is a ckseg0 address, convert to a physical | |
1554 | * address. Shifting right by 29 and adding 4 will | |
1555 | * result in zero for these addresses. | |
1556 | * | |
1557 | */ | |
1558 | UASM_i_SRA(&p, a1, a0, 29); | |
1559 | UASM_i_ADDIU(&p, a1, a1, 4); | |
1560 | uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1); | |
1561 | uasm_i_nop(&p); | |
1562 | uasm_i_dinsm(&p, a0, 0, 29, 64 - 29); | |
1563 | uasm_l_tlbl_goaround1(&l, p); | |
1564 | UASM_i_SLL(&p, a0, a0, 11); | |
1565 | uasm_i_jr(&p, 31); | |
1566 | UASM_i_MTC0(&p, a0, C0_CONTEXT); | |
1567 | } else { | |
1568 | /* PGD in c0_KScratch */ | |
1569 | uasm_i_jr(&p, 31); | |
1570 | UASM_i_MTC0(&p, a0, 31, pgd_reg); | |
1571 | } | |
1572 | if (p - tlbmiss_handler_setup_pgd > ARRAY_SIZE(tlbmiss_handler_setup_pgd)) | |
1573 | panic("tlbmiss_handler_setup_pgd space exceeded"); | |
1574 | uasm_resolve_relocs(relocs, labels); | |
1575 | pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n", | |
1576 | (unsigned int)(p - tlbmiss_handler_setup_pgd)); | |
1577 | ||
a2c763e0 RB |
1578 | dump_handler("tlbmiss_handler", |
1579 | tlbmiss_handler_setup_pgd, | |
3d8bfdd0 DD |
1580 | ARRAY_SIZE(tlbmiss_handler_setup_pgd)); |
1581 | } | |
1582 | #endif | |
1da177e4 | 1583 | |
234fcd14 | 1584 | static void __cpuinit |
bd1437e4 | 1585 | iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) |
1da177e4 LT |
1586 | { |
1587 | #ifdef CONFIG_SMP | |
1588 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1589 | if (cpu_has_64bits) | |
e30ec452 | 1590 | uasm_i_lld(p, pte, 0, ptr); |
1da177e4 LT |
1591 | else |
1592 | # endif | |
e30ec452 | 1593 | UASM_i_LL(p, pte, 0, ptr); |
1da177e4 LT |
1594 | #else |
1595 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1596 | if (cpu_has_64bits) | |
e30ec452 | 1597 | uasm_i_ld(p, pte, 0, ptr); |
1da177e4 LT |
1598 | else |
1599 | # endif | |
e30ec452 | 1600 | UASM_i_LW(p, pte, 0, ptr); |
1da177e4 LT |
1601 | #endif |
1602 | } | |
1603 | ||
234fcd14 | 1604 | static void __cpuinit |
e30ec452 | 1605 | iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, |
63b2d2f4 | 1606 | unsigned int mode) |
1da177e4 | 1607 | { |
63b2d2f4 TS |
1608 | #ifdef CONFIG_64BIT_PHYS_ADDR |
1609 | unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); | |
1610 | #endif | |
1611 | ||
e30ec452 | 1612 | uasm_i_ori(p, pte, pte, mode); |
1da177e4 LT |
1613 | #ifdef CONFIG_SMP |
1614 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1615 | if (cpu_has_64bits) | |
e30ec452 | 1616 | uasm_i_scd(p, pte, 0, ptr); |
1da177e4 LT |
1617 | else |
1618 | # endif | |
e30ec452 | 1619 | UASM_i_SC(p, pte, 0, ptr); |
1da177e4 LT |
1620 | |
1621 | if (r10000_llsc_war()) | |
e30ec452 | 1622 | uasm_il_beqzl(p, r, pte, label_smp_pgtable_change); |
1da177e4 | 1623 | else |
e30ec452 | 1624 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); |
1da177e4 LT |
1625 | |
1626 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1627 | if (!cpu_has_64bits) { | |
e30ec452 TS |
1628 | /* no uasm_i_nop needed */ |
1629 | uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr); | |
1630 | uasm_i_ori(p, pte, pte, hwmode); | |
1631 | uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr); | |
1632 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); | |
1633 | /* no uasm_i_nop needed */ | |
1634 | uasm_i_lw(p, pte, 0, ptr); | |
1da177e4 | 1635 | } else |
e30ec452 | 1636 | uasm_i_nop(p); |
1da177e4 | 1637 | # else |
e30ec452 | 1638 | uasm_i_nop(p); |
1da177e4 LT |
1639 | # endif |
1640 | #else | |
1641 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1642 | if (cpu_has_64bits) | |
e30ec452 | 1643 | uasm_i_sd(p, pte, 0, ptr); |
1da177e4 LT |
1644 | else |
1645 | # endif | |
e30ec452 | 1646 | UASM_i_SW(p, pte, 0, ptr); |
1da177e4 LT |
1647 | |
1648 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1649 | if (!cpu_has_64bits) { | |
e30ec452 TS |
1650 | uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr); |
1651 | uasm_i_ori(p, pte, pte, hwmode); | |
1652 | uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr); | |
1653 | uasm_i_lw(p, pte, 0, ptr); | |
1da177e4 LT |
1654 | } |
1655 | # endif | |
1656 | #endif | |
1657 | } | |
1658 | ||
1659 | /* | |
1660 | * Check if PTE is present, if not then jump to LABEL. PTR points to | |
1661 | * the page table where this PTE is located, PTE will be re-loaded | |
1662 | * with it's original value. | |
1663 | */ | |
234fcd14 | 1664 | static void __cpuinit |
bd1437e4 | 1665 | build_pte_present(u32 **p, struct uasm_reloc **r, |
bf28607f | 1666 | int pte, int ptr, int scratch, enum label_id lid) |
1da177e4 | 1667 | { |
bf28607f DD |
1668 | int t = scratch >= 0 ? scratch : pte; |
1669 | ||
05857c64 | 1670 | if (cpu_has_rixi) { |
cc33ae43 DD |
1671 | if (use_bbit_insns()) { |
1672 | uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); | |
1673 | uasm_i_nop(p); | |
1674 | } else { | |
bf28607f DD |
1675 | uasm_i_andi(p, t, pte, _PAGE_PRESENT); |
1676 | uasm_il_beqz(p, r, t, lid); | |
1677 | if (pte == t) | |
1678 | /* You lose the SMP race :-(*/ | |
1679 | iPTE_LW(p, pte, ptr); | |
cc33ae43 | 1680 | } |
6dd9344c | 1681 | } else { |
bf28607f DD |
1682 | uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_READ); |
1683 | uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_READ); | |
1684 | uasm_il_bnez(p, r, t, lid); | |
1685 | if (pte == t) | |
1686 | /* You lose the SMP race :-(*/ | |
1687 | iPTE_LW(p, pte, ptr); | |
6dd9344c | 1688 | } |
1da177e4 LT |
1689 | } |
1690 | ||
1691 | /* Make PTE valid, store result in PTR. */ | |
234fcd14 | 1692 | static void __cpuinit |
e30ec452 | 1693 | build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte, |
1da177e4 LT |
1694 | unsigned int ptr) |
1695 | { | |
63b2d2f4 TS |
1696 | unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; |
1697 | ||
1698 | iPTE_SW(p, r, pte, ptr, mode); | |
1da177e4 LT |
1699 | } |
1700 | ||
1701 | /* | |
1702 | * Check if PTE can be written to, if not branch to LABEL. Regardless | |
1703 | * restore PTE with value from PTR when done. | |
1704 | */ | |
234fcd14 | 1705 | static void __cpuinit |
bd1437e4 | 1706 | build_pte_writable(u32 **p, struct uasm_reloc **r, |
bf28607f DD |
1707 | unsigned int pte, unsigned int ptr, int scratch, |
1708 | enum label_id lid) | |
1da177e4 | 1709 | { |
bf28607f DD |
1710 | int t = scratch >= 0 ? scratch : pte; |
1711 | ||
1712 | uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_WRITE); | |
1713 | uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_WRITE); | |
1714 | uasm_il_bnez(p, r, t, lid); | |
1715 | if (pte == t) | |
1716 | /* You lose the SMP race :-(*/ | |
cc33ae43 | 1717 | iPTE_LW(p, pte, ptr); |
bf28607f DD |
1718 | else |
1719 | uasm_i_nop(p); | |
1da177e4 LT |
1720 | } |
1721 | ||
1722 | /* Make PTE writable, update software status bits as well, then store | |
1723 | * at PTR. | |
1724 | */ | |
234fcd14 | 1725 | static void __cpuinit |
e30ec452 | 1726 | build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte, |
1da177e4 LT |
1727 | unsigned int ptr) |
1728 | { | |
63b2d2f4 TS |
1729 | unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID |
1730 | | _PAGE_DIRTY); | |
1731 | ||
1732 | iPTE_SW(p, r, pte, ptr, mode); | |
1da177e4 LT |
1733 | } |
1734 | ||
1735 | /* | |
1736 | * Check if PTE can be modified, if not branch to LABEL. Regardless | |
1737 | * restore PTE with value from PTR when done. | |
1738 | */ | |
234fcd14 | 1739 | static void __cpuinit |
bd1437e4 | 1740 | build_pte_modifiable(u32 **p, struct uasm_reloc **r, |
bf28607f DD |
1741 | unsigned int pte, unsigned int ptr, int scratch, |
1742 | enum label_id lid) | |
1da177e4 | 1743 | { |
cc33ae43 DD |
1744 | if (use_bbit_insns()) { |
1745 | uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid); | |
1746 | uasm_i_nop(p); | |
1747 | } else { | |
bf28607f DD |
1748 | int t = scratch >= 0 ? scratch : pte; |
1749 | uasm_i_andi(p, t, pte, _PAGE_WRITE); | |
1750 | uasm_il_beqz(p, r, t, lid); | |
1751 | if (pte == t) | |
1752 | /* You lose the SMP race :-(*/ | |
1753 | iPTE_LW(p, pte, ptr); | |
cc33ae43 | 1754 | } |
1da177e4 LT |
1755 | } |
1756 | ||
82622284 | 1757 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
3d8bfdd0 DD |
1758 | |
1759 | ||
1da177e4 LT |
1760 | /* |
1761 | * R3000 style TLB load/store/modify handlers. | |
1762 | */ | |
1763 | ||
fded2e50 MR |
1764 | /* |
1765 | * This places the pte into ENTRYLO0 and writes it with tlbwi. | |
1766 | * Then it returns. | |
1767 | */ | |
234fcd14 | 1768 | static void __cpuinit |
fded2e50 | 1769 | build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) |
1da177e4 | 1770 | { |
e30ec452 TS |
1771 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ |
1772 | uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ | |
1773 | uasm_i_tlbwi(p); | |
1774 | uasm_i_jr(p, tmp); | |
1775 | uasm_i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1776 | } |
1777 | ||
1778 | /* | |
fded2e50 MR |
1779 | * This places the pte into ENTRYLO0 and writes it with tlbwi |
1780 | * or tlbwr as appropriate. This is because the index register | |
1781 | * may have the probe fail bit set as a result of a trap on a | |
1782 | * kseg2 access, i.e. without refill. Then it returns. | |
1da177e4 | 1783 | */ |
234fcd14 | 1784 | static void __cpuinit |
e30ec452 TS |
1785 | build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l, |
1786 | struct uasm_reloc **r, unsigned int pte, | |
1787 | unsigned int tmp) | |
1788 | { | |
1789 | uasm_i_mfc0(p, tmp, C0_INDEX); | |
1790 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ | |
1791 | uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ | |
1792 | uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */ | |
1793 | uasm_i_tlbwi(p); /* cp0 delay */ | |
1794 | uasm_i_jr(p, tmp); | |
1795 | uasm_i_rfe(p); /* branch delay */ | |
1796 | uasm_l_r3000_write_probe_fail(l, *p); | |
1797 | uasm_i_tlbwr(p); /* cp0 delay */ | |
1798 | uasm_i_jr(p, tmp); | |
1799 | uasm_i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1800 | } |
1801 | ||
234fcd14 | 1802 | static void __cpuinit |
1da177e4 LT |
1803 | build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, |
1804 | unsigned int ptr) | |
1805 | { | |
1806 | long pgdc = (long)pgd_current; | |
1807 | ||
e30ec452 TS |
1808 | uasm_i_mfc0(p, pte, C0_BADVADDR); |
1809 | uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */ | |
1810 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1811 | uasm_i_srl(p, pte, pte, 22); /* load delay */ | |
1812 | uasm_i_sll(p, pte, pte, 2); | |
1813 | uasm_i_addu(p, ptr, ptr, pte); | |
1814 | uasm_i_mfc0(p, pte, C0_CONTEXT); | |
1815 | uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */ | |
1816 | uasm_i_andi(p, pte, pte, 0xffc); /* load delay */ | |
1817 | uasm_i_addu(p, ptr, ptr, pte); | |
1818 | uasm_i_lw(p, pte, 0, ptr); | |
1819 | uasm_i_tlbp(p); /* load delay */ | |
1da177e4 LT |
1820 | } |
1821 | ||
234fcd14 | 1822 | static void __cpuinit build_r3000_tlb_load_handler(void) |
1da177e4 LT |
1823 | { |
1824 | u32 *p = handle_tlbl; | |
e30ec452 TS |
1825 | struct uasm_label *l = labels; |
1826 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1827 | |
1828 | memset(handle_tlbl, 0, sizeof(handle_tlbl)); | |
1829 | memset(labels, 0, sizeof(labels)); | |
1830 | memset(relocs, 0, sizeof(relocs)); | |
1831 | ||
1832 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
bf28607f | 1833 | build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl); |
e30ec452 | 1834 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1835 | build_make_valid(&p, &r, K0, K1); |
fded2e50 | 1836 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 | 1837 | |
e30ec452 TS |
1838 | uasm_l_nopage_tlbl(&l, p); |
1839 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); | |
1840 | uasm_i_nop(&p); | |
1da177e4 LT |
1841 | |
1842 | if ((p - handle_tlbl) > FASTPATH_SIZE) | |
1843 | panic("TLB load handler fastpath space exceeded"); | |
1844 | ||
e30ec452 TS |
1845 | uasm_resolve_relocs(relocs, labels); |
1846 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", | |
1847 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 1848 | |
a2c763e0 | 1849 | dump_handler("r3000_tlb_load", handle_tlbl, ARRAY_SIZE(handle_tlbl)); |
1da177e4 LT |
1850 | } |
1851 | ||
234fcd14 | 1852 | static void __cpuinit build_r3000_tlb_store_handler(void) |
1da177e4 LT |
1853 | { |
1854 | u32 *p = handle_tlbs; | |
e30ec452 TS |
1855 | struct uasm_label *l = labels; |
1856 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1857 | |
1858 | memset(handle_tlbs, 0, sizeof(handle_tlbs)); | |
1859 | memset(labels, 0, sizeof(labels)); | |
1860 | memset(relocs, 0, sizeof(relocs)); | |
1861 | ||
1862 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
bf28607f | 1863 | build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs); |
e30ec452 | 1864 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1865 | build_make_write(&p, &r, K0, K1); |
fded2e50 | 1866 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 | 1867 | |
e30ec452 TS |
1868 | uasm_l_nopage_tlbs(&l, p); |
1869 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1870 | uasm_i_nop(&p); | |
1da177e4 LT |
1871 | |
1872 | if ((p - handle_tlbs) > FASTPATH_SIZE) | |
1873 | panic("TLB store handler fastpath space exceeded"); | |
1874 | ||
e30ec452 TS |
1875 | uasm_resolve_relocs(relocs, labels); |
1876 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", | |
1877 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 1878 | |
a2c763e0 | 1879 | dump_handler("r3000_tlb_store", handle_tlbs, ARRAY_SIZE(handle_tlbs)); |
1da177e4 LT |
1880 | } |
1881 | ||
234fcd14 | 1882 | static void __cpuinit build_r3000_tlb_modify_handler(void) |
1da177e4 LT |
1883 | { |
1884 | u32 *p = handle_tlbm; | |
e30ec452 TS |
1885 | struct uasm_label *l = labels; |
1886 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1887 | |
1888 | memset(handle_tlbm, 0, sizeof(handle_tlbm)); | |
1889 | memset(labels, 0, sizeof(labels)); | |
1890 | memset(relocs, 0, sizeof(relocs)); | |
1891 | ||
1892 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
d954ffe3 | 1893 | build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm); |
e30ec452 | 1894 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1895 | build_make_write(&p, &r, K0, K1); |
fded2e50 | 1896 | build_r3000_pte_reload_tlbwi(&p, K0, K1); |
1da177e4 | 1897 | |
e30ec452 TS |
1898 | uasm_l_nopage_tlbm(&l, p); |
1899 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1900 | uasm_i_nop(&p); | |
1da177e4 LT |
1901 | |
1902 | if ((p - handle_tlbm) > FASTPATH_SIZE) | |
1903 | panic("TLB modify handler fastpath space exceeded"); | |
1904 | ||
e30ec452 TS |
1905 | uasm_resolve_relocs(relocs, labels); |
1906 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", | |
1907 | (unsigned int)(p - handle_tlbm)); | |
1da177e4 | 1908 | |
a2c763e0 | 1909 | dump_handler("r3000_tlb_modify", handle_tlbm, ARRAY_SIZE(handle_tlbm)); |
1da177e4 | 1910 | } |
82622284 | 1911 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ |
1da177e4 LT |
1912 | |
1913 | /* | |
1914 | * R4000 style TLB load/store/modify handlers. | |
1915 | */ | |
bf28607f | 1916 | static struct work_registers __cpuinit |
e30ec452 | 1917 | build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l, |
bf28607f | 1918 | struct uasm_reloc **r) |
1da177e4 | 1919 | { |
bf28607f DD |
1920 | struct work_registers wr = build_get_work_registers(p); |
1921 | ||
875d43e7 | 1922 | #ifdef CONFIG_64BIT |
bf28607f | 1923 | build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */ |
1da177e4 | 1924 | #else |
bf28607f | 1925 | build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */ |
1da177e4 LT |
1926 | #endif |
1927 | ||
aa1762f4 | 1928 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
1929 | /* |
1930 | * For huge tlb entries, pmd doesn't contain an address but | |
1931 | * instead contains the tlb pte. Check the PAGE_HUGE bit and | |
1932 | * see if we need to jump to huge tlb processing. | |
1933 | */ | |
bf28607f | 1934 | build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update); |
fd062c84 DD |
1935 | #endif |
1936 | ||
bf28607f DD |
1937 | UASM_i_MFC0(p, wr.r1, C0_BADVADDR); |
1938 | UASM_i_LW(p, wr.r2, 0, wr.r2); | |
1939 | UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); | |
1940 | uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2); | |
1941 | UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1); | |
1da177e4 LT |
1942 | |
1943 | #ifdef CONFIG_SMP | |
e30ec452 TS |
1944 | uasm_l_smp_pgtable_change(l, *p); |
1945 | #endif | |
bf28607f | 1946 | iPTE_LW(p, wr.r1, wr.r2); /* get even pte */ |
8df5beac MR |
1947 | if (!m4kc_tlbp_war()) |
1948 | build_tlb_probe_entry(p); | |
bf28607f | 1949 | return wr; |
1da177e4 LT |
1950 | } |
1951 | ||
234fcd14 | 1952 | static void __cpuinit |
e30ec452 TS |
1953 | build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, |
1954 | struct uasm_reloc **r, unsigned int tmp, | |
1da177e4 LT |
1955 | unsigned int ptr) |
1956 | { | |
e30ec452 TS |
1957 | uasm_i_ori(p, ptr, ptr, sizeof(pte_t)); |
1958 | uasm_i_xori(p, ptr, ptr, sizeof(pte_t)); | |
1da177e4 LT |
1959 | build_update_entries(p, tmp, ptr); |
1960 | build_tlb_write_entry(p, l, r, tlb_indexed); | |
e30ec452 | 1961 | uasm_l_leave(l, *p); |
bf28607f | 1962 | build_restore_work_registers(p); |
e30ec452 | 1963 | uasm_i_eret(p); /* return from trap */ |
1da177e4 | 1964 | |
875d43e7 | 1965 | #ifdef CONFIG_64BIT |
1ec56329 | 1966 | build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill); |
1da177e4 LT |
1967 | #endif |
1968 | } | |
1969 | ||
234fcd14 | 1970 | static void __cpuinit build_r4000_tlb_load_handler(void) |
1da177e4 LT |
1971 | { |
1972 | u32 *p = handle_tlbl; | |
e30ec452 TS |
1973 | struct uasm_label *l = labels; |
1974 | struct uasm_reloc *r = relocs; | |
bf28607f | 1975 | struct work_registers wr; |
1da177e4 LT |
1976 | |
1977 | memset(handle_tlbl, 0, sizeof(handle_tlbl)); | |
1978 | memset(labels, 0, sizeof(labels)); | |
1979 | memset(relocs, 0, sizeof(relocs)); | |
1980 | ||
1981 | if (bcm1250_m3_war()) { | |
3d45285d RB |
1982 | unsigned int segbits = 44; |
1983 | ||
1984 | uasm_i_dmfc0(&p, K0, C0_BADVADDR); | |
1985 | uasm_i_dmfc0(&p, K1, C0_ENTRYHI); | |
e30ec452 | 1986 | uasm_i_xor(&p, K0, K0, K1); |
3be6022c DD |
1987 | uasm_i_dsrl_safe(&p, K1, K0, 62); |
1988 | uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); | |
1989 | uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); | |
3d45285d | 1990 | uasm_i_or(&p, K0, K0, K1); |
e30ec452 TS |
1991 | uasm_il_bnez(&p, &r, K0, label_leave); |
1992 | /* No need for uasm_i_nop */ | |
1da177e4 LT |
1993 | } |
1994 | ||
bf28607f DD |
1995 | wr = build_r4000_tlbchange_handler_head(&p, &l, &r); |
1996 | build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); | |
8df5beac MR |
1997 | if (m4kc_tlbp_war()) |
1998 | build_tlb_probe_entry(&p); | |
6dd9344c | 1999 | |
05857c64 | 2000 | if (cpu_has_rixi) { |
6dd9344c DD |
2001 | /* |
2002 | * If the page is not _PAGE_VALID, RI or XI could not | |
2003 | * have triggered it. Skip the expensive test.. | |
2004 | */ | |
cc33ae43 | 2005 | if (use_bbit_insns()) { |
bf28607f | 2006 | uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), |
cc33ae43 DD |
2007 | label_tlbl_goaround1); |
2008 | } else { | |
bf28607f DD |
2009 | uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); |
2010 | uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1); | |
cc33ae43 | 2011 | } |
6dd9344c DD |
2012 | uasm_i_nop(&p); |
2013 | ||
2014 | uasm_i_tlbr(&p); | |
2015 | /* Examine entrylo 0 or 1 based on ptr. */ | |
cc33ae43 | 2016 | if (use_bbit_insns()) { |
bf28607f | 2017 | uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); |
cc33ae43 | 2018 | } else { |
bf28607f DD |
2019 | uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); |
2020 | uasm_i_beqz(&p, wr.r3, 8); | |
cc33ae43 | 2021 | } |
bf28607f DD |
2022 | /* load it in the delay slot*/ |
2023 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); | |
2024 | /* load it if ptr is odd */ | |
2025 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); | |
6dd9344c | 2026 | /* |
bf28607f | 2027 | * If the entryLo (now in wr.r3) is valid (bit 1), RI or |
6dd9344c DD |
2028 | * XI must have triggered it. |
2029 | */ | |
cc33ae43 | 2030 | if (use_bbit_insns()) { |
bf28607f DD |
2031 | uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl); |
2032 | uasm_i_nop(&p); | |
cc33ae43 DD |
2033 | uasm_l_tlbl_goaround1(&l, p); |
2034 | } else { | |
bf28607f DD |
2035 | uasm_i_andi(&p, wr.r3, wr.r3, 2); |
2036 | uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl); | |
2037 | uasm_i_nop(&p); | |
cc33ae43 | 2038 | } |
bf28607f | 2039 | uasm_l_tlbl_goaround1(&l, p); |
6dd9344c | 2040 | } |
bf28607f DD |
2041 | build_make_valid(&p, &r, wr.r1, wr.r2); |
2042 | build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); | |
1da177e4 | 2043 | |
aa1762f4 | 2044 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
2045 | /* |
2046 | * This is the entry point when build_r4000_tlbchange_handler_head | |
2047 | * spots a huge page. | |
2048 | */ | |
2049 | uasm_l_tlb_huge_update(&l, p); | |
bf28607f DD |
2050 | iPTE_LW(&p, wr.r1, wr.r2); |
2051 | build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); | |
fd062c84 | 2052 | build_tlb_probe_entry(&p); |
6dd9344c | 2053 | |
05857c64 | 2054 | if (cpu_has_rixi) { |
6dd9344c DD |
2055 | /* |
2056 | * If the page is not _PAGE_VALID, RI or XI could not | |
2057 | * have triggered it. Skip the expensive test.. | |
2058 | */ | |
cc33ae43 | 2059 | if (use_bbit_insns()) { |
bf28607f | 2060 | uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), |
cc33ae43 DD |
2061 | label_tlbl_goaround2); |
2062 | } else { | |
bf28607f DD |
2063 | uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); |
2064 | uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); | |
cc33ae43 | 2065 | } |
6dd9344c DD |
2066 | uasm_i_nop(&p); |
2067 | ||
2068 | uasm_i_tlbr(&p); | |
2069 | /* Examine entrylo 0 or 1 based on ptr. */ | |
cc33ae43 | 2070 | if (use_bbit_insns()) { |
bf28607f | 2071 | uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); |
cc33ae43 | 2072 | } else { |
bf28607f DD |
2073 | uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); |
2074 | uasm_i_beqz(&p, wr.r3, 8); | |
cc33ae43 | 2075 | } |
bf28607f DD |
2076 | /* load it in the delay slot*/ |
2077 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); | |
2078 | /* load it if ptr is odd */ | |
2079 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); | |
6dd9344c | 2080 | /* |
bf28607f | 2081 | * If the entryLo (now in wr.r3) is valid (bit 1), RI or |
6dd9344c DD |
2082 | * XI must have triggered it. |
2083 | */ | |
cc33ae43 | 2084 | if (use_bbit_insns()) { |
bf28607f | 2085 | uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2); |
cc33ae43 | 2086 | } else { |
bf28607f DD |
2087 | uasm_i_andi(&p, wr.r3, wr.r3, 2); |
2088 | uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); | |
cc33ae43 | 2089 | } |
0f4ccbc8 DD |
2090 | if (PM_DEFAULT_MASK == 0) |
2091 | uasm_i_nop(&p); | |
6dd9344c DD |
2092 | /* |
2093 | * We clobbered C0_PAGEMASK, restore it. On the other branch | |
2094 | * it is restored in build_huge_tlb_write_entry. | |
2095 | */ | |
bf28607f | 2096 | build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0); |
6dd9344c DD |
2097 | |
2098 | uasm_l_tlbl_goaround2(&l, p); | |
2099 | } | |
bf28607f DD |
2100 | uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID)); |
2101 | build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2); | |
fd062c84 DD |
2102 | #endif |
2103 | ||
e30ec452 | 2104 | uasm_l_nopage_tlbl(&l, p); |
bf28607f | 2105 | build_restore_work_registers(&p); |
e30ec452 TS |
2106 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); |
2107 | uasm_i_nop(&p); | |
1da177e4 LT |
2108 | |
2109 | if ((p - handle_tlbl) > FASTPATH_SIZE) | |
2110 | panic("TLB load handler fastpath space exceeded"); | |
2111 | ||
e30ec452 TS |
2112 | uasm_resolve_relocs(relocs, labels); |
2113 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", | |
2114 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 2115 | |
a2c763e0 | 2116 | dump_handler("r4000_tlb_load", handle_tlbl, ARRAY_SIZE(handle_tlbl)); |
1da177e4 LT |
2117 | } |
2118 | ||
234fcd14 | 2119 | static void __cpuinit build_r4000_tlb_store_handler(void) |
1da177e4 LT |
2120 | { |
2121 | u32 *p = handle_tlbs; | |
e30ec452 TS |
2122 | struct uasm_label *l = labels; |
2123 | struct uasm_reloc *r = relocs; | |
bf28607f | 2124 | struct work_registers wr; |
1da177e4 LT |
2125 | |
2126 | memset(handle_tlbs, 0, sizeof(handle_tlbs)); | |
2127 | memset(labels, 0, sizeof(labels)); | |
2128 | memset(relocs, 0, sizeof(relocs)); | |
2129 | ||
bf28607f DD |
2130 | wr = build_r4000_tlbchange_handler_head(&p, &l, &r); |
2131 | build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); | |
8df5beac MR |
2132 | if (m4kc_tlbp_war()) |
2133 | build_tlb_probe_entry(&p); | |
bf28607f DD |
2134 | build_make_write(&p, &r, wr.r1, wr.r2); |
2135 | build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); | |
1da177e4 | 2136 | |
aa1762f4 | 2137 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
2138 | /* |
2139 | * This is the entry point when | |
2140 | * build_r4000_tlbchange_handler_head spots a huge page. | |
2141 | */ | |
2142 | uasm_l_tlb_huge_update(&l, p); | |
bf28607f DD |
2143 | iPTE_LW(&p, wr.r1, wr.r2); |
2144 | build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); | |
fd062c84 | 2145 | build_tlb_probe_entry(&p); |
bf28607f | 2146 | uasm_i_ori(&p, wr.r1, wr.r1, |
fd062c84 | 2147 | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); |
bf28607f | 2148 | build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2); |
fd062c84 DD |
2149 | #endif |
2150 | ||
e30ec452 | 2151 | uasm_l_nopage_tlbs(&l, p); |
bf28607f | 2152 | build_restore_work_registers(&p); |
e30ec452 TS |
2153 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); |
2154 | uasm_i_nop(&p); | |
1da177e4 LT |
2155 | |
2156 | if ((p - handle_tlbs) > FASTPATH_SIZE) | |
2157 | panic("TLB store handler fastpath space exceeded"); | |
2158 | ||
e30ec452 TS |
2159 | uasm_resolve_relocs(relocs, labels); |
2160 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", | |
2161 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 2162 | |
a2c763e0 | 2163 | dump_handler("r4000_tlb_store", handle_tlbs, ARRAY_SIZE(handle_tlbs)); |
1da177e4 LT |
2164 | } |
2165 | ||
234fcd14 | 2166 | static void __cpuinit build_r4000_tlb_modify_handler(void) |
1da177e4 LT |
2167 | { |
2168 | u32 *p = handle_tlbm; | |
e30ec452 TS |
2169 | struct uasm_label *l = labels; |
2170 | struct uasm_reloc *r = relocs; | |
bf28607f | 2171 | struct work_registers wr; |
1da177e4 LT |
2172 | |
2173 | memset(handle_tlbm, 0, sizeof(handle_tlbm)); | |
2174 | memset(labels, 0, sizeof(labels)); | |
2175 | memset(relocs, 0, sizeof(relocs)); | |
2176 | ||
bf28607f DD |
2177 | wr = build_r4000_tlbchange_handler_head(&p, &l, &r); |
2178 | build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); | |
8df5beac MR |
2179 | if (m4kc_tlbp_war()) |
2180 | build_tlb_probe_entry(&p); | |
1da177e4 | 2181 | /* Present and writable bits set, set accessed and dirty bits. */ |
bf28607f DD |
2182 | build_make_write(&p, &r, wr.r1, wr.r2); |
2183 | build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); | |
1da177e4 | 2184 | |
aa1762f4 | 2185 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
2186 | /* |
2187 | * This is the entry point when | |
2188 | * build_r4000_tlbchange_handler_head spots a huge page. | |
2189 | */ | |
2190 | uasm_l_tlb_huge_update(&l, p); | |
bf28607f DD |
2191 | iPTE_LW(&p, wr.r1, wr.r2); |
2192 | build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); | |
fd062c84 | 2193 | build_tlb_probe_entry(&p); |
bf28607f | 2194 | uasm_i_ori(&p, wr.r1, wr.r1, |
fd062c84 | 2195 | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); |
bf28607f | 2196 | build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2); |
fd062c84 DD |
2197 | #endif |
2198 | ||
e30ec452 | 2199 | uasm_l_nopage_tlbm(&l, p); |
bf28607f | 2200 | build_restore_work_registers(&p); |
e30ec452 TS |
2201 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); |
2202 | uasm_i_nop(&p); | |
1da177e4 LT |
2203 | |
2204 | if ((p - handle_tlbm) > FASTPATH_SIZE) | |
2205 | panic("TLB modify handler fastpath space exceeded"); | |
2206 | ||
e30ec452 TS |
2207 | uasm_resolve_relocs(relocs, labels); |
2208 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", | |
2209 | (unsigned int)(p - handle_tlbm)); | |
115f2a44 | 2210 | |
a2c763e0 | 2211 | dump_handler("r4000_tlb_modify", handle_tlbm, ARRAY_SIZE(handle_tlbm)); |
1da177e4 LT |
2212 | } |
2213 | ||
234fcd14 | 2214 | void __cpuinit build_tlb_refill_handler(void) |
1da177e4 LT |
2215 | { |
2216 | /* | |
2217 | * The refill handler is generated per-CPU, multi-node systems | |
2218 | * may have local storage for it. The other handlers are only | |
2219 | * needed once. | |
2220 | */ | |
2221 | static int run_once = 0; | |
2222 | ||
a2c763e0 RB |
2223 | output_pgtable_bits_defines(); |
2224 | ||
1ec56329 DD |
2225 | #ifdef CONFIG_64BIT |
2226 | check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); | |
2227 | #endif | |
2228 | ||
10cc3529 | 2229 | switch (current_cpu_type()) { |
1da177e4 LT |
2230 | case CPU_R2000: |
2231 | case CPU_R3000: | |
2232 | case CPU_R3000A: | |
2233 | case CPU_R3081E: | |
2234 | case CPU_TX3912: | |
2235 | case CPU_TX3922: | |
2236 | case CPU_TX3927: | |
82622284 | 2237 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
d532f3d2 | 2238 | setup_asid(0x40, 0xfc0, 0xf000, ASID_FIRST_VERSION_R3000); |
1da177e4 LT |
2239 | build_r3000_tlb_refill_handler(); |
2240 | if (!run_once) { | |
2241 | build_r3000_tlb_load_handler(); | |
2242 | build_r3000_tlb_store_handler(); | |
2243 | build_r3000_tlb_modify_handler(); | |
2244 | run_once++; | |
2245 | } | |
82622284 DD |
2246 | #else |
2247 | panic("No R3000 TLB refill handler"); | |
2248 | #endif | |
1da177e4 LT |
2249 | break; |
2250 | ||
2251 | case CPU_R6000: | |
2252 | case CPU_R6000A: | |
2253 | panic("No R6000 TLB refill handler yet"); | |
2254 | break; | |
2255 | ||
2256 | case CPU_R8000: | |
2257 | panic("No R8000 TLB refill handler yet"); | |
2258 | break; | |
2259 | ||
2260 | default: | |
d532f3d2 SH |
2261 | #ifndef CONFIG_MIPS_MT_SMTC |
2262 | setup_asid(0x1, 0xff, 0xff00, ASID_FIRST_VERSION_R4000); | |
2263 | #else | |
2264 | setup_asid(0x1, smtc_asid_mask, 0xff00, ASID_FIRST_VERSION_R4000); | |
2265 | #endif | |
1da177e4 | 2266 | if (!run_once) { |
bf28607f | 2267 | scratch_reg = allocate_kscratch(); |
3d8bfdd0 DD |
2268 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
2269 | build_r4000_setup_pgd(); | |
2270 | #endif | |
1da177e4 LT |
2271 | build_r4000_tlb_load_handler(); |
2272 | build_r4000_tlb_store_handler(); | |
2273 | build_r4000_tlb_modify_handler(); | |
2274 | run_once++; | |
2275 | } | |
3d8bfdd0 | 2276 | build_r4000_tlb_refill_handler(); |
1da177e4 LT |
2277 | } |
2278 | } | |
1d40cfcd | 2279 | |
234fcd14 | 2280 | void __cpuinit flush_tlb_handlers(void) |
1d40cfcd | 2281 | { |
e0cee3ee | 2282 | local_flush_icache_range((unsigned long)handle_tlbl, |
1d40cfcd | 2283 | (unsigned long)handle_tlbl + sizeof(handle_tlbl)); |
e0cee3ee | 2284 | local_flush_icache_range((unsigned long)handle_tlbs, |
1d40cfcd | 2285 | (unsigned long)handle_tlbs + sizeof(handle_tlbs)); |
e0cee3ee | 2286 | local_flush_icache_range((unsigned long)handle_tlbm, |
1d40cfcd | 2287 | (unsigned long)handle_tlbm + sizeof(handle_tlbm)); |
3d8bfdd0 DD |
2288 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
2289 | local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, | |
2290 | (unsigned long)tlbmiss_handler_setup_pgd + sizeof(handle_tlbm)); | |
2291 | #endif | |
1d40cfcd | 2292 | } |